1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 MediaTek Inc.
5 * Zhigang.Wei <zhigang.wei@mediatek.com>
6 * Chunfeng.Yun <chunfeng.yun@mediatek.com>
15 * To simplify scheduler algorithm, set a upper limit for ESIT,
16 * if a synchromous ep's ESIT is larger than @XHCI_MTK_MAX_ESIT,
17 * round down to the limit value, that means allocating more
20 #define XHCI_MTK_MAX_ESIT 64
23 * struct mu3h_sch_bw_info: schedule information for bandwidth domain
25 * @bus_bw: array to keep track of bandwidth already used at each uframes
26 * @bw_ep_list: eps in the bandwidth domain
28 * treat a HS root port as a bandwidth domain, but treat a SS root port as
29 * two bandwidth domains, one for IN eps and another for OUT eps.
31 struct mu3h_sch_bw_info {
32 u32 bus_bw[XHCI_MTK_MAX_ESIT];
33 struct list_head bw_ep_list;
37 * struct mu3h_sch_ep_info: schedule information for endpoint
39 * @esit: unit is 125us, equal to 2 << Interval field in ep-context
40 * @num_budget_microframes: number of continuous uframes
41 * (@repeat==1) scheduled within the interval
42 * @bw_cost_per_microframe: bandwidth cost per microframe
43 * @endpoint: linked into bandwidth domain which it belongs to
44 * @ep: address of usb_host_endpoint struct
45 * @offset: which uframe of the interval that transfer should be
46 * scheduled first time within the interval
47 * @repeat: the time gap between two uframes that transfers are
48 * scheduled within a interval. in the simple algorithm, only
49 * assign 0 or 1 to it; 0 means using only one uframe in a
50 * interval, and 1 means using @num_budget_microframes
52 * @pkts: number of packets to be transferred in the scheduled uframes
53 * @cs_count: number of CS that host will trigger
54 * @burst_mode: burst mode for scheduling. 0: normal burst mode,
55 * distribute the bMaxBurst+1 packets for a single burst
56 * according to @pkts and @repeat, repeate the burst multiple
57 * times; 1: distribute the (bMaxBurst+1)*(Mult+1) packets
58 * according to @pkts and @repeat. normal mode is used by
61 struct mu3h_sch_ep_info {
63 u32 num_budget_microframes;
64 u32 bw_cost_per_microframe;
65 struct list_head endpoint;
68 * mtk xHCI scheduling information put into reserved DWs
78 #define MU3C_U3_PORT_MAX 4
79 #define MU3C_U2_PORT_MAX 5
82 * struct mu3c_ippc_regs: MTK ssusb ip port control registers
83 * @ip_pw_ctr0~3: ip power and clock control registers
84 * @ip_pw_sts1~2: ip power and clock status registers
85 * @ip_xhci_cap: ip xHCI capability register
86 * @u3_ctrl_p[x]: ip usb3 port x control register, only low 4bytes are used
87 * @u2_ctrl_p[x]: ip usb2 port x control register, only low 4bytes are used
88 * @u2_phy_pll: usb2 phy pll control register
90 struct mu3c_ippc_regs {
100 __le64 u3_ctrl_p[MU3C_U3_PORT_MAX];
101 __le64 u2_ctrl_p[MU3C_U2_PORT_MAX];
104 __le32 reserved3[33]; /* 0x80 ~ 0xff */
107 struct xhci_hcd_mtk {
110 struct mu3h_sch_bw_info *sch_array;
111 struct mu3c_ippc_regs __iomem *ippc_regs;
116 struct regulator *vusb33;
117 struct regulator *vbus;
118 struct clk *sys_clk; /* sys and mac clock */
122 struct regmap *pericfg;
127 /* usb remote wakeup */
134 static inline struct xhci_hcd_mtk *hcd_to_mtk(struct usb_hcd *hcd)
136 return dev_get_drvdata(hcd->self.controller);
139 #if IS_ENABLED(CONFIG_USB_XHCI_MTK)
140 int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk);
141 void xhci_mtk_sch_exit(struct xhci_hcd_mtk *mtk);
142 int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
143 struct usb_host_endpoint *ep);
144 void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
145 struct usb_host_endpoint *ep);
148 static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
149 struct usb_device *udev, struct usb_host_endpoint *ep)
154 static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
155 struct usb_device *udev, struct usb_host_endpoint *ep)
161 #endif /* _XHCI_MTK_H_ */