1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek xHCI Host Controller Driver
5 * Copyright (c) 2015 MediaTek Inc.
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
25 /* ip_pw_ctrl0 register */
26 #define CTRL0_IP_SW_RST BIT(0)
28 /* ip_pw_ctrl1 register */
29 #define CTRL1_IP_HOST_PDN BIT(0)
31 /* ip_pw_ctrl2 register */
32 #define CTRL2_IP_DEV_PDN BIT(0)
34 /* ip_pw_sts1 register */
35 #define STS1_IP_SLEEP_STS BIT(30)
36 #define STS1_U3_MAC_RST BIT(16)
37 #define STS1_XHCI_RST BIT(11)
38 #define STS1_SYS125_RST BIT(10)
39 #define STS1_REF_RST BIT(8)
40 #define STS1_SYSPLL_STABLE BIT(0)
42 /* ip_xhci_cap register */
43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
46 /* u3_ctrl_p register */
47 #define CTRL_U3_PORT_HOST_SEL BIT(2)
48 #define CTRL_U3_PORT_PDN BIT(1)
49 #define CTRL_U3_PORT_DIS BIT(0)
51 /* u2_ctrl_p register */
52 #define CTRL_U2_PORT_HOST_SEL BIT(2)
53 #define CTRL_U2_PORT_PDN BIT(1)
54 #define CTRL_U2_PORT_DIS BIT(0)
56 /* u2_phy_pll register */
57 #define CTRL_U2_FORCE_PLL_STB BIT(28)
59 /* usb remote wakeup registers in syscon */
61 #define PERI_WK_CTRL1 0x4
62 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
63 #define WC1_IS_EN BIT(25)
64 #define WC1_IS_P BIT(6) /* polarity for ip sleep */
67 #define PERI_SSUSB_SPM_CTRL 0x0
68 #define SSC_IP_SLEEP_EN BIT(4)
69 #define SSC_SPM_INT_EN BIT(1)
76 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
78 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
80 int u3_ports_disabled = 0;
87 /* power on host ip */
88 value = readl(&ippc->ip_pw_ctr1);
89 value &= ~CTRL1_IP_HOST_PDN;
90 writel(value, &ippc->ip_pw_ctr1);
92 /* power on and enable u3 ports except skipped ones */
93 for (i = 0; i < mtk->num_u3_ports; i++) {
94 if ((0x1 << i) & mtk->u3p_dis_msk) {
99 value = readl(&ippc->u3_ctrl_p[i]);
100 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
101 value |= CTRL_U3_PORT_HOST_SEL;
102 writel(value, &ippc->u3_ctrl_p[i]);
105 /* power on and enable all u2 ports */
106 for (i = 0; i < mtk->num_u2_ports; i++) {
107 value = readl(&ippc->u2_ctrl_p[i]);
108 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
109 value |= CTRL_U2_PORT_HOST_SEL;
110 writel(value, &ippc->u2_ctrl_p[i]);
114 * wait for clocks to be stable, and clock domains reset to
115 * be inactive after power on and enable ports
117 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
118 STS1_SYS125_RST | STS1_XHCI_RST;
120 if (mtk->num_u3_ports > u3_ports_disabled)
121 check_val |= STS1_U3_MAC_RST;
123 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
124 (check_val == (value & check_val)), 100, 20000);
126 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
133 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
135 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
143 /* power down u3 ports except skipped ones */
144 for (i = 0; i < mtk->num_u3_ports; i++) {
145 if ((0x1 << i) & mtk->u3p_dis_msk)
148 value = readl(&ippc->u3_ctrl_p[i]);
149 value |= CTRL_U3_PORT_PDN;
150 writel(value, &ippc->u3_ctrl_p[i]);
153 /* power down all u2 ports */
154 for (i = 0; i < mtk->num_u2_ports; i++) {
155 value = readl(&ippc->u2_ctrl_p[i]);
156 value |= CTRL_U2_PORT_PDN;
157 writel(value, &ippc->u2_ctrl_p[i]);
160 /* power down host ip */
161 value = readl(&ippc->ip_pw_ctr1);
162 value |= CTRL1_IP_HOST_PDN;
163 writel(value, &ippc->ip_pw_ctr1);
165 /* wait for host ip to sleep */
166 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
167 (value & STS1_IP_SLEEP_STS), 100, 100000);
169 dev_err(mtk->dev, "ip sleep failed!!!\n");
175 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
177 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
184 value = readl(&ippc->ip_pw_ctr0);
185 value |= CTRL0_IP_SW_RST;
186 writel(value, &ippc->ip_pw_ctr0);
188 value = readl(&ippc->ip_pw_ctr0);
189 value &= ~CTRL0_IP_SW_RST;
190 writel(value, &ippc->ip_pw_ctr0);
193 * device ip is default power-on in fact
194 * power down device ip, otherwise ip-sleep will fail
196 value = readl(&ippc->ip_pw_ctr2);
197 value |= CTRL2_IP_DEV_PDN;
198 writel(value, &ippc->ip_pw_ctr2);
200 value = readl(&ippc->ip_xhci_cap);
201 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
202 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
203 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
204 mtk->num_u2_ports, mtk->num_u3_ports);
206 return xhci_mtk_host_enable(mtk);
209 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
211 struct device *dev = mtk->dev;
213 mtk->sys_clk = devm_clk_get(dev, "sys_ck");
214 if (IS_ERR(mtk->sys_clk)) {
215 dev_err(dev, "fail to get sys_ck\n");
216 return PTR_ERR(mtk->sys_clk);
219 mtk->xhci_clk = devm_clk_get_optional(dev, "xhci_ck");
220 if (IS_ERR(mtk->xhci_clk))
221 return PTR_ERR(mtk->xhci_clk);
223 mtk->ref_clk = devm_clk_get_optional(dev, "ref_ck");
224 if (IS_ERR(mtk->ref_clk))
225 return PTR_ERR(mtk->ref_clk);
227 mtk->mcu_clk = devm_clk_get_optional(dev, "mcu_ck");
228 if (IS_ERR(mtk->mcu_clk))
229 return PTR_ERR(mtk->mcu_clk);
231 mtk->dma_clk = devm_clk_get_optional(dev, "dma_ck");
232 return PTR_ERR_OR_ZERO(mtk->dma_clk);
235 static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
239 ret = clk_prepare_enable(mtk->ref_clk);
241 dev_err(mtk->dev, "failed to enable ref_clk\n");
245 ret = clk_prepare_enable(mtk->sys_clk);
247 dev_err(mtk->dev, "failed to enable sys_clk\n");
251 ret = clk_prepare_enable(mtk->xhci_clk);
253 dev_err(mtk->dev, "failed to enable xhci_clk\n");
257 ret = clk_prepare_enable(mtk->mcu_clk);
259 dev_err(mtk->dev, "failed to enable mcu_clk\n");
263 ret = clk_prepare_enable(mtk->dma_clk);
265 dev_err(mtk->dev, "failed to enable dma_clk\n");
272 clk_disable_unprepare(mtk->mcu_clk);
274 clk_disable_unprepare(mtk->xhci_clk);
276 clk_disable_unprepare(mtk->sys_clk);
278 clk_disable_unprepare(mtk->ref_clk);
283 static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
285 clk_disable_unprepare(mtk->dma_clk);
286 clk_disable_unprepare(mtk->mcu_clk);
287 clk_disable_unprepare(mtk->xhci_clk);
288 clk_disable_unprepare(mtk->sys_clk);
289 clk_disable_unprepare(mtk->ref_clk);
292 /* only clocks can be turn off for ip-sleep wakeup mode */
293 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
297 switch (mtk->uwk_vers) {
299 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
300 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
301 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
304 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
305 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
306 val = enable ? msk : 0;
311 regmap_update_bits(mtk->uwk, reg, msk, val);
314 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
315 struct device_node *dn)
317 struct of_phandle_args args;
320 /* Wakeup function is optional */
321 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
325 ret = of_parse_phandle_with_fixed_args(dn,
326 "mediatek,syscon-wakeup", 2, 0, &args);
330 mtk->uwk_reg_base = args.args[0];
331 mtk->uwk_vers = args.args[1];
332 mtk->uwk = syscon_node_to_regmap(args.np);
333 of_node_put(args.np);
334 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
335 mtk->uwk_reg_base, mtk->uwk_vers);
337 return PTR_ERR_OR_ZERO(mtk->uwk);
341 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
344 usb_wakeup_ip_sleep_set(mtk, enable);
347 static int xhci_mtk_setup(struct usb_hcd *hcd);
348 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
349 .reset = xhci_mtk_setup,
350 .check_bandwidth = xhci_mtk_check_bandwidth,
351 .reset_bandwidth = xhci_mtk_reset_bandwidth,
354 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
356 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
360 ret = regulator_enable(mtk->vbus);
362 dev_err(mtk->dev, "failed to enable vbus\n");
366 ret = regulator_enable(mtk->vusb33);
368 dev_err(mtk->dev, "failed to enable vusb33\n");
369 regulator_disable(mtk->vbus);
375 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
377 regulator_disable(mtk->vbus);
378 regulator_disable(mtk->vusb33);
381 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
383 struct usb_hcd *hcd = xhci_to_hcd(xhci);
384 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
387 * As of now platform drivers don't provide MSI support so we ensure
388 * here that the generic code does not try to make a pci_dev from our
389 * dev struct in order to setup MSI
391 xhci->quirks |= XHCI_PLAT;
392 xhci->quirks |= XHCI_MTK_HOST;
394 * MTK host controller gives a spurious successful event after a
395 * short transfer. Ignore it.
397 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
398 if (mtk->lpm_support)
399 xhci->quirks |= XHCI_LPM_SUPPORT;
400 if (mtk->u2_lpm_disable)
401 xhci->quirks |= XHCI_HW_LPM_DISABLE;
404 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
405 * and it's 3 when support it.
407 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
408 xhci->quirks |= XHCI_BROKEN_STREAMS;
411 /* called during probe() after chip reset completes */
412 static int xhci_mtk_setup(struct usb_hcd *hcd)
414 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
417 if (usb_hcd_is_primary_hcd(hcd)) {
418 ret = xhci_mtk_ssusb_config(mtk);
423 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
427 if (usb_hcd_is_primary_hcd(hcd)) {
428 ret = xhci_mtk_sch_init(mtk);
436 static int xhci_mtk_probe(struct platform_device *pdev)
438 struct device *dev = &pdev->dev;
439 struct device_node *node = dev->of_node;
440 struct xhci_hcd_mtk *mtk;
441 const struct hc_driver *driver;
442 struct xhci_hcd *xhci;
443 struct resource *res;
451 driver = &xhci_mtk_hc_driver;
452 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
457 mtk->vbus = devm_regulator_get(dev, "vbus");
458 if (IS_ERR(mtk->vbus)) {
459 dev_err(dev, "fail to get vbus\n");
460 return PTR_ERR(mtk->vbus);
463 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
464 if (IS_ERR(mtk->vusb33)) {
465 dev_err(dev, "fail to get vusb33\n");
466 return PTR_ERR(mtk->vusb33);
469 ret = xhci_mtk_clks_get(mtk);
473 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
474 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
475 /* optional property, ignore the error if it does not exist */
476 of_property_read_u32(node, "mediatek,u3p-dis-msk",
479 ret = usb_wakeup_of_property_parse(mtk, node);
481 dev_err(dev, "failed to parse uwk property\n");
485 pm_runtime_enable(dev);
486 pm_runtime_get_sync(dev);
487 device_enable_async_suspend(dev);
489 ret = xhci_mtk_ldos_enable(mtk);
493 ret = xhci_mtk_clks_enable(mtk);
497 irq = platform_get_irq(pdev, 0);
503 hcd = usb_create_hcd(driver, dev, dev_name(dev));
510 * USB 2.0 roothub is stored in the platform_device.
511 * Swap it with mtk HCD.
513 mtk->hcd = platform_get_drvdata(pdev);
514 platform_set_drvdata(pdev, mtk);
516 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
517 hcd->regs = devm_ioremap_resource(dev, res);
518 if (IS_ERR(hcd->regs)) {
519 ret = PTR_ERR(hcd->regs);
522 hcd->rsrc_start = res->start;
523 hcd->rsrc_len = resource_size(res);
525 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
526 if (res) { /* ippc register is optional */
527 mtk->ippc_regs = devm_ioremap_resource(dev, res);
528 if (IS_ERR(mtk->ippc_regs)) {
529 ret = PTR_ERR(mtk->ippc_regs);
532 mtk->has_ippc = true;
534 mtk->has_ippc = false;
537 device_init_wakeup(dev, true);
539 xhci = hcd_to_xhci(hcd);
540 xhci->main_hcd = hcd;
543 * imod_interval is the interrupt moderation value in nanoseconds.
544 * The increment interval is 8 times as much as that defined in
545 * the xHCI spec on MTK's controller.
547 xhci->imod_interval = 5000;
548 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
550 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
552 if (!xhci->shared_hcd) {
554 goto disable_device_wakeup;
557 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
561 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
562 !(xhci->quirks & XHCI_BROKEN_STREAMS))
563 xhci->shared_hcd->can_do_streams = 1;
565 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
567 goto dealloc_usb2_hcd;
575 xhci_mtk_sch_exit(mtk);
576 usb_put_hcd(xhci->shared_hcd);
578 disable_device_wakeup:
579 device_init_wakeup(dev, false);
585 xhci_mtk_clks_disable(mtk);
588 xhci_mtk_ldos_disable(mtk);
591 pm_runtime_put_sync(dev);
592 pm_runtime_disable(dev);
596 static int xhci_mtk_remove(struct platform_device *dev)
598 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
599 struct usb_hcd *hcd = mtk->hcd;
600 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
601 struct usb_hcd *shared_hcd = xhci->shared_hcd;
603 pm_runtime_put_noidle(&dev->dev);
604 pm_runtime_disable(&dev->dev);
606 usb_remove_hcd(shared_hcd);
607 xhci->shared_hcd = NULL;
608 device_init_wakeup(&dev->dev, false);
611 usb_put_hcd(shared_hcd);
613 xhci_mtk_sch_exit(mtk);
614 xhci_mtk_clks_disable(mtk);
615 xhci_mtk_ldos_disable(mtk);
621 * if ip sleep fails, and all clocks are disabled, access register will hang
622 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
623 * and no need to check whether ip sleep failed or not; this will cause SPM
624 * to wake up system immediately after system suspend complete if ip sleep
625 * fails, it is what we wanted.
627 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
629 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
630 struct usb_hcd *hcd = mtk->hcd;
631 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
633 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
634 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
635 del_timer_sync(&hcd->rh_timer);
636 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
637 del_timer_sync(&xhci->shared_hcd->rh_timer);
639 xhci_mtk_host_disable(mtk);
640 xhci_mtk_clks_disable(mtk);
641 usb_wakeup_set(mtk, true);
645 static int __maybe_unused xhci_mtk_resume(struct device *dev)
647 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
648 struct usb_hcd *hcd = mtk->hcd;
649 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
651 usb_wakeup_set(mtk, false);
652 xhci_mtk_clks_enable(mtk);
653 xhci_mtk_host_enable(mtk);
655 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
656 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
657 usb_hcd_poll_rh_status(xhci->shared_hcd);
658 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
659 usb_hcd_poll_rh_status(hcd);
663 static const struct dev_pm_ops xhci_mtk_pm_ops = {
664 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
666 #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
669 static const struct of_device_id mtk_xhci_of_match[] = {
670 { .compatible = "mediatek,mt8173-xhci"},
671 { .compatible = "mediatek,mtk-xhci"},
674 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
677 static struct platform_driver mtk_xhci_driver = {
678 .probe = xhci_mtk_probe,
679 .remove = xhci_mtk_remove,
683 .of_match_table = of_match_ptr(mtk_xhci_of_match),
686 MODULE_ALIAS("platform:xhci-mtk");
688 static int __init xhci_mtk_init(void)
690 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
691 return platform_driver_register(&mtk_xhci_driver);
693 module_init(xhci_mtk_init);
695 static void __exit xhci_mtk_exit(void)
697 platform_driver_unregister(&mtk_xhci_driver);
699 module_exit(xhci_mtk_exit);
701 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
702 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
703 MODULE_LICENSE("GPL v2");