2 * MediaTek xHCI Host Controller Driver
4 * Copyright (c) 2015 MediaTek Inc.
6 * Chunfeng Yun <chunfeng.yun@mediatek.com>
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/clk.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
26 #include <linux/phy/phy.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/regmap.h>
30 #include <linux/regulator/consumer.h>
35 /* ip_pw_ctrl0 register */
36 #define CTRL0_IP_SW_RST BIT(0)
38 /* ip_pw_ctrl1 register */
39 #define CTRL1_IP_HOST_PDN BIT(0)
41 /* ip_pw_ctrl2 register */
42 #define CTRL2_IP_DEV_PDN BIT(0)
44 /* ip_pw_sts1 register */
45 #define STS1_IP_SLEEP_STS BIT(30)
46 #define STS1_XHCI_RST BIT(11)
47 #define STS1_SYS125_RST BIT(10)
48 #define STS1_REF_RST BIT(8)
49 #define STS1_SYSPLL_STABLE BIT(0)
51 /* ip_xhci_cap register */
52 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
53 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
55 /* u3_ctrl_p register */
56 #define CTRL_U3_PORT_HOST_SEL BIT(2)
57 #define CTRL_U3_PORT_PDN BIT(1)
58 #define CTRL_U3_PORT_DIS BIT(0)
60 /* u2_ctrl_p register */
61 #define CTRL_U2_PORT_HOST_SEL BIT(2)
62 #define CTRL_U2_PORT_PDN BIT(1)
63 #define CTRL_U2_PORT_DIS BIT(0)
65 /* u2_phy_pll register */
66 #define CTRL_U2_FORCE_PLL_STB BIT(28)
68 #define PERI_WK_CTRL0 0x400
69 #define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */
70 #define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/
71 #define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
72 #define UWK_CTL1_1P_LS_E BIT(0)
74 #define PERI_WK_CTRL1 0x404
75 #define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
76 #define UWK_CTL1_IS_E BIT(25)
77 #define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
78 #define UWK_CTL1_0P_LS_E BIT(20)
79 #define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
80 #define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
81 #define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
82 #define UWK_CTL1_0P_LS_P BIT(7)
83 #define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
85 enum ssusb_wakeup_src {
86 SSUSB_WK_IP_SLEEP = 1,
87 SSUSB_WK_LINE_STATE = 2,
90 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
92 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
97 /* power on host ip */
98 value = readl(&ippc->ip_pw_ctr1);
99 value &= ~CTRL1_IP_HOST_PDN;
100 writel(value, &ippc->ip_pw_ctr1);
102 /* power on and enable all u3 ports */
103 for (i = 0; i < mtk->num_u3_ports; i++) {
104 value = readl(&ippc->u3_ctrl_p[i]);
105 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
106 value |= CTRL_U3_PORT_HOST_SEL;
107 writel(value, &ippc->u3_ctrl_p[i]);
110 /* power on and enable all u2 ports */
111 for (i = 0; i < mtk->num_u2_ports; i++) {
112 value = readl(&ippc->u2_ctrl_p[i]);
113 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
114 value |= CTRL_U2_PORT_HOST_SEL;
115 writel(value, &ippc->u2_ctrl_p[i]);
119 * wait for clocks to be stable, and clock domains reset to
120 * be inactive after power on and enable ports
122 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
123 STS1_SYS125_RST | STS1_XHCI_RST;
125 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
126 (check_val == (value & check_val)), 100, 20000);
128 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
135 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
137 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
142 /* power down all u3 ports */
143 for (i = 0; i < mtk->num_u3_ports; i++) {
144 value = readl(&ippc->u3_ctrl_p[i]);
145 value |= CTRL_U3_PORT_PDN;
146 writel(value, &ippc->u3_ctrl_p[i]);
149 /* power down all u2 ports */
150 for (i = 0; i < mtk->num_u2_ports; i++) {
151 value = readl(&ippc->u2_ctrl_p[i]);
152 value |= CTRL_U2_PORT_PDN;
153 writel(value, &ippc->u2_ctrl_p[i]);
156 /* power down host ip */
157 value = readl(&ippc->ip_pw_ctr1);
158 value |= CTRL1_IP_HOST_PDN;
159 writel(value, &ippc->ip_pw_ctr1);
161 /* wait for host ip to sleep */
162 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
163 (value & STS1_IP_SLEEP_STS), 100, 100000);
165 dev_err(mtk->dev, "ip sleep failed!!!\n");
171 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
173 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
177 value = readl(&ippc->ip_pw_ctr0);
178 value |= CTRL0_IP_SW_RST;
179 writel(value, &ippc->ip_pw_ctr0);
181 value = readl(&ippc->ip_pw_ctr0);
182 value &= ~CTRL0_IP_SW_RST;
183 writel(value, &ippc->ip_pw_ctr0);
186 * device ip is default power-on in fact
187 * power down device ip, otherwise ip-sleep will fail
189 value = readl(&ippc->ip_pw_ctr2);
190 value |= CTRL2_IP_DEV_PDN;
191 writel(value, &ippc->ip_pw_ctr2);
193 value = readl(&ippc->ip_xhci_cap);
194 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
195 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
196 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
197 mtk->num_u2_ports, mtk->num_u3_ports);
199 return xhci_mtk_host_enable(mtk);
202 static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
206 ret = clk_prepare_enable(mtk->sys_clk);
208 dev_err(mtk->dev, "failed to enable sys_clk\n");
212 if (mtk->wakeup_src) {
213 ret = clk_prepare_enable(mtk->wk_deb_p0);
215 dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
219 ret = clk_prepare_enable(mtk->wk_deb_p1);
221 dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
228 clk_disable_unprepare(mtk->wk_deb_p0);
230 clk_disable_unprepare(mtk->sys_clk);
235 static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
237 if (mtk->wakeup_src) {
238 clk_disable_unprepare(mtk->wk_deb_p1);
239 clk_disable_unprepare(mtk->wk_deb_p0);
241 clk_disable_unprepare(mtk->sys_clk);
244 /* only clocks can be turn off for ip-sleep wakeup mode */
245 static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
248 struct regmap *pericfg = mtk->pericfg;
250 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
251 tmp &= ~UWK_CTL1_IS_P;
252 tmp &= ~(UWK_CTL1_IS_C(0xf));
253 tmp |= UWK_CTL1_IS_C(0x8);
254 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
255 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
257 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
258 dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
262 static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
266 regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
267 tmp &= ~UWK_CTL1_IS_E;
268 regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
272 * for line-state wakeup mode, phy's power should not power-down
273 * and only support cable plug in/out
275 static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
278 struct regmap *pericfg = mtk->pericfg;
280 /* line-state of u2-port0 */
281 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
282 tmp &= ~UWK_CTL1_0P_LS_P;
283 tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
284 tmp |= UWK_CTL1_0P_LS_C(0x8);
285 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
286 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
287 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
289 /* line-state of u2-port1 */
290 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
291 tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
292 tmp |= UWK_CTL1_1P_LS_C(0x8);
293 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
294 regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
297 static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
300 struct regmap *pericfg = mtk->pericfg;
302 /* line-state of u2-port0 */
303 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
304 tmp &= ~UWK_CTL1_0P_LS_E;
305 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
307 /* line-state of u2-port1 */
308 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
309 tmp &= ~UWK_CTL1_1P_LS_E;
310 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
313 static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
315 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
316 usb_wakeup_ip_sleep_en(mtk);
317 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
318 usb_wakeup_line_state_en(mtk);
321 static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
323 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
324 usb_wakeup_ip_sleep_dis(mtk);
325 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
326 usb_wakeup_line_state_dis(mtk);
329 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
330 struct device_node *dn)
332 struct device *dev = mtk->dev;
335 * wakeup function is optional, so it is not an error if this property
336 * does not exist, and in such case, no need to get relative
337 * properties anymore.
339 of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
340 if (!mtk->wakeup_src)
343 mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
344 if (IS_ERR(mtk->wk_deb_p0)) {
345 dev_err(dev, "fail to get wakeup_deb_p0\n");
346 return PTR_ERR(mtk->wk_deb_p0);
349 mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
350 if (IS_ERR(mtk->wk_deb_p1)) {
351 dev_err(dev, "fail to get wakeup_deb_p1\n");
352 return PTR_ERR(mtk->wk_deb_p1);
355 mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
356 "mediatek,syscon-wakeup");
357 if (IS_ERR(mtk->pericfg)) {
358 dev_err(dev, "fail to get pericfg regs\n");
359 return PTR_ERR(mtk->pericfg);
365 static int xhci_mtk_setup(struct usb_hcd *hcd);
366 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
367 .extra_priv_size = sizeof(struct xhci_hcd),
368 .reset = xhci_mtk_setup,
371 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
373 static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
378 for (i = 0; i < mtk->num_phys; i++) {
379 ret = phy_init(mtk->phys[i]);
387 phy_exit(mtk->phys[i - 1]);
392 static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
396 for (i = 0; i < mtk->num_phys; i++)
397 phy_exit(mtk->phys[i]);
402 static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
407 for (i = 0; i < mtk->num_phys; i++) {
408 ret = phy_power_on(mtk->phys[i]);
416 phy_power_off(mtk->phys[i - 1]);
421 static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
425 for (i = 0; i < mtk->num_phys; i++)
426 phy_power_off(mtk->phys[i]);
429 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
433 ret = regulator_enable(mtk->vbus);
435 dev_err(mtk->dev, "failed to enable vbus\n");
439 ret = regulator_enable(mtk->vusb33);
441 dev_err(mtk->dev, "failed to enable vusb33\n");
442 regulator_disable(mtk->vbus);
448 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
450 regulator_disable(mtk->vbus);
451 regulator_disable(mtk->vusb33);
454 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
456 struct usb_hcd *hcd = xhci_to_hcd(xhci);
457 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
460 * As of now platform drivers don't provide MSI support so we ensure
461 * here that the generic code does not try to make a pci_dev from our
462 * dev struct in order to setup MSI
464 xhci->quirks |= XHCI_PLAT;
465 xhci->quirks |= XHCI_MTK_HOST;
467 * MTK host controller gives a spurious successful event after a
468 * short transfer. Ignore it.
470 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
471 if (mtk->lpm_support)
472 xhci->quirks |= XHCI_LPM_SUPPORT;
475 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
476 * and it's 3 when support it.
478 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
479 xhci->quirks |= XHCI_BROKEN_STREAMS;
482 /* called during probe() after chip reset completes */
483 static int xhci_mtk_setup(struct usb_hcd *hcd)
485 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
488 if (usb_hcd_is_primary_hcd(hcd)) {
489 ret = xhci_mtk_ssusb_config(mtk);
492 ret = xhci_mtk_sch_init(mtk);
497 return xhci_gen_setup(hcd, xhci_mtk_quirks);
500 static int xhci_mtk_probe(struct platform_device *pdev)
502 struct device *dev = &pdev->dev;
503 struct device_node *node = dev->of_node;
504 struct xhci_hcd_mtk *mtk;
505 const struct hc_driver *driver;
506 struct xhci_hcd *xhci;
507 struct resource *res;
517 driver = &xhci_mtk_hc_driver;
518 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
523 mtk->vbus = devm_regulator_get(dev, "vbus");
524 if (IS_ERR(mtk->vbus)) {
525 dev_err(dev, "fail to get vbus\n");
526 return PTR_ERR(mtk->vbus);
529 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
530 if (IS_ERR(mtk->vusb33)) {
531 dev_err(dev, "fail to get vusb33\n");
532 return PTR_ERR(mtk->vusb33);
535 mtk->sys_clk = devm_clk_get(dev, "sys_ck");
536 if (IS_ERR(mtk->sys_clk)) {
537 dev_err(dev, "fail to get sys_ck\n");
538 return PTR_ERR(mtk->sys_clk);
541 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
543 ret = usb_wakeup_of_property_parse(mtk, node);
547 mtk->num_phys = of_count_phandle_with_args(node,
548 "phys", "#phy-cells");
549 if (mtk->num_phys > 0) {
550 mtk->phys = devm_kcalloc(dev, mtk->num_phys,
551 sizeof(*mtk->phys), GFP_KERNEL);
557 pm_runtime_enable(dev);
558 pm_runtime_get_sync(dev);
559 device_enable_async_suspend(dev);
561 ret = xhci_mtk_ldos_enable(mtk);
565 ret = xhci_mtk_clks_enable(mtk);
569 irq = platform_get_irq(pdev, 0);
575 /* Initialize dma_mask and coherent_dma_mask to 32-bits */
576 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
581 dev->dma_mask = &dev->coherent_dma_mask;
583 dma_set_mask(dev, DMA_BIT_MASK(32));
585 hcd = usb_create_hcd(driver, dev, dev_name(dev));
592 * USB 2.0 roothub is stored in the platform_device.
593 * Swap it with mtk HCD.
595 mtk->hcd = platform_get_drvdata(pdev);
596 platform_set_drvdata(pdev, mtk);
598 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
599 hcd->regs = devm_ioremap_resource(dev, res);
600 if (IS_ERR(hcd->regs)) {
601 ret = PTR_ERR(hcd->regs);
604 hcd->rsrc_start = res->start;
605 hcd->rsrc_len = resource_size(res);
607 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
608 mtk->ippc_regs = devm_ioremap_resource(dev, res);
609 if (IS_ERR(mtk->ippc_regs)) {
610 ret = PTR_ERR(mtk->ippc_regs);
614 for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
615 phy = devm_of_phy_get_by_index(dev, node, phy_num);
620 mtk->phys[phy_num] = phy;
623 ret = xhci_mtk_phy_init(mtk);
627 ret = xhci_mtk_phy_power_on(mtk);
631 device_init_wakeup(dev, true);
633 xhci = hcd_to_xhci(hcd);
634 xhci->main_hcd = hcd;
635 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
637 if (!xhci->shared_hcd) {
642 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
646 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
647 !(xhci->quirks & XHCI_BROKEN_STREAMS))
648 xhci->shared_hcd->can_do_streams = 1;
650 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
652 goto dealloc_usb2_hcd;
660 xhci_mtk_sch_exit(mtk);
661 usb_put_hcd(xhci->shared_hcd);
664 xhci_mtk_phy_power_off(mtk);
665 device_init_wakeup(dev, false);
668 xhci_mtk_phy_exit(mtk);
674 xhci_mtk_clks_disable(mtk);
677 xhci_mtk_ldos_disable(mtk);
680 pm_runtime_put_sync(dev);
681 pm_runtime_disable(dev);
685 static int xhci_mtk_remove(struct platform_device *dev)
687 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
688 struct usb_hcd *hcd = mtk->hcd;
689 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
691 usb_remove_hcd(xhci->shared_hcd);
692 xhci_mtk_phy_power_off(mtk);
693 xhci_mtk_phy_exit(mtk);
694 device_init_wakeup(&dev->dev, false);
697 usb_put_hcd(xhci->shared_hcd);
699 xhci_mtk_sch_exit(mtk);
700 xhci_mtk_clks_disable(mtk);
701 xhci_mtk_ldos_disable(mtk);
702 pm_runtime_put_sync(&dev->dev);
703 pm_runtime_disable(&dev->dev);
709 * if ip sleep fails, and all clocks are disabled, access register will hang
710 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
711 * and no need to check whether ip sleep failed or not; this will cause SPM
712 * to wake up system immediately after system suspend complete if ip sleep
713 * fails, it is what we wanted.
715 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
717 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
718 struct usb_hcd *hcd = mtk->hcd;
719 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
721 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
722 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
723 del_timer_sync(&hcd->rh_timer);
724 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
725 del_timer_sync(&xhci->shared_hcd->rh_timer);
727 xhci_mtk_host_disable(mtk);
728 xhci_mtk_phy_power_off(mtk);
729 xhci_mtk_clks_disable(mtk);
730 usb_wakeup_enable(mtk);
734 static int __maybe_unused xhci_mtk_resume(struct device *dev)
736 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
737 struct usb_hcd *hcd = mtk->hcd;
738 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
740 usb_wakeup_disable(mtk);
741 xhci_mtk_clks_enable(mtk);
742 xhci_mtk_phy_power_on(mtk);
743 xhci_mtk_host_enable(mtk);
745 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
746 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
747 usb_hcd_poll_rh_status(xhci->shared_hcd);
748 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
749 usb_hcd_poll_rh_status(hcd);
753 static const struct dev_pm_ops xhci_mtk_pm_ops = {
754 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
756 #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
759 static const struct of_device_id mtk_xhci_of_match[] = {
760 { .compatible = "mediatek,mt8173-xhci"},
763 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
766 static struct platform_driver mtk_xhci_driver = {
767 .probe = xhci_mtk_probe,
768 .remove = xhci_mtk_remove,
772 .of_match_table = of_match_ptr(mtk_xhci_of_match),
775 MODULE_ALIAS("platform:xhci-mtk");
777 static int __init xhci_mtk_init(void)
779 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
780 return platform_driver_register(&mtk_xhci_driver);
782 module_init(xhci_mtk_init);
784 static void __exit xhci_mtk_exit(void)
786 platform_driver_unregister(&mtk_xhci_driver);
788 module_exit(xhci_mtk_exit);
790 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
791 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
792 MODULE_LICENSE("GPL v2");