2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
27 #include <linux/dma-mapping.h>
30 #include "xhci-trace.h"
33 * Allocates a generic ring segment from the ring pool, sets the dma address,
34 * initializes the segment to zero, and sets the private next pointer to NULL.
37 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
39 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
40 unsigned int cycle_state,
41 unsigned int max_packet,
44 struct xhci_segment *seg;
48 seg = kzalloc(sizeof *seg, flags);
52 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma);
59 seg->bounce_buf = kzalloc(max_packet, flags);
60 if (!seg->bounce_buf) {
61 dma_pool_free(xhci->segment_pool, seg->trbs, dma);
66 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
67 if (cycle_state == 0) {
68 for (i = 0; i < TRBS_PER_SEGMENT; i++)
69 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
77 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
80 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
83 kfree(seg->bounce_buf);
87 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
88 struct xhci_segment *first)
90 struct xhci_segment *seg;
93 while (seg != first) {
94 struct xhci_segment *next = seg->next;
95 xhci_segment_free(xhci, seg);
98 xhci_segment_free(xhci, first);
102 * Make the prev segment point to the next segment.
104 * Change the last TRB in the prev segment to be a Link TRB which points to the
105 * DMA address of the next segment. The caller needs to set any Link TRB
106 * related flags, such as End TRB, Toggle Cycle, and no snoop.
108 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
109 struct xhci_segment *next, enum xhci_ring_type type)
116 if (type != TYPE_EVENT) {
117 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
118 cpu_to_le64(next->dma);
120 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
121 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
122 val &= ~TRB_TYPE_BITMASK;
123 val |= TRB_TYPE(TRB_LINK);
124 /* Always set the chain bit with 0.95 hardware */
125 /* Set chain bit for isoc rings on AMD 0.96 host */
126 if (xhci_link_trb_quirk(xhci) ||
127 (type == TYPE_ISOC &&
128 (xhci->quirks & XHCI_AMD_0x96_HOST)))
130 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
135 * Link the ring to the new segments.
136 * Set Toggle Cycle for the new ring if needed.
138 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
139 struct xhci_segment *first, struct xhci_segment *last,
140 unsigned int num_segs)
142 struct xhci_segment *next;
144 if (!ring || !first || !last)
147 next = ring->enq_seg->next;
148 xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
149 xhci_link_segments(xhci, last, next, ring->type);
150 ring->num_segs += num_segs;
151 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
153 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
154 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
155 &= ~cpu_to_le32(LINK_TOGGLE);
156 last->trbs[TRBS_PER_SEGMENT-1].link.control
157 |= cpu_to_le32(LINK_TOGGLE);
158 ring->last_seg = last;
163 * We need a radix tree for mapping physical addresses of TRBs to which stream
164 * ID they belong to. We need to do this because the host controller won't tell
165 * us which stream ring the TRB came from. We could store the stream ID in an
166 * event data TRB, but that doesn't help us for the cancellation case, since the
167 * endpoint may stop before it reaches that event data TRB.
169 * The radix tree maps the upper portion of the TRB DMA address to a ring
170 * segment that has the same upper portion of DMA addresses. For example, say I
171 * have segments of size 1KB, that are always 1KB aligned. A segment may
172 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
173 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
174 * pass the radix tree a key to get the right stream ID:
176 * 0x10c90fff >> 10 = 0x43243
177 * 0x10c912c0 >> 10 = 0x43244
178 * 0x10c91400 >> 10 = 0x43245
180 * Obviously, only those TRBs with DMA addresses that are within the segment
181 * will make the radix tree return the stream ID for that ring.
183 * Caveats for the radix tree:
185 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
186 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
187 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
188 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
189 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
190 * extended systems (where the DMA address can be bigger than 32-bits),
191 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
193 static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
194 struct xhci_ring *ring,
195 struct xhci_segment *seg,
201 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
202 /* Skip any segments that were already added. */
203 if (radix_tree_lookup(trb_address_map, key))
206 ret = radix_tree_maybe_preload(mem_flags);
209 ret = radix_tree_insert(trb_address_map,
211 radix_tree_preload_end();
215 static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
216 struct xhci_segment *seg)
220 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
221 if (radix_tree_lookup(trb_address_map, key))
222 radix_tree_delete(trb_address_map, key);
225 static int xhci_update_stream_segment_mapping(
226 struct radix_tree_root *trb_address_map,
227 struct xhci_ring *ring,
228 struct xhci_segment *first_seg,
229 struct xhci_segment *last_seg,
232 struct xhci_segment *seg;
233 struct xhci_segment *failed_seg;
236 if (WARN_ON_ONCE(trb_address_map == NULL))
241 ret = xhci_insert_segment_mapping(trb_address_map,
242 ring, seg, mem_flags);
248 } while (seg != first_seg);
256 xhci_remove_segment_mapping(trb_address_map, seg);
257 if (seg == failed_seg)
260 } while (seg != first_seg);
265 static void xhci_remove_stream_mapping(struct xhci_ring *ring)
267 struct xhci_segment *seg;
269 if (WARN_ON_ONCE(ring->trb_address_map == NULL))
272 seg = ring->first_seg;
274 xhci_remove_segment_mapping(ring->trb_address_map, seg);
276 } while (seg != ring->first_seg);
279 static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
281 return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
282 ring->first_seg, ring->last_seg, mem_flags);
285 /* XXX: Do we need the hcd structure in all these functions? */
286 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
291 trace_xhci_ring_free(ring);
293 if (ring->first_seg) {
294 if (ring->type == TYPE_STREAM)
295 xhci_remove_stream_mapping(ring);
296 xhci_free_segments_for_ring(xhci, ring->first_seg);
302 static void xhci_initialize_ring_info(struct xhci_ring *ring,
303 unsigned int cycle_state)
305 /* The ring is empty, so the enqueue pointer == dequeue pointer */
306 ring->enqueue = ring->first_seg->trbs;
307 ring->enq_seg = ring->first_seg;
308 ring->dequeue = ring->enqueue;
309 ring->deq_seg = ring->first_seg;
310 /* The ring is initialized to 0. The producer must write 1 to the cycle
311 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
312 * compare CCS to the cycle bit to check ownership, so CCS = 1.
314 * New rings are initialized with cycle state equal to 1; if we are
315 * handling ring expansion, set the cycle state equal to the old ring.
317 ring->cycle_state = cycle_state;
320 * Each segment has a link TRB, and leave an extra TRB for SW
323 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
326 /* Allocate segments and link them for a ring */
327 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
328 struct xhci_segment **first, struct xhci_segment **last,
329 unsigned int num_segs, unsigned int cycle_state,
330 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
332 struct xhci_segment *prev;
334 prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
340 while (num_segs > 0) {
341 struct xhci_segment *next;
343 next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
348 xhci_segment_free(xhci, prev);
353 xhci_link_segments(xhci, prev, next, type);
358 xhci_link_segments(xhci, prev, *first, type);
365 * Create a new ring with zero or more segments.
367 * Link each segment together into a ring.
368 * Set the end flag and the cycle toggle bit on the last segment.
369 * See section 4.9.1 and figures 15 and 16.
371 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
372 unsigned int num_segs, unsigned int cycle_state,
373 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
375 struct xhci_ring *ring;
378 ring = kzalloc(sizeof *(ring), flags);
382 ring->num_segs = num_segs;
383 ring->bounce_buf_len = max_packet;
384 INIT_LIST_HEAD(&ring->td_list);
389 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
390 &ring->last_seg, num_segs, cycle_state, type,
395 /* Only event ring does not use link TRB */
396 if (type != TYPE_EVENT) {
397 /* See section 4.9.2.1 and 6.4.4.1 */
398 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
399 cpu_to_le32(LINK_TOGGLE);
401 xhci_initialize_ring_info(ring, cycle_state);
402 trace_xhci_ring_alloc(ring);
410 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
411 struct xhci_virt_device *virt_dev,
412 unsigned int ep_index)
414 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
415 virt_dev->eps[ep_index].ring = NULL;
419 * Expand an existing ring.
420 * Allocate a new ring which has same segment numbers and link the two rings.
422 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
423 unsigned int num_trbs, gfp_t flags)
425 struct xhci_segment *first;
426 struct xhci_segment *last;
427 unsigned int num_segs;
428 unsigned int num_segs_needed;
431 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
432 (TRBS_PER_SEGMENT - 1);
434 /* Allocate number of segments we needed, or double the ring size */
435 num_segs = ring->num_segs > num_segs_needed ?
436 ring->num_segs : num_segs_needed;
438 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
439 num_segs, ring->cycle_state, ring->type,
440 ring->bounce_buf_len, flags);
444 if (ring->type == TYPE_STREAM)
445 ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
446 ring, first, last, flags);
448 struct xhci_segment *next;
451 xhci_segment_free(xhci, first);
459 xhci_link_rings(xhci, ring, first, last, num_segs);
460 trace_xhci_ring_expansion(ring);
461 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
462 "ring expansion succeed, now has %d segments",
468 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
470 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
471 int type, gfp_t flags)
473 struct xhci_container_ctx *ctx;
475 if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
478 ctx = kzalloc(sizeof(*ctx), flags);
483 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
484 if (type == XHCI_CTX_TYPE_INPUT)
485 ctx->size += CTX_SIZE(xhci->hcc_params);
487 ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma);
495 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
496 struct xhci_container_ctx *ctx)
500 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
504 struct xhci_input_control_ctx *xhci_get_input_control_ctx(
505 struct xhci_container_ctx *ctx)
507 if (ctx->type != XHCI_CTX_TYPE_INPUT)
510 return (struct xhci_input_control_ctx *)ctx->bytes;
513 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
514 struct xhci_container_ctx *ctx)
516 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
517 return (struct xhci_slot_ctx *)ctx->bytes;
519 return (struct xhci_slot_ctx *)
520 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
523 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
524 struct xhci_container_ctx *ctx,
525 unsigned int ep_index)
527 /* increment ep index by offset of start of ep ctx array */
529 if (ctx->type == XHCI_CTX_TYPE_INPUT)
532 return (struct xhci_ep_ctx *)
533 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
537 /***************** Streams structures manipulation *************************/
539 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
540 unsigned int num_stream_ctxs,
541 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
543 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
544 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
546 if (size > MEDIUM_STREAM_ARRAY_SIZE)
547 dma_free_coherent(dev, size,
549 else if (size <= SMALL_STREAM_ARRAY_SIZE)
550 return dma_pool_free(xhci->small_streams_pool,
553 return dma_pool_free(xhci->medium_streams_pool,
558 * The stream context array for each endpoint with bulk streams enabled can
559 * vary in size, based on:
560 * - how many streams the endpoint supports,
561 * - the maximum primary stream array size the host controller supports,
562 * - and how many streams the device driver asks for.
564 * The stream context array must be a power of 2, and can be as small as
565 * 64 bytes or as large as 1MB.
567 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
568 unsigned int num_stream_ctxs, dma_addr_t *dma,
571 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
572 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
574 if (size > MEDIUM_STREAM_ARRAY_SIZE)
575 return dma_alloc_coherent(dev, size,
577 else if (size <= SMALL_STREAM_ARRAY_SIZE)
578 return dma_pool_alloc(xhci->small_streams_pool,
581 return dma_pool_alloc(xhci->medium_streams_pool,
585 struct xhci_ring *xhci_dma_to_transfer_ring(
586 struct xhci_virt_ep *ep,
589 if (ep->ep_state & EP_HAS_STREAMS)
590 return radix_tree_lookup(&ep->stream_info->trb_address_map,
591 address >> TRB_SEGMENT_SHIFT);
595 struct xhci_ring *xhci_stream_id_to_ring(
596 struct xhci_virt_device *dev,
597 unsigned int ep_index,
598 unsigned int stream_id)
600 struct xhci_virt_ep *ep = &dev->eps[ep_index];
604 if (!ep->stream_info)
607 if (stream_id >= ep->stream_info->num_streams)
609 return ep->stream_info->stream_rings[stream_id];
613 * Change an endpoint's internal structure so it supports stream IDs. The
614 * number of requested streams includes stream 0, which cannot be used by device
617 * The number of stream contexts in the stream context array may be bigger than
618 * the number of streams the driver wants to use. This is because the number of
619 * stream context array entries must be a power of two.
621 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
622 unsigned int num_stream_ctxs,
623 unsigned int num_streams,
624 unsigned int max_packet, gfp_t mem_flags)
626 struct xhci_stream_info *stream_info;
628 struct xhci_ring *cur_ring;
632 xhci_dbg(xhci, "Allocating %u streams and %u "
633 "stream context array entries.\n",
634 num_streams, num_stream_ctxs);
635 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
636 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
639 xhci->cmd_ring_reserved_trbs++;
641 stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
645 stream_info->num_streams = num_streams;
646 stream_info->num_stream_ctxs = num_stream_ctxs;
648 /* Initialize the array of virtual pointers to stream rings. */
649 stream_info->stream_rings = kzalloc(
650 sizeof(struct xhci_ring *)*num_streams,
652 if (!stream_info->stream_rings)
655 /* Initialize the array of DMA addresses for stream rings for the HW. */
656 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
657 num_stream_ctxs, &stream_info->ctx_array_dma,
659 if (!stream_info->stream_ctx_array)
661 memset(stream_info->stream_ctx_array, 0,
662 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
664 /* Allocate everything needed to free the stream rings later */
665 stream_info->free_streams_command =
666 xhci_alloc_command(xhci, true, true, mem_flags);
667 if (!stream_info->free_streams_command)
670 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
672 /* Allocate rings for all the streams that the driver will use,
673 * and add their segment DMA addresses to the radix tree.
674 * Stream 0 is reserved.
677 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
678 stream_info->stream_rings[cur_stream] =
679 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet,
681 cur_ring = stream_info->stream_rings[cur_stream];
684 cur_ring->stream_id = cur_stream;
685 cur_ring->trb_address_map = &stream_info->trb_address_map;
686 /* Set deq ptr, cycle bit, and stream context type */
687 addr = cur_ring->first_seg->dma |
688 SCT_FOR_CTX(SCT_PRI_TR) |
689 cur_ring->cycle_state;
690 stream_info->stream_ctx_array[cur_stream].stream_ring =
692 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
693 cur_stream, (unsigned long long) addr);
695 ret = xhci_update_stream_mapping(cur_ring, mem_flags);
697 xhci_ring_free(xhci, cur_ring);
698 stream_info->stream_rings[cur_stream] = NULL;
702 /* Leave the other unused stream ring pointers in the stream context
703 * array initialized to zero. This will cause the xHC to give us an
704 * error if the device asks for a stream ID we don't have setup (if it
705 * was any other way, the host controller would assume the ring is
706 * "empty" and wait forever for data to be queued to that stream ID).
712 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
713 cur_ring = stream_info->stream_rings[cur_stream];
715 xhci_ring_free(xhci, cur_ring);
716 stream_info->stream_rings[cur_stream] = NULL;
719 xhci_free_command(xhci, stream_info->free_streams_command);
721 kfree(stream_info->stream_rings);
725 xhci->cmd_ring_reserved_trbs--;
729 * Sets the MaxPStreams field and the Linear Stream Array field.
730 * Sets the dequeue pointer to the stream context array.
732 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
733 struct xhci_ep_ctx *ep_ctx,
734 struct xhci_stream_info *stream_info)
736 u32 max_primary_streams;
737 /* MaxPStreams is the number of stream context array entries, not the
738 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
739 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
741 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
742 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
743 "Setting number of stream ctx array entries to %u",
744 1 << (max_primary_streams + 1));
745 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
746 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
748 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
752 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
753 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
754 * not at the beginning of the ring).
756 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
757 struct xhci_virt_ep *ep)
760 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
761 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
762 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
765 /* Frees all stream contexts associated with the endpoint,
767 * Caller should fix the endpoint context streams fields.
769 void xhci_free_stream_info(struct xhci_hcd *xhci,
770 struct xhci_stream_info *stream_info)
773 struct xhci_ring *cur_ring;
778 for (cur_stream = 1; cur_stream < stream_info->num_streams;
780 cur_ring = stream_info->stream_rings[cur_stream];
782 xhci_ring_free(xhci, cur_ring);
783 stream_info->stream_rings[cur_stream] = NULL;
786 xhci_free_command(xhci, stream_info->free_streams_command);
787 xhci->cmd_ring_reserved_trbs--;
788 if (stream_info->stream_ctx_array)
789 xhci_free_stream_ctx(xhci,
790 stream_info->num_stream_ctxs,
791 stream_info->stream_ctx_array,
792 stream_info->ctx_array_dma);
794 kfree(stream_info->stream_rings);
799 /***************** Device context manipulation *************************/
801 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
802 struct xhci_virt_ep *ep)
804 setup_timer(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog,
809 static void xhci_free_tt_info(struct xhci_hcd *xhci,
810 struct xhci_virt_device *virt_dev,
813 struct list_head *tt_list_head;
814 struct xhci_tt_bw_info *tt_info, *next;
815 bool slot_found = false;
817 /* If the device never made it past the Set Address stage,
818 * it may not have the real_port set correctly.
820 if (virt_dev->real_port == 0 ||
821 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
822 xhci_dbg(xhci, "Bad real port.\n");
826 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
827 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
828 /* Multi-TT hubs will have more than one entry */
829 if (tt_info->slot_id == slot_id) {
831 list_del(&tt_info->tt_list);
833 } else if (slot_found) {
839 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
840 struct xhci_virt_device *virt_dev,
841 struct usb_device *hdev,
842 struct usb_tt *tt, gfp_t mem_flags)
844 struct xhci_tt_bw_info *tt_info;
845 unsigned int num_ports;
851 num_ports = hdev->maxchild;
853 for (i = 0; i < num_ports; i++, tt_info++) {
854 struct xhci_interval_bw_table *bw_table;
856 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
859 INIT_LIST_HEAD(&tt_info->tt_list);
860 list_add(&tt_info->tt_list,
861 &xhci->rh_bw[virt_dev->real_port - 1].tts);
862 tt_info->slot_id = virt_dev->udev->slot_id;
864 tt_info->ttport = i+1;
865 bw_table = &tt_info->bw_table;
866 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
867 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
872 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
877 /* All the xhci_tds in the ring's TD list should be freed at this point.
878 * Should be called with xhci->lock held if there is any chance the TT lists
879 * will be manipulated by the configure endpoint, allocate device, or update
880 * hub functions while this function is removing the TT entries from the list.
882 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
884 struct xhci_virt_device *dev;
886 int old_active_eps = 0;
888 /* Slot ID 0 is reserved */
889 if (slot_id == 0 || !xhci->devs[slot_id])
892 dev = xhci->devs[slot_id];
894 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
898 trace_xhci_free_virt_device(dev);
901 old_active_eps = dev->tt_info->active_eps;
903 for (i = 0; i < 31; i++) {
904 if (dev->eps[i].ring)
905 xhci_ring_free(xhci, dev->eps[i].ring);
906 if (dev->eps[i].stream_info)
907 xhci_free_stream_info(xhci,
908 dev->eps[i].stream_info);
909 /* Endpoints on the TT/root port lists should have been removed
910 * when usb_disable_device() was called for the device.
911 * We can't drop them anyway, because the udev might have gone
912 * away by this point, and we can't tell what speed it was.
914 if (!list_empty(&dev->eps[i].bw_endpoint_list))
915 xhci_warn(xhci, "Slot %u endpoint %u "
916 "not removed from BW list!\n",
919 /* If this is a hub, free the TT(s) from the TT list */
920 xhci_free_tt_info(xhci, dev, slot_id);
921 /* If necessary, update the number of active TTs on this root port */
922 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
925 xhci_free_container_ctx(xhci, dev->in_ctx);
927 xhci_free_container_ctx(xhci, dev->out_ctx);
929 if (dev->udev && dev->udev->slot_id)
930 dev->udev->slot_id = 0;
931 kfree(xhci->devs[slot_id]);
932 xhci->devs[slot_id] = NULL;
936 * Free a virt_device structure.
937 * If the virt_device added a tt_info (a hub) and has children pointing to
938 * that tt_info, then free the child first. Recursive.
939 * We can't rely on udev at this point to find child-parent relationships.
941 void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
943 struct xhci_virt_device *vdev;
944 struct list_head *tt_list_head;
945 struct xhci_tt_bw_info *tt_info, *next;
948 vdev = xhci->devs[slot_id];
952 if (vdev->real_port == 0 ||
953 vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
954 xhci_dbg(xhci, "Bad vdev->real_port.\n");
958 tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts);
959 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
960 /* is this a hub device that added a tt_info to the tts list */
961 if (tt_info->slot_id == slot_id) {
962 /* are any devices using this tt_info? */
963 for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
964 vdev = xhci->devs[i];
965 if (vdev && (vdev->tt_info == tt_info))
966 xhci_free_virt_devices_depth_first(
972 /* we are now at a leaf device */
973 xhci_free_virt_device(xhci, slot_id);
976 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
977 struct usb_device *udev, gfp_t flags)
979 struct xhci_virt_device *dev;
982 /* Slot ID 0 is reserved */
983 if (slot_id == 0 || xhci->devs[slot_id]) {
984 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
988 dev = kzalloc(sizeof(*dev), flags);
992 /* Allocate the (output) device context that will be used in the HC. */
993 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
997 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
998 (unsigned long long)dev->out_ctx->dma);
1000 /* Allocate the (input) device context for address device command */
1001 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
1005 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
1006 (unsigned long long)dev->in_ctx->dma);
1008 /* Initialize the cancellation list and watchdog timers for each ep */
1009 for (i = 0; i < 31; i++) {
1010 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
1011 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1012 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1015 /* Allocate endpoint 0 ring */
1016 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags);
1017 if (!dev->eps[0].ring)
1022 /* Point to output device context in dcbaa. */
1023 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1024 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1026 &xhci->dcbaa->dev_context_ptrs[slot_id],
1027 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1029 trace_xhci_alloc_virt_device(dev);
1031 xhci->devs[slot_id] = dev;
1037 xhci_free_container_ctx(xhci, dev->in_ctx);
1039 xhci_free_container_ctx(xhci, dev->out_ctx);
1045 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1046 struct usb_device *udev)
1048 struct xhci_virt_device *virt_dev;
1049 struct xhci_ep_ctx *ep0_ctx;
1050 struct xhci_ring *ep_ring;
1052 virt_dev = xhci->devs[udev->slot_id];
1053 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1054 ep_ring = virt_dev->eps[0].ring;
1056 * FIXME we don't keep track of the dequeue pointer very well after a
1057 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1058 * host to our enqueue pointer. This should only be called after a
1059 * configured device has reset, so all control transfers should have
1060 * been completed or cancelled before the reset.
1062 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1064 | ep_ring->cycle_state);
1068 * The xHCI roothub may have ports of differing speeds in any order in the port
1069 * status registers. xhci->port_array provides an array of the port speed for
1070 * each offset into the port status registers.
1072 * The xHCI hardware wants to know the roothub port number that the USB device
1073 * is attached to (or the roothub port its ancestor hub is attached to). All we
1074 * know is the index of that port under either the USB 2.0 or the USB 3.0
1075 * roothub, but that doesn't give us the real index into the HW port status
1076 * registers. Call xhci_find_raw_port_number() to get real index.
1078 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1079 struct usb_device *udev)
1081 struct usb_device *top_dev;
1082 struct usb_hcd *hcd;
1084 if (udev->speed >= USB_SPEED_SUPER)
1085 hcd = xhci->shared_hcd;
1087 hcd = xhci->main_hcd;
1089 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1090 top_dev = top_dev->parent)
1091 /* Found device below root hub */;
1093 return xhci_find_raw_port_number(hcd, top_dev->portnum);
1096 /* Setup an xHCI virtual device for a Set Address command */
1097 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1099 struct xhci_virt_device *dev;
1100 struct xhci_ep_ctx *ep0_ctx;
1101 struct xhci_slot_ctx *slot_ctx;
1104 struct usb_device *top_dev;
1106 dev = xhci->devs[udev->slot_id];
1107 /* Slot ID 0 is reserved */
1108 if (udev->slot_id == 0 || !dev) {
1109 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1113 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1114 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1116 /* 3) Only the control endpoint is valid - one endpoint context */
1117 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1118 switch (udev->speed) {
1119 case USB_SPEED_SUPER_PLUS:
1120 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1121 max_packets = MAX_PACKET(512);
1123 case USB_SPEED_SUPER:
1124 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1125 max_packets = MAX_PACKET(512);
1127 case USB_SPEED_HIGH:
1128 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1129 max_packets = MAX_PACKET(64);
1131 /* USB core guesses at a 64-byte max packet first for FS devices */
1132 case USB_SPEED_FULL:
1133 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1134 max_packets = MAX_PACKET(64);
1137 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1138 max_packets = MAX_PACKET(8);
1140 case USB_SPEED_WIRELESS:
1141 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1145 /* Speed was set earlier, this shouldn't happen. */
1148 /* Find the root hub port this device is under */
1149 port_num = xhci_find_real_port_number(xhci, udev);
1152 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1153 /* Set the port number in the virtual_device to the faked port number */
1154 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1155 top_dev = top_dev->parent)
1156 /* Found device below root hub */;
1157 dev->fake_port = top_dev->portnum;
1158 dev->real_port = port_num;
1159 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1160 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1162 /* Find the right bandwidth table that this device will be a part of.
1163 * If this is a full speed device attached directly to a root port (or a
1164 * decendent of one), it counts as a primary bandwidth domain, not a
1165 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1166 * will never be created for the HS root hub.
1168 if (!udev->tt || !udev->tt->hub->parent) {
1169 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1171 struct xhci_root_port_bw_info *rh_bw;
1172 struct xhci_tt_bw_info *tt_bw;
1174 rh_bw = &xhci->rh_bw[port_num - 1];
1175 /* Find the right TT. */
1176 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1177 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1180 if (!dev->udev->tt->multi ||
1182 tt_bw->ttport == dev->udev->ttport)) {
1183 dev->bw_table = &tt_bw->bw_table;
1184 dev->tt_info = tt_bw;
1189 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1192 /* Is this a LS/FS device under an external HS hub? */
1193 if (udev->tt && udev->tt->hub->parent) {
1194 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1195 (udev->ttport << 8));
1196 if (udev->tt->multi)
1197 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1199 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1200 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1202 /* Step 4 - ring already allocated */
1204 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1206 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1207 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1210 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1211 dev->eps[0].ring->cycle_state);
1213 trace_xhci_setup_addressable_virt_device(dev);
1215 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1221 * Convert interval expressed as 2^(bInterval - 1) == interval into
1222 * straight exponent value 2^n == interval.
1225 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1226 struct usb_host_endpoint *ep)
1228 unsigned int interval;
1230 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1231 if (interval != ep->desc.bInterval - 1)
1232 dev_warn(&udev->dev,
1233 "ep %#x - rounding interval to %d %sframes\n",
1234 ep->desc.bEndpointAddress,
1236 udev->speed == USB_SPEED_FULL ? "" : "micro");
1238 if (udev->speed == USB_SPEED_FULL) {
1240 * Full speed isoc endpoints specify interval in frames,
1241 * not microframes. We are using microframes everywhere,
1242 * so adjust accordingly.
1244 interval += 3; /* 1 frame = 2^3 uframes */
1251 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1252 * microframes, rounded down to nearest power of 2.
1254 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1255 struct usb_host_endpoint *ep, unsigned int desc_interval,
1256 unsigned int min_exponent, unsigned int max_exponent)
1258 unsigned int interval;
1260 interval = fls(desc_interval) - 1;
1261 interval = clamp_val(interval, min_exponent, max_exponent);
1262 if ((1 << interval) != desc_interval)
1264 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1265 ep->desc.bEndpointAddress,
1272 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1273 struct usb_host_endpoint *ep)
1275 if (ep->desc.bInterval == 0)
1277 return xhci_microframes_to_exponent(udev, ep,
1278 ep->desc.bInterval, 0, 15);
1282 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1283 struct usb_host_endpoint *ep)
1285 return xhci_microframes_to_exponent(udev, ep,
1286 ep->desc.bInterval * 8, 3, 10);
1289 /* Return the polling or NAK interval.
1291 * The polling interval is expressed in "microframes". If xHCI's Interval field
1292 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1294 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1297 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1298 struct usb_host_endpoint *ep)
1300 unsigned int interval = 0;
1302 switch (udev->speed) {
1303 case USB_SPEED_HIGH:
1305 if (usb_endpoint_xfer_control(&ep->desc) ||
1306 usb_endpoint_xfer_bulk(&ep->desc)) {
1307 interval = xhci_parse_microframe_interval(udev, ep);
1310 /* Fall through - SS and HS isoc/int have same decoding */
1312 case USB_SPEED_SUPER_PLUS:
1313 case USB_SPEED_SUPER:
1314 if (usb_endpoint_xfer_int(&ep->desc) ||
1315 usb_endpoint_xfer_isoc(&ep->desc)) {
1316 interval = xhci_parse_exponent_interval(udev, ep);
1320 case USB_SPEED_FULL:
1321 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1322 interval = xhci_parse_exponent_interval(udev, ep);
1326 * Fall through for interrupt endpoint interval decoding
1327 * since it uses the same rules as low speed interrupt
1332 if (usb_endpoint_xfer_int(&ep->desc) ||
1333 usb_endpoint_xfer_isoc(&ep->desc)) {
1335 interval = xhci_parse_frame_interval(udev, ep);
1345 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1346 * High speed endpoint descriptors can define "the number of additional
1347 * transaction opportunities per microframe", but that goes in the Max Burst
1348 * endpoint context field.
1350 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1351 struct usb_host_endpoint *ep)
1353 if (udev->speed < USB_SPEED_SUPER ||
1354 !usb_endpoint_xfer_isoc(&ep->desc))
1356 return ep->ss_ep_comp.bmAttributes;
1359 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1360 struct usb_host_endpoint *ep)
1362 /* Super speed and Plus have max burst in ep companion desc */
1363 if (udev->speed >= USB_SPEED_SUPER)
1364 return ep->ss_ep_comp.bMaxBurst;
1366 if (udev->speed == USB_SPEED_HIGH &&
1367 (usb_endpoint_xfer_isoc(&ep->desc) ||
1368 usb_endpoint_xfer_int(&ep->desc)))
1369 return usb_endpoint_maxp_mult(&ep->desc) - 1;
1374 static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1378 in = usb_endpoint_dir_in(&ep->desc);
1380 switch (usb_endpoint_type(&ep->desc)) {
1381 case USB_ENDPOINT_XFER_CONTROL:
1383 case USB_ENDPOINT_XFER_BULK:
1384 return in ? BULK_IN_EP : BULK_OUT_EP;
1385 case USB_ENDPOINT_XFER_ISOC:
1386 return in ? ISOC_IN_EP : ISOC_OUT_EP;
1387 case USB_ENDPOINT_XFER_INT:
1388 return in ? INT_IN_EP : INT_OUT_EP;
1393 /* Return the maximum endpoint service interval time (ESIT) payload.
1394 * Basically, this is the maxpacket size, multiplied by the burst size
1397 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
1398 struct usb_host_endpoint *ep)
1403 /* Only applies for interrupt or isochronous endpoints */
1404 if (usb_endpoint_xfer_control(&ep->desc) ||
1405 usb_endpoint_xfer_bulk(&ep->desc))
1408 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1409 if ((udev->speed >= USB_SPEED_SUPER_PLUS) &&
1410 USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes))
1411 return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval);
1412 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1413 else if (udev->speed >= USB_SPEED_SUPER)
1414 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1416 max_packet = usb_endpoint_maxp(&ep->desc);
1417 max_burst = usb_endpoint_maxp_mult(&ep->desc);
1418 /* A 0 in max burst means 1 transfer per ESIT */
1419 return max_packet * max_burst;
1422 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1423 * Drivers will have to call usb_alloc_streams() to do that.
1425 int xhci_endpoint_init(struct xhci_hcd *xhci,
1426 struct xhci_virt_device *virt_dev,
1427 struct usb_device *udev,
1428 struct usb_host_endpoint *ep,
1431 unsigned int ep_index;
1432 struct xhci_ep_ctx *ep_ctx;
1433 struct xhci_ring *ep_ring;
1434 unsigned int max_packet;
1435 enum xhci_ring_type ring_type;
1436 u32 max_esit_payload;
1438 unsigned int max_burst;
1439 unsigned int interval;
1441 unsigned int avg_trb_len;
1442 unsigned int err_count = 0;
1444 ep_index = xhci_get_endpoint_index(&ep->desc);
1445 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1447 endpoint_type = xhci_get_endpoint_type(ep);
1451 ring_type = usb_endpoint_type(&ep->desc);
1454 * Get values to fill the endpoint context, mostly from ep descriptor.
1455 * The average TRB buffer lengt for bulk endpoints is unclear as we
1456 * have no clue on scatter gather list entry size. For Isoc and Int,
1457 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1459 max_esit_payload = xhci_get_max_esit_payload(udev, ep);
1460 interval = xhci_get_endpoint_interval(udev, ep);
1462 /* Periodic endpoint bInterval limit quirk */
1463 if (usb_endpoint_xfer_int(&ep->desc) ||
1464 usb_endpoint_xfer_isoc(&ep->desc)) {
1465 if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
1466 udev->speed >= USB_SPEED_HIGH &&
1472 mult = xhci_get_endpoint_mult(udev, ep);
1473 max_packet = usb_endpoint_maxp(&ep->desc);
1474 max_burst = xhci_get_endpoint_max_burst(udev, ep);
1475 avg_trb_len = max_esit_payload;
1477 /* FIXME dig Mult and streams info out of ep companion desc */
1479 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1480 if (!usb_endpoint_xfer_isoc(&ep->desc))
1482 /* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */
1483 if (usb_endpoint_xfer_bulk(&ep->desc)) {
1484 if (udev->speed == USB_SPEED_HIGH)
1486 if (udev->speed == USB_SPEED_FULL) {
1487 max_packet = rounddown_pow_of_two(max_packet);
1488 max_packet = clamp_val(max_packet, 8, 64);
1491 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1492 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
1494 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1495 if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2))
1498 /* Set up the endpoint ring */
1499 virt_dev->eps[ep_index].new_ring =
1500 xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags);
1501 if (!virt_dev->eps[ep_index].new_ring)
1504 virt_dev->eps[ep_index].skip = false;
1505 ep_ring = virt_dev->eps[ep_index].new_ring;
1507 /* Fill the endpoint context */
1508 ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
1509 EP_INTERVAL(interval) |
1511 ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1512 MAX_PACKET(max_packet) |
1513 MAX_BURST(max_burst) |
1514 ERROR_COUNT(err_count));
1515 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1516 ep_ring->cycle_state);
1518 ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1519 EP_AVG_TRB_LENGTH(avg_trb_len));
1521 /* FIXME Debug endpoint context */
1525 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1526 struct xhci_virt_device *virt_dev,
1527 struct usb_host_endpoint *ep)
1529 unsigned int ep_index;
1530 struct xhci_ep_ctx *ep_ctx;
1532 ep_index = xhci_get_endpoint_index(&ep->desc);
1533 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1535 ep_ctx->ep_info = 0;
1536 ep_ctx->ep_info2 = 0;
1538 ep_ctx->tx_info = 0;
1539 /* Don't free the endpoint ring until the set interface or configuration
1544 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1546 bw_info->ep_interval = 0;
1548 bw_info->num_packets = 0;
1549 bw_info->max_packet_size = 0;
1551 bw_info->max_esit_payload = 0;
1554 void xhci_update_bw_info(struct xhci_hcd *xhci,
1555 struct xhci_container_ctx *in_ctx,
1556 struct xhci_input_control_ctx *ctrl_ctx,
1557 struct xhci_virt_device *virt_dev)
1559 struct xhci_bw_info *bw_info;
1560 struct xhci_ep_ctx *ep_ctx;
1561 unsigned int ep_type;
1564 for (i = 1; i < 31; i++) {
1565 bw_info = &virt_dev->eps[i].bw_info;
1567 /* We can't tell what endpoint type is being dropped, but
1568 * unconditionally clearing the bandwidth info for non-periodic
1569 * endpoints should be harmless because the info will never be
1570 * set in the first place.
1572 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1573 /* Dropped endpoint */
1574 xhci_clear_endpoint_bw_info(bw_info);
1578 if (EP_IS_ADDED(ctrl_ctx, i)) {
1579 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1580 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1582 /* Ignore non-periodic endpoints */
1583 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1584 ep_type != ISOC_IN_EP &&
1585 ep_type != INT_IN_EP)
1588 /* Added or changed endpoint */
1589 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1590 le32_to_cpu(ep_ctx->ep_info));
1591 /* Number of packets and mult are zero-based in the
1592 * input context, but we want one-based for the
1595 bw_info->mult = CTX_TO_EP_MULT(
1596 le32_to_cpu(ep_ctx->ep_info)) + 1;
1597 bw_info->num_packets = CTX_TO_MAX_BURST(
1598 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1599 bw_info->max_packet_size = MAX_PACKET_DECODED(
1600 le32_to_cpu(ep_ctx->ep_info2));
1601 bw_info->type = ep_type;
1602 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1603 le32_to_cpu(ep_ctx->tx_info));
1608 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1609 * Useful when you want to change one particular aspect of the endpoint and then
1610 * issue a configure endpoint command.
1612 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1613 struct xhci_container_ctx *in_ctx,
1614 struct xhci_container_ctx *out_ctx,
1615 unsigned int ep_index)
1617 struct xhci_ep_ctx *out_ep_ctx;
1618 struct xhci_ep_ctx *in_ep_ctx;
1620 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1621 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1623 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1624 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1625 in_ep_ctx->deq = out_ep_ctx->deq;
1626 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1629 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1630 * Useful when you want to change one particular aspect of the endpoint and then
1631 * issue a configure endpoint command. Only the context entries field matters,
1632 * but we'll copy the whole thing anyway.
1634 void xhci_slot_copy(struct xhci_hcd *xhci,
1635 struct xhci_container_ctx *in_ctx,
1636 struct xhci_container_ctx *out_ctx)
1638 struct xhci_slot_ctx *in_slot_ctx;
1639 struct xhci_slot_ctx *out_slot_ctx;
1641 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1642 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1644 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1645 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1646 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1647 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1650 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1651 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1654 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1655 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1657 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1658 "Allocating %d scratchpad buffers", num_sp);
1663 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1664 if (!xhci->scratchpad)
1667 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1668 num_sp * sizeof(u64),
1669 &xhci->scratchpad->sp_dma, flags);
1670 if (!xhci->scratchpad->sp_array)
1673 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1674 if (!xhci->scratchpad->sp_buffers)
1677 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1678 for (i = 0; i < num_sp; i++) {
1680 void *buf = dma_zalloc_coherent(dev, xhci->page_size, &dma,
1685 xhci->scratchpad->sp_array[i] = dma;
1686 xhci->scratchpad->sp_buffers[i] = buf;
1692 for (i = i - 1; i >= 0; i--) {
1693 dma_free_coherent(dev, xhci->page_size,
1694 xhci->scratchpad->sp_buffers[i],
1695 xhci->scratchpad->sp_array[i]);
1698 kfree(xhci->scratchpad->sp_buffers);
1701 dma_free_coherent(dev, num_sp * sizeof(u64),
1702 xhci->scratchpad->sp_array,
1703 xhci->scratchpad->sp_dma);
1706 kfree(xhci->scratchpad);
1707 xhci->scratchpad = NULL;
1713 static void scratchpad_free(struct xhci_hcd *xhci)
1717 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1719 if (!xhci->scratchpad)
1722 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1724 for (i = 0; i < num_sp; i++) {
1725 dma_free_coherent(dev, xhci->page_size,
1726 xhci->scratchpad->sp_buffers[i],
1727 xhci->scratchpad->sp_array[i]);
1729 kfree(xhci->scratchpad->sp_buffers);
1730 dma_free_coherent(dev, num_sp * sizeof(u64),
1731 xhci->scratchpad->sp_array,
1732 xhci->scratchpad->sp_dma);
1733 kfree(xhci->scratchpad);
1734 xhci->scratchpad = NULL;
1737 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1738 bool allocate_in_ctx, bool allocate_completion,
1741 struct xhci_command *command;
1743 command = kzalloc(sizeof(*command), mem_flags);
1747 if (allocate_in_ctx) {
1749 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1751 if (!command->in_ctx) {
1757 if (allocate_completion) {
1758 command->completion =
1759 kzalloc(sizeof(struct completion), mem_flags);
1760 if (!command->completion) {
1761 xhci_free_container_ctx(xhci, command->in_ctx);
1765 init_completion(command->completion);
1768 command->status = 0;
1769 INIT_LIST_HEAD(&command->cmd_list);
1773 void xhci_urb_free_priv(struct urb_priv *urb_priv)
1778 void xhci_free_command(struct xhci_hcd *xhci,
1779 struct xhci_command *command)
1781 xhci_free_container_ctx(xhci,
1783 kfree(command->completion);
1787 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1789 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1791 int i, j, num_ports;
1793 cancel_delayed_work_sync(&xhci->cmd_timer);
1795 /* Free the Event Ring Segment Table and the actual Event Ring */
1796 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1797 if (xhci->erst.entries)
1798 dma_free_coherent(dev, size,
1799 xhci->erst.entries, xhci->erst.erst_dma_addr);
1800 xhci->erst.entries = NULL;
1801 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed ERST");
1802 if (xhci->event_ring)
1803 xhci_ring_free(xhci, xhci->event_ring);
1804 xhci->event_ring = NULL;
1805 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring");
1807 if (xhci->lpm_command)
1808 xhci_free_command(xhci, xhci->lpm_command);
1809 xhci->lpm_command = NULL;
1811 xhci_ring_free(xhci, xhci->cmd_ring);
1812 xhci->cmd_ring = NULL;
1813 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1814 xhci_cleanup_command_queue(xhci);
1816 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1817 for (i = 0; i < num_ports && xhci->rh_bw; i++) {
1818 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1819 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1820 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1821 while (!list_empty(ep))
1822 list_del_init(ep->next);
1826 for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--)
1827 xhci_free_virt_devices_depth_first(xhci, i);
1829 dma_pool_destroy(xhci->segment_pool);
1830 xhci->segment_pool = NULL;
1831 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1833 dma_pool_destroy(xhci->device_pool);
1834 xhci->device_pool = NULL;
1835 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1837 dma_pool_destroy(xhci->small_streams_pool);
1838 xhci->small_streams_pool = NULL;
1839 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1840 "Freed small stream array pool");
1842 dma_pool_destroy(xhci->medium_streams_pool);
1843 xhci->medium_streams_pool = NULL;
1844 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1845 "Freed medium stream array pool");
1848 dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1849 xhci->dcbaa, xhci->dcbaa->dma);
1852 scratchpad_free(xhci);
1857 for (i = 0; i < num_ports; i++) {
1858 struct xhci_tt_bw_info *tt, *n;
1859 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1860 list_del(&tt->tt_list);
1866 xhci->cmd_ring_reserved_trbs = 0;
1867 xhci->num_usb2_ports = 0;
1868 xhci->num_usb3_ports = 0;
1869 xhci->num_active_eps = 0;
1870 kfree(xhci->usb2_ports);
1871 kfree(xhci->usb3_ports);
1872 kfree(xhci->port_array);
1874 kfree(xhci->ext_caps);
1875 kfree(xhci->usb2_rhub.psi);
1876 kfree(xhci->usb3_rhub.psi);
1878 xhci->usb2_ports = NULL;
1879 xhci->usb3_ports = NULL;
1880 xhci->port_array = NULL;
1881 xhci->usb2_rhub.psi = NULL;
1882 xhci->usb3_rhub.psi = NULL;
1884 xhci->ext_caps = NULL;
1886 xhci->page_size = 0;
1887 xhci->page_shift = 0;
1888 xhci->bus_state[0].bus_suspended = 0;
1889 xhci->bus_state[1].bus_suspended = 0;
1892 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1893 struct xhci_segment *input_seg,
1894 union xhci_trb *start_trb,
1895 union xhci_trb *end_trb,
1896 dma_addr_t input_dma,
1897 struct xhci_segment *result_seg,
1898 char *test_name, int test_number)
1900 unsigned long long start_dma;
1901 unsigned long long end_dma;
1902 struct xhci_segment *seg;
1904 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1905 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1907 seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false);
1908 if (seg != result_seg) {
1909 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1910 test_name, test_number);
1911 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1912 "input DMA 0x%llx\n",
1914 (unsigned long long) input_dma);
1915 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1916 "ending TRB %p (0x%llx DMA)\n",
1917 start_trb, start_dma,
1919 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1921 trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma,
1928 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1929 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci)
1932 dma_addr_t input_dma;
1933 struct xhci_segment *result_seg;
1934 } simple_test_vector [] = {
1935 /* A zeroed DMA field should fail */
1937 /* One TRB before the ring start should fail */
1938 { xhci->event_ring->first_seg->dma - 16, NULL },
1939 /* One byte before the ring start should fail */
1940 { xhci->event_ring->first_seg->dma - 1, NULL },
1941 /* Starting TRB should succeed */
1942 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1943 /* Ending TRB should succeed */
1944 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1945 xhci->event_ring->first_seg },
1946 /* One byte after the ring end should fail */
1947 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1948 /* One TRB after the ring end should fail */
1949 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1950 /* An address of all ones should fail */
1951 { (dma_addr_t) (~0), NULL },
1954 struct xhci_segment *input_seg;
1955 union xhci_trb *start_trb;
1956 union xhci_trb *end_trb;
1957 dma_addr_t input_dma;
1958 struct xhci_segment *result_seg;
1959 } complex_test_vector [] = {
1960 /* Test feeding a valid DMA address from a different ring */
1961 { .input_seg = xhci->event_ring->first_seg,
1962 .start_trb = xhci->event_ring->first_seg->trbs,
1963 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1964 .input_dma = xhci->cmd_ring->first_seg->dma,
1967 /* Test feeding a valid end TRB from a different ring */
1968 { .input_seg = xhci->event_ring->first_seg,
1969 .start_trb = xhci->event_ring->first_seg->trbs,
1970 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1971 .input_dma = xhci->cmd_ring->first_seg->dma,
1974 /* Test feeding a valid start and end TRB from a different ring */
1975 { .input_seg = xhci->event_ring->first_seg,
1976 .start_trb = xhci->cmd_ring->first_seg->trbs,
1977 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1978 .input_dma = xhci->cmd_ring->first_seg->dma,
1981 /* TRB in this ring, but after this TD */
1982 { .input_seg = xhci->event_ring->first_seg,
1983 .start_trb = &xhci->event_ring->first_seg->trbs[0],
1984 .end_trb = &xhci->event_ring->first_seg->trbs[3],
1985 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1988 /* TRB in this ring, but before this TD */
1989 { .input_seg = xhci->event_ring->first_seg,
1990 .start_trb = &xhci->event_ring->first_seg->trbs[3],
1991 .end_trb = &xhci->event_ring->first_seg->trbs[6],
1992 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1995 /* TRB in this ring, but after this wrapped TD */
1996 { .input_seg = xhci->event_ring->first_seg,
1997 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1998 .end_trb = &xhci->event_ring->first_seg->trbs[1],
1999 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2002 /* TRB in this ring, but before this wrapped TD */
2003 { .input_seg = xhci->event_ring->first_seg,
2004 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2005 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2006 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
2009 /* TRB not in this ring, and we have a wrapped TD */
2010 { .input_seg = xhci->event_ring->first_seg,
2011 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2012 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2013 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
2018 unsigned int num_tests;
2021 num_tests = ARRAY_SIZE(simple_test_vector);
2022 for (i = 0; i < num_tests; i++) {
2023 ret = xhci_test_trb_in_td(xhci,
2024 xhci->event_ring->first_seg,
2025 xhci->event_ring->first_seg->trbs,
2026 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2027 simple_test_vector[i].input_dma,
2028 simple_test_vector[i].result_seg,
2034 num_tests = ARRAY_SIZE(complex_test_vector);
2035 for (i = 0; i < num_tests; i++) {
2036 ret = xhci_test_trb_in_td(xhci,
2037 complex_test_vector[i].input_seg,
2038 complex_test_vector[i].start_trb,
2039 complex_test_vector[i].end_trb,
2040 complex_test_vector[i].input_dma,
2041 complex_test_vector[i].result_seg,
2046 xhci_dbg(xhci, "TRB math tests passed.\n");
2050 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2055 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2056 xhci->event_ring->dequeue);
2057 if (deq == 0 && !in_interrupt())
2058 xhci_warn(xhci, "WARN something wrong with SW event ring "
2060 /* Update HC event ring dequeue pointer */
2061 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2062 temp &= ERST_PTR_MASK;
2063 /* Don't clear the EHB bit (which is RW1C) because
2064 * there might be more events to service.
2067 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2068 "// Write event ring dequeue pointer, "
2069 "preserving EHB bit");
2070 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2071 &xhci->ir_set->erst_dequeue);
2074 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2075 __le32 __iomem *addr, int max_caps)
2077 u32 temp, port_offset, port_count;
2079 u8 major_revision, minor_revision;
2080 struct xhci_hub *rhub;
2083 major_revision = XHCI_EXT_PORT_MAJOR(temp);
2084 minor_revision = XHCI_EXT_PORT_MINOR(temp);
2086 if (major_revision == 0x03) {
2087 rhub = &xhci->usb3_rhub;
2089 * Some hosts incorrectly use sub-minor version for minor
2090 * version (i.e. 0x02 instead of 0x20 for bcdUSB 0x320 and 0x01
2091 * for bcdUSB 0x310). Since there is no USB release with sub
2092 * minor version 0x301 to 0x309, we can assume that they are
2093 * incorrect and fix it here.
2095 if (minor_revision > 0x00 && minor_revision < 0x10)
2096 minor_revision <<= 4;
2097 } else if (major_revision <= 0x02) {
2098 rhub = &xhci->usb2_rhub;
2100 xhci_warn(xhci, "Ignoring unknown port speed, "
2101 "Ext Cap %p, revision = 0x%x\n",
2102 addr, major_revision);
2103 /* Ignoring port protocol we can't understand. FIXME */
2106 rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
2108 if (rhub->min_rev < minor_revision)
2109 rhub->min_rev = minor_revision;
2111 /* Port offset and count in the third dword, see section 7.2 */
2112 temp = readl(addr + 2);
2113 port_offset = XHCI_EXT_PORT_OFF(temp);
2114 port_count = XHCI_EXT_PORT_COUNT(temp);
2115 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2116 "Ext Cap %p, port offset = %u, "
2117 "count = %u, revision = 0x%x",
2118 addr, port_offset, port_count, major_revision);
2119 /* Port count includes the current port offset */
2120 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2121 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2124 rhub->psi_count = XHCI_EXT_PORT_PSIC(temp);
2125 if (rhub->psi_count) {
2126 rhub->psi = kcalloc(rhub->psi_count, sizeof(*rhub->psi),
2129 rhub->psi_count = 0;
2131 rhub->psi_uid_count++;
2132 for (i = 0; i < rhub->psi_count; i++) {
2133 rhub->psi[i] = readl(addr + 4 + i);
2135 /* count unique ID values, two consecutive entries can
2136 * have the same ID if link is assymetric
2138 if (i && (XHCI_EXT_PORT_PSIV(rhub->psi[i]) !=
2139 XHCI_EXT_PORT_PSIV(rhub->psi[i - 1])))
2140 rhub->psi_uid_count++;
2142 xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2143 XHCI_EXT_PORT_PSIV(rhub->psi[i]),
2144 XHCI_EXT_PORT_PSIE(rhub->psi[i]),
2145 XHCI_EXT_PORT_PLT(rhub->psi[i]),
2146 XHCI_EXT_PORT_PFD(rhub->psi[i]),
2147 XHCI_EXT_PORT_LP(rhub->psi[i]),
2148 XHCI_EXT_PORT_PSIM(rhub->psi[i]));
2151 /* cache usb2 port capabilities */
2152 if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2153 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2155 /* Check the host's USB2 LPM capability */
2156 if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2157 (temp & XHCI_L1C)) {
2158 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2159 "xHCI 0.96: support USB2 software lpm");
2160 xhci->sw_lpm_support = 1;
2163 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2164 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2165 "xHCI 1.0: support USB2 software lpm");
2166 xhci->sw_lpm_support = 1;
2167 if (temp & XHCI_HLC) {
2168 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2169 "xHCI 1.0: support USB2 hardware lpm");
2170 xhci->hw_lpm_support = 1;
2175 for (i = port_offset; i < (port_offset + port_count); i++) {
2176 /* Duplicate entry. Ignore the port if the revisions differ. */
2177 if (xhci->port_array[i] != 0) {
2178 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2179 " port %u\n", addr, i);
2180 xhci_warn(xhci, "Port was marked as USB %u, "
2181 "duplicated as USB %u\n",
2182 xhci->port_array[i], major_revision);
2183 /* Only adjust the roothub port counts if we haven't
2184 * found a similar duplicate.
2186 if (xhci->port_array[i] != major_revision &&
2187 xhci->port_array[i] != DUPLICATE_ENTRY) {
2188 if (xhci->port_array[i] == 0x03)
2189 xhci->num_usb3_ports--;
2191 xhci->num_usb2_ports--;
2192 xhci->port_array[i] = DUPLICATE_ENTRY;
2194 /* FIXME: Should we disable the port? */
2197 xhci->port_array[i] = major_revision;
2198 if (major_revision == 0x03)
2199 xhci->num_usb3_ports++;
2201 xhci->num_usb2_ports++;
2203 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2207 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2208 * specify what speeds each port is supposed to be. We can't count on the port
2209 * speed bits in the PORTSC register being correct until a device is connected,
2210 * but we need to set up the two fake roothubs with the correct number of USB
2211 * 3.0 and USB 2.0 ports at host controller initialization time.
2213 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2217 unsigned int num_ports;
2218 int i, j, port_index;
2222 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2223 xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2224 if (!xhci->port_array)
2227 xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2230 for (i = 0; i < num_ports; i++) {
2231 struct xhci_interval_bw_table *bw_table;
2233 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2234 bw_table = &xhci->rh_bw[i].bw_table;
2235 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2236 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2238 base = &xhci->cap_regs->hc_capbase;
2240 cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL);
2242 xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2247 /* count extended protocol capability entries for later caching */
2250 offset = xhci_find_next_ext_cap(base, offset,
2251 XHCI_EXT_CAPS_PROTOCOL);
2254 xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags);
2255 if (!xhci->ext_caps)
2261 xhci_add_in_port(xhci, num_ports, base + offset, cap_count);
2262 if (xhci->num_usb2_ports + xhci->num_usb3_ports == num_ports)
2264 offset = xhci_find_next_ext_cap(base, offset,
2265 XHCI_EXT_CAPS_PROTOCOL);
2268 if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2269 xhci_warn(xhci, "No ports on the roothubs?\n");
2272 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2273 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2274 xhci->num_usb2_ports, xhci->num_usb3_ports);
2276 /* Place limits on the number of roothub ports so that the hub
2277 * descriptors aren't longer than the USB core will allocate.
2279 if (xhci->num_usb3_ports > USB_SS_MAXPORTS) {
2280 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2281 "Limiting USB 3.0 roothub ports to %u.",
2283 xhci->num_usb3_ports = USB_SS_MAXPORTS;
2285 if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2286 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2287 "Limiting USB 2.0 roothub ports to %u.",
2289 xhci->num_usb2_ports = USB_MAXCHILDREN;
2293 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2294 * Not sure how the USB core will handle a hub with no ports...
2296 if (xhci->num_usb2_ports) {
2297 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2298 xhci->num_usb2_ports, flags);
2299 if (!xhci->usb2_ports)
2303 for (i = 0; i < num_ports; i++) {
2304 if (xhci->port_array[i] == 0x03 ||
2305 xhci->port_array[i] == 0 ||
2306 xhci->port_array[i] == DUPLICATE_ENTRY)
2309 xhci->usb2_ports[port_index] =
2310 &xhci->op_regs->port_status_base +
2312 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2313 "USB 2.0 port at index %u, "
2315 xhci->usb2_ports[port_index]);
2317 if (port_index == xhci->num_usb2_ports)
2321 if (xhci->num_usb3_ports) {
2322 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2323 xhci->num_usb3_ports, flags);
2324 if (!xhci->usb3_ports)
2328 for (i = 0; i < num_ports; i++)
2329 if (xhci->port_array[i] == 0x03) {
2330 xhci->usb3_ports[port_index] =
2331 &xhci->op_regs->port_status_base +
2333 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2334 "USB 3.0 port at index %u, "
2336 xhci->usb3_ports[port_index]);
2338 if (port_index == xhci->num_usb3_ports)
2345 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2348 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2349 unsigned int val, val2;
2351 struct xhci_segment *seg;
2352 u32 page_size, temp;
2355 INIT_LIST_HEAD(&xhci->cmd_list);
2357 /* init command timeout work */
2358 INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout);
2359 init_completion(&xhci->cmd_ring_stop_completion);
2361 page_size = readl(&xhci->op_regs->page_size);
2362 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2363 "Supported page size register = 0x%x", page_size);
2364 for (i = 0; i < 16; i++) {
2365 if ((0x1 & page_size) != 0)
2367 page_size = page_size >> 1;
2370 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2371 "Supported page size of %iK", (1 << (i+12)) / 1024);
2373 xhci_warn(xhci, "WARN: no supported page size\n");
2374 /* Use 4K pages, since that's common and the minimum the HC supports */
2375 xhci->page_shift = 12;
2376 xhci->page_size = 1 << xhci->page_shift;
2377 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2378 "HCD page size set to %iK", xhci->page_size / 1024);
2381 * Program the Number of Device Slots Enabled field in the CONFIG
2382 * register with the max value of slots the HC can handle.
2384 val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2385 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2386 "// xHC can handle at most %d device slots.", val);
2387 val2 = readl(&xhci->op_regs->config_reg);
2388 val |= (val2 & ~HCS_SLOTS_MASK);
2389 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2390 "// Setting Max device slots reg = 0x%x.", val);
2391 writel(val, &xhci->op_regs->config_reg);
2394 * xHCI section 5.4.6 - doorbell array must be
2395 * "physically contiguous and 64-byte (cache line) aligned".
2397 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2401 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2402 xhci->dcbaa->dma = dma;
2403 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2404 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2405 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2406 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2409 * Initialize the ring segment pool. The ring must be a contiguous
2410 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2411 * however, the command ring segment needs 64-byte aligned segments
2412 * and our use of dma addresses in the trb_address_map radix tree needs
2413 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2415 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2416 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2418 /* See Table 46 and Note on Figure 55 */
2419 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2420 2112, 64, xhci->page_size);
2421 if (!xhci->segment_pool || !xhci->device_pool)
2424 /* Linear stream context arrays don't have any boundary restrictions,
2425 * and only need to be 16-byte aligned.
2427 xhci->small_streams_pool =
2428 dma_pool_create("xHCI 256 byte stream ctx arrays",
2429 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2430 xhci->medium_streams_pool =
2431 dma_pool_create("xHCI 1KB stream ctx arrays",
2432 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2433 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2434 * will be allocated with dma_alloc_coherent()
2437 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2440 /* Set up the command ring to have one segments for now. */
2441 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags);
2442 if (!xhci->cmd_ring)
2444 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2445 "Allocated command ring at %p", xhci->cmd_ring);
2446 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx",
2447 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2449 /* Set the address in the Command Ring Control register */
2450 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2451 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2452 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2453 xhci->cmd_ring->cycle_state;
2454 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2455 "// Setting command ring address to 0x%016llx", val_64);
2456 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2457 xhci_dbg_cmd_ptrs(xhci);
2459 xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2460 if (!xhci->lpm_command)
2463 /* Reserve one command ring TRB for disabling LPM.
2464 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2465 * disabling LPM, we only need to reserve one TRB for all devices.
2467 xhci->cmd_ring_reserved_trbs++;
2469 val = readl(&xhci->cap_regs->db_off);
2471 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2472 "// Doorbell array is located at offset 0x%x"
2473 " from cap regs base addr", val);
2474 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2475 xhci_dbg_regs(xhci);
2476 xhci_print_run_regs(xhci);
2477 /* Set ir_set to interrupt register set 0 */
2478 xhci->ir_set = &xhci->run_regs->ir_set[0];
2481 * Event ring setup: Allocate a normal ring, but also setup
2482 * the event ring segment table (ERST). Section 4.9.3.
2484 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring");
2485 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2487 if (!xhci->event_ring)
2489 if (xhci_check_trb_in_td_math(xhci) < 0)
2492 xhci->erst.entries = dma_alloc_coherent(dev,
2493 sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2495 if (!xhci->erst.entries)
2497 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2498 "// Allocated event ring segment table at 0x%llx",
2499 (unsigned long long)dma);
2501 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2502 xhci->erst.num_entries = ERST_NUM_SEGS;
2503 xhci->erst.erst_dma_addr = dma;
2504 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2505 "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx",
2506 xhci->erst.num_entries,
2508 (unsigned long long)xhci->erst.erst_dma_addr);
2510 /* set ring base address and size for each segment table entry */
2511 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2512 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2513 entry->seg_addr = cpu_to_le64(seg->dma);
2514 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2519 /* set ERST count with the number of entries in the segment table */
2520 val = readl(&xhci->ir_set->erst_size);
2521 val &= ERST_SIZE_MASK;
2522 val |= ERST_NUM_SEGS;
2523 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2524 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2526 writel(val, &xhci->ir_set->erst_size);
2528 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2529 "// Set ERST entries to point to event ring.");
2530 /* set the segment table base address */
2531 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2532 "// Set ERST base address for ir_set 0 = 0x%llx",
2533 (unsigned long long)xhci->erst.erst_dma_addr);
2534 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2535 val_64 &= ERST_PTR_MASK;
2536 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2537 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2539 /* Set the event ring dequeue address */
2540 xhci_set_hc_event_deq(xhci);
2541 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2542 "Wrote ERST address to ir_set 0.");
2543 xhci_print_ir_set(xhci, 0);
2546 * XXX: Might need to set the Interrupter Moderation Register to
2547 * something other than the default (~1ms minimum between interrupts).
2548 * See section 5.5.1.2.
2550 for (i = 0; i < MAX_HC_SLOTS; i++)
2551 xhci->devs[i] = NULL;
2552 for (i = 0; i < USB_MAXCHILDREN; i++) {
2553 xhci->bus_state[0].resume_done[i] = 0;
2554 xhci->bus_state[1].resume_done[i] = 0;
2555 /* Only the USB 2.0 completions will ever be used. */
2556 init_completion(&xhci->bus_state[1].rexit_done[i]);
2559 if (scratchpad_alloc(xhci, flags))
2561 if (xhci_setup_port_arrays(xhci, flags))
2564 /* Enable USB 3.0 device notifications for function remote wake, which
2565 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2566 * U3 (device suspend).
2568 temp = readl(&xhci->op_regs->dev_notification);
2569 temp &= ~DEV_NOTE_MASK;
2570 temp |= DEV_NOTE_FWAKE;
2571 writel(temp, &xhci->op_regs->dev_notification);
2578 xhci_mem_cleanup(xhci);