1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/usb.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/dmapool.h>
15 #include <linux/dma-mapping.h>
18 #include "xhci-trace.h"
19 #include "xhci-debugfs.h"
22 * Allocates a generic ring segment from the ring pool, sets the dma address,
23 * initializes the segment to zero, and sets the private next pointer to NULL.
26 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
28 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
29 unsigned int cycle_state,
30 unsigned int max_packet,
33 struct xhci_segment *seg;
36 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
38 seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev));
42 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma);
49 seg->bounce_buf = kzalloc_node(max_packet, flags,
51 if (!seg->bounce_buf) {
52 dma_pool_free(xhci->segment_pool, seg->trbs, dma);
57 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
58 if (cycle_state == 0) {
59 for (i = 0; i < TRBS_PER_SEGMENT; i++)
60 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
68 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
71 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
74 kfree(seg->bounce_buf);
78 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
79 struct xhci_segment *first)
81 struct xhci_segment *seg;
84 while (seg != first) {
85 struct xhci_segment *next = seg->next;
86 xhci_segment_free(xhci, seg);
89 xhci_segment_free(xhci, first);
93 * Make the prev segment point to the next segment.
95 * Change the last TRB in the prev segment to be a Link TRB which points to the
96 * DMA address of the next segment. The caller needs to set any Link TRB
97 * related flags, such as End TRB, Toggle Cycle, and no snoop.
99 static void xhci_link_segments(struct xhci_segment *prev,
100 struct xhci_segment *next,
101 enum xhci_ring_type type, bool chain_links)
108 if (type != TYPE_EVENT) {
109 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
110 cpu_to_le64(next->dma);
112 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
113 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
114 val &= ~TRB_TYPE_BITMASK;
115 val |= TRB_TYPE(TRB_LINK);
118 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
123 * Link the ring to the new segments.
124 * Set Toggle Cycle for the new ring if needed.
126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
127 struct xhci_segment *first, struct xhci_segment *last,
128 unsigned int num_segs)
130 struct xhci_segment *next;
133 if (!ring || !first || !last)
136 /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
137 chain_links = !!(xhci_link_trb_quirk(xhci) ||
138 (ring->type == TYPE_ISOC &&
139 (xhci->quirks & XHCI_AMD_0x96_HOST)));
141 next = ring->enq_seg->next;
142 xhci_link_segments(ring->enq_seg, first, ring->type, chain_links);
143 xhci_link_segments(last, next, ring->type, chain_links);
144 ring->num_segs += num_segs;
145 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
147 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
148 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
149 &= ~cpu_to_le32(LINK_TOGGLE);
150 last->trbs[TRBS_PER_SEGMENT-1].link.control
151 |= cpu_to_le32(LINK_TOGGLE);
152 ring->last_seg = last;
157 * We need a radix tree for mapping physical addresses of TRBs to which stream
158 * ID they belong to. We need to do this because the host controller won't tell
159 * us which stream ring the TRB came from. We could store the stream ID in an
160 * event data TRB, but that doesn't help us for the cancellation case, since the
161 * endpoint may stop before it reaches that event data TRB.
163 * The radix tree maps the upper portion of the TRB DMA address to a ring
164 * segment that has the same upper portion of DMA addresses. For example, say I
165 * have segments of size 1KB, that are always 1KB aligned. A segment may
166 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
167 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
168 * pass the radix tree a key to get the right stream ID:
170 * 0x10c90fff >> 10 = 0x43243
171 * 0x10c912c0 >> 10 = 0x43244
172 * 0x10c91400 >> 10 = 0x43245
174 * Obviously, only those TRBs with DMA addresses that are within the segment
175 * will make the radix tree return the stream ID for that ring.
177 * Caveats for the radix tree:
179 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
180 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
181 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
182 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
183 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
184 * extended systems (where the DMA address can be bigger than 32-bits),
185 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
187 static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
188 struct xhci_ring *ring,
189 struct xhci_segment *seg,
195 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
196 /* Skip any segments that were already added. */
197 if (radix_tree_lookup(trb_address_map, key))
200 ret = radix_tree_maybe_preload(mem_flags);
203 ret = radix_tree_insert(trb_address_map,
205 radix_tree_preload_end();
209 static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
210 struct xhci_segment *seg)
214 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
215 if (radix_tree_lookup(trb_address_map, key))
216 radix_tree_delete(trb_address_map, key);
219 static int xhci_update_stream_segment_mapping(
220 struct radix_tree_root *trb_address_map,
221 struct xhci_ring *ring,
222 struct xhci_segment *first_seg,
223 struct xhci_segment *last_seg,
226 struct xhci_segment *seg;
227 struct xhci_segment *failed_seg;
230 if (WARN_ON_ONCE(trb_address_map == NULL))
235 ret = xhci_insert_segment_mapping(trb_address_map,
236 ring, seg, mem_flags);
242 } while (seg != first_seg);
250 xhci_remove_segment_mapping(trb_address_map, seg);
251 if (seg == failed_seg)
254 } while (seg != first_seg);
259 static void xhci_remove_stream_mapping(struct xhci_ring *ring)
261 struct xhci_segment *seg;
263 if (WARN_ON_ONCE(ring->trb_address_map == NULL))
266 seg = ring->first_seg;
268 xhci_remove_segment_mapping(ring->trb_address_map, seg);
270 } while (seg != ring->first_seg);
273 static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
275 return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
276 ring->first_seg, ring->last_seg, mem_flags);
279 /* XXX: Do we need the hcd structure in all these functions? */
280 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
285 trace_xhci_ring_free(ring);
287 if (ring->first_seg) {
288 if (ring->type == TYPE_STREAM)
289 xhci_remove_stream_mapping(ring);
290 xhci_free_segments_for_ring(xhci, ring->first_seg);
296 void xhci_initialize_ring_info(struct xhci_ring *ring,
297 unsigned int cycle_state)
299 /* The ring is empty, so the enqueue pointer == dequeue pointer */
300 ring->enqueue = ring->first_seg->trbs;
301 ring->enq_seg = ring->first_seg;
302 ring->dequeue = ring->enqueue;
303 ring->deq_seg = ring->first_seg;
304 /* The ring is initialized to 0. The producer must write 1 to the cycle
305 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
306 * compare CCS to the cycle bit to check ownership, so CCS = 1.
308 * New rings are initialized with cycle state equal to 1; if we are
309 * handling ring expansion, set the cycle state equal to the old ring.
311 ring->cycle_state = cycle_state;
314 * Each segment has a link TRB, and leave an extra TRB for SW
317 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
320 /* Allocate segments and link them for a ring */
321 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
322 struct xhci_segment **first, struct xhci_segment **last,
323 unsigned int num_segs, unsigned int cycle_state,
324 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
326 struct xhci_segment *prev;
329 /* Set chain bit for 0.95 hosts, and for isoc rings on AMD 0.96 host */
330 chain_links = !!(xhci_link_trb_quirk(xhci) ||
331 (type == TYPE_ISOC &&
332 (xhci->quirks & XHCI_AMD_0x96_HOST)));
334 prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
340 while (num_segs > 0) {
341 struct xhci_segment *next;
343 next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
348 xhci_segment_free(xhci, prev);
353 xhci_link_segments(prev, next, type, chain_links);
358 xhci_link_segments(prev, *first, type, chain_links);
365 * Create a new ring with zero or more segments.
367 * Link each segment together into a ring.
368 * Set the end flag and the cycle toggle bit on the last segment.
369 * See section 4.9.1 and figures 15 and 16.
371 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
372 unsigned int num_segs, unsigned int cycle_state,
373 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
375 struct xhci_ring *ring;
377 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
379 ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev));
383 ring->num_segs = num_segs;
384 ring->bounce_buf_len = max_packet;
385 INIT_LIST_HEAD(&ring->td_list);
390 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
391 &ring->last_seg, num_segs, cycle_state, type,
396 /* Only event ring does not use link TRB */
397 if (type != TYPE_EVENT) {
398 /* See section 4.9.2.1 and 6.4.4.1 */
399 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
400 cpu_to_le32(LINK_TOGGLE);
402 xhci_initialize_ring_info(ring, cycle_state);
403 trace_xhci_ring_alloc(ring);
411 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
412 struct xhci_virt_device *virt_dev,
413 unsigned int ep_index)
415 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
416 virt_dev->eps[ep_index].ring = NULL;
420 * Expand an existing ring.
421 * Allocate a new ring which has same segment numbers and link the two rings.
423 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
424 unsigned int num_trbs, gfp_t flags)
426 struct xhci_segment *first;
427 struct xhci_segment *last;
428 unsigned int num_segs;
429 unsigned int num_segs_needed;
432 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
433 (TRBS_PER_SEGMENT - 1);
435 /* Allocate number of segments we needed, or double the ring size */
436 num_segs = ring->num_segs > num_segs_needed ?
437 ring->num_segs : num_segs_needed;
439 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
440 num_segs, ring->cycle_state, ring->type,
441 ring->bounce_buf_len, flags);
445 if (ring->type == TYPE_STREAM)
446 ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
447 ring, first, last, flags);
449 struct xhci_segment *next;
452 xhci_segment_free(xhci, first);
460 xhci_link_rings(xhci, ring, first, last, num_segs);
461 trace_xhci_ring_expansion(ring);
462 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
463 "ring expansion succeed, now has %d segments",
469 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
470 int type, gfp_t flags)
472 struct xhci_container_ctx *ctx;
473 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
475 if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
478 ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
483 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
484 if (type == XHCI_CTX_TYPE_INPUT)
485 ctx->size += CTX_SIZE(xhci->hcc_params);
487 ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma);
495 void xhci_free_container_ctx(struct xhci_hcd *xhci,
496 struct xhci_container_ctx *ctx)
500 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
504 struct xhci_input_control_ctx *xhci_get_input_control_ctx(
505 struct xhci_container_ctx *ctx)
507 if (ctx->type != XHCI_CTX_TYPE_INPUT)
510 return (struct xhci_input_control_ctx *)ctx->bytes;
513 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
514 struct xhci_container_ctx *ctx)
516 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
517 return (struct xhci_slot_ctx *)ctx->bytes;
519 return (struct xhci_slot_ctx *)
520 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
523 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
524 struct xhci_container_ctx *ctx,
525 unsigned int ep_index)
527 /* increment ep index by offset of start of ep ctx array */
529 if (ctx->type == XHCI_CTX_TYPE_INPUT)
532 return (struct xhci_ep_ctx *)
533 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
537 /***************** Streams structures manipulation *************************/
539 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
540 unsigned int num_stream_ctxs,
541 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
543 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
544 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
546 if (size > MEDIUM_STREAM_ARRAY_SIZE)
547 dma_free_coherent(dev, size,
549 else if (size <= SMALL_STREAM_ARRAY_SIZE)
550 return dma_pool_free(xhci->small_streams_pool,
553 return dma_pool_free(xhci->medium_streams_pool,
558 * The stream context array for each endpoint with bulk streams enabled can
559 * vary in size, based on:
560 * - how many streams the endpoint supports,
561 * - the maximum primary stream array size the host controller supports,
562 * - and how many streams the device driver asks for.
564 * The stream context array must be a power of 2, and can be as small as
565 * 64 bytes or as large as 1MB.
567 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
568 unsigned int num_stream_ctxs, dma_addr_t *dma,
571 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
572 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
574 if (size > MEDIUM_STREAM_ARRAY_SIZE)
575 return dma_alloc_coherent(dev, size,
577 else if (size <= SMALL_STREAM_ARRAY_SIZE)
578 return dma_pool_alloc(xhci->small_streams_pool,
581 return dma_pool_alloc(xhci->medium_streams_pool,
585 struct xhci_ring *xhci_dma_to_transfer_ring(
586 struct xhci_virt_ep *ep,
589 if (ep->ep_state & EP_HAS_STREAMS)
590 return radix_tree_lookup(&ep->stream_info->trb_address_map,
591 address >> TRB_SEGMENT_SHIFT);
595 struct xhci_ring *xhci_stream_id_to_ring(
596 struct xhci_virt_device *dev,
597 unsigned int ep_index,
598 unsigned int stream_id)
600 struct xhci_virt_ep *ep = &dev->eps[ep_index];
604 if (!ep->stream_info)
607 if (stream_id >= ep->stream_info->num_streams)
609 return ep->stream_info->stream_rings[stream_id];
613 * Change an endpoint's internal structure so it supports stream IDs. The
614 * number of requested streams includes stream 0, which cannot be used by device
617 * The number of stream contexts in the stream context array may be bigger than
618 * the number of streams the driver wants to use. This is because the number of
619 * stream context array entries must be a power of two.
621 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
622 unsigned int num_stream_ctxs,
623 unsigned int num_streams,
624 unsigned int max_packet, gfp_t mem_flags)
626 struct xhci_stream_info *stream_info;
628 struct xhci_ring *cur_ring;
631 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
633 xhci_dbg(xhci, "Allocating %u streams and %u "
634 "stream context array entries.\n",
635 num_streams, num_stream_ctxs);
636 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
637 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
640 xhci->cmd_ring_reserved_trbs++;
642 stream_info = kzalloc_node(sizeof(*stream_info), mem_flags,
647 stream_info->num_streams = num_streams;
648 stream_info->num_stream_ctxs = num_stream_ctxs;
650 /* Initialize the array of virtual pointers to stream rings. */
651 stream_info->stream_rings = kcalloc_node(
652 num_streams, sizeof(struct xhci_ring *), mem_flags,
654 if (!stream_info->stream_rings)
657 /* Initialize the array of DMA addresses for stream rings for the HW. */
658 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
659 num_stream_ctxs, &stream_info->ctx_array_dma,
661 if (!stream_info->stream_ctx_array)
662 goto cleanup_ring_array;
663 memset(stream_info->stream_ctx_array, 0,
664 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
666 /* Allocate everything needed to free the stream rings later */
667 stream_info->free_streams_command =
668 xhci_alloc_command_with_ctx(xhci, true, mem_flags);
669 if (!stream_info->free_streams_command)
672 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
674 /* Allocate rings for all the streams that the driver will use,
675 * and add their segment DMA addresses to the radix tree.
676 * Stream 0 is reserved.
679 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
680 stream_info->stream_rings[cur_stream] =
681 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet,
683 cur_ring = stream_info->stream_rings[cur_stream];
686 cur_ring->stream_id = cur_stream;
687 cur_ring->trb_address_map = &stream_info->trb_address_map;
688 /* Set deq ptr, cycle bit, and stream context type */
689 addr = cur_ring->first_seg->dma |
690 SCT_FOR_CTX(SCT_PRI_TR) |
691 cur_ring->cycle_state;
692 stream_info->stream_ctx_array[cur_stream].stream_ring =
694 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
695 cur_stream, (unsigned long long) addr);
697 ret = xhci_update_stream_mapping(cur_ring, mem_flags);
699 xhci_ring_free(xhci, cur_ring);
700 stream_info->stream_rings[cur_stream] = NULL;
704 /* Leave the other unused stream ring pointers in the stream context
705 * array initialized to zero. This will cause the xHC to give us an
706 * error if the device asks for a stream ID we don't have setup (if it
707 * was any other way, the host controller would assume the ring is
708 * "empty" and wait forever for data to be queued to that stream ID).
714 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
715 cur_ring = stream_info->stream_rings[cur_stream];
717 xhci_ring_free(xhci, cur_ring);
718 stream_info->stream_rings[cur_stream] = NULL;
721 xhci_free_command(xhci, stream_info->free_streams_command);
723 xhci_free_stream_ctx(xhci,
724 stream_info->num_stream_ctxs,
725 stream_info->stream_ctx_array,
726 stream_info->ctx_array_dma);
728 kfree(stream_info->stream_rings);
732 xhci->cmd_ring_reserved_trbs--;
736 * Sets the MaxPStreams field and the Linear Stream Array field.
737 * Sets the dequeue pointer to the stream context array.
739 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
740 struct xhci_ep_ctx *ep_ctx,
741 struct xhci_stream_info *stream_info)
743 u32 max_primary_streams;
744 /* MaxPStreams is the number of stream context array entries, not the
745 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
746 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
748 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
749 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
750 "Setting number of stream ctx array entries to %u",
751 1 << (max_primary_streams + 1));
752 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
753 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
755 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
759 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
760 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
761 * not at the beginning of the ring).
763 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
764 struct xhci_virt_ep *ep)
767 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
768 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
769 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
772 /* Frees all stream contexts associated with the endpoint,
774 * Caller should fix the endpoint context streams fields.
776 void xhci_free_stream_info(struct xhci_hcd *xhci,
777 struct xhci_stream_info *stream_info)
780 struct xhci_ring *cur_ring;
785 for (cur_stream = 1; cur_stream < stream_info->num_streams;
787 cur_ring = stream_info->stream_rings[cur_stream];
789 xhci_ring_free(xhci, cur_ring);
790 stream_info->stream_rings[cur_stream] = NULL;
793 xhci_free_command(xhci, stream_info->free_streams_command);
794 xhci->cmd_ring_reserved_trbs--;
795 if (stream_info->stream_ctx_array)
796 xhci_free_stream_ctx(xhci,
797 stream_info->num_stream_ctxs,
798 stream_info->stream_ctx_array,
799 stream_info->ctx_array_dma);
801 kfree(stream_info->stream_rings);
806 /***************** Device context manipulation *************************/
808 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
809 struct xhci_virt_ep *ep)
811 timer_setup(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog,
816 static void xhci_free_tt_info(struct xhci_hcd *xhci,
817 struct xhci_virt_device *virt_dev,
820 struct list_head *tt_list_head;
821 struct xhci_tt_bw_info *tt_info, *next;
822 bool slot_found = false;
824 /* If the device never made it past the Set Address stage,
825 * it may not have the real_port set correctly.
827 if (virt_dev->real_port == 0 ||
828 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
829 xhci_dbg(xhci, "Bad real port.\n");
833 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
834 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
835 /* Multi-TT hubs will have more than one entry */
836 if (tt_info->slot_id == slot_id) {
838 list_del(&tt_info->tt_list);
840 } else if (slot_found) {
846 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
847 struct xhci_virt_device *virt_dev,
848 struct usb_device *hdev,
849 struct usb_tt *tt, gfp_t mem_flags)
851 struct xhci_tt_bw_info *tt_info;
852 unsigned int num_ports;
854 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
859 num_ports = hdev->maxchild;
861 for (i = 0; i < num_ports; i++, tt_info++) {
862 struct xhci_interval_bw_table *bw_table;
864 tt_info = kzalloc_node(sizeof(*tt_info), mem_flags,
868 INIT_LIST_HEAD(&tt_info->tt_list);
869 list_add(&tt_info->tt_list,
870 &xhci->rh_bw[virt_dev->real_port - 1].tts);
871 tt_info->slot_id = virt_dev->udev->slot_id;
873 tt_info->ttport = i+1;
874 bw_table = &tt_info->bw_table;
875 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
876 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
881 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
886 /* All the xhci_tds in the ring's TD list should be freed at this point.
887 * Should be called with xhci->lock held if there is any chance the TT lists
888 * will be manipulated by the configure endpoint, allocate device, or update
889 * hub functions while this function is removing the TT entries from the list.
891 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
893 struct xhci_virt_device *dev;
895 int old_active_eps = 0;
897 /* Slot ID 0 is reserved */
898 if (slot_id == 0 || !xhci->devs[slot_id])
901 dev = xhci->devs[slot_id];
903 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
907 trace_xhci_free_virt_device(dev);
910 old_active_eps = dev->tt_info->active_eps;
912 for (i = 0; i < 31; i++) {
913 if (dev->eps[i].ring)
914 xhci_ring_free(xhci, dev->eps[i].ring);
915 if (dev->eps[i].stream_info)
916 xhci_free_stream_info(xhci,
917 dev->eps[i].stream_info);
919 * Endpoints are normally deleted from the bandwidth list when
920 * endpoints are dropped, before device is freed.
921 * If host is dying or being removed then endpoints aren't
922 * dropped cleanly, so delete the endpoint from list here.
923 * Only applicable for hosts with software bandwidth checking.
926 if (!list_empty(&dev->eps[i].bw_endpoint_list)) {
927 list_del_init(&dev->eps[i].bw_endpoint_list);
928 xhci_dbg(xhci, "Slot %u endpoint %u not removed from BW list!\n",
932 /* If this is a hub, free the TT(s) from the TT list */
933 xhci_free_tt_info(xhci, dev, slot_id);
934 /* If necessary, update the number of active TTs on this root port */
935 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
938 xhci_free_container_ctx(xhci, dev->in_ctx);
940 xhci_free_container_ctx(xhci, dev->out_ctx);
942 if (dev->udev && dev->udev->slot_id)
943 dev->udev->slot_id = 0;
944 kfree(xhci->devs[slot_id]);
945 xhci->devs[slot_id] = NULL;
949 * Free a virt_device structure.
950 * If the virt_device added a tt_info (a hub) and has children pointing to
951 * that tt_info, then free the child first. Recursive.
952 * We can't rely on udev at this point to find child-parent relationships.
954 static void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
956 struct xhci_virt_device *vdev;
957 struct list_head *tt_list_head;
958 struct xhci_tt_bw_info *tt_info, *next;
961 vdev = xhci->devs[slot_id];
965 if (vdev->real_port == 0 ||
966 vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
967 xhci_dbg(xhci, "Bad vdev->real_port.\n");
971 tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts);
972 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
973 /* is this a hub device that added a tt_info to the tts list */
974 if (tt_info->slot_id == slot_id) {
975 /* are any devices using this tt_info? */
976 for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
977 vdev = xhci->devs[i];
978 if (vdev && (vdev->tt_info == tt_info))
979 xhci_free_virt_devices_depth_first(
985 /* we are now at a leaf device */
986 xhci_debugfs_remove_slot(xhci, slot_id);
987 xhci_free_virt_device(xhci, slot_id);
990 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
991 struct usb_device *udev, gfp_t flags)
993 struct xhci_virt_device *dev;
996 /* Slot ID 0 is reserved */
997 if (slot_id == 0 || xhci->devs[slot_id]) {
998 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
1002 dev = kzalloc(sizeof(*dev), flags);
1006 dev->slot_id = slot_id;
1008 /* Allocate the (output) device context that will be used in the HC. */
1009 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
1013 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
1014 (unsigned long long)dev->out_ctx->dma);
1016 /* Allocate the (input) device context for address device command */
1017 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
1021 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
1022 (unsigned long long)dev->in_ctx->dma);
1024 /* Initialize the cancellation list and watchdog timers for each ep */
1025 for (i = 0; i < 31; i++) {
1026 dev->eps[i].ep_index = i;
1027 dev->eps[i].vdev = dev;
1028 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
1029 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1030 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1033 /* Allocate endpoint 0 ring */
1034 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags);
1035 if (!dev->eps[0].ring)
1040 /* Point to output device context in dcbaa. */
1041 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1042 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1044 &xhci->dcbaa->dev_context_ptrs[slot_id],
1045 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1047 trace_xhci_alloc_virt_device(dev);
1049 xhci->devs[slot_id] = dev;
1055 xhci_free_container_ctx(xhci, dev->in_ctx);
1057 xhci_free_container_ctx(xhci, dev->out_ctx);
1063 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1064 struct usb_device *udev)
1066 struct xhci_virt_device *virt_dev;
1067 struct xhci_ep_ctx *ep0_ctx;
1068 struct xhci_ring *ep_ring;
1070 virt_dev = xhci->devs[udev->slot_id];
1071 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1072 ep_ring = virt_dev->eps[0].ring;
1074 * FIXME we don't keep track of the dequeue pointer very well after a
1075 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1076 * host to our enqueue pointer. This should only be called after a
1077 * configured device has reset, so all control transfers should have
1078 * been completed or cancelled before the reset.
1080 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1082 | ep_ring->cycle_state);
1086 * The xHCI roothub may have ports of differing speeds in any order in the port
1089 * The xHCI hardware wants to know the roothub port number that the USB device
1090 * is attached to (or the roothub port its ancestor hub is attached to). All we
1091 * know is the index of that port under either the USB 2.0 or the USB 3.0
1092 * roothub, but that doesn't give us the real index into the HW port status
1093 * registers. Call xhci_find_raw_port_number() to get real index.
1095 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1096 struct usb_device *udev)
1098 struct usb_device *top_dev;
1099 struct usb_hcd *hcd;
1101 if (udev->speed >= USB_SPEED_SUPER)
1102 hcd = xhci->shared_hcd;
1104 hcd = xhci->main_hcd;
1106 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1107 top_dev = top_dev->parent)
1108 /* Found device below root hub */;
1110 return xhci_find_raw_port_number(hcd, top_dev->portnum);
1113 /* Setup an xHCI virtual device for a Set Address command */
1114 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1116 struct xhci_virt_device *dev;
1117 struct xhci_ep_ctx *ep0_ctx;
1118 struct xhci_slot_ctx *slot_ctx;
1121 struct usb_device *top_dev;
1123 dev = xhci->devs[udev->slot_id];
1124 /* Slot ID 0 is reserved */
1125 if (udev->slot_id == 0 || !dev) {
1126 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1130 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1131 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1133 /* 3) Only the control endpoint is valid - one endpoint context */
1134 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1135 switch (udev->speed) {
1136 case USB_SPEED_SUPER_PLUS:
1137 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1138 max_packets = MAX_PACKET(512);
1140 case USB_SPEED_SUPER:
1141 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1142 max_packets = MAX_PACKET(512);
1144 case USB_SPEED_HIGH:
1145 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1146 max_packets = MAX_PACKET(64);
1148 /* USB core guesses at a 64-byte max packet first for FS devices */
1149 case USB_SPEED_FULL:
1150 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1151 max_packets = MAX_PACKET(64);
1154 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1155 max_packets = MAX_PACKET(8);
1157 case USB_SPEED_WIRELESS:
1158 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1162 /* Speed was set earlier, this shouldn't happen. */
1165 /* Find the root hub port this device is under */
1166 port_num = xhci_find_real_port_number(xhci, udev);
1169 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1170 /* Set the port number in the virtual_device to the faked port number */
1171 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1172 top_dev = top_dev->parent)
1173 /* Found device below root hub */;
1174 dev->fake_port = top_dev->portnum;
1175 dev->real_port = port_num;
1176 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1177 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1179 /* Find the right bandwidth table that this device will be a part of.
1180 * If this is a full speed device attached directly to a root port (or a
1181 * decendent of one), it counts as a primary bandwidth domain, not a
1182 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1183 * will never be created for the HS root hub.
1185 if (!udev->tt || !udev->tt->hub->parent) {
1186 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1188 struct xhci_root_port_bw_info *rh_bw;
1189 struct xhci_tt_bw_info *tt_bw;
1191 rh_bw = &xhci->rh_bw[port_num - 1];
1192 /* Find the right TT. */
1193 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1194 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1197 if (!dev->udev->tt->multi ||
1199 tt_bw->ttport == dev->udev->ttport)) {
1200 dev->bw_table = &tt_bw->bw_table;
1201 dev->tt_info = tt_bw;
1206 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1209 /* Is this a LS/FS device under an external HS hub? */
1210 if (udev->tt && udev->tt->hub->parent) {
1211 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1212 (udev->ttport << 8));
1213 if (udev->tt->multi)
1214 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1216 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1217 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1219 /* Step 4 - ring already allocated */
1221 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1223 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1224 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1227 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1228 dev->eps[0].ring->cycle_state);
1230 trace_xhci_setup_addressable_virt_device(dev);
1232 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1238 * Convert interval expressed as 2^(bInterval - 1) == interval into
1239 * straight exponent value 2^n == interval.
1242 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1243 struct usb_host_endpoint *ep)
1245 unsigned int interval;
1247 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1248 if (interval != ep->desc.bInterval - 1)
1249 dev_warn(&udev->dev,
1250 "ep %#x - rounding interval to %d %sframes\n",
1251 ep->desc.bEndpointAddress,
1253 udev->speed == USB_SPEED_FULL ? "" : "micro");
1255 if (udev->speed == USB_SPEED_FULL) {
1257 * Full speed isoc endpoints specify interval in frames,
1258 * not microframes. We are using microframes everywhere,
1259 * so adjust accordingly.
1261 interval += 3; /* 1 frame = 2^3 uframes */
1268 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1269 * microframes, rounded down to nearest power of 2.
1271 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1272 struct usb_host_endpoint *ep, unsigned int desc_interval,
1273 unsigned int min_exponent, unsigned int max_exponent)
1275 unsigned int interval;
1277 interval = fls(desc_interval) - 1;
1278 interval = clamp_val(interval, min_exponent, max_exponent);
1279 if ((1 << interval) != desc_interval)
1281 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1282 ep->desc.bEndpointAddress,
1289 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1290 struct usb_host_endpoint *ep)
1292 if (ep->desc.bInterval == 0)
1294 return xhci_microframes_to_exponent(udev, ep,
1295 ep->desc.bInterval, 0, 15);
1299 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1300 struct usb_host_endpoint *ep)
1302 return xhci_microframes_to_exponent(udev, ep,
1303 ep->desc.bInterval * 8, 3, 10);
1306 /* Return the polling or NAK interval.
1308 * The polling interval is expressed in "microframes". If xHCI's Interval field
1309 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1311 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1314 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1315 struct usb_host_endpoint *ep)
1317 unsigned int interval = 0;
1319 switch (udev->speed) {
1320 case USB_SPEED_HIGH:
1322 if (usb_endpoint_xfer_control(&ep->desc) ||
1323 usb_endpoint_xfer_bulk(&ep->desc)) {
1324 interval = xhci_parse_microframe_interval(udev, ep);
1327 fallthrough; /* SS and HS isoc/int have same decoding */
1329 case USB_SPEED_SUPER_PLUS:
1330 case USB_SPEED_SUPER:
1331 if (usb_endpoint_xfer_int(&ep->desc) ||
1332 usb_endpoint_xfer_isoc(&ep->desc)) {
1333 interval = xhci_parse_exponent_interval(udev, ep);
1337 case USB_SPEED_FULL:
1338 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1339 interval = xhci_parse_exponent_interval(udev, ep);
1343 * Fall through for interrupt endpoint interval decoding
1344 * since it uses the same rules as low speed interrupt
1350 if (usb_endpoint_xfer_int(&ep->desc) ||
1351 usb_endpoint_xfer_isoc(&ep->desc)) {
1353 interval = xhci_parse_frame_interval(udev, ep);
1363 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1364 * High speed endpoint descriptors can define "the number of additional
1365 * transaction opportunities per microframe", but that goes in the Max Burst
1366 * endpoint context field.
1368 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1369 struct usb_host_endpoint *ep)
1371 if (udev->speed < USB_SPEED_SUPER ||
1372 !usb_endpoint_xfer_isoc(&ep->desc))
1374 return ep->ss_ep_comp.bmAttributes;
1377 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1378 struct usb_host_endpoint *ep)
1380 /* Super speed and Plus have max burst in ep companion desc */
1381 if (udev->speed >= USB_SPEED_SUPER)
1382 return ep->ss_ep_comp.bMaxBurst;
1384 if (udev->speed == USB_SPEED_HIGH &&
1385 (usb_endpoint_xfer_isoc(&ep->desc) ||
1386 usb_endpoint_xfer_int(&ep->desc)))
1387 return usb_endpoint_maxp_mult(&ep->desc) - 1;
1392 static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1396 in = usb_endpoint_dir_in(&ep->desc);
1398 switch (usb_endpoint_type(&ep->desc)) {
1399 case USB_ENDPOINT_XFER_CONTROL:
1401 case USB_ENDPOINT_XFER_BULK:
1402 return in ? BULK_IN_EP : BULK_OUT_EP;
1403 case USB_ENDPOINT_XFER_ISOC:
1404 return in ? ISOC_IN_EP : ISOC_OUT_EP;
1405 case USB_ENDPOINT_XFER_INT:
1406 return in ? INT_IN_EP : INT_OUT_EP;
1411 /* Return the maximum endpoint service interval time (ESIT) payload.
1412 * Basically, this is the maxpacket size, multiplied by the burst size
1415 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
1416 struct usb_host_endpoint *ep)
1421 /* Only applies for interrupt or isochronous endpoints */
1422 if (usb_endpoint_xfer_control(&ep->desc) ||
1423 usb_endpoint_xfer_bulk(&ep->desc))
1426 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1427 if ((udev->speed >= USB_SPEED_SUPER_PLUS) &&
1428 USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes))
1429 return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval);
1430 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1431 else if (udev->speed >= USB_SPEED_SUPER)
1432 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1434 max_packet = usb_endpoint_maxp(&ep->desc);
1435 max_burst = usb_endpoint_maxp_mult(&ep->desc);
1436 /* A 0 in max burst means 1 transfer per ESIT */
1437 return max_packet * max_burst;
1440 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1441 * Drivers will have to call usb_alloc_streams() to do that.
1443 int xhci_endpoint_init(struct xhci_hcd *xhci,
1444 struct xhci_virt_device *virt_dev,
1445 struct usb_device *udev,
1446 struct usb_host_endpoint *ep,
1449 unsigned int ep_index;
1450 struct xhci_ep_ctx *ep_ctx;
1451 struct xhci_ring *ep_ring;
1452 unsigned int max_packet;
1453 enum xhci_ring_type ring_type;
1454 u32 max_esit_payload;
1456 unsigned int max_burst;
1457 unsigned int interval;
1459 unsigned int avg_trb_len;
1460 unsigned int err_count = 0;
1462 ep_index = xhci_get_endpoint_index(&ep->desc);
1463 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1465 endpoint_type = xhci_get_endpoint_type(ep);
1469 ring_type = usb_endpoint_type(&ep->desc);
1472 * Get values to fill the endpoint context, mostly from ep descriptor.
1473 * The average TRB buffer lengt for bulk endpoints is unclear as we
1474 * have no clue on scatter gather list entry size. For Isoc and Int,
1475 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1477 max_esit_payload = xhci_get_max_esit_payload(udev, ep);
1478 interval = xhci_get_endpoint_interval(udev, ep);
1480 /* Periodic endpoint bInterval limit quirk */
1481 if (usb_endpoint_xfer_int(&ep->desc) ||
1482 usb_endpoint_xfer_isoc(&ep->desc)) {
1483 if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
1484 udev->speed >= USB_SPEED_HIGH &&
1490 mult = xhci_get_endpoint_mult(udev, ep);
1491 max_packet = usb_endpoint_maxp(&ep->desc);
1492 max_burst = xhci_get_endpoint_max_burst(udev, ep);
1493 avg_trb_len = max_esit_payload;
1495 /* FIXME dig Mult and streams info out of ep companion desc */
1497 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1498 if (!usb_endpoint_xfer_isoc(&ep->desc))
1500 /* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */
1501 if (usb_endpoint_xfer_bulk(&ep->desc)) {
1502 if (udev->speed == USB_SPEED_HIGH)
1504 if (udev->speed == USB_SPEED_FULL) {
1505 max_packet = rounddown_pow_of_two(max_packet);
1506 max_packet = clamp_val(max_packet, 8, 64);
1509 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1510 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
1512 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1513 if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2))
1516 /* Set up the endpoint ring */
1517 virt_dev->eps[ep_index].new_ring =
1518 xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags);
1519 if (!virt_dev->eps[ep_index].new_ring)
1522 virt_dev->eps[ep_index].skip = false;
1523 ep_ring = virt_dev->eps[ep_index].new_ring;
1525 /* Fill the endpoint context */
1526 ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
1527 EP_INTERVAL(interval) |
1529 ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1530 MAX_PACKET(max_packet) |
1531 MAX_BURST(max_burst) |
1532 ERROR_COUNT(err_count));
1533 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1534 ep_ring->cycle_state);
1536 ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1537 EP_AVG_TRB_LENGTH(avg_trb_len));
1542 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1543 struct xhci_virt_device *virt_dev,
1544 struct usb_host_endpoint *ep)
1546 unsigned int ep_index;
1547 struct xhci_ep_ctx *ep_ctx;
1549 ep_index = xhci_get_endpoint_index(&ep->desc);
1550 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1552 ep_ctx->ep_info = 0;
1553 ep_ctx->ep_info2 = 0;
1555 ep_ctx->tx_info = 0;
1556 /* Don't free the endpoint ring until the set interface or configuration
1561 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1563 bw_info->ep_interval = 0;
1565 bw_info->num_packets = 0;
1566 bw_info->max_packet_size = 0;
1568 bw_info->max_esit_payload = 0;
1571 void xhci_update_bw_info(struct xhci_hcd *xhci,
1572 struct xhci_container_ctx *in_ctx,
1573 struct xhci_input_control_ctx *ctrl_ctx,
1574 struct xhci_virt_device *virt_dev)
1576 struct xhci_bw_info *bw_info;
1577 struct xhci_ep_ctx *ep_ctx;
1578 unsigned int ep_type;
1581 for (i = 1; i < 31; i++) {
1582 bw_info = &virt_dev->eps[i].bw_info;
1584 /* We can't tell what endpoint type is being dropped, but
1585 * unconditionally clearing the bandwidth info for non-periodic
1586 * endpoints should be harmless because the info will never be
1587 * set in the first place.
1589 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1590 /* Dropped endpoint */
1591 xhci_clear_endpoint_bw_info(bw_info);
1595 if (EP_IS_ADDED(ctrl_ctx, i)) {
1596 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1597 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1599 /* Ignore non-periodic endpoints */
1600 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1601 ep_type != ISOC_IN_EP &&
1602 ep_type != INT_IN_EP)
1605 /* Added or changed endpoint */
1606 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1607 le32_to_cpu(ep_ctx->ep_info));
1608 /* Number of packets and mult are zero-based in the
1609 * input context, but we want one-based for the
1612 bw_info->mult = CTX_TO_EP_MULT(
1613 le32_to_cpu(ep_ctx->ep_info)) + 1;
1614 bw_info->num_packets = CTX_TO_MAX_BURST(
1615 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1616 bw_info->max_packet_size = MAX_PACKET_DECODED(
1617 le32_to_cpu(ep_ctx->ep_info2));
1618 bw_info->type = ep_type;
1619 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1620 le32_to_cpu(ep_ctx->tx_info));
1625 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1626 * Useful when you want to change one particular aspect of the endpoint and then
1627 * issue a configure endpoint command.
1629 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1630 struct xhci_container_ctx *in_ctx,
1631 struct xhci_container_ctx *out_ctx,
1632 unsigned int ep_index)
1634 struct xhci_ep_ctx *out_ep_ctx;
1635 struct xhci_ep_ctx *in_ep_ctx;
1637 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1638 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1640 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1641 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1642 in_ep_ctx->deq = out_ep_ctx->deq;
1643 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1644 if (xhci->quirks & XHCI_MTK_HOST) {
1645 in_ep_ctx->reserved[0] = out_ep_ctx->reserved[0];
1646 in_ep_ctx->reserved[1] = out_ep_ctx->reserved[1];
1650 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1651 * Useful when you want to change one particular aspect of the endpoint and then
1652 * issue a configure endpoint command. Only the context entries field matters,
1653 * but we'll copy the whole thing anyway.
1655 void xhci_slot_copy(struct xhci_hcd *xhci,
1656 struct xhci_container_ctx *in_ctx,
1657 struct xhci_container_ctx *out_ctx)
1659 struct xhci_slot_ctx *in_slot_ctx;
1660 struct xhci_slot_ctx *out_slot_ctx;
1662 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1663 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1665 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1666 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1667 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1668 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1671 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1672 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1675 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1676 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1678 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1679 "Allocating %d scratchpad buffers", num_sp);
1684 xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags,
1686 if (!xhci->scratchpad)
1689 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1690 num_sp * sizeof(u64),
1691 &xhci->scratchpad->sp_dma, flags);
1692 if (!xhci->scratchpad->sp_array)
1695 xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *),
1696 flags, dev_to_node(dev));
1697 if (!xhci->scratchpad->sp_buffers)
1700 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1701 for (i = 0; i < num_sp; i++) {
1703 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1708 xhci->scratchpad->sp_array[i] = dma;
1709 xhci->scratchpad->sp_buffers[i] = buf;
1715 for (i = i - 1; i >= 0; i--) {
1716 dma_free_coherent(dev, xhci->page_size,
1717 xhci->scratchpad->sp_buffers[i],
1718 xhci->scratchpad->sp_array[i]);
1721 kfree(xhci->scratchpad->sp_buffers);
1724 dma_free_coherent(dev, num_sp * sizeof(u64),
1725 xhci->scratchpad->sp_array,
1726 xhci->scratchpad->sp_dma);
1729 kfree(xhci->scratchpad);
1730 xhci->scratchpad = NULL;
1736 static void scratchpad_free(struct xhci_hcd *xhci)
1740 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1742 if (!xhci->scratchpad)
1745 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1747 for (i = 0; i < num_sp; i++) {
1748 dma_free_coherent(dev, xhci->page_size,
1749 xhci->scratchpad->sp_buffers[i],
1750 xhci->scratchpad->sp_array[i]);
1752 kfree(xhci->scratchpad->sp_buffers);
1753 dma_free_coherent(dev, num_sp * sizeof(u64),
1754 xhci->scratchpad->sp_array,
1755 xhci->scratchpad->sp_dma);
1756 kfree(xhci->scratchpad);
1757 xhci->scratchpad = NULL;
1760 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1761 bool allocate_completion, gfp_t mem_flags)
1763 struct xhci_command *command;
1764 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1766 command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev));
1770 if (allocate_completion) {
1771 command->completion =
1772 kzalloc_node(sizeof(struct completion), mem_flags,
1774 if (!command->completion) {
1778 init_completion(command->completion);
1781 command->status = 0;
1782 INIT_LIST_HEAD(&command->cmd_list);
1786 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1787 bool allocate_completion, gfp_t mem_flags)
1789 struct xhci_command *command;
1791 command = xhci_alloc_command(xhci, allocate_completion, mem_flags);
1795 command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1797 if (!command->in_ctx) {
1798 kfree(command->completion);
1805 void xhci_urb_free_priv(struct urb_priv *urb_priv)
1810 void xhci_free_command(struct xhci_hcd *xhci,
1811 struct xhci_command *command)
1813 xhci_free_container_ctx(xhci,
1815 kfree(command->completion);
1819 int xhci_alloc_erst(struct xhci_hcd *xhci,
1820 struct xhci_ring *evt_ring,
1821 struct xhci_erst *erst,
1826 struct xhci_segment *seg;
1827 struct xhci_erst_entry *entry;
1829 size = sizeof(struct xhci_erst_entry) * evt_ring->num_segs;
1830 erst->entries = dma_alloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
1831 size, &erst->erst_dma_addr, flags);
1835 erst->num_entries = evt_ring->num_segs;
1837 seg = evt_ring->first_seg;
1838 for (val = 0; val < evt_ring->num_segs; val++) {
1839 entry = &erst->entries[val];
1840 entry->seg_addr = cpu_to_le64(seg->dma);
1841 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
1849 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
1852 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1854 size = sizeof(struct xhci_erst_entry) * (erst->num_entries);
1856 dma_free_coherent(dev, size,
1858 erst->erst_dma_addr);
1859 erst->entries = NULL;
1862 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1864 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1865 int i, j, num_ports;
1867 cancel_delayed_work_sync(&xhci->cmd_timer);
1869 xhci_free_erst(xhci, &xhci->erst);
1871 if (xhci->event_ring)
1872 xhci_ring_free(xhci, xhci->event_ring);
1873 xhci->event_ring = NULL;
1874 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring");
1876 if (xhci->lpm_command)
1877 xhci_free_command(xhci, xhci->lpm_command);
1878 xhci->lpm_command = NULL;
1880 xhci_ring_free(xhci, xhci->cmd_ring);
1881 xhci->cmd_ring = NULL;
1882 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1883 xhci_cleanup_command_queue(xhci);
1885 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1886 for (i = 0; i < num_ports && xhci->rh_bw; i++) {
1887 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1888 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1889 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1890 while (!list_empty(ep))
1891 list_del_init(ep->next);
1895 for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--)
1896 xhci_free_virt_devices_depth_first(xhci, i);
1898 dma_pool_destroy(xhci->segment_pool);
1899 xhci->segment_pool = NULL;
1900 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1902 dma_pool_destroy(xhci->device_pool);
1903 xhci->device_pool = NULL;
1904 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1906 dma_pool_destroy(xhci->small_streams_pool);
1907 xhci->small_streams_pool = NULL;
1908 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1909 "Freed small stream array pool");
1911 dma_pool_destroy(xhci->medium_streams_pool);
1912 xhci->medium_streams_pool = NULL;
1913 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1914 "Freed medium stream array pool");
1917 dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1918 xhci->dcbaa, xhci->dcbaa->dma);
1921 scratchpad_free(xhci);
1926 for (i = 0; i < num_ports; i++) {
1927 struct xhci_tt_bw_info *tt, *n;
1928 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1929 list_del(&tt->tt_list);
1935 xhci->cmd_ring_reserved_trbs = 0;
1936 xhci->usb2_rhub.num_ports = 0;
1937 xhci->usb3_rhub.num_ports = 0;
1938 xhci->num_active_eps = 0;
1939 kfree(xhci->usb2_rhub.ports);
1940 kfree(xhci->usb3_rhub.ports);
1941 kfree(xhci->hw_ports);
1943 kfree(xhci->ext_caps);
1944 for (i = 0; i < xhci->num_port_caps; i++)
1945 kfree(xhci->port_caps[i].psi);
1946 kfree(xhci->port_caps);
1947 xhci->num_port_caps = 0;
1949 xhci->usb2_rhub.ports = NULL;
1950 xhci->usb3_rhub.ports = NULL;
1951 xhci->hw_ports = NULL;
1953 xhci->ext_caps = NULL;
1954 xhci->port_caps = NULL;
1956 xhci->page_size = 0;
1957 xhci->page_shift = 0;
1958 xhci->usb2_rhub.bus_state.bus_suspended = 0;
1959 xhci->usb3_rhub.bus_state.bus_suspended = 0;
1962 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1963 struct xhci_segment *input_seg,
1964 union xhci_trb *start_trb,
1965 union xhci_trb *end_trb,
1966 dma_addr_t input_dma,
1967 struct xhci_segment *result_seg,
1968 char *test_name, int test_number)
1970 unsigned long long start_dma;
1971 unsigned long long end_dma;
1972 struct xhci_segment *seg;
1974 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1975 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1977 seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false);
1978 if (seg != result_seg) {
1979 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1980 test_name, test_number);
1981 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1982 "input DMA 0x%llx\n",
1984 (unsigned long long) input_dma);
1985 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1986 "ending TRB %p (0x%llx DMA)\n",
1987 start_trb, start_dma,
1989 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1991 trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma,
1998 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1999 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci)
2002 dma_addr_t input_dma;
2003 struct xhci_segment *result_seg;
2004 } simple_test_vector [] = {
2005 /* A zeroed DMA field should fail */
2007 /* One TRB before the ring start should fail */
2008 { xhci->event_ring->first_seg->dma - 16, NULL },
2009 /* One byte before the ring start should fail */
2010 { xhci->event_ring->first_seg->dma - 1, NULL },
2011 /* Starting TRB should succeed */
2012 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
2013 /* Ending TRB should succeed */
2014 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
2015 xhci->event_ring->first_seg },
2016 /* One byte after the ring end should fail */
2017 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
2018 /* One TRB after the ring end should fail */
2019 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
2020 /* An address of all ones should fail */
2021 { (dma_addr_t) (~0), NULL },
2024 struct xhci_segment *input_seg;
2025 union xhci_trb *start_trb;
2026 union xhci_trb *end_trb;
2027 dma_addr_t input_dma;
2028 struct xhci_segment *result_seg;
2029 } complex_test_vector [] = {
2030 /* Test feeding a valid DMA address from a different ring */
2031 { .input_seg = xhci->event_ring->first_seg,
2032 .start_trb = xhci->event_ring->first_seg->trbs,
2033 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2034 .input_dma = xhci->cmd_ring->first_seg->dma,
2037 /* Test feeding a valid end TRB from a different ring */
2038 { .input_seg = xhci->event_ring->first_seg,
2039 .start_trb = xhci->event_ring->first_seg->trbs,
2040 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2041 .input_dma = xhci->cmd_ring->first_seg->dma,
2044 /* Test feeding a valid start and end TRB from a different ring */
2045 { .input_seg = xhci->event_ring->first_seg,
2046 .start_trb = xhci->cmd_ring->first_seg->trbs,
2047 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2048 .input_dma = xhci->cmd_ring->first_seg->dma,
2051 /* TRB in this ring, but after this TD */
2052 { .input_seg = xhci->event_ring->first_seg,
2053 .start_trb = &xhci->event_ring->first_seg->trbs[0],
2054 .end_trb = &xhci->event_ring->first_seg->trbs[3],
2055 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
2058 /* TRB in this ring, but before this TD */
2059 { .input_seg = xhci->event_ring->first_seg,
2060 .start_trb = &xhci->event_ring->first_seg->trbs[3],
2061 .end_trb = &xhci->event_ring->first_seg->trbs[6],
2062 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2065 /* TRB in this ring, but after this wrapped TD */
2066 { .input_seg = xhci->event_ring->first_seg,
2067 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2068 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2069 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2072 /* TRB in this ring, but before this wrapped TD */
2073 { .input_seg = xhci->event_ring->first_seg,
2074 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2075 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2076 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
2079 /* TRB not in this ring, and we have a wrapped TD */
2080 { .input_seg = xhci->event_ring->first_seg,
2081 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2082 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2083 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
2088 unsigned int num_tests;
2091 num_tests = ARRAY_SIZE(simple_test_vector);
2092 for (i = 0; i < num_tests; i++) {
2093 ret = xhci_test_trb_in_td(xhci,
2094 xhci->event_ring->first_seg,
2095 xhci->event_ring->first_seg->trbs,
2096 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2097 simple_test_vector[i].input_dma,
2098 simple_test_vector[i].result_seg,
2104 num_tests = ARRAY_SIZE(complex_test_vector);
2105 for (i = 0; i < num_tests; i++) {
2106 ret = xhci_test_trb_in_td(xhci,
2107 complex_test_vector[i].input_seg,
2108 complex_test_vector[i].start_trb,
2109 complex_test_vector[i].end_trb,
2110 complex_test_vector[i].input_dma,
2111 complex_test_vector[i].result_seg,
2116 xhci_dbg(xhci, "TRB math tests passed.\n");
2120 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2125 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2126 xhci->event_ring->dequeue);
2127 if (deq == 0 && !in_interrupt())
2128 xhci_warn(xhci, "WARN something wrong with SW event ring "
2130 /* Update HC event ring dequeue pointer */
2131 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2132 temp &= ERST_PTR_MASK;
2133 /* Don't clear the EHB bit (which is RW1C) because
2134 * there might be more events to service.
2137 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2138 "// Write event ring dequeue pointer, "
2139 "preserving EHB bit");
2140 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2141 &xhci->ir_set->erst_dequeue);
2144 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2145 __le32 __iomem *addr, int max_caps)
2147 u32 temp, port_offset, port_count;
2149 u8 major_revision, minor_revision, tmp_minor_revision;
2150 struct xhci_hub *rhub;
2151 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2152 struct xhci_port_cap *port_cap;
2155 major_revision = XHCI_EXT_PORT_MAJOR(temp);
2156 minor_revision = XHCI_EXT_PORT_MINOR(temp);
2158 if (major_revision == 0x03) {
2159 rhub = &xhci->usb3_rhub;
2161 * Some hosts incorrectly use sub-minor version for minor
2162 * version (i.e. 0x02 instead of 0x20 for bcdUSB 0x320 and 0x01
2163 * for bcdUSB 0x310). Since there is no USB release with sub
2164 * minor version 0x301 to 0x309, we can assume that they are
2165 * incorrect and fix it here.
2167 if (minor_revision > 0x00 && minor_revision < 0x10)
2168 minor_revision <<= 4;
2170 * Some zhaoxin's xHCI controller that follow usb3.1 spec
2171 * but only support Gen1.
2173 if (xhci->quirks & XHCI_ZHAOXIN_HOST) {
2174 tmp_minor_revision = minor_revision;
2178 } else if (major_revision <= 0x02) {
2179 rhub = &xhci->usb2_rhub;
2181 xhci_warn(xhci, "Ignoring unknown port speed, "
2182 "Ext Cap %p, revision = 0x%x\n",
2183 addr, major_revision);
2184 /* Ignoring port protocol we can't understand. FIXME */
2188 /* Port offset and count in the third dword, see section 7.2 */
2189 temp = readl(addr + 2);
2190 port_offset = XHCI_EXT_PORT_OFF(temp);
2191 port_count = XHCI_EXT_PORT_COUNT(temp);
2192 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2193 "Ext Cap %p, port offset = %u, "
2194 "count = %u, revision = 0x%x",
2195 addr, port_offset, port_count, major_revision);
2196 /* Port count includes the current port offset */
2197 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2198 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2201 port_cap = &xhci->port_caps[xhci->num_port_caps++];
2202 if (xhci->num_port_caps > max_caps)
2205 port_cap->psi_count = XHCI_EXT_PORT_PSIC(temp);
2207 if (port_cap->psi_count) {
2208 port_cap->psi = kcalloc_node(port_cap->psi_count,
2209 sizeof(*port_cap->psi),
2210 GFP_KERNEL, dev_to_node(dev));
2212 port_cap->psi_count = 0;
2214 port_cap->psi_uid_count++;
2215 for (i = 0; i < port_cap->psi_count; i++) {
2216 port_cap->psi[i] = readl(addr + 4 + i);
2218 /* count unique ID values, two consecutive entries can
2219 * have the same ID if link is assymetric
2221 if (i && (XHCI_EXT_PORT_PSIV(port_cap->psi[i]) !=
2222 XHCI_EXT_PORT_PSIV(port_cap->psi[i - 1])))
2223 port_cap->psi_uid_count++;
2225 if (xhci->quirks & XHCI_ZHAOXIN_HOST &&
2226 major_revision == 0x03 &&
2227 XHCI_EXT_PORT_PSIV(port_cap->psi[i]) >= 5)
2228 minor_revision = tmp_minor_revision;
2230 xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2231 XHCI_EXT_PORT_PSIV(port_cap->psi[i]),
2232 XHCI_EXT_PORT_PSIE(port_cap->psi[i]),
2233 XHCI_EXT_PORT_PLT(port_cap->psi[i]),
2234 XHCI_EXT_PORT_PFD(port_cap->psi[i]),
2235 XHCI_EXT_PORT_LP(port_cap->psi[i]),
2236 XHCI_EXT_PORT_PSIM(port_cap->psi[i]));
2240 rhub->maj_rev = major_revision;
2242 if (rhub->min_rev < minor_revision)
2243 rhub->min_rev = minor_revision;
2245 port_cap->maj_rev = major_revision;
2246 port_cap->min_rev = minor_revision;
2248 /* cache usb2 port capabilities */
2249 if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2250 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2252 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03) &&
2253 (temp & XHCI_HLC)) {
2254 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2255 "xHCI 1.0: support USB2 hardware lpm");
2256 xhci->hw_lpm_support = 1;
2260 for (i = port_offset; i < (port_offset + port_count); i++) {
2261 struct xhci_port *hw_port = &xhci->hw_ports[i];
2262 /* Duplicate entry. Ignore the port if the revisions differ. */
2263 if (hw_port->rhub) {
2264 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2265 " port %u\n", addr, i);
2266 xhci_warn(xhci, "Port was marked as USB %u, "
2267 "duplicated as USB %u\n",
2268 hw_port->rhub->maj_rev, major_revision);
2269 /* Only adjust the roothub port counts if we haven't
2270 * found a similar duplicate.
2272 if (hw_port->rhub != rhub &&
2273 hw_port->hcd_portnum != DUPLICATE_ENTRY) {
2274 hw_port->rhub->num_ports--;
2275 hw_port->hcd_portnum = DUPLICATE_ENTRY;
2279 hw_port->rhub = rhub;
2280 hw_port->port_cap = port_cap;
2283 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2286 static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
2287 struct xhci_hub *rhub, gfp_t flags)
2291 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2293 if (!rhub->num_ports)
2295 rhub->ports = kcalloc_node(rhub->num_ports, sizeof(*rhub->ports),
2296 flags, dev_to_node(dev));
2300 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
2301 if (xhci->hw_ports[i].rhub != rhub ||
2302 xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
2304 xhci->hw_ports[i].hcd_portnum = port_index;
2305 rhub->ports[port_index] = &xhci->hw_ports[i];
2307 if (port_index == rhub->num_ports)
2313 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2314 * specify what speeds each port is supposed to be. We can't count on the port
2315 * speed bits in the PORTSC register being correct until a device is connected,
2316 * but we need to set up the two fake roothubs with the correct number of USB
2317 * 3.0 and USB 2.0 ports at host controller initialization time.
2319 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2323 unsigned int num_ports;
2327 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2329 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2330 xhci->hw_ports = kcalloc_node(num_ports, sizeof(*xhci->hw_ports),
2331 flags, dev_to_node(dev));
2332 if (!xhci->hw_ports)
2335 for (i = 0; i < num_ports; i++) {
2336 xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base +
2338 xhci->hw_ports[i].hw_portnum = i;
2340 init_completion(&xhci->hw_ports[i].rexit_done);
2341 init_completion(&xhci->hw_ports[i].u3exit_done);
2344 xhci->rh_bw = kcalloc_node(num_ports, sizeof(*xhci->rh_bw), flags,
2348 for (i = 0; i < num_ports; i++) {
2349 struct xhci_interval_bw_table *bw_table;
2351 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2352 bw_table = &xhci->rh_bw[i].bw_table;
2353 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2354 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2356 base = &xhci->cap_regs->hc_capbase;
2358 cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL);
2360 xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2365 /* count extended protocol capability entries for later caching */
2368 offset = xhci_find_next_ext_cap(base, offset,
2369 XHCI_EXT_CAPS_PROTOCOL);
2372 xhci->ext_caps = kcalloc_node(cap_count, sizeof(*xhci->ext_caps),
2373 flags, dev_to_node(dev));
2374 if (!xhci->ext_caps)
2377 xhci->port_caps = kcalloc_node(cap_count, sizeof(*xhci->port_caps),
2378 flags, dev_to_node(dev));
2379 if (!xhci->port_caps)
2385 xhci_add_in_port(xhci, num_ports, base + offset, cap_count);
2386 if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports ==
2389 offset = xhci_find_next_ext_cap(base, offset,
2390 XHCI_EXT_CAPS_PROTOCOL);
2392 if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) {
2393 xhci_warn(xhci, "No ports on the roothubs?\n");
2396 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2397 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2398 xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports);
2400 /* Place limits on the number of roothub ports so that the hub
2401 * descriptors aren't longer than the USB core will allocate.
2403 if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) {
2404 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2405 "Limiting USB 3.0 roothub ports to %u.",
2407 xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS;
2409 if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) {
2410 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2411 "Limiting USB 2.0 roothub ports to %u.",
2413 xhci->usb2_rhub.num_ports = USB_MAXCHILDREN;
2417 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2418 * Not sure how the USB core will handle a hub with no ports...
2421 xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags);
2422 xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags);
2427 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2430 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2431 unsigned int val, val2;
2433 u32 page_size, temp;
2436 INIT_LIST_HEAD(&xhci->cmd_list);
2438 /* init command timeout work */
2439 INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout);
2440 init_completion(&xhci->cmd_ring_stop_completion);
2442 page_size = readl(&xhci->op_regs->page_size);
2443 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2444 "Supported page size register = 0x%x", page_size);
2445 for (i = 0; i < 16; i++) {
2446 if ((0x1 & page_size) != 0)
2448 page_size = page_size >> 1;
2451 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2452 "Supported page size of %iK", (1 << (i+12)) / 1024);
2454 xhci_warn(xhci, "WARN: no supported page size\n");
2455 /* Use 4K pages, since that's common and the minimum the HC supports */
2456 xhci->page_shift = 12;
2457 xhci->page_size = 1 << xhci->page_shift;
2458 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2459 "HCD page size set to %iK", xhci->page_size / 1024);
2462 * Program the Number of Device Slots Enabled field in the CONFIG
2463 * register with the max value of slots the HC can handle.
2465 val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2466 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2467 "// xHC can handle at most %d device slots.", val);
2468 val2 = readl(&xhci->op_regs->config_reg);
2469 val |= (val2 & ~HCS_SLOTS_MASK);
2470 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2471 "// Setting Max device slots reg = 0x%x.", val);
2472 writel(val, &xhci->op_regs->config_reg);
2475 * xHCI section 5.4.6 - doorbell array must be
2476 * "physically contiguous and 64-byte (cache line) aligned".
2478 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2482 xhci->dcbaa->dma = dma;
2483 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2484 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2485 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2486 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2489 * Initialize the ring segment pool. The ring must be a contiguous
2490 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2491 * however, the command ring segment needs 64-byte aligned segments
2492 * and our use of dma addresses in the trb_address_map radix tree needs
2493 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2495 if (xhci->quirks & XHCI_ZHAOXIN_TRB_FETCH)
2496 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2497 TRB_SEGMENT_SIZE * 2, TRB_SEGMENT_SIZE * 2, xhci->page_size * 2);
2499 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2500 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2502 /* See Table 46 and Note on Figure 55 */
2503 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2504 2112, 64, xhci->page_size);
2505 if (!xhci->segment_pool || !xhci->device_pool)
2508 /* Linear stream context arrays don't have any boundary restrictions,
2509 * and only need to be 16-byte aligned.
2511 xhci->small_streams_pool =
2512 dma_pool_create("xHCI 256 byte stream ctx arrays",
2513 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2514 xhci->medium_streams_pool =
2515 dma_pool_create("xHCI 1KB stream ctx arrays",
2516 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2517 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2518 * will be allocated with dma_alloc_coherent()
2521 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2524 /* Set up the command ring to have one segments for now. */
2525 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags);
2526 if (!xhci->cmd_ring)
2528 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2529 "Allocated command ring at %p", xhci->cmd_ring);
2530 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx",
2531 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2533 /* Set the address in the Command Ring Control register */
2534 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2535 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2536 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2537 xhci->cmd_ring->cycle_state;
2538 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2539 "// Setting command ring address to 0x%016llx", val_64);
2540 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2542 xhci->lpm_command = xhci_alloc_command_with_ctx(xhci, true, flags);
2543 if (!xhci->lpm_command)
2546 /* Reserve one command ring TRB for disabling LPM.
2547 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2548 * disabling LPM, we only need to reserve one TRB for all devices.
2550 xhci->cmd_ring_reserved_trbs++;
2552 val = readl(&xhci->cap_regs->db_off);
2554 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2555 "// Doorbell array is located at offset 0x%x"
2556 " from cap regs base addr", val);
2557 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2558 /* Set ir_set to interrupt register set 0 */
2559 xhci->ir_set = &xhci->run_regs->ir_set[0];
2562 * Event ring setup: Allocate a normal ring, but also setup
2563 * the event ring segment table (ERST). Section 4.9.3.
2565 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring");
2566 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2568 if (!xhci->event_ring)
2570 if (xhci_check_trb_in_td_math(xhci) < 0)
2573 ret = xhci_alloc_erst(xhci, xhci->event_ring, &xhci->erst, flags);
2577 /* set ERST count with the number of entries in the segment table */
2578 val = readl(&xhci->ir_set->erst_size);
2579 val &= ERST_SIZE_MASK;
2580 val |= ERST_NUM_SEGS;
2581 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2582 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2584 writel(val, &xhci->ir_set->erst_size);
2586 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2587 "// Set ERST entries to point to event ring.");
2588 /* set the segment table base address */
2589 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2590 "// Set ERST base address for ir_set 0 = 0x%llx",
2591 (unsigned long long)xhci->erst.erst_dma_addr);
2592 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2593 val_64 &= ERST_PTR_MASK;
2594 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2595 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2597 /* Set the event ring dequeue address */
2598 xhci_set_hc_event_deq(xhci);
2599 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2600 "Wrote ERST address to ir_set 0.");
2603 * XXX: Might need to set the Interrupter Moderation Register to
2604 * something other than the default (~1ms minimum between interrupts).
2605 * See section 5.5.1.2.
2607 for (i = 0; i < MAX_HC_SLOTS; i++)
2608 xhci->devs[i] = NULL;
2610 if (scratchpad_alloc(xhci, flags))
2612 if (xhci_setup_port_arrays(xhci, flags))
2615 /* Enable USB 3.0 device notifications for function remote wake, which
2616 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2617 * U3 (device suspend).
2619 temp = readl(&xhci->op_regs->dev_notification);
2620 temp &= ~DEV_NOTE_MASK;
2621 temp |= DEV_NOTE_FWAKE;
2622 writel(temp, &xhci->op_regs->dev_notification);
2628 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
2629 xhci_mem_cleanup(xhci);