2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
72 u16 desc_size, ssp_cap_size, ssa_size = 0;
75 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
76 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci->usb3_rhub.min_rev >= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci->usb3_rhub.psi_count) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
84 ssa_size = ssa_count * sizeof(u32);
85 ssp_cap_size -= 16; /* skip copying the default SSA */
87 desc_size += ssp_cap_size;
90 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
95 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
101 /* Indicate whether the host has LTM support. */
102 temp = readl(&xhci->cap_regs->hcc_params);
104 buf[8] |= USB_LTM_SUPPORT;
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
108 temp = readl(&xhci->cap_regs->hcs_params3);
109 buf[12] = HCS_U1_LATENCY(temp);
110 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1 && xhci->usb3_rhub.psi_count) {
115 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
118 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
120 if (wLength < desc_size)
122 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib = (ssa_count - 1) & 0x1f;
126 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
127 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
129 if (wLength < desc_size + ssa_size)
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
139 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
140 psi = xhci->usb3_rhub.psi[i];
141 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
142 psi_exp = XHCI_EXT_PORT_PSIE(psi);
143 psi_mant = XHCI_EXT_PORT_PSIM(psi);
145 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
146 for (; psi_exp < 3; psi_exp++)
151 if ((psi & PLT_MASK) == PLT_SYM) {
152 /* Symmetric, create SSA RX and TX from one PSI entry */
153 put_unaligned_le32(psi, &buf[offset]);
154 psi |= 1 << 7; /* turn entry to TX */
156 if (offset >= desc_size + ssa_size)
157 return desc_size + ssa_size;
158 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
159 /* Asymetric RX, flip bits 7:6 for SSA */
162 put_unaligned_le32(psi, &buf[offset]);
164 if (offset >= desc_size + ssa_size)
165 return desc_size + ssa_size;
168 /* ssa_size is 0 for other than usb 3.1 hosts */
169 return desc_size + ssa_size;
172 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
173 struct usb_hub_descriptor *desc, int ports)
177 desc->bHubContrCurrent = 0;
179 desc->bNbrPorts = ports;
181 /* Bits 1:0 - support per-port power switching, or power always on */
182 if (HCC_PPC(xhci->hcc_params))
183 temp |= HUB_CHAR_INDV_PORT_LPSM;
185 temp |= HUB_CHAR_NO_LPSM;
186 /* Bit 2 - root hubs are not part of a compound device */
187 /* Bits 4:3 - individual port over current protection */
188 temp |= HUB_CHAR_INDV_PORT_OCPM;
189 /* Bits 6:5 - no TTs in root ports */
190 /* Bit 7 - no port indicators */
191 desc->wHubCharacteristics = cpu_to_le16(temp);
194 /* Fill in the USB 2.0 roothub descriptor */
195 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
196 struct usb_hub_descriptor *desc)
200 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
204 ports = xhci->num_usb2_ports;
206 xhci_common_hub_descriptor(xhci, desc, ports);
207 desc->bDescriptorType = USB_DT_HUB;
208 temp = 1 + (ports / 8);
209 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
210 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */
212 /* The Device Removable bits are reported on a byte granularity.
213 * If the port doesn't exist within that byte, the bit is set to 0.
215 memset(port_removable, 0, sizeof(port_removable));
216 for (i = 0; i < ports; i++) {
217 portsc = readl(xhci->usb2_ports[i]);
218 /* If a device is removable, PORTSC reports a 0, same as in the
219 * hub descriptor DeviceRemovable bits.
221 if (portsc & PORT_DEV_REMOVE)
222 /* This math is hairy because bit 0 of DeviceRemovable
223 * is reserved, and bit 1 is for port 1, etc.
225 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
228 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
229 * ports on it. The USB 2.0 specification says that there are two
230 * variable length fields at the end of the hub descriptor:
231 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
232 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
233 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
234 * 0xFF, so we initialize the both arrays (DeviceRemovable and
235 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
236 * set of ports that actually exist.
238 memset(desc->u.hs.DeviceRemovable, 0xff,
239 sizeof(desc->u.hs.DeviceRemovable));
240 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
241 sizeof(desc->u.hs.PortPwrCtrlMask));
243 for (i = 0; i < (ports + 1 + 7) / 8; i++)
244 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
248 /* Fill in the USB 3.0 roothub descriptor */
249 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
250 struct usb_hub_descriptor *desc)
257 ports = xhci->num_usb3_ports;
258 xhci_common_hub_descriptor(xhci, desc, ports);
259 desc->bDescriptorType = USB_DT_SS_HUB;
260 desc->bDescLength = USB_DT_SS_HUB_SIZE;
261 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */
263 /* header decode latency should be zero for roothubs,
264 * see section 4.23.5.2.
266 desc->u.ss.bHubHdrDecLat = 0;
267 desc->u.ss.wHubDelay = 0;
270 /* bit 0 is reserved, bit 1 is for port 1, etc. */
271 for (i = 0; i < ports; i++) {
272 portsc = readl(xhci->usb3_ports[i]);
273 if (portsc & PORT_DEV_REMOVE)
274 port_removable |= 1 << (i + 1);
277 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
281 struct usb_hub_descriptor *desc)
284 if (hcd->speed >= HCD_USB3)
285 xhci_usb3_hub_descriptor(hcd, xhci, desc);
287 xhci_usb2_hub_descriptor(hcd, xhci, desc);
291 static unsigned int xhci_port_speed(unsigned int port_status)
293 if (DEV_LOWSPEED(port_status))
294 return USB_PORT_STAT_LOW_SPEED;
295 if (DEV_HIGHSPEED(port_status))
296 return USB_PORT_STAT_HIGH_SPEED;
298 * FIXME: Yes, we should check for full speed, but the core uses that as
299 * a default in portspeed() in usb/core/hub.c (which is the only place
300 * USB_PORT_STAT_*_SPEED is used).
306 * These bits are Read Only (RO) and should be saved and written to the
307 * registers: 0, 3, 10:13, 30
308 * connect status, over-current status, port speed, and device removable.
309 * connect status and port speed are also sticky - meaning they're in
310 * the AUX well and they aren't changed by a hot, warm, or cold reset.
312 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
314 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
315 * bits 5:8, 9, 14:15, 25:27
316 * link state, port power, port indicator state, "wake on" enable state
318 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
320 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
323 #define XHCI_PORT_RW1S ((1<<4))
325 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
326 * bits 1, 17, 18, 19, 20, 21, 22, 23
327 * port enable/disable, and
328 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
329 * over-current, reset, link state, and L1 change
331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
333 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
336 #define XHCI_PORT_RW ((1<<16))
338 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
341 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
344 * Given a port state, this function returns a value that would result in the
345 * port being in the same state, if the value was written to the port status
347 * Save Read Only (RO) bits and save read/write bits where
348 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
349 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
351 u32 xhci_port_state_to_neutral(u32 state)
353 /* Save read-only status and port state */
354 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
358 * find slot id based on port number.
359 * @port: The one-based port number from one of the two split roothubs.
361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
366 enum usb_device_speed speed;
369 for (i = 0; i < MAX_HC_SLOTS; i++) {
370 if (!xhci->devs[i] || !xhci->devs[i]->udev)
372 speed = xhci->devs[i]->udev->speed;
373 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
374 && xhci->devs[i]->fake_port == port) {
385 * It issues stop endpoint command for EP 0 to 30. And wait the last command
387 * suspend will set to 1, if suspend bit need to set in command.
389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
391 struct xhci_virt_device *virt_dev;
392 struct xhci_command *cmd;
398 virt_dev = xhci->devs[slot_id];
402 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
404 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
408 spin_lock_irqsave(&xhci->lock, flags);
409 for (i = LAST_EP_INDEX; i > 0; i--) {
410 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
411 struct xhci_command *command;
412 command = xhci_alloc_command(xhci, false, false,
415 spin_unlock_irqrestore(&xhci->lock, flags);
420 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
423 spin_unlock_irqrestore(&xhci->lock, flags);
424 xhci_free_command(xhci, command);
429 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
431 spin_unlock_irqrestore(&xhci->lock, flags);
435 xhci_ring_cmd_db(xhci);
436 spin_unlock_irqrestore(&xhci->lock, flags);
438 /* Wait for last stop endpoint command to finish */
439 wait_for_completion(cmd->completion);
441 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
442 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
447 xhci_free_command(xhci, cmd);
452 * Ring device, it rings the all doorbells unconditionally.
454 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
457 struct xhci_virt_ep *ep;
459 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
460 ep = &xhci->devs[slot_id]->eps[i];
462 if (ep->ep_state & EP_HAS_STREAMS) {
463 for (s = 1; s < ep->stream_info->num_streams; s++)
464 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
465 } else if (ep->ring && ep->ring->dequeue) {
466 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
473 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
474 u16 wIndex, __le32 __iomem *addr, u32 port_status)
476 /* Don't allow the USB core to disable SuperSpeed ports. */
477 if (hcd->speed >= HCD_USB3) {
478 xhci_dbg(xhci, "Ignoring request to disable "
479 "SuperSpeed port.\n");
483 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
485 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
489 /* Write 1 to disable the port */
490 writel(port_status | PORT_PE, addr);
491 port_status = readl(addr);
492 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
493 wIndex, port_status);
496 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
497 u16 wIndex, __le32 __iomem *addr, u32 port_status)
499 char *port_change_bit;
503 case USB_PORT_FEAT_C_RESET:
505 port_change_bit = "reset";
507 case USB_PORT_FEAT_C_BH_PORT_RESET:
509 port_change_bit = "warm(BH) reset";
511 case USB_PORT_FEAT_C_CONNECTION:
513 port_change_bit = "connect";
515 case USB_PORT_FEAT_C_OVER_CURRENT:
517 port_change_bit = "over-current";
519 case USB_PORT_FEAT_C_ENABLE:
521 port_change_bit = "enable/disable";
523 case USB_PORT_FEAT_C_SUSPEND:
525 port_change_bit = "suspend/resume";
527 case USB_PORT_FEAT_C_PORT_LINK_STATE:
529 port_change_bit = "link state";
531 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
533 port_change_bit = "config error";
536 /* Should never happen */
539 /* Change bits are all write 1 to clear */
540 writel(port_status | status, addr);
541 port_status = readl(addr);
542 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
543 port_change_bit, wIndex, port_status);
546 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
549 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
551 if (hcd->speed >= HCD_USB3) {
552 max_ports = xhci->num_usb3_ports;
553 *port_array = xhci->usb3_ports;
555 max_ports = xhci->num_usb2_ports;
556 *port_array = xhci->usb2_ports;
562 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
563 int port_id, u32 link_state)
567 temp = readl(port_array[port_id]);
568 temp = xhci_port_state_to_neutral(temp);
569 temp &= ~PORT_PLS_MASK;
570 temp |= PORT_LINK_STROBE | link_state;
571 writel(temp, port_array[port_id]);
574 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
575 __le32 __iomem **port_array, int port_id, u16 wake_mask)
579 temp = readl(port_array[port_id]);
580 temp = xhci_port_state_to_neutral(temp);
582 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
583 temp |= PORT_WKCONN_E;
585 temp &= ~PORT_WKCONN_E;
587 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
588 temp |= PORT_WKDISC_E;
590 temp &= ~PORT_WKDISC_E;
592 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
595 temp &= ~PORT_WKOC_E;
597 writel(temp, port_array[port_id]);
600 /* Test and clear port RWC bit */
601 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
602 int port_id, u32 port_bit)
606 temp = readl(port_array[port_id]);
607 if (temp & port_bit) {
608 temp = xhci_port_state_to_neutral(temp);
610 writel(temp, port_array[port_id]);
614 /* Updates Link Status for USB 2.1 port */
615 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
617 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
618 *status |= USB_PORT_STAT_L1;
621 /* Updates Link Status for super Speed port */
622 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
623 u32 *status, u32 status_reg)
625 u32 pls = status_reg & PORT_PLS_MASK;
627 /* When the CAS bit is set then warm reset
628 * should be performed on port
630 if (status_reg & PORT_CAS) {
631 /* The CAS bit can be set while the port is
633 * Only roothubs have CAS bit, so we
634 * pretend to be in compliance mode
635 * unless we're already in compliance
636 * or the inactive state.
638 if (pls != USB_SS_PORT_LS_COMP_MOD &&
639 pls != USB_SS_PORT_LS_SS_INACTIVE) {
640 pls = USB_SS_PORT_LS_COMP_MOD;
642 /* Return also connection bit -
643 * hub state machine resets port
644 * when this bit is set.
646 pls |= USB_PORT_STAT_CONNECTION;
649 * Resume state is an xHCI internal state. Do not report it to
650 * usb core, instead, pretend to be U3, thus usb core knows
651 * it's not ready for transfer.
653 if (pls == XDEV_RESUME) {
654 *status |= USB_SS_PORT_LS_U3;
659 * If CAS bit isn't set but the Port is already at
660 * Compliance Mode, fake a connection so the USB core
661 * notices the Compliance state and resets the port.
662 * This resolves an issue generated by the SN65LVPE502CP
663 * in which sometimes the port enters compliance mode
664 * caused by a delay on the host-device negotiation.
666 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
667 (pls == USB_SS_PORT_LS_COMP_MOD))
668 pls |= USB_PORT_STAT_CONNECTION;
671 /* update status field */
676 * Function for Compliance Mode Quirk.
678 * This Function verifies if all xhc USB3 ports have entered U0, if so,
679 * the compliance mode timer is deleted. A port won't enter
680 * compliance mode if it has previously entered U0.
682 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
685 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
686 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
688 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
691 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
692 xhci->port_status_u0 |= 1 << wIndex;
693 if (xhci->port_status_u0 == all_ports_seen_u0) {
694 del_timer_sync(&xhci->comp_mode_recovery_timer);
695 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
696 "All USB3 ports have entered U0 already!");
697 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
698 "Compliance Mode Recovery Timer Deleted.");
703 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
708 /* only support rx and tx lane counts of 1 in usb3.1 spec */
709 speed_id = DEV_PORT_SPEED(raw_port_status);
710 ext_stat |= speed_id; /* bits 3:0, RX speed id */
711 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
713 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
714 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
720 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
723 * Possible side effects:
724 * - Mark a port as being done with device resume,
725 * and ring the endpoint doorbells.
726 * - Stop the Synopsys redriver Compliance Mode polling.
727 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
729 static u32 xhci_get_port_status(struct usb_hcd *hcd,
730 struct xhci_bus_state *bus_state,
731 __le32 __iomem **port_array,
732 u16 wIndex, u32 raw_port_status,
733 unsigned long *flags)
734 __releases(&xhci->lock)
735 __acquires(&xhci->lock)
737 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
741 /* wPortChange bits */
742 if (raw_port_status & PORT_CSC)
743 status |= USB_PORT_STAT_C_CONNECTION << 16;
744 if (raw_port_status & PORT_PEC)
745 status |= USB_PORT_STAT_C_ENABLE << 16;
746 if ((raw_port_status & PORT_OCC))
747 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
748 if ((raw_port_status & PORT_RC))
749 status |= USB_PORT_STAT_C_RESET << 16;
751 if (hcd->speed >= HCD_USB3) {
752 /* Port link change with port in resume state should not be
753 * reported to usbcore, as this is an internal state to be
754 * handled by xhci driver. Reporting PLC to usbcore may
755 * cause usbcore clearing PLC first and port change event
756 * irq won't be generated.
758 if ((raw_port_status & PORT_PLC) &&
759 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
760 status |= USB_PORT_STAT_C_LINK_STATE << 16;
761 if ((raw_port_status & PORT_WRC))
762 status |= USB_PORT_STAT_C_BH_RESET << 16;
763 if ((raw_port_status & PORT_CEC))
764 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
766 /* USB3 remote wake resume signaling completed */
767 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
768 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
769 (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
770 bus_state->port_remote_wakeup &= ~(1 << wIndex);
771 usb_hcd_end_port_resume(&hcd->self, wIndex);
775 if (hcd->speed < HCD_USB3) {
776 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
777 && (raw_port_status & PORT_POWER))
778 status |= USB_PORT_STAT_SUSPEND;
780 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
781 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
782 if ((raw_port_status & PORT_RESET) ||
783 !(raw_port_status & PORT_PE))
785 /* did port event handler already start resume timing? */
786 if (!bus_state->resume_done[wIndex]) {
787 /* If not, maybe we are in a host initated resume? */
788 if (test_bit(wIndex, &bus_state->resuming_ports)) {
789 /* Host initated resume doesn't time the resume
790 * signalling using resume_done[].
791 * It manually sets RESUME state, sleeps 20ms
792 * and sets U0 state. This should probably be
793 * changed, but not right now.
796 /* port resume was discovered now and here,
797 * start resume timing
799 unsigned long timeout = jiffies +
800 msecs_to_jiffies(USB_RESUME_TIMEOUT);
802 set_bit(wIndex, &bus_state->resuming_ports);
803 bus_state->resume_done[wIndex] = timeout;
804 mod_timer(&hcd->rh_timer, timeout);
806 /* Has resume been signalled for USB_RESUME_TIME yet? */
807 } else if (time_after_eq(jiffies,
808 bus_state->resume_done[wIndex])) {
811 xhci_dbg(xhci, "Resume USB2 port %d\n",
813 bus_state->resume_done[wIndex] = 0;
814 clear_bit(wIndex, &bus_state->resuming_ports);
816 set_bit(wIndex, &bus_state->rexit_ports);
818 xhci_test_and_clear_bit(xhci, port_array, wIndex,
820 xhci_set_link_state(xhci, port_array, wIndex,
823 spin_unlock_irqrestore(&xhci->lock, *flags);
824 time_left = wait_for_completion_timeout(
825 &bus_state->rexit_done[wIndex],
827 XHCI_MAX_REXIT_TIMEOUT_MS));
828 spin_lock_irqsave(&xhci->lock, *flags);
831 slot_id = xhci_find_slot_id_by_port(hcd,
834 xhci_dbg(xhci, "slot_id is zero\n");
837 xhci_ring_device(xhci, slot_id);
839 int port_status = readl(port_array[wIndex]);
840 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
841 XHCI_MAX_REXIT_TIMEOUT_MS,
843 status |= USB_PORT_STAT_SUSPEND;
844 clear_bit(wIndex, &bus_state->rexit_ports);
847 bus_state->port_c_suspend |= 1 << wIndex;
848 bus_state->suspended_ports &= ~(1 << wIndex);
851 * The resume has been signaling for less than
852 * USB_RESUME_TIME. Report the port status as SUSPEND,
853 * let the usbcore check port status again and clear
854 * resume signaling later.
856 status |= USB_PORT_STAT_SUSPEND;
860 * Clear stale usb2 resume signalling variables in case port changed
861 * state during resume signalling. For example on error
863 if ((bus_state->resume_done[wIndex] ||
864 test_bit(wIndex, &bus_state->resuming_ports)) &&
865 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
866 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
867 bus_state->resume_done[wIndex] = 0;
868 clear_bit(wIndex, &bus_state->resuming_ports);
872 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
873 (raw_port_status & PORT_POWER)) {
874 if (bus_state->suspended_ports & (1 << wIndex)) {
875 bus_state->suspended_ports &= ~(1 << wIndex);
876 if (hcd->speed < HCD_USB3)
877 bus_state->port_c_suspend |= 1 << wIndex;
879 bus_state->resume_done[wIndex] = 0;
880 clear_bit(wIndex, &bus_state->resuming_ports);
882 if (raw_port_status & PORT_CONNECT) {
883 status |= USB_PORT_STAT_CONNECTION;
884 status |= xhci_port_speed(raw_port_status);
886 if (raw_port_status & PORT_PE)
887 status |= USB_PORT_STAT_ENABLE;
888 if (raw_port_status & PORT_OC)
889 status |= USB_PORT_STAT_OVERCURRENT;
890 if (raw_port_status & PORT_RESET)
891 status |= USB_PORT_STAT_RESET;
892 if (raw_port_status & PORT_POWER) {
893 if (hcd->speed >= HCD_USB3)
894 status |= USB_SS_PORT_STAT_POWER;
896 status |= USB_PORT_STAT_POWER;
898 /* Update Port Link State */
899 if (hcd->speed >= HCD_USB3) {
900 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
902 * Verify if all USB3 Ports Have entered U0 already.
903 * Delete Compliance Mode Timer if so.
905 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
907 xhci_hub_report_usb2_link_state(&status, raw_port_status);
909 if (bus_state->port_c_suspend & (1 << wIndex))
910 status |= USB_PORT_STAT_C_SUSPEND << 16;
915 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
916 u16 wIndex, char *buf, u16 wLength)
918 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
923 __le32 __iomem **port_array;
925 struct xhci_bus_state *bus_state;
930 max_ports = xhci_get_ports(hcd, &port_array);
931 bus_state = &xhci->bus_state[hcd_index(hcd)];
933 spin_lock_irqsave(&xhci->lock, flags);
936 /* No power source, over-current reported per port */
939 case GetHubDescriptor:
940 /* Check to make sure userspace is asking for the USB 3.0 hub
941 * descriptor for the USB 3.0 roothub. If not, we stall the
942 * endpoint, like external hubs do.
944 if (hcd->speed >= HCD_USB3 &&
945 (wLength < USB_DT_SS_HUB_SIZE ||
946 wValue != (USB_DT_SS_HUB << 8))) {
947 xhci_dbg(xhci, "Wrong hub descriptor type for "
948 "USB 3.0 roothub.\n");
951 xhci_hub_descriptor(hcd, xhci,
952 (struct usb_hub_descriptor *) buf);
954 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
955 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
958 if (hcd->speed < HCD_USB3)
961 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
962 spin_unlock_irqrestore(&xhci->lock, flags);
965 if (!wIndex || wIndex > max_ports)
968 temp = readl(port_array[wIndex]);
969 if (temp == 0xffffffff) {
973 status = xhci_get_port_status(hcd, bus_state, port_array,
974 wIndex, temp, &flags);
975 if (status == 0xffffffff)
978 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
980 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
982 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
983 /* if USB 3.1 extended port status return additional 4 bytes */
984 if (wValue == 0x02) {
987 if (hcd->speed < HCD_USB31 || wLength != 8) {
988 xhci_err(xhci, "get ext port status invalid parameter\n");
992 port_li = readl(port_array[wIndex] + PORTLI);
993 status = xhci_get_ext_port_status(temp, port_li);
994 put_unaligned_le32(status, &buf[4]);
998 if (wValue == USB_PORT_FEAT_LINK_STATE)
999 link_state = (wIndex & 0xff00) >> 3;
1000 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1001 wake_mask = wIndex & 0xff00;
1002 /* The MSB of wIndex is the U1/U2 timeout */
1003 timeout = (wIndex & 0xff00) >> 8;
1005 if (!wIndex || wIndex > max_ports)
1008 temp = readl(port_array[wIndex]);
1009 if (temp == 0xffffffff) {
1013 temp = xhci_port_state_to_neutral(temp);
1014 /* FIXME: What new port features do we need to support? */
1016 case USB_PORT_FEAT_SUSPEND:
1017 temp = readl(port_array[wIndex]);
1018 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1019 /* Resume the port to U0 first */
1020 xhci_set_link_state(xhci, port_array, wIndex,
1022 spin_unlock_irqrestore(&xhci->lock, flags);
1024 spin_lock_irqsave(&xhci->lock, flags);
1026 /* In spec software should not attempt to suspend
1027 * a port unless the port reports that it is in the
1028 * enabled (PED = ‘1’,PLS < ‘3’) state.
1030 temp = readl(port_array[wIndex]);
1031 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1032 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1033 xhci_warn(xhci, "USB core suspending device "
1034 "not in U0/U1/U2.\n");
1038 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1041 xhci_warn(xhci, "slot_id is zero\n");
1044 /* unlock to execute stop endpoint commands */
1045 spin_unlock_irqrestore(&xhci->lock, flags);
1046 xhci_stop_device(xhci, slot_id, 1);
1047 spin_lock_irqsave(&xhci->lock, flags);
1049 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1051 spin_unlock_irqrestore(&xhci->lock, flags);
1052 msleep(10); /* wait device to enter */
1053 spin_lock_irqsave(&xhci->lock, flags);
1055 temp = readl(port_array[wIndex]);
1056 bus_state->suspended_ports |= 1 << wIndex;
1058 case USB_PORT_FEAT_LINK_STATE:
1059 temp = readl(port_array[wIndex]);
1062 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1063 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1064 temp = xhci_port_state_to_neutral(temp);
1066 * Clear all change bits, so that we get a new
1069 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1070 PORT_OCC | PORT_RC | PORT_PLC |
1072 writel(temp | PORT_PE, port_array[wIndex]);
1073 temp = readl(port_array[wIndex]);
1077 /* Put link in RxDetect (enable port) */
1078 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1079 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1080 xhci_set_link_state(xhci, port_array, wIndex,
1082 temp = readl(port_array[wIndex]);
1085 /* Port must be enabled */
1086 if (!(temp & PORT_PE)) {
1090 /* Can't set port link state above '3' (U3) */
1091 if (link_state > USB_SS_PORT_LS_U3) {
1092 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1093 wIndex, link_state);
1096 if (link_state == USB_SS_PORT_LS_U3) {
1097 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1100 /* unlock to execute stop endpoint
1102 spin_unlock_irqrestore(&xhci->lock,
1104 xhci_stop_device(xhci, slot_id, 1);
1105 spin_lock_irqsave(&xhci->lock, flags);
1109 xhci_set_link_state(xhci, port_array, wIndex,
1112 spin_unlock_irqrestore(&xhci->lock, flags);
1113 msleep(20); /* wait device to enter */
1114 spin_lock_irqsave(&xhci->lock, flags);
1116 temp = readl(port_array[wIndex]);
1117 if (link_state == USB_SS_PORT_LS_U3)
1118 bus_state->suspended_ports |= 1 << wIndex;
1120 case USB_PORT_FEAT_POWER:
1122 * Turn on ports, even if there isn't per-port switching.
1123 * HC will report connect events even before this is set.
1124 * However, hub_wq will ignore the roothub events until
1125 * the roothub is registered.
1127 writel(temp | PORT_POWER, port_array[wIndex]);
1129 temp = readl(port_array[wIndex]);
1130 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
1132 spin_unlock_irqrestore(&xhci->lock, flags);
1133 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1136 usb_acpi_set_power_state(hcd->self.root_hub,
1138 spin_lock_irqsave(&xhci->lock, flags);
1140 case USB_PORT_FEAT_RESET:
1141 temp = (temp | PORT_RESET);
1142 writel(temp, port_array[wIndex]);
1144 temp = readl(port_array[wIndex]);
1145 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1147 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1148 xhci_set_remote_wake_mask(xhci, port_array,
1150 temp = readl(port_array[wIndex]);
1151 xhci_dbg(xhci, "set port remote wake mask, "
1152 "actual port %d status = 0x%x\n",
1155 case USB_PORT_FEAT_BH_PORT_RESET:
1157 writel(temp, port_array[wIndex]);
1159 temp = readl(port_array[wIndex]);
1161 case USB_PORT_FEAT_U1_TIMEOUT:
1162 if (hcd->speed < HCD_USB3)
1164 temp = readl(port_array[wIndex] + PORTPMSC);
1165 temp &= ~PORT_U1_TIMEOUT_MASK;
1166 temp |= PORT_U1_TIMEOUT(timeout);
1167 writel(temp, port_array[wIndex] + PORTPMSC);
1169 case USB_PORT_FEAT_U2_TIMEOUT:
1170 if (hcd->speed < HCD_USB3)
1172 temp = readl(port_array[wIndex] + PORTPMSC);
1173 temp &= ~PORT_U2_TIMEOUT_MASK;
1174 temp |= PORT_U2_TIMEOUT(timeout);
1175 writel(temp, port_array[wIndex] + PORTPMSC);
1180 /* unblock any posted writes */
1181 temp = readl(port_array[wIndex]);
1183 case ClearPortFeature:
1184 if (!wIndex || wIndex > max_ports)
1187 temp = readl(port_array[wIndex]);
1188 if (temp == 0xffffffff) {
1192 /* FIXME: What new port features do we need to support? */
1193 temp = xhci_port_state_to_neutral(temp);
1195 case USB_PORT_FEAT_SUSPEND:
1196 temp = readl(port_array[wIndex]);
1197 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1198 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1199 if (temp & PORT_RESET)
1201 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1202 if ((temp & PORT_PE) == 0)
1205 set_bit(wIndex, &bus_state->resuming_ports);
1206 xhci_set_link_state(xhci, port_array, wIndex,
1208 spin_unlock_irqrestore(&xhci->lock, flags);
1209 msleep(USB_RESUME_TIMEOUT);
1210 spin_lock_irqsave(&xhci->lock, flags);
1211 xhci_set_link_state(xhci, port_array, wIndex,
1213 clear_bit(wIndex, &bus_state->resuming_ports);
1215 bus_state->port_c_suspend |= 1 << wIndex;
1217 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1220 xhci_dbg(xhci, "slot_id is zero\n");
1223 xhci_ring_device(xhci, slot_id);
1225 case USB_PORT_FEAT_C_SUSPEND:
1226 bus_state->port_c_suspend &= ~(1 << wIndex);
1227 case USB_PORT_FEAT_C_RESET:
1228 case USB_PORT_FEAT_C_BH_PORT_RESET:
1229 case USB_PORT_FEAT_C_CONNECTION:
1230 case USB_PORT_FEAT_C_OVER_CURRENT:
1231 case USB_PORT_FEAT_C_ENABLE:
1232 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1233 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1234 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1235 port_array[wIndex], temp);
1237 case USB_PORT_FEAT_ENABLE:
1238 xhci_disable_port(hcd, xhci, wIndex,
1239 port_array[wIndex], temp);
1241 case USB_PORT_FEAT_POWER:
1242 writel(temp & ~PORT_POWER, port_array[wIndex]);
1244 spin_unlock_irqrestore(&xhci->lock, flags);
1245 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1248 usb_acpi_set_power_state(hcd->self.root_hub,
1250 spin_lock_irqsave(&xhci->lock, flags);
1258 /* "stall" on error */
1261 spin_unlock_irqrestore(&xhci->lock, flags);
1266 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1267 * Ports are 0-indexed from the HCD point of view,
1268 * and 1-indexed from the USB core pointer of view.
1270 * Note that the status change bits will be cleared as soon as a port status
1271 * change event is generated, so we use the saved status from that event.
1273 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1275 unsigned long flags;
1279 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1281 __le32 __iomem **port_array;
1282 struct xhci_bus_state *bus_state;
1283 bool reset_change = false;
1285 max_ports = xhci_get_ports(hcd, &port_array);
1286 bus_state = &xhci->bus_state[hcd_index(hcd)];
1288 /* Initial status is no changes */
1289 retval = (max_ports + 8) / 8;
1290 memset(buf, 0, retval);
1293 * Inform the usbcore about resume-in-progress by returning
1294 * a non-zero value even if there are no status changes.
1296 spin_lock_irqsave(&xhci->lock, flags);
1298 status = bus_state->resuming_ports;
1301 * SS devices are only visible to roothub after link training completes.
1302 * Keep polling roothubs for a grace period after xHC start
1304 if (xhci->run_graceperiod) {
1305 if (time_before(jiffies, xhci->run_graceperiod))
1308 xhci->run_graceperiod = 0;
1311 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1313 /* For each port, did anything change? If so, set that bit in buf. */
1314 for (i = 0; i < max_ports; i++) {
1315 temp = readl(port_array[i]);
1316 if (temp == 0xffffffff) {
1320 if ((temp & mask) != 0 ||
1321 (bus_state->port_c_suspend & 1 << i) ||
1322 (bus_state->resume_done[i] && time_after_eq(
1323 jiffies, bus_state->resume_done[i]))) {
1324 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1327 if ((temp & PORT_RC))
1328 reset_change = true;
1330 if (!status && !reset_change) {
1331 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1332 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1334 spin_unlock_irqrestore(&xhci->lock, flags);
1335 return status ? retval : 0;
1340 int xhci_bus_suspend(struct usb_hcd *hcd)
1342 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1343 int max_ports, port_index;
1344 __le32 __iomem **port_array;
1345 struct xhci_bus_state *bus_state;
1346 unsigned long flags;
1347 u32 portsc_buf[USB_MAXCHILDREN];
1350 max_ports = xhci_get_ports(hcd, &port_array);
1351 bus_state = &xhci->bus_state[hcd_index(hcd)];
1352 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1354 spin_lock_irqsave(&xhci->lock, flags);
1357 if (bus_state->resuming_ports || /* USB2 */
1358 bus_state->port_remote_wakeup) { /* USB3 */
1359 spin_unlock_irqrestore(&xhci->lock, flags);
1360 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1365 * Prepare ports for suspend, but don't write anything before all ports
1366 * are checked and we know bus suspend can proceed
1368 bus_state->bus_suspended = 0;
1369 port_index = max_ports;
1370 while (port_index--) {
1373 t1 = readl(port_array[port_index]);
1374 t2 = xhci_port_state_to_neutral(t1);
1375 portsc_buf[port_index] = 0;
1377 /* Bail out if a USB3 port has a new device in link training */
1378 if ((hcd->speed >= HCD_USB3) &&
1379 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1380 bus_state->bus_suspended = 0;
1381 spin_unlock_irqrestore(&xhci->lock, flags);
1382 xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1386 /* suspend ports in U0, or bail out for new connect changes */
1387 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1388 if ((t1 & PORT_CSC) && wake_enabled) {
1389 bus_state->bus_suspended = 0;
1390 spin_unlock_irqrestore(&xhci->lock, flags);
1391 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1394 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1395 t2 &= ~PORT_PLS_MASK;
1396 t2 |= PORT_LINK_STROBE | XDEV_U3;
1397 set_bit(port_index, &bus_state->bus_suspended);
1399 /* USB core sets remote wake mask for USB 3.0 hubs,
1400 * including the USB 3.0 roothub, but only if CONFIG_PM
1401 * is enabled, so also enable remote wake here.
1404 if (t1 & PORT_CONNECT) {
1405 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1406 t2 &= ~PORT_WKCONN_E;
1408 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1409 t2 &= ~PORT_WKDISC_E;
1412 t2 &= ~PORT_WAKE_BITS;
1414 t1 = xhci_port_state_to_neutral(t1);
1416 portsc_buf[port_index] = t2;
1419 /* write port settings, stopping and suspending ports if needed */
1420 port_index = max_ports;
1421 while (port_index--) {
1422 if (!portsc_buf[port_index])
1424 if (test_bit(port_index, &bus_state->bus_suspended)) {
1427 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1430 spin_unlock_irqrestore(&xhci->lock, flags);
1431 xhci_stop_device(xhci, slot_id, 1);
1432 spin_lock_irqsave(&xhci->lock, flags);
1435 writel(portsc_buf[port_index], port_array[port_index]);
1437 hcd->state = HC_STATE_SUSPENDED;
1438 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1439 spin_unlock_irqrestore(&xhci->lock, flags);
1441 if (bus_state->bus_suspended)
1442 usleep_range(5000, 10000);
1448 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1449 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1450 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1452 static bool xhci_port_missing_cas_quirk(int port_index,
1453 __le32 __iomem **port_array)
1457 portsc = readl(port_array[port_index]);
1459 /* if any of these are set we are not stuck */
1460 if (portsc & (PORT_CONNECT | PORT_CAS))
1463 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1464 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1467 /* clear wakeup/change bits, and do a warm port reset */
1468 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1470 writel(portsc, port_array[port_index]);
1472 readl(port_array[port_index]);
1476 int xhci_bus_resume(struct usb_hcd *hcd)
1478 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1479 int max_ports, port_index;
1480 __le32 __iomem **port_array;
1481 struct xhci_bus_state *bus_state;
1483 unsigned long flags;
1484 unsigned long port_was_suspended = 0;
1485 bool need_usb2_u3_exit = false;
1489 max_ports = xhci_get_ports(hcd, &port_array);
1490 bus_state = &xhci->bus_state[hcd_index(hcd)];
1492 if (time_before(jiffies, bus_state->next_statechange))
1495 spin_lock_irqsave(&xhci->lock, flags);
1496 if (!HCD_HW_ACCESSIBLE(hcd)) {
1497 spin_unlock_irqrestore(&xhci->lock, flags);
1501 /* delay the irqs */
1502 temp = readl(&xhci->op_regs->command);
1504 writel(temp, &xhci->op_regs->command);
1506 port_index = max_ports;
1507 while (port_index--) {
1508 /* Check whether need resume ports. If needed
1509 resume port and disable remote wakeup */
1512 temp = readl(port_array[port_index]);
1514 /* warm reset CAS limited ports stuck in polling/compliance */
1515 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1516 (hcd->speed >= HCD_USB3) &&
1517 xhci_port_missing_cas_quirk(port_index, port_array)) {
1518 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1521 if (DEV_SUPERSPEED_ANY(temp))
1522 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1524 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1525 if (test_bit(port_index, &bus_state->bus_suspended) &&
1526 (temp & PORT_PLS_MASK)) {
1527 set_bit(port_index, &port_was_suspended);
1528 if (!DEV_SUPERSPEED_ANY(temp)) {
1529 xhci_set_link_state(xhci, port_array,
1530 port_index, XDEV_RESUME);
1531 need_usb2_u3_exit = true;
1534 writel(temp, port_array[port_index]);
1537 if (need_usb2_u3_exit) {
1538 spin_unlock_irqrestore(&xhci->lock, flags);
1539 msleep(USB_RESUME_TIMEOUT);
1540 spin_lock_irqsave(&xhci->lock, flags);
1543 port_index = max_ports;
1544 while (port_index--) {
1545 if (!(port_was_suspended & BIT(port_index)))
1547 /* Clear PLC to poll it later after XDEV_U0 */
1548 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1549 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1552 port_index = max_ports;
1553 while (port_index--) {
1554 if (!(port_was_suspended & BIT(port_index)))
1556 /* Poll and Clear PLC */
1557 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1558 PORT_PLC, 10 * 1000);
1560 xhci_warn(xhci, "port %d resume PLC timeout\n",
1562 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1563 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1565 xhci_ring_device(xhci, slot_id);
1568 (void) readl(&xhci->op_regs->command);
1570 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1571 /* re-enable irqs */
1572 temp = readl(&xhci->op_regs->command);
1574 writel(temp, &xhci->op_regs->command);
1575 temp = readl(&xhci->op_regs->command);
1577 spin_unlock_irqrestore(&xhci->lock, flags);
1581 #endif /* CONFIG_PM */