2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x0c, /* bLength 12, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x00, 0x00, 0x00, 0x00, /* bmAttributes, get from xhci psic */
58 0x00, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Sublink Speed Attributes are added in xhci_create_usb3_bos_desc() */
63 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
68 u16 desc_size, ssp_cap_size, ssa_size = 0;
71 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
72 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
74 /* does xhci support USB 3.1 Enhanced SuperSpeed */
75 if (xhci->usb3_rhub.min_rev >= 0x01 && xhci->usb3_rhub.psi_uid_count) {
76 /* two SSA entries for each unique PSI ID, one RX and one TX */
77 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
78 ssa_size = ssa_count * sizeof(u32);
79 desc_size += ssp_cap_size;
82 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
85 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
87 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
90 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
93 /* Indicate whether the host has LTM support. */
94 temp = readl(&xhci->cap_regs->hcc_params);
96 buf[8] |= USB_LTM_SUPPORT;
98 /* Set the U1 and U2 exit latencies. */
99 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
100 temp = readl(&xhci->cap_regs->hcs_params3);
101 buf[12] = HCS_U1_LATENCY(temp);
102 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
106 u32 ssp_cap_base, bm_attrib, psi;
109 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
111 if (wLength < desc_size)
113 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
115 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
116 bm_attrib = (ssa_count - 1) & 0x1f;
117 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
118 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
120 if (wLength < desc_size + ssa_size)
123 * Create the Sublink Speed Attributes (SSA) array.
124 * The xhci PSI field and USB 3.1 SSA fields are very similar,
125 * but link type bits 7:6 differ for values 01b and 10b.
126 * xhci has also only one PSI entry for a symmetric link when
127 * USB 3.1 requires two SSA entries (RX and TX) for every link
130 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
131 psi = xhci->usb3_rhub.psi[i];
132 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
133 if ((psi & PLT_MASK) == PLT_SYM) {
134 /* Symmetric, create SSA RX and TX from one PSI entry */
135 put_unaligned_le32(psi, &buf[offset]);
136 psi |= 1 << 7; /* turn entry to TX */
138 if (offset >= desc_size + ssa_size)
139 return desc_size + ssa_size;
140 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
141 /* Asymetric RX, flip bits 7:6 for SSA */
144 put_unaligned_le32(psi, &buf[offset]);
146 if (offset >= desc_size + ssa_size)
147 return desc_size + ssa_size;
150 /* ssa_size is 0 for other than usb 3.1 hosts */
151 return desc_size + ssa_size;
154 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
155 struct usb_hub_descriptor *desc, int ports)
159 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
160 desc->bHubContrCurrent = 0;
162 desc->bNbrPorts = ports;
164 /* Bits 1:0 - support per-port power switching, or power always on */
165 if (HCC_PPC(xhci->hcc_params))
166 temp |= HUB_CHAR_INDV_PORT_LPSM;
168 temp |= HUB_CHAR_NO_LPSM;
169 /* Bit 2 - root hubs are not part of a compound device */
170 /* Bits 4:3 - individual port over current protection */
171 temp |= HUB_CHAR_INDV_PORT_OCPM;
172 /* Bits 6:5 - no TTs in root ports */
173 /* Bit 7 - no port indicators */
174 desc->wHubCharacteristics = cpu_to_le16(temp);
177 /* Fill in the USB 2.0 roothub descriptor */
178 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
179 struct usb_hub_descriptor *desc)
183 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
187 ports = xhci->num_usb2_ports;
189 xhci_common_hub_descriptor(xhci, desc, ports);
190 desc->bDescriptorType = USB_DT_HUB;
191 temp = 1 + (ports / 8);
192 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
194 /* The Device Removable bits are reported on a byte granularity.
195 * If the port doesn't exist within that byte, the bit is set to 0.
197 memset(port_removable, 0, sizeof(port_removable));
198 for (i = 0; i < ports; i++) {
199 portsc = readl(xhci->usb2_ports[i]);
200 /* If a device is removable, PORTSC reports a 0, same as in the
201 * hub descriptor DeviceRemovable bits.
203 if (portsc & PORT_DEV_REMOVE)
204 /* This math is hairy because bit 0 of DeviceRemovable
205 * is reserved, and bit 1 is for port 1, etc.
207 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
210 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
211 * ports on it. The USB 2.0 specification says that there are two
212 * variable length fields at the end of the hub descriptor:
213 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
214 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
215 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
216 * 0xFF, so we initialize the both arrays (DeviceRemovable and
217 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
218 * set of ports that actually exist.
220 memset(desc->u.hs.DeviceRemovable, 0xff,
221 sizeof(desc->u.hs.DeviceRemovable));
222 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
223 sizeof(desc->u.hs.PortPwrCtrlMask));
225 for (i = 0; i < (ports + 1 + 7) / 8; i++)
226 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
230 /* Fill in the USB 3.0 roothub descriptor */
231 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
232 struct usb_hub_descriptor *desc)
239 ports = xhci->num_usb3_ports;
240 xhci_common_hub_descriptor(xhci, desc, ports);
241 desc->bDescriptorType = USB_DT_SS_HUB;
242 desc->bDescLength = USB_DT_SS_HUB_SIZE;
244 /* header decode latency should be zero for roothubs,
245 * see section 4.23.5.2.
247 desc->u.ss.bHubHdrDecLat = 0;
248 desc->u.ss.wHubDelay = 0;
251 /* bit 0 is reserved, bit 1 is for port 1, etc. */
252 for (i = 0; i < ports; i++) {
253 portsc = readl(xhci->usb3_ports[i]);
254 if (portsc & PORT_DEV_REMOVE)
255 port_removable |= 1 << (i + 1);
258 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
261 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
262 struct usb_hub_descriptor *desc)
265 if (hcd->speed >= HCD_USB3)
266 xhci_usb3_hub_descriptor(hcd, xhci, desc);
268 xhci_usb2_hub_descriptor(hcd, xhci, desc);
272 static unsigned int xhci_port_speed(unsigned int port_status)
274 if (DEV_LOWSPEED(port_status))
275 return USB_PORT_STAT_LOW_SPEED;
276 if (DEV_HIGHSPEED(port_status))
277 return USB_PORT_STAT_HIGH_SPEED;
279 * FIXME: Yes, we should check for full speed, but the core uses that as
280 * a default in portspeed() in usb/core/hub.c (which is the only place
281 * USB_PORT_STAT_*_SPEED is used).
287 * These bits are Read Only (RO) and should be saved and written to the
288 * registers: 0, 3, 10:13, 30
289 * connect status, over-current status, port speed, and device removable.
290 * connect status and port speed are also sticky - meaning they're in
291 * the AUX well and they aren't changed by a hot, warm, or cold reset.
293 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
295 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
296 * bits 5:8, 9, 14:15, 25:27
297 * link state, port power, port indicator state, "wake on" enable state
299 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
301 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
304 #define XHCI_PORT_RW1S ((1<<4))
306 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
307 * bits 1, 17, 18, 19, 20, 21, 22, 23
308 * port enable/disable, and
309 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
310 * over-current, reset, link state, and L1 change
312 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
314 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
317 #define XHCI_PORT_RW ((1<<16))
319 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
322 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
325 * Given a port state, this function returns a value that would result in the
326 * port being in the same state, if the value was written to the port status
328 * Save Read Only (RO) bits and save read/write bits where
329 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
330 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
332 u32 xhci_port_state_to_neutral(u32 state)
334 /* Save read-only status and port state */
335 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
339 * find slot id based on port number.
340 * @port: The one-based port number from one of the two split roothubs.
342 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
347 enum usb_device_speed speed;
350 for (i = 0; i < MAX_HC_SLOTS; i++) {
351 if (!xhci->devs[i] || !xhci->devs[i]->udev)
353 speed = xhci->devs[i]->udev->speed;
354 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
355 && xhci->devs[i]->fake_port == port) {
366 * It issues stop endpoint command for EP 0 to 30. And wait the last command
368 * suspend will set to 1, if suspend bit need to set in command.
370 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
372 struct xhci_virt_device *virt_dev;
373 struct xhci_command *cmd;
379 virt_dev = xhci->devs[slot_id];
383 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
385 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
389 spin_lock_irqsave(&xhci->lock, flags);
390 for (i = LAST_EP_INDEX; i > 0; i--) {
391 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
392 struct xhci_command *command;
393 command = xhci_alloc_command(xhci, false, false,
396 spin_unlock_irqrestore(&xhci->lock, flags);
401 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
404 spin_unlock_irqrestore(&xhci->lock, flags);
405 xhci_free_command(xhci, command);
410 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
412 spin_unlock_irqrestore(&xhci->lock, flags);
416 xhci_ring_cmd_db(xhci);
417 spin_unlock_irqrestore(&xhci->lock, flags);
419 /* Wait for last stop endpoint command to finish */
420 wait_for_completion(cmd->completion);
422 if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
423 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
428 xhci_free_command(xhci, cmd);
433 * Ring device, it rings the all doorbells unconditionally.
435 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
438 struct xhci_virt_ep *ep;
440 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
441 ep = &xhci->devs[slot_id]->eps[i];
443 if (ep->ep_state & EP_HAS_STREAMS) {
444 for (s = 1; s < ep->stream_info->num_streams; s++)
445 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
446 } else if (ep->ring && ep->ring->dequeue) {
447 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
454 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
455 u16 wIndex, __le32 __iomem *addr, u32 port_status)
457 /* Don't allow the USB core to disable SuperSpeed ports. */
458 if (hcd->speed >= HCD_USB3) {
459 xhci_dbg(xhci, "Ignoring request to disable "
460 "SuperSpeed port.\n");
464 /* Write 1 to disable the port */
465 writel(port_status | PORT_PE, addr);
466 port_status = readl(addr);
467 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
468 wIndex, port_status);
471 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
472 u16 wIndex, __le32 __iomem *addr, u32 port_status)
474 char *port_change_bit;
478 case USB_PORT_FEAT_C_RESET:
480 port_change_bit = "reset";
482 case USB_PORT_FEAT_C_BH_PORT_RESET:
484 port_change_bit = "warm(BH) reset";
486 case USB_PORT_FEAT_C_CONNECTION:
488 port_change_bit = "connect";
490 case USB_PORT_FEAT_C_OVER_CURRENT:
492 port_change_bit = "over-current";
494 case USB_PORT_FEAT_C_ENABLE:
496 port_change_bit = "enable/disable";
498 case USB_PORT_FEAT_C_SUSPEND:
500 port_change_bit = "suspend/resume";
502 case USB_PORT_FEAT_C_PORT_LINK_STATE:
504 port_change_bit = "link state";
506 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
508 port_change_bit = "config error";
511 /* Should never happen */
514 /* Change bits are all write 1 to clear */
515 writel(port_status | status, addr);
516 port_status = readl(addr);
517 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
518 port_change_bit, wIndex, port_status);
521 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
524 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
526 if (hcd->speed >= HCD_USB3) {
527 max_ports = xhci->num_usb3_ports;
528 *port_array = xhci->usb3_ports;
530 max_ports = xhci->num_usb2_ports;
531 *port_array = xhci->usb2_ports;
537 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
538 int port_id, u32 link_state)
542 temp = readl(port_array[port_id]);
543 temp = xhci_port_state_to_neutral(temp);
544 temp &= ~PORT_PLS_MASK;
545 temp |= PORT_LINK_STROBE | link_state;
546 writel(temp, port_array[port_id]);
549 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
550 __le32 __iomem **port_array, int port_id, u16 wake_mask)
554 temp = readl(port_array[port_id]);
555 temp = xhci_port_state_to_neutral(temp);
557 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
558 temp |= PORT_WKCONN_E;
560 temp &= ~PORT_WKCONN_E;
562 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
563 temp |= PORT_WKDISC_E;
565 temp &= ~PORT_WKDISC_E;
567 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
570 temp &= ~PORT_WKOC_E;
572 writel(temp, port_array[port_id]);
575 /* Test and clear port RWC bit */
576 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
577 int port_id, u32 port_bit)
581 temp = readl(port_array[port_id]);
582 if (temp & port_bit) {
583 temp = xhci_port_state_to_neutral(temp);
585 writel(temp, port_array[port_id]);
589 /* Updates Link Status for USB 2.1 port */
590 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
592 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
593 *status |= USB_PORT_STAT_L1;
596 /* Updates Link Status for super Speed port */
597 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
598 u32 *status, u32 status_reg)
600 u32 pls = status_reg & PORT_PLS_MASK;
602 /* When the CAS bit is set then warm reset
603 * should be performed on port
605 if (status_reg & PORT_CAS) {
606 /* The CAS bit can be set while the port is
608 * Only roothubs have CAS bit, so we
609 * pretend to be in compliance mode
610 * unless we're already in compliance
611 * or the inactive state.
613 if (pls != USB_SS_PORT_LS_COMP_MOD &&
614 pls != USB_SS_PORT_LS_SS_INACTIVE) {
615 pls = USB_SS_PORT_LS_COMP_MOD;
617 /* Return also connection bit -
618 * hub state machine resets port
619 * when this bit is set.
621 pls |= USB_PORT_STAT_CONNECTION;
624 * Resume state is an xHCI internal state. Do not report it to
625 * usb core, instead, pretend to be U3, thus usb core knows
626 * it's not ready for transfer.
628 if (pls == XDEV_RESUME) {
629 *status |= USB_SS_PORT_LS_U3;
634 * If CAS bit isn't set but the Port is already at
635 * Compliance Mode, fake a connection so the USB core
636 * notices the Compliance state and resets the port.
637 * This resolves an issue generated by the SN65LVPE502CP
638 * in which sometimes the port enters compliance mode
639 * caused by a delay on the host-device negotiation.
641 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
642 (pls == USB_SS_PORT_LS_COMP_MOD))
643 pls |= USB_PORT_STAT_CONNECTION;
646 /* update status field */
651 * Function for Compliance Mode Quirk.
653 * This Function verifies if all xhc USB3 ports have entered U0, if so,
654 * the compliance mode timer is deleted. A port won't enter
655 * compliance mode if it has previously entered U0.
657 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
660 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
661 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
663 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
666 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
667 xhci->port_status_u0 |= 1 << wIndex;
668 if (xhci->port_status_u0 == all_ports_seen_u0) {
669 del_timer_sync(&xhci->comp_mode_recovery_timer);
670 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
671 "All USB3 ports have entered U0 already!");
672 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
673 "Compliance Mode Recovery Timer Deleted.");
678 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
683 /* only support rx and tx lane counts of 1 in usb3.1 spec */
684 speed_id = DEV_PORT_SPEED(raw_port_status);
685 ext_stat |= speed_id; /* bits 3:0, RX speed id */
686 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
688 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
689 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
695 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
698 * Possible side effects:
699 * - Mark a port as being done with device resume,
700 * and ring the endpoint doorbells.
701 * - Stop the Synopsys redriver Compliance Mode polling.
702 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
704 static u32 xhci_get_port_status(struct usb_hcd *hcd,
705 struct xhci_bus_state *bus_state,
706 __le32 __iomem **port_array,
707 u16 wIndex, u32 raw_port_status,
708 unsigned long *flags)
709 __releases(&xhci->lock)
710 __acquires(&xhci->lock)
712 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
716 /* wPortChange bits */
717 if (raw_port_status & PORT_CSC)
718 status |= USB_PORT_STAT_C_CONNECTION << 16;
719 if (raw_port_status & PORT_PEC)
720 status |= USB_PORT_STAT_C_ENABLE << 16;
721 if ((raw_port_status & PORT_OCC))
722 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
723 if ((raw_port_status & PORT_RC))
724 status |= USB_PORT_STAT_C_RESET << 16;
726 if (hcd->speed >= HCD_USB3) {
727 /* Port link change with port in resume state should not be
728 * reported to usbcore, as this is an internal state to be
729 * handled by xhci driver. Reporting PLC to usbcore may
730 * cause usbcore clearing PLC first and port change event
731 * irq won't be generated.
733 if ((raw_port_status & PORT_PLC) &&
734 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
735 status |= USB_PORT_STAT_C_LINK_STATE << 16;
736 if ((raw_port_status & PORT_WRC))
737 status |= USB_PORT_STAT_C_BH_RESET << 16;
738 if ((raw_port_status & PORT_CEC))
739 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
741 /* USB3 remote wake resume signaling completed */
742 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
743 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
744 (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
745 bus_state->port_remote_wakeup &= ~(1 << wIndex);
746 usb_hcd_end_port_resume(&hcd->self, wIndex);
750 if (hcd->speed < HCD_USB3) {
751 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
752 && (raw_port_status & PORT_POWER))
753 status |= USB_PORT_STAT_SUSPEND;
755 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
756 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
757 if ((raw_port_status & PORT_RESET) ||
758 !(raw_port_status & PORT_PE))
760 /* did port event handler already start resume timing? */
761 if (!bus_state->resume_done[wIndex]) {
762 /* If not, maybe we are in a host initated resume? */
763 if (test_bit(wIndex, &bus_state->resuming_ports)) {
764 /* Host initated resume doesn't time the resume
765 * signalling using resume_done[].
766 * It manually sets RESUME state, sleeps 20ms
767 * and sets U0 state. This should probably be
768 * changed, but not right now.
771 /* port resume was discovered now and here,
772 * start resume timing
774 unsigned long timeout = jiffies +
775 msecs_to_jiffies(USB_RESUME_TIMEOUT);
777 set_bit(wIndex, &bus_state->resuming_ports);
778 bus_state->resume_done[wIndex] = timeout;
779 mod_timer(&hcd->rh_timer, timeout);
781 /* Has resume been signalled for USB_RESUME_TIME yet? */
782 } else if (time_after_eq(jiffies,
783 bus_state->resume_done[wIndex])) {
786 xhci_dbg(xhci, "Resume USB2 port %d\n",
788 bus_state->resume_done[wIndex] = 0;
789 clear_bit(wIndex, &bus_state->resuming_ports);
791 set_bit(wIndex, &bus_state->rexit_ports);
793 xhci_test_and_clear_bit(xhci, port_array, wIndex,
795 xhci_set_link_state(xhci, port_array, wIndex,
798 spin_unlock_irqrestore(&xhci->lock, *flags);
799 time_left = wait_for_completion_timeout(
800 &bus_state->rexit_done[wIndex],
802 XHCI_MAX_REXIT_TIMEOUT_MS));
803 spin_lock_irqsave(&xhci->lock, *flags);
806 slot_id = xhci_find_slot_id_by_port(hcd,
809 xhci_dbg(xhci, "slot_id is zero\n");
812 xhci_ring_device(xhci, slot_id);
814 int port_status = readl(port_array[wIndex]);
815 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
816 XHCI_MAX_REXIT_TIMEOUT_MS,
818 status |= USB_PORT_STAT_SUSPEND;
819 clear_bit(wIndex, &bus_state->rexit_ports);
822 bus_state->port_c_suspend |= 1 << wIndex;
823 bus_state->suspended_ports &= ~(1 << wIndex);
826 * The resume has been signaling for less than
827 * USB_RESUME_TIME. Report the port status as SUSPEND,
828 * let the usbcore check port status again and clear
829 * resume signaling later.
831 status |= USB_PORT_STAT_SUSPEND;
835 * Clear stale usb2 resume signalling variables in case port changed
836 * state during resume signalling. For example on error
838 if ((bus_state->resume_done[wIndex] ||
839 test_bit(wIndex, &bus_state->resuming_ports)) &&
840 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
841 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
842 bus_state->resume_done[wIndex] = 0;
843 clear_bit(wIndex, &bus_state->resuming_ports);
847 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
848 (raw_port_status & PORT_POWER)) {
849 if (bus_state->suspended_ports & (1 << wIndex)) {
850 bus_state->suspended_ports &= ~(1 << wIndex);
851 if (hcd->speed < HCD_USB3)
852 bus_state->port_c_suspend |= 1 << wIndex;
854 bus_state->resume_done[wIndex] = 0;
855 clear_bit(wIndex, &bus_state->resuming_ports);
857 if (raw_port_status & PORT_CONNECT) {
858 status |= USB_PORT_STAT_CONNECTION;
859 status |= xhci_port_speed(raw_port_status);
861 if (raw_port_status & PORT_PE)
862 status |= USB_PORT_STAT_ENABLE;
863 if (raw_port_status & PORT_OC)
864 status |= USB_PORT_STAT_OVERCURRENT;
865 if (raw_port_status & PORT_RESET)
866 status |= USB_PORT_STAT_RESET;
867 if (raw_port_status & PORT_POWER) {
868 if (hcd->speed >= HCD_USB3)
869 status |= USB_SS_PORT_STAT_POWER;
871 status |= USB_PORT_STAT_POWER;
873 /* Update Port Link State */
874 if (hcd->speed >= HCD_USB3) {
875 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
877 * Verify if all USB3 Ports Have entered U0 already.
878 * Delete Compliance Mode Timer if so.
880 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
882 xhci_hub_report_usb2_link_state(&status, raw_port_status);
884 if (bus_state->port_c_suspend & (1 << wIndex))
885 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
890 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
891 u16 wIndex, char *buf, u16 wLength)
893 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
898 __le32 __iomem **port_array;
900 struct xhci_bus_state *bus_state;
905 max_ports = xhci_get_ports(hcd, &port_array);
906 bus_state = &xhci->bus_state[hcd_index(hcd)];
908 spin_lock_irqsave(&xhci->lock, flags);
911 /* No power source, over-current reported per port */
914 case GetHubDescriptor:
915 /* Check to make sure userspace is asking for the USB 3.0 hub
916 * descriptor for the USB 3.0 roothub. If not, we stall the
917 * endpoint, like external hubs do.
919 if (hcd->speed >= HCD_USB3 &&
920 (wLength < USB_DT_SS_HUB_SIZE ||
921 wValue != (USB_DT_SS_HUB << 8))) {
922 xhci_dbg(xhci, "Wrong hub descriptor type for "
923 "USB 3.0 roothub.\n");
926 xhci_hub_descriptor(hcd, xhci,
927 (struct usb_hub_descriptor *) buf);
929 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
930 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
933 if (hcd->speed < HCD_USB3)
936 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
937 spin_unlock_irqrestore(&xhci->lock, flags);
940 if (!wIndex || wIndex > max_ports)
943 temp = readl(port_array[wIndex]);
944 if (temp == 0xffffffff) {
948 status = xhci_get_port_status(hcd, bus_state, port_array,
949 wIndex, temp, &flags);
950 if (status == 0xffffffff)
953 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
955 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
957 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
958 /* if USB 3.1 extended port status return additional 4 bytes */
959 if (wValue == 0x02) {
962 if (hcd->speed < HCD_USB31 || wLength != 8) {
963 xhci_err(xhci, "get ext port status invalid parameter\n");
967 port_li = readl(port_array[wIndex] + PORTLI);
968 status = xhci_get_ext_port_status(temp, port_li);
969 put_unaligned_le32(status, &buf[4]);
973 if (wValue == USB_PORT_FEAT_LINK_STATE)
974 link_state = (wIndex & 0xff00) >> 3;
975 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
976 wake_mask = wIndex & 0xff00;
977 /* The MSB of wIndex is the U1/U2 timeout */
978 timeout = (wIndex & 0xff00) >> 8;
980 if (!wIndex || wIndex > max_ports)
983 temp = readl(port_array[wIndex]);
984 if (temp == 0xffffffff) {
988 temp = xhci_port_state_to_neutral(temp);
989 /* FIXME: What new port features do we need to support? */
991 case USB_PORT_FEAT_SUSPEND:
992 temp = readl(port_array[wIndex]);
993 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
994 /* Resume the port to U0 first */
995 xhci_set_link_state(xhci, port_array, wIndex,
997 spin_unlock_irqrestore(&xhci->lock, flags);
999 spin_lock_irqsave(&xhci->lock, flags);
1001 /* In spec software should not attempt to suspend
1002 * a port unless the port reports that it is in the
1003 * enabled (PED = ‘1’,PLS < ‘3’) state.
1005 temp = readl(port_array[wIndex]);
1006 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1007 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1008 xhci_warn(xhci, "USB core suspending device "
1009 "not in U0/U1/U2.\n");
1013 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1016 xhci_warn(xhci, "slot_id is zero\n");
1019 /* unlock to execute stop endpoint commands */
1020 spin_unlock_irqrestore(&xhci->lock, flags);
1021 xhci_stop_device(xhci, slot_id, 1);
1022 spin_lock_irqsave(&xhci->lock, flags);
1024 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1026 spin_unlock_irqrestore(&xhci->lock, flags);
1027 msleep(10); /* wait device to enter */
1028 spin_lock_irqsave(&xhci->lock, flags);
1030 temp = readl(port_array[wIndex]);
1031 bus_state->suspended_ports |= 1 << wIndex;
1033 case USB_PORT_FEAT_LINK_STATE:
1034 temp = readl(port_array[wIndex]);
1037 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1038 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1039 temp = xhci_port_state_to_neutral(temp);
1041 * Clear all change bits, so that we get a new
1044 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1045 PORT_OCC | PORT_RC | PORT_PLC |
1047 writel(temp | PORT_PE, port_array[wIndex]);
1048 temp = readl(port_array[wIndex]);
1052 /* Put link in RxDetect (enable port) */
1053 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1054 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1055 xhci_set_link_state(xhci, port_array, wIndex,
1057 temp = readl(port_array[wIndex]);
1060 /* Port must be enabled */
1061 if (!(temp & PORT_PE)) {
1065 /* Can't set port link state above '3' (U3) */
1066 if (link_state > USB_SS_PORT_LS_U3) {
1067 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1068 wIndex, link_state);
1071 if (link_state == USB_SS_PORT_LS_U3) {
1072 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1075 /* unlock to execute stop endpoint
1077 spin_unlock_irqrestore(&xhci->lock,
1079 xhci_stop_device(xhci, slot_id, 1);
1080 spin_lock_irqsave(&xhci->lock, flags);
1084 xhci_set_link_state(xhci, port_array, wIndex,
1087 spin_unlock_irqrestore(&xhci->lock, flags);
1088 msleep(20); /* wait device to enter */
1089 spin_lock_irqsave(&xhci->lock, flags);
1091 temp = readl(port_array[wIndex]);
1092 if (link_state == USB_SS_PORT_LS_U3)
1093 bus_state->suspended_ports |= 1 << wIndex;
1095 case USB_PORT_FEAT_POWER:
1097 * Turn on ports, even if there isn't per-port switching.
1098 * HC will report connect events even before this is set.
1099 * However, hub_wq will ignore the roothub events until
1100 * the roothub is registered.
1102 writel(temp | PORT_POWER, port_array[wIndex]);
1104 temp = readl(port_array[wIndex]);
1105 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
1107 spin_unlock_irqrestore(&xhci->lock, flags);
1108 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1111 usb_acpi_set_power_state(hcd->self.root_hub,
1113 spin_lock_irqsave(&xhci->lock, flags);
1115 case USB_PORT_FEAT_RESET:
1116 temp = (temp | PORT_RESET);
1117 writel(temp, port_array[wIndex]);
1119 temp = readl(port_array[wIndex]);
1120 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1122 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1123 xhci_set_remote_wake_mask(xhci, port_array,
1125 temp = readl(port_array[wIndex]);
1126 xhci_dbg(xhci, "set port remote wake mask, "
1127 "actual port %d status = 0x%x\n",
1130 case USB_PORT_FEAT_BH_PORT_RESET:
1132 writel(temp, port_array[wIndex]);
1134 temp = readl(port_array[wIndex]);
1136 case USB_PORT_FEAT_U1_TIMEOUT:
1137 if (hcd->speed < HCD_USB3)
1139 temp = readl(port_array[wIndex] + PORTPMSC);
1140 temp &= ~PORT_U1_TIMEOUT_MASK;
1141 temp |= PORT_U1_TIMEOUT(timeout);
1142 writel(temp, port_array[wIndex] + PORTPMSC);
1144 case USB_PORT_FEAT_U2_TIMEOUT:
1145 if (hcd->speed < HCD_USB3)
1147 temp = readl(port_array[wIndex] + PORTPMSC);
1148 temp &= ~PORT_U2_TIMEOUT_MASK;
1149 temp |= PORT_U2_TIMEOUT(timeout);
1150 writel(temp, port_array[wIndex] + PORTPMSC);
1155 /* unblock any posted writes */
1156 temp = readl(port_array[wIndex]);
1158 case ClearPortFeature:
1159 if (!wIndex || wIndex > max_ports)
1162 temp = readl(port_array[wIndex]);
1163 if (temp == 0xffffffff) {
1167 /* FIXME: What new port features do we need to support? */
1168 temp = xhci_port_state_to_neutral(temp);
1170 case USB_PORT_FEAT_SUSPEND:
1171 temp = readl(port_array[wIndex]);
1172 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1173 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1174 if (temp & PORT_RESET)
1176 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1177 if ((temp & PORT_PE) == 0)
1180 set_bit(wIndex, &bus_state->resuming_ports);
1181 xhci_set_link_state(xhci, port_array, wIndex,
1183 spin_unlock_irqrestore(&xhci->lock, flags);
1184 msleep(USB_RESUME_TIMEOUT);
1185 spin_lock_irqsave(&xhci->lock, flags);
1186 xhci_set_link_state(xhci, port_array, wIndex,
1188 clear_bit(wIndex, &bus_state->resuming_ports);
1190 bus_state->port_c_suspend |= 1 << wIndex;
1192 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1195 xhci_dbg(xhci, "slot_id is zero\n");
1198 xhci_ring_device(xhci, slot_id);
1200 case USB_PORT_FEAT_C_SUSPEND:
1201 bus_state->port_c_suspend &= ~(1 << wIndex);
1202 case USB_PORT_FEAT_C_RESET:
1203 case USB_PORT_FEAT_C_BH_PORT_RESET:
1204 case USB_PORT_FEAT_C_CONNECTION:
1205 case USB_PORT_FEAT_C_OVER_CURRENT:
1206 case USB_PORT_FEAT_C_ENABLE:
1207 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1208 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1209 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1210 port_array[wIndex], temp);
1212 case USB_PORT_FEAT_ENABLE:
1213 xhci_disable_port(hcd, xhci, wIndex,
1214 port_array[wIndex], temp);
1216 case USB_PORT_FEAT_POWER:
1217 writel(temp & ~PORT_POWER, port_array[wIndex]);
1219 spin_unlock_irqrestore(&xhci->lock, flags);
1220 temp = usb_acpi_power_manageable(hcd->self.root_hub,
1223 usb_acpi_set_power_state(hcd->self.root_hub,
1225 spin_lock_irqsave(&xhci->lock, flags);
1233 /* "stall" on error */
1236 spin_unlock_irqrestore(&xhci->lock, flags);
1241 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1242 * Ports are 0-indexed from the HCD point of view,
1243 * and 1-indexed from the USB core pointer of view.
1245 * Note that the status change bits will be cleared as soon as a port status
1246 * change event is generated, so we use the saved status from that event.
1248 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1250 unsigned long flags;
1254 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1256 __le32 __iomem **port_array;
1257 struct xhci_bus_state *bus_state;
1258 bool reset_change = false;
1260 max_ports = xhci_get_ports(hcd, &port_array);
1261 bus_state = &xhci->bus_state[hcd_index(hcd)];
1263 /* Initial status is no changes */
1264 retval = (max_ports + 8) / 8;
1265 memset(buf, 0, retval);
1268 * Inform the usbcore about resume-in-progress by returning
1269 * a non-zero value even if there are no status changes.
1271 spin_lock_irqsave(&xhci->lock, flags);
1273 status = bus_state->resuming_ports;
1275 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1277 /* For each port, did anything change? If so, set that bit in buf. */
1278 for (i = 0; i < max_ports; i++) {
1279 temp = readl(port_array[i]);
1280 if (temp == 0xffffffff) {
1284 if ((temp & mask) != 0 ||
1285 (bus_state->port_c_suspend & 1 << i) ||
1286 (bus_state->resume_done[i] && time_after_eq(
1287 jiffies, bus_state->resume_done[i]))) {
1288 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1291 if ((temp & PORT_RC))
1292 reset_change = true;
1294 if (!status && !reset_change) {
1295 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1296 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1298 spin_unlock_irqrestore(&xhci->lock, flags);
1299 return status ? retval : 0;
1304 int xhci_bus_suspend(struct usb_hcd *hcd)
1306 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1307 int max_ports, port_index;
1308 __le32 __iomem **port_array;
1309 struct xhci_bus_state *bus_state;
1310 unsigned long flags;
1311 u32 portsc_buf[USB_MAXCHILDREN];
1314 max_ports = xhci_get_ports(hcd, &port_array);
1315 bus_state = &xhci->bus_state[hcd_index(hcd)];
1316 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1318 spin_lock_irqsave(&xhci->lock, flags);
1321 if (bus_state->resuming_ports || /* USB2 */
1322 bus_state->port_remote_wakeup) { /* USB3 */
1323 spin_unlock_irqrestore(&xhci->lock, flags);
1324 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1329 * Prepare ports for suspend, but don't write anything before all ports
1330 * are checked and we know bus suspend can proceed
1332 bus_state->bus_suspended = 0;
1333 port_index = max_ports;
1334 while (port_index--) {
1337 t1 = readl(port_array[port_index]);
1338 t2 = xhci_port_state_to_neutral(t1);
1339 portsc_buf[port_index] = 0;
1341 /* Bail out if a USB3 port has a new device in link training */
1342 if ((hcd->speed >= HCD_USB3) &&
1343 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1344 bus_state->bus_suspended = 0;
1345 spin_unlock_irqrestore(&xhci->lock, flags);
1346 xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1350 /* suspend ports in U0, or bail out for new connect changes */
1351 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1352 if ((t1 & PORT_CSC) && wake_enabled) {
1353 bus_state->bus_suspended = 0;
1354 spin_unlock_irqrestore(&xhci->lock, flags);
1355 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1358 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1359 t2 &= ~PORT_PLS_MASK;
1360 t2 |= PORT_LINK_STROBE | XDEV_U3;
1361 set_bit(port_index, &bus_state->bus_suspended);
1363 /* USB core sets remote wake mask for USB 3.0 hubs,
1364 * including the USB 3.0 roothub, but only if CONFIG_PM
1365 * is enabled, so also enable remote wake here.
1368 if (t1 & PORT_CONNECT) {
1369 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1370 t2 &= ~PORT_WKCONN_E;
1372 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1373 t2 &= ~PORT_WKDISC_E;
1376 t2 &= ~PORT_WAKE_BITS;
1378 t1 = xhci_port_state_to_neutral(t1);
1380 portsc_buf[port_index] = t2;
1383 /* write port settings, stopping and suspending ports if needed */
1384 port_index = max_ports;
1385 while (port_index--) {
1386 if (!portsc_buf[port_index])
1388 if (test_bit(port_index, &bus_state->bus_suspended)) {
1391 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1394 spin_unlock_irqrestore(&xhci->lock, flags);
1395 xhci_stop_device(xhci, slot_id, 1);
1396 spin_lock_irqsave(&xhci->lock, flags);
1399 writel(portsc_buf[port_index], port_array[port_index]);
1401 hcd->state = HC_STATE_SUSPENDED;
1402 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1403 spin_unlock_irqrestore(&xhci->lock, flags);
1405 if (bus_state->bus_suspended)
1406 usleep_range(5000, 10000);
1412 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1413 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1414 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1416 static bool xhci_port_missing_cas_quirk(int port_index,
1417 __le32 __iomem **port_array)
1421 portsc = readl(port_array[port_index]);
1423 /* if any of these are set we are not stuck */
1424 if (portsc & (PORT_CONNECT | PORT_CAS))
1427 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1428 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1431 /* clear wakeup/change bits, and do a warm port reset */
1432 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1434 writel(portsc, port_array[port_index]);
1436 readl(port_array[port_index]);
1440 int xhci_bus_resume(struct usb_hcd *hcd)
1442 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1443 int max_ports, port_index;
1444 __le32 __iomem **port_array;
1445 struct xhci_bus_state *bus_state;
1447 unsigned long flags;
1448 unsigned long port_was_suspended = 0;
1449 bool need_usb2_u3_exit = false;
1453 max_ports = xhci_get_ports(hcd, &port_array);
1454 bus_state = &xhci->bus_state[hcd_index(hcd)];
1456 if (time_before(jiffies, bus_state->next_statechange))
1459 spin_lock_irqsave(&xhci->lock, flags);
1460 if (!HCD_HW_ACCESSIBLE(hcd)) {
1461 spin_unlock_irqrestore(&xhci->lock, flags);
1465 /* delay the irqs */
1466 temp = readl(&xhci->op_regs->command);
1468 writel(temp, &xhci->op_regs->command);
1470 port_index = max_ports;
1471 while (port_index--) {
1472 /* Check whether need resume ports. If needed
1473 resume port and disable remote wakeup */
1476 temp = readl(port_array[port_index]);
1478 /* warm reset CAS limited ports stuck in polling/compliance */
1479 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1480 (hcd->speed >= HCD_USB3) &&
1481 xhci_port_missing_cas_quirk(port_index, port_array)) {
1482 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1485 if (DEV_SUPERSPEED_ANY(temp))
1486 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1488 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1489 if (test_bit(port_index, &bus_state->bus_suspended) &&
1490 (temp & PORT_PLS_MASK)) {
1491 set_bit(port_index, &port_was_suspended);
1492 if (!DEV_SUPERSPEED_ANY(temp)) {
1493 xhci_set_link_state(xhci, port_array,
1494 port_index, XDEV_RESUME);
1495 need_usb2_u3_exit = true;
1498 writel(temp, port_array[port_index]);
1501 if (need_usb2_u3_exit) {
1502 spin_unlock_irqrestore(&xhci->lock, flags);
1503 msleep(USB_RESUME_TIMEOUT);
1504 spin_lock_irqsave(&xhci->lock, flags);
1507 port_index = max_ports;
1508 while (port_index--) {
1509 if (!(port_was_suspended & BIT(port_index)))
1511 /* Clear PLC to poll it later after XDEV_U0 */
1512 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1513 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1516 port_index = max_ports;
1517 while (port_index--) {
1518 if (!(port_was_suspended & BIT(port_index)))
1520 /* Poll and Clear PLC */
1521 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1522 PORT_PLC, 10 * 1000);
1524 xhci_warn(xhci, "port %d resume PLC timeout\n",
1526 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1527 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1529 xhci_ring_device(xhci, slot_id);
1532 (void) readl(&xhci->op_regs->command);
1534 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1535 /* re-enable irqs */
1536 temp = readl(&xhci->op_regs->command);
1538 writel(temp, &xhci->op_regs->command);
1539 temp = readl(&xhci->op_regs->command);
1541 spin_unlock_irqrestore(&xhci->lock, flags);
1545 #endif /* CONFIG_PM */