1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
16 #include "xhci-trace.h"
18 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
19 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
20 PORT_RC | PORT_PLC | PORT_PE)
22 /* USB 3 BOS descriptor and a capability descriptors, combined.
23 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
25 static u8 usb_bos_descriptor [] = {
26 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
27 USB_DT_BOS, /* __u8 bDescriptorType */
28 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
29 0x1, /* __u8 bNumDeviceCaps */
30 /* First device capability, SuperSpeed */
31 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
32 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
33 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
34 0x00, /* bmAttributes, LTM off by default */
35 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
36 0x03, /* bFunctionalitySupport,
38 0x00, /* bU1DevExitLat, set later. */
39 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
40 /* Second device capability, SuperSpeedPlus */
41 0x1c, /* bLength 28, will be adjusted later */
42 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
43 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
44 0x00, /* bReserved 0 */
45 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
46 0x01, 0x00, /* wFunctionalitySupport */
47 0x00, 0x00, /* wReserved 0 */
48 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
49 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
50 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
51 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
52 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
58 struct xhci_port_cap *port_cap = NULL;
61 u16 desc_size, ssp_cap_size, ssa_size = 0;
64 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
65 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
67 /* does xhci support USB 3.1 Enhanced SuperSpeed */
68 for (i = 0; i < xhci->num_port_caps; i++) {
69 if (xhci->port_caps[i].maj_rev == 0x03 &&
70 xhci->port_caps[i].min_rev >= 0x01) {
72 port_cap = &xhci->port_caps[i];
78 /* does xhci provide a PSI table for SSA speed attributes? */
79 if (port_cap->psi_count) {
80 /* two SSA entries for each unique PSI ID, RX and TX */
81 ssa_count = port_cap->psi_uid_count * 2;
82 ssa_size = ssa_count * sizeof(u32);
83 ssp_cap_size -= 16; /* skip copying the default SSA */
85 desc_size += ssp_cap_size;
87 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
90 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
92 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
95 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
98 /* Indicate whether the host has LTM support. */
99 temp = readl(&xhci->cap_regs->hcc_params);
101 buf[8] |= USB_LTM_SUPPORT;
103 /* Set the U1 and U2 exit latencies. */
104 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
105 temp = readl(&xhci->cap_regs->hcs_params3);
106 buf[12] = HCS_U1_LATENCY(temp);
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
110 /* If PSI table exists, add the custom speed attributes from it */
111 if (usb3_1 && port_cap->psi_count) {
112 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
115 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
117 if (wLength < desc_size)
119 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
121 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
122 bm_attrib = (ssa_count - 1) & 0x1f;
123 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
124 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
126 if (wLength < desc_size + ssa_size)
129 * Create the Sublink Speed Attributes (SSA) array.
130 * The xhci PSI field and USB 3.1 SSA fields are very similar,
131 * but link type bits 7:6 differ for values 01b and 10b.
132 * xhci has also only one PSI entry for a symmetric link when
133 * USB 3.1 requires two SSA entries (RX and TX) for every link
136 for (i = 0; i < port_cap->psi_count; i++) {
137 psi = port_cap->psi[i];
138 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
139 psi_exp = XHCI_EXT_PORT_PSIE(psi);
140 psi_mant = XHCI_EXT_PORT_PSIM(psi);
142 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
143 for (; psi_exp < 3; psi_exp++)
148 if ((psi & PLT_MASK) == PLT_SYM) {
149 /* Symmetric, create SSA RX and TX from one PSI entry */
150 put_unaligned_le32(psi, &buf[offset]);
151 psi |= 1 << 7; /* turn entry to TX */
153 if (offset >= desc_size + ssa_size)
154 return desc_size + ssa_size;
155 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
156 /* Asymetric RX, flip bits 7:6 for SSA */
159 put_unaligned_le32(psi, &buf[offset]);
161 if (offset >= desc_size + ssa_size)
162 return desc_size + ssa_size;
165 /* ssa_size is 0 for other than usb 3.1 hosts */
166 return desc_size + ssa_size;
169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
170 struct usb_hub_descriptor *desc, int ports)
174 desc->bHubContrCurrent = 0;
176 desc->bNbrPorts = ports;
178 /* Bits 1:0 - support per-port power switching, or power always on */
179 if (HCC_PPC(xhci->hcc_params))
180 temp |= HUB_CHAR_INDV_PORT_LPSM;
182 temp |= HUB_CHAR_NO_LPSM;
183 /* Bit 2 - root hubs are not part of a compound device */
184 /* Bits 4:3 - individual port over current protection */
185 temp |= HUB_CHAR_INDV_PORT_OCPM;
186 /* Bits 6:5 - no TTs in root ports */
187 /* Bit 7 - no port indicators */
188 desc->wHubCharacteristics = cpu_to_le16(temp);
191 /* Fill in the USB 2.0 roothub descriptor */
192 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
193 struct usb_hub_descriptor *desc)
197 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
200 struct xhci_hub *rhub;
202 rhub = &xhci->usb2_rhub;
203 ports = rhub->num_ports;
204 xhci_common_hub_descriptor(xhci, desc, ports);
205 desc->bDescriptorType = USB_DT_HUB;
206 temp = 1 + (ports / 8);
207 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
208 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */
210 /* The Device Removable bits are reported on a byte granularity.
211 * If the port doesn't exist within that byte, the bit is set to 0.
213 memset(port_removable, 0, sizeof(port_removable));
214 for (i = 0; i < ports; i++) {
215 portsc = readl(rhub->ports[i]->addr);
216 /* If a device is removable, PORTSC reports a 0, same as in the
217 * hub descriptor DeviceRemovable bits.
219 if (portsc & PORT_DEV_REMOVE)
220 /* This math is hairy because bit 0 of DeviceRemovable
221 * is reserved, and bit 1 is for port 1, etc.
223 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
226 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
227 * ports on it. The USB 2.0 specification says that there are two
228 * variable length fields at the end of the hub descriptor:
229 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
230 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
231 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
232 * 0xFF, so we initialize the both arrays (DeviceRemovable and
233 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
234 * set of ports that actually exist.
236 memset(desc->u.hs.DeviceRemovable, 0xff,
237 sizeof(desc->u.hs.DeviceRemovable));
238 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
239 sizeof(desc->u.hs.PortPwrCtrlMask));
241 for (i = 0; i < (ports + 1 + 7) / 8; i++)
242 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
246 /* Fill in the USB 3.0 roothub descriptor */
247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
248 struct usb_hub_descriptor *desc)
254 struct xhci_hub *rhub;
256 rhub = &xhci->usb3_rhub;
257 ports = rhub->num_ports;
258 xhci_common_hub_descriptor(xhci, desc, ports);
259 desc->bDescriptorType = USB_DT_SS_HUB;
260 desc->bDescLength = USB_DT_SS_HUB_SIZE;
261 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */
263 /* header decode latency should be zero for roothubs,
264 * see section 4.23.5.2.
266 desc->u.ss.bHubHdrDecLat = 0;
267 desc->u.ss.wHubDelay = 0;
270 /* bit 0 is reserved, bit 1 is for port 1, etc. */
271 for (i = 0; i < ports; i++) {
272 portsc = readl(rhub->ports[i]->addr);
273 if (portsc & PORT_DEV_REMOVE)
274 port_removable |= 1 << (i + 1);
277 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
281 struct usb_hub_descriptor *desc)
284 if (hcd->speed >= HCD_USB3)
285 xhci_usb3_hub_descriptor(hcd, xhci, desc);
287 xhci_usb2_hub_descriptor(hcd, xhci, desc);
291 static unsigned int xhci_port_speed(unsigned int port_status)
293 if (DEV_LOWSPEED(port_status))
294 return USB_PORT_STAT_LOW_SPEED;
295 if (DEV_HIGHSPEED(port_status))
296 return USB_PORT_STAT_HIGH_SPEED;
298 * FIXME: Yes, we should check for full speed, but the core uses that as
299 * a default in portspeed() in usb/core/hub.c (which is the only place
300 * USB_PORT_STAT_*_SPEED is used).
306 * These bits are Read Only (RO) and should be saved and written to the
307 * registers: 0, 3, 10:13, 30
308 * connect status, over-current status, port speed, and device removable.
309 * connect status and port speed are also sticky - meaning they're in
310 * the AUX well and they aren't changed by a hot, warm, or cold reset.
312 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
314 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
315 * bits 5:8, 9, 14:15, 25:27
316 * link state, port power, port indicator state, "wake on" enable state
318 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
320 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
323 #define XHCI_PORT_RW1S ((1<<4))
325 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
326 * bits 1, 17, 18, 19, 20, 21, 22, 23
327 * port enable/disable, and
328 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
329 * over-current, reset, link state, and L1 change
331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
333 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
336 #define XHCI_PORT_RW ((1<<16))
338 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
341 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
344 * Given a port state, this function returns a value that would result in the
345 * port being in the same state, if the value was written to the port status
347 * Save Read Only (RO) bits and save read/write bits where
348 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
349 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
351 u32 xhci_port_state_to_neutral(u32 state)
353 /* Save read-only status and port state */
354 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
358 * find slot id based on port number.
359 * @port: The one-based port number from one of the two split roothubs.
361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
366 enum usb_device_speed speed;
369 for (i = 0; i < MAX_HC_SLOTS; i++) {
370 if (!xhci->devs[i] || !xhci->devs[i]->udev)
372 speed = xhci->devs[i]->udev->speed;
373 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
374 && xhci->devs[i]->fake_port == port) {
385 * It issues stop endpoint command for EP 0 to 30. And wait the last command
387 * suspend will set to 1, if suspend bit need to set in command.
389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
391 struct xhci_virt_device *virt_dev;
392 struct xhci_command *cmd;
398 virt_dev = xhci->devs[slot_id];
402 trace_xhci_stop_device(virt_dev);
404 cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
408 spin_lock_irqsave(&xhci->lock, flags);
409 for (i = LAST_EP_INDEX; i > 0; i--) {
410 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
411 struct xhci_ep_ctx *ep_ctx;
412 struct xhci_command *command;
414 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
416 /* Check ep is running, required by AMD SNPS 3.1 xHC */
417 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
420 command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
422 spin_unlock_irqrestore(&xhci->lock, flags);
427 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
430 spin_unlock_irqrestore(&xhci->lock, flags);
431 xhci_free_command(xhci, command);
436 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
438 spin_unlock_irqrestore(&xhci->lock, flags);
442 xhci_ring_cmd_db(xhci);
443 spin_unlock_irqrestore(&xhci->lock, flags);
445 /* Wait for last stop endpoint command to finish */
446 wait_for_completion(cmd->completion);
448 if (cmd->status == COMP_COMMAND_ABORTED ||
449 cmd->status == COMP_COMMAND_RING_STOPPED) {
450 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
455 xhci_free_command(xhci, cmd);
460 * Ring device, it rings the all doorbells unconditionally.
462 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
465 struct xhci_virt_ep *ep;
467 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
468 ep = &xhci->devs[slot_id]->eps[i];
470 if (ep->ep_state & EP_HAS_STREAMS) {
471 for (s = 1; s < ep->stream_info->num_streams; s++)
472 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
473 } else if (ep->ring && ep->ring->dequeue) {
474 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
481 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
482 u16 wIndex, __le32 __iomem *addr, u32 port_status)
484 /* Don't allow the USB core to disable SuperSpeed ports. */
485 if (hcd->speed >= HCD_USB3) {
486 xhci_dbg(xhci, "Ignoring request to disable "
487 "SuperSpeed port.\n");
491 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
493 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
497 /* Write 1 to disable the port */
498 writel(port_status | PORT_PE, addr);
499 port_status = readl(addr);
500 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
501 hcd->self.busnum, wIndex + 1, port_status);
504 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
505 u16 wIndex, __le32 __iomem *addr, u32 port_status)
507 char *port_change_bit;
511 case USB_PORT_FEAT_C_RESET:
513 port_change_bit = "reset";
515 case USB_PORT_FEAT_C_BH_PORT_RESET:
517 port_change_bit = "warm(BH) reset";
519 case USB_PORT_FEAT_C_CONNECTION:
521 port_change_bit = "connect";
523 case USB_PORT_FEAT_C_OVER_CURRENT:
525 port_change_bit = "over-current";
527 case USB_PORT_FEAT_C_ENABLE:
529 port_change_bit = "enable/disable";
531 case USB_PORT_FEAT_C_SUSPEND:
533 port_change_bit = "suspend/resume";
535 case USB_PORT_FEAT_C_PORT_LINK_STATE:
537 port_change_bit = "link state";
539 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
541 port_change_bit = "config error";
544 /* Should never happen */
547 /* Change bits are all write 1 to clear */
548 writel(port_status | status, addr);
549 port_status = readl(addr);
551 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
552 wIndex + 1, port_change_bit, port_status);
555 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
557 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
559 if (hcd->speed >= HCD_USB3)
560 return &xhci->usb3_rhub;
561 return &xhci->usb2_rhub;
565 * xhci_set_port_power() must be called with xhci->lock held.
566 * It will release and re-aquire the lock while calling ACPI
569 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
570 u16 index, bool on, unsigned long *flags)
571 __must_hold(&xhci->lock)
573 struct xhci_hub *rhub;
574 struct xhci_port *port;
577 rhub = xhci_get_rhub(hcd);
578 port = rhub->ports[index];
579 temp = readl(port->addr);
581 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
582 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
584 temp = xhci_port_state_to_neutral(temp);
588 writel(temp | PORT_POWER, port->addr);
592 writel(temp & ~PORT_POWER, port->addr);
595 spin_unlock_irqrestore(&xhci->lock, *flags);
596 temp = usb_acpi_power_manageable(hcd->self.root_hub,
599 usb_acpi_set_power_state(hcd->self.root_hub,
601 spin_lock_irqsave(&xhci->lock, *flags);
604 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
605 u16 test_mode, u16 wIndex)
608 struct xhci_port *port;
610 /* xhci only supports test mode for usb2 ports */
611 port = xhci->usb2_rhub.ports[wIndex];
612 temp = readl(port->addr + PORTPMSC);
613 temp |= test_mode << PORT_TEST_MODE_SHIFT;
614 writel(temp, port->addr + PORTPMSC);
615 xhci->test_mode = test_mode;
616 if (test_mode == USB_TEST_FORCE_ENABLE)
620 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
621 u16 test_mode, u16 wIndex, unsigned long *flags)
622 __must_hold(&xhci->lock)
626 /* Disable all Device Slots */
627 xhci_dbg(xhci, "Disable all slots\n");
628 spin_unlock_irqrestore(&xhci->lock, *flags);
629 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
633 retval = xhci_disable_slot(xhci, i);
634 xhci_free_virt_device(xhci, i);
636 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
639 spin_lock_irqsave(&xhci->lock, *flags);
640 /* Put all ports to the Disable state by clear PP */
641 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
642 /* Power off USB3 ports*/
643 for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
644 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
645 /* Power off USB2 ports*/
646 for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
647 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
648 /* Stop the controller */
649 xhci_dbg(xhci, "Stop controller\n");
650 retval = xhci_halt(xhci);
653 /* Disable runtime PM for test mode */
654 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
655 /* Set PORTPMSC.PTC field to enter selected test mode */
656 /* Port is selected by wIndex. port_id = wIndex + 1 */
657 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
658 test_mode, wIndex + 1);
659 xhci_port_set_test_mode(xhci, test_mode, wIndex);
663 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
667 if (!xhci->test_mode) {
668 xhci_err(xhci, "Not in test mode, do nothing.\n");
671 if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
672 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
673 retval = xhci_halt(xhci);
677 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
679 return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
682 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
688 portsc = readl(port->addr);
689 temp = xhci_port_state_to_neutral(portsc);
690 temp &= ~PORT_PLS_MASK;
691 temp |= PORT_LINK_STROBE | link_state;
692 writel(temp, port->addr);
694 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
695 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
699 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
700 struct xhci_port *port, u16 wake_mask)
704 temp = readl(port->addr);
705 temp = xhci_port_state_to_neutral(temp);
707 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
708 temp |= PORT_WKCONN_E;
710 temp &= ~PORT_WKCONN_E;
712 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
713 temp |= PORT_WKDISC_E;
715 temp &= ~PORT_WKDISC_E;
717 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
720 temp &= ~PORT_WKOC_E;
722 writel(temp, port->addr);
725 /* Test and clear port RWC bit */
726 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
731 temp = readl(port->addr);
732 if (temp & port_bit) {
733 temp = xhci_port_state_to_neutral(temp);
735 writel(temp, port->addr);
739 /* Updates Link Status for super Speed port */
740 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
741 u32 *status, u32 status_reg)
743 u32 pls = status_reg & PORT_PLS_MASK;
745 /* When the CAS bit is set then warm reset
746 * should be performed on port
748 if (status_reg & PORT_CAS) {
749 /* The CAS bit can be set while the port is
751 * Only roothubs have CAS bit, so we
752 * pretend to be in compliance mode
753 * unless we're already in compliance
754 * or the inactive state.
756 if (pls != USB_SS_PORT_LS_COMP_MOD &&
757 pls != USB_SS_PORT_LS_SS_INACTIVE) {
758 pls = USB_SS_PORT_LS_COMP_MOD;
760 /* Return also connection bit -
761 * hub state machine resets port
762 * when this bit is set.
764 pls |= USB_PORT_STAT_CONNECTION;
767 * Resume state is an xHCI internal state. Do not report it to
768 * usb core, instead, pretend to be U3, thus usb core knows
769 * it's not ready for transfer.
771 if (pls == XDEV_RESUME) {
772 *status |= USB_SS_PORT_LS_U3;
777 * If CAS bit isn't set but the Port is already at
778 * Compliance Mode, fake a connection so the USB core
779 * notices the Compliance state and resets the port.
780 * This resolves an issue generated by the SN65LVPE502CP
781 * in which sometimes the port enters compliance mode
782 * caused by a delay on the host-device negotiation.
784 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
785 (pls == USB_SS_PORT_LS_COMP_MOD))
786 pls |= USB_PORT_STAT_CONNECTION;
789 /* update status field */
794 * Function for Compliance Mode Quirk.
796 * This Function verifies if all xhc USB3 ports have entered U0, if so,
797 * the compliance mode timer is deleted. A port won't enter
798 * compliance mode if it has previously entered U0.
800 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
803 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
804 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
806 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
809 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
810 xhci->port_status_u0 |= 1 << wIndex;
811 if (xhci->port_status_u0 == all_ports_seen_u0) {
812 del_timer_sync(&xhci->comp_mode_recovery_timer);
813 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
814 "All USB3 ports have entered U0 already!");
815 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
816 "Compliance Mode Recovery Timer Deleted.");
821 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
823 unsigned long *flags)
825 struct xhci_bus_state *bus_state;
826 struct xhci_hcd *xhci;
831 hcd = port->rhub->hcd;
832 bus_state = &port->rhub->bus_state;
833 xhci = hcd_to_xhci(hcd);
834 wIndex = port->hcd_portnum;
836 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
839 /* did port event handler already start resume timing? */
840 if (!port->resume_timestamp) {
841 /* If not, maybe we are in a host initated resume? */
842 if (test_bit(wIndex, &bus_state->resuming_ports)) {
843 /* Host initated resume doesn't time the resume
844 * signalling using resume_done[].
845 * It manually sets RESUME state, sleeps 20ms
846 * and sets U0 state. This should probably be
847 * changed, but not right now.
850 /* port resume was discovered now and here,
851 * start resume timing
853 unsigned long timeout = jiffies +
854 msecs_to_jiffies(USB_RESUME_TIMEOUT);
856 set_bit(wIndex, &bus_state->resuming_ports);
857 port->resume_timestamp = timeout;
858 mod_timer(&hcd->rh_timer, timeout);
859 usb_hcd_start_port_resume(&hcd->self, wIndex);
861 /* Has resume been signalled for USB_RESUME_TIME yet? */
862 } else if (time_after_eq(jiffies, port->resume_timestamp)) {
865 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
866 hcd->self.busnum, wIndex + 1);
868 port->resume_timestamp = 0;
869 clear_bit(wIndex, &bus_state->resuming_ports);
871 reinit_completion(&port->rexit_done);
872 port->rexit_active = true;
874 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
875 xhci_set_link_state(xhci, port, XDEV_U0);
877 spin_unlock_irqrestore(&xhci->lock, *flags);
878 time_left = wait_for_completion_timeout(
880 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
881 spin_lock_irqsave(&xhci->lock, *flags);
884 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
887 xhci_dbg(xhci, "slot_id is zero\n");
890 xhci_ring_device(xhci, slot_id);
892 int port_status = readl(port->addr);
894 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
895 hcd->self.busnum, wIndex + 1, port_status);
897 * keep rexit_active set if U0 transition failed so we
898 * know to report PORT_STAT_SUSPEND status back to
899 * usbcore. It will be cleared later once the port is
900 * out of RESUME/U3 state
904 usb_hcd_end_port_resume(&hcd->self, wIndex);
905 bus_state->port_c_suspend |= 1 << wIndex;
906 bus_state->suspended_ports &= ~(1 << wIndex);
912 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
917 /* only support rx and tx lane counts of 1 in usb3.1 spec */
918 speed_id = DEV_PORT_SPEED(raw_port_status);
919 ext_stat |= speed_id; /* bits 3:0, RX speed id */
920 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
922 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
923 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
928 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
931 struct xhci_bus_state *bus_state;
932 struct xhci_hcd *xhci;
937 bus_state = &port->rhub->bus_state;
938 xhci = hcd_to_xhci(port->rhub->hcd);
939 hcd = port->rhub->hcd;
940 link_state = portsc & PORT_PLS_MASK;
941 portnum = port->hcd_portnum;
943 /* USB3 specific wPortChange bits
945 * Port link change with port in resume state should not be
946 * reported to usbcore, as this is an internal state to be
947 * handled by xhci driver. Reporting PLC to usbcore may
948 * cause usbcore clearing PLC first and port change event
949 * irq won't be generated.
952 if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
953 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
954 if (portsc & PORT_WRC)
955 *status |= USB_PORT_STAT_C_BH_RESET << 16;
956 if (portsc & PORT_CEC)
957 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
959 /* USB3 specific wPortStatus bits */
960 if (portsc & PORT_POWER)
961 *status |= USB_SS_PORT_STAT_POWER;
963 /* no longer suspended or resuming */
964 if (link_state != XDEV_U3 &&
965 link_state != XDEV_RESUME &&
966 link_state != XDEV_RECOVERY) {
967 /* remote wake resume signaling complete */
968 if (bus_state->port_remote_wakeup & (1 << portnum)) {
969 bus_state->port_remote_wakeup &= ~(1 << portnum);
970 usb_hcd_end_port_resume(&hcd->self, portnum);
972 bus_state->suspended_ports &= ~(1 << portnum);
975 xhci_hub_report_usb3_link_state(xhci, status, portsc);
976 xhci_del_comp_mod_timer(xhci, portsc, portnum);
979 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
980 u32 portsc, unsigned long *flags)
982 struct xhci_bus_state *bus_state;
987 bus_state = &port->rhub->bus_state;
988 link_state = portsc & PORT_PLS_MASK;
989 portnum = port->hcd_portnum;
991 /* USB2 wPortStatus bits */
992 if (portsc & PORT_POWER) {
993 *status |= USB_PORT_STAT_POWER;
995 /* link state is only valid if port is powered */
996 if (link_state == XDEV_U3)
997 *status |= USB_PORT_STAT_SUSPEND;
998 if (link_state == XDEV_U2)
999 *status |= USB_PORT_STAT_L1;
1000 if (link_state == XDEV_U0) {
1001 if (bus_state->suspended_ports & (1 << portnum)) {
1002 bus_state->suspended_ports &= ~(1 << portnum);
1003 bus_state->port_c_suspend |= 1 << portnum;
1006 if (link_state == XDEV_RESUME) {
1007 err = xhci_handle_usb2_port_link_resume(port, portsc,
1010 *status = 0xffffffff;
1011 else if (port->resume_timestamp || port->rexit_active)
1012 *status |= USB_PORT_STAT_SUSPEND;
1017 * Clear usb2 resume signalling variables if port is no longer suspended
1018 * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a
1019 * error state. Resume related variables should be cleared in all those cases.
1021 if (link_state != XDEV_U3 && link_state != XDEV_RESUME) {
1022 if (port->resume_timestamp ||
1023 test_bit(portnum, &bus_state->resuming_ports)) {
1024 port->resume_timestamp = 0;
1025 clear_bit(portnum, &bus_state->resuming_ports);
1026 usb_hcd_end_port_resume(&port->rhub->hcd->self, portnum);
1028 port->rexit_active = 0;
1029 bus_state->suspended_ports &= ~(1 << portnum);
1034 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1037 * Possible side effects:
1038 * - Mark a port as being done with device resume,
1039 * and ring the endpoint doorbells.
1040 * - Stop the Synopsys redriver Compliance Mode polling.
1041 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1043 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1044 struct xhci_bus_state *bus_state,
1045 u16 wIndex, u32 raw_port_status,
1046 unsigned long *flags)
1047 __releases(&xhci->lock)
1048 __acquires(&xhci->lock)
1051 struct xhci_hub *rhub;
1052 struct xhci_port *port;
1054 rhub = xhci_get_rhub(hcd);
1055 port = rhub->ports[wIndex];
1057 /* common wPortChange bits */
1058 if (raw_port_status & PORT_CSC)
1059 status |= USB_PORT_STAT_C_CONNECTION << 16;
1060 if (raw_port_status & PORT_PEC)
1061 status |= USB_PORT_STAT_C_ENABLE << 16;
1062 if ((raw_port_status & PORT_OCC))
1063 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1064 if ((raw_port_status & PORT_RC))
1065 status |= USB_PORT_STAT_C_RESET << 16;
1067 /* common wPortStatus bits */
1068 if (raw_port_status & PORT_CONNECT) {
1069 status |= USB_PORT_STAT_CONNECTION;
1070 status |= xhci_port_speed(raw_port_status);
1072 if (raw_port_status & PORT_PE)
1073 status |= USB_PORT_STAT_ENABLE;
1074 if (raw_port_status & PORT_OC)
1075 status |= USB_PORT_STAT_OVERCURRENT;
1076 if (raw_port_status & PORT_RESET)
1077 status |= USB_PORT_STAT_RESET;
1079 /* USB2 and USB3 specific bits, including Port Link State */
1080 if (hcd->speed >= HCD_USB3)
1081 xhci_get_usb3_port_status(port, &status, raw_port_status);
1083 xhci_get_usb2_port_status(port, &status, raw_port_status,
1086 if (bus_state->port_c_suspend & (1 << wIndex))
1087 status |= USB_PORT_STAT_C_SUSPEND << 16;
1092 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1093 u16 wIndex, char *buf, u16 wLength)
1095 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1097 unsigned long flags;
1101 struct xhci_bus_state *bus_state;
1106 struct xhci_hub *rhub;
1107 struct xhci_port **ports;
1108 struct xhci_port *port;
1111 rhub = xhci_get_rhub(hcd);
1112 ports = rhub->ports;
1113 max_ports = rhub->num_ports;
1114 bus_state = &rhub->bus_state;
1115 portnum1 = wIndex & 0xff;
1117 spin_lock_irqsave(&xhci->lock, flags);
1120 /* No power source, over-current reported per port */
1123 case GetHubDescriptor:
1124 /* Check to make sure userspace is asking for the USB 3.0 hub
1125 * descriptor for the USB 3.0 roothub. If not, we stall the
1126 * endpoint, like external hubs do.
1128 if (hcd->speed >= HCD_USB3 &&
1129 (wLength < USB_DT_SS_HUB_SIZE ||
1130 wValue != (USB_DT_SS_HUB << 8))) {
1131 xhci_dbg(xhci, "Wrong hub descriptor type for "
1132 "USB 3.0 roothub.\n");
1135 xhci_hub_descriptor(hcd, xhci,
1136 (struct usb_hub_descriptor *) buf);
1138 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1139 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1142 if (hcd->speed < HCD_USB3)
1145 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1146 spin_unlock_irqrestore(&xhci->lock, flags);
1149 if (!portnum1 || portnum1 > max_ports)
1153 port = ports[portnum1 - 1];
1154 temp = readl(port->addr);
1155 if (temp == ~(u32)0) {
1160 trace_xhci_get_port_status(wIndex, temp);
1161 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1163 if (status == 0xffffffff)
1166 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1167 hcd->self.busnum, portnum1, temp, status);
1169 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1170 /* if USB 3.1 extended port status return additional 4 bytes */
1171 if (wValue == 0x02) {
1174 if (hcd->speed < HCD_USB31 || wLength != 8) {
1175 xhci_err(xhci, "get ext port status invalid parameter\n");
1179 port_li = readl(port->addr + PORTLI);
1180 status = xhci_get_ext_port_status(temp, port_li);
1181 put_unaligned_le32(status, &buf[4]);
1184 case SetPortFeature:
1185 if (wValue == USB_PORT_FEAT_LINK_STATE)
1186 link_state = (wIndex & 0xff00) >> 3;
1187 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1188 wake_mask = wIndex & 0xff00;
1189 if (wValue == USB_PORT_FEAT_TEST)
1190 test_mode = (wIndex & 0xff00) >> 8;
1191 /* The MSB of wIndex is the U1/U2 timeout */
1192 timeout = (wIndex & 0xff00) >> 8;
1195 if (!portnum1 || portnum1 > max_ports)
1198 port = ports[portnum1 - 1];
1200 temp = readl(port->addr);
1201 if (temp == ~(u32)0) {
1206 temp = xhci_port_state_to_neutral(temp);
1207 /* FIXME: What new port features do we need to support? */
1209 case USB_PORT_FEAT_SUSPEND:
1210 temp = readl(port->addr);
1211 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1212 /* Resume the port to U0 first */
1213 xhci_set_link_state(xhci, port, XDEV_U0);
1214 spin_unlock_irqrestore(&xhci->lock, flags);
1216 spin_lock_irqsave(&xhci->lock, flags);
1218 /* In spec software should not attempt to suspend
1219 * a port unless the port reports that it is in the
1220 * enabled (PED = ‘1’,PLS < ‘3’) state.
1222 temp = readl(port->addr);
1223 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1224 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1225 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1226 hcd->self.busnum, portnum1);
1230 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1233 xhci_warn(xhci, "slot_id is zero\n");
1236 /* unlock to execute stop endpoint commands */
1237 spin_unlock_irqrestore(&xhci->lock, flags);
1238 xhci_stop_device(xhci, slot_id, 1);
1239 spin_lock_irqsave(&xhci->lock, flags);
1241 xhci_set_link_state(xhci, port, XDEV_U3);
1243 spin_unlock_irqrestore(&xhci->lock, flags);
1244 msleep(10); /* wait device to enter */
1245 spin_lock_irqsave(&xhci->lock, flags);
1247 temp = readl(port->addr);
1248 bus_state->suspended_ports |= 1 << wIndex;
1250 case USB_PORT_FEAT_LINK_STATE:
1251 temp = readl(port->addr);
1253 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1254 xhci_dbg(xhci, "Disable port %d-%d\n",
1255 hcd->self.busnum, portnum1);
1256 temp = xhci_port_state_to_neutral(temp);
1258 * Clear all change bits, so that we get a new
1261 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1262 PORT_OCC | PORT_RC | PORT_PLC |
1264 writel(temp | PORT_PE, port->addr);
1265 temp = readl(port->addr);
1269 /* Put link in RxDetect (enable port) */
1270 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1271 xhci_dbg(xhci, "Enable port %d-%d\n",
1272 hcd->self.busnum, portnum1);
1273 xhci_set_link_state(xhci, port, link_state);
1274 temp = readl(port->addr);
1279 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1280 * root hub port's transition to compliance mode upon
1281 * detecting LFPS timeout may be controlled by an
1282 * Compliance Transition Enabled (CTE) flag (not
1283 * software visible). This flag is set by writing 0xA
1284 * to PORTSC PLS field which will allow transition to
1285 * compliance mode the next time LFPS timeout is
1286 * encountered. A warm reset will clear it.
1288 * The CTE flag is only supported if the HCCPARAMS2 CTC
1289 * flag is set, otherwise, the compliance substate is
1290 * automatically entered as on 1.0 and prior.
1292 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1293 if (!HCC2_CTC(xhci->hcc_params2)) {
1294 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1298 if ((temp & PORT_CONNECT)) {
1299 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1303 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1304 hcd->self.busnum, portnum1);
1305 xhci_set_link_state(xhci, port, link_state);
1307 temp = readl(port->addr);
1310 /* Port must be enabled */
1311 if (!(temp & PORT_PE)) {
1315 /* Can't set port link state above '3' (U3) */
1316 if (link_state > USB_SS_PORT_LS_U3) {
1317 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1318 hcd->self.busnum, portnum1, link_state);
1323 * set link to U0, steps depend on current link state.
1324 * U3: set link to U0 and wait for u3exit completion.
1325 * U1/U2: no PLC complete event, only set link to U0.
1326 * Resume/Recovery: device initiated U0, only wait for
1329 if (link_state == USB_SS_PORT_LS_U0) {
1330 u32 pls = temp & PORT_PLS_MASK;
1331 bool wait_u0 = false;
1336 if (pls == XDEV_U3 ||
1337 pls == XDEV_RESUME ||
1338 pls == XDEV_RECOVERY) {
1340 reinit_completion(&port->u3exit_done);
1342 if (pls <= XDEV_U3) /* U1, U2, U3 */
1343 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U0);
1349 spin_unlock_irqrestore(&xhci->lock, flags);
1350 if (!wait_for_completion_timeout(&port->u3exit_done,
1351 msecs_to_jiffies(500)))
1352 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1353 hcd->self.busnum, portnum1);
1354 spin_lock_irqsave(&xhci->lock, flags);
1355 temp = readl(port->addr);
1359 if (link_state == USB_SS_PORT_LS_U3) {
1361 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1364 /* unlock to execute stop endpoint
1366 spin_unlock_irqrestore(&xhci->lock,
1368 xhci_stop_device(xhci, slot_id, 1);
1369 spin_lock_irqsave(&xhci->lock, flags);
1371 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U3);
1372 spin_unlock_irqrestore(&xhci->lock, flags);
1374 usleep_range(4000, 8000);
1375 temp = readl(port->addr);
1376 if ((temp & PORT_PLS_MASK) == XDEV_U3)
1379 spin_lock_irqsave(&xhci->lock, flags);
1380 temp = readl(port->addr);
1381 bus_state->suspended_ports |= 1 << wIndex;
1384 case USB_PORT_FEAT_POWER:
1386 * Turn on ports, even if there isn't per-port switching.
1387 * HC will report connect events even before this is set.
1388 * However, hub_wq will ignore the roothub events until
1389 * the roothub is registered.
1391 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1393 case USB_PORT_FEAT_RESET:
1394 temp = (temp | PORT_RESET);
1395 writel(temp, port->addr);
1397 temp = readl(port->addr);
1398 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n",
1399 hcd->self.busnum, portnum1, temp);
1401 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1402 xhci_set_remote_wake_mask(xhci, port, wake_mask);
1403 temp = readl(port->addr);
1404 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1405 hcd->self.busnum, portnum1, temp);
1407 case USB_PORT_FEAT_BH_PORT_RESET:
1409 writel(temp, port->addr);
1410 temp = readl(port->addr);
1412 case USB_PORT_FEAT_U1_TIMEOUT:
1413 if (hcd->speed < HCD_USB3)
1415 temp = readl(port->addr + PORTPMSC);
1416 temp &= ~PORT_U1_TIMEOUT_MASK;
1417 temp |= PORT_U1_TIMEOUT(timeout);
1418 writel(temp, port->addr + PORTPMSC);
1420 case USB_PORT_FEAT_U2_TIMEOUT:
1421 if (hcd->speed < HCD_USB3)
1423 temp = readl(port->addr + PORTPMSC);
1424 temp &= ~PORT_U2_TIMEOUT_MASK;
1425 temp |= PORT_U2_TIMEOUT(timeout);
1426 writel(temp, port->addr + PORTPMSC);
1428 case USB_PORT_FEAT_TEST:
1429 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1430 if (hcd->speed != HCD_USB2)
1432 if (test_mode > USB_TEST_FORCE_ENABLE ||
1433 test_mode < USB_TEST_J)
1435 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1441 /* unblock any posted writes */
1442 temp = readl(port->addr);
1444 case ClearPortFeature:
1445 if (!portnum1 || portnum1 > max_ports)
1448 port = ports[portnum1 - 1];
1451 temp = readl(port->addr);
1452 if (temp == ~(u32)0) {
1457 /* FIXME: What new port features do we need to support? */
1458 temp = xhci_port_state_to_neutral(temp);
1460 case USB_PORT_FEAT_SUSPEND:
1461 temp = readl(port->addr);
1462 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1463 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1464 if (temp & PORT_RESET)
1466 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1467 if ((temp & PORT_PE) == 0)
1470 set_bit(wIndex, &bus_state->resuming_ports);
1471 usb_hcd_start_port_resume(&hcd->self, wIndex);
1472 xhci_set_link_state(xhci, port, XDEV_RESUME);
1473 spin_unlock_irqrestore(&xhci->lock, flags);
1474 msleep(USB_RESUME_TIMEOUT);
1475 spin_lock_irqsave(&xhci->lock, flags);
1476 xhci_set_link_state(xhci, port, XDEV_U0);
1477 clear_bit(wIndex, &bus_state->resuming_ports);
1478 usb_hcd_end_port_resume(&hcd->self, wIndex);
1480 bus_state->port_c_suspend |= 1 << wIndex;
1482 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1485 xhci_dbg(xhci, "slot_id is zero\n");
1488 xhci_ring_device(xhci, slot_id);
1490 case USB_PORT_FEAT_C_SUSPEND:
1491 bus_state->port_c_suspend &= ~(1 << wIndex);
1493 case USB_PORT_FEAT_C_RESET:
1494 case USB_PORT_FEAT_C_BH_PORT_RESET:
1495 case USB_PORT_FEAT_C_CONNECTION:
1496 case USB_PORT_FEAT_C_OVER_CURRENT:
1497 case USB_PORT_FEAT_C_ENABLE:
1498 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1499 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1500 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1503 case USB_PORT_FEAT_ENABLE:
1504 xhci_disable_port(hcd, xhci, wIndex,
1507 case USB_PORT_FEAT_POWER:
1508 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1510 case USB_PORT_FEAT_TEST:
1511 retval = xhci_exit_test_mode(xhci);
1519 /* "stall" on error */
1522 spin_unlock_irqrestore(&xhci->lock, flags);
1527 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1528 * Ports are 0-indexed from the HCD point of view,
1529 * and 1-indexed from the USB core pointer of view.
1531 * Note that the status change bits will be cleared as soon as a port status
1532 * change event is generated, so we use the saved status from that event.
1534 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1536 unsigned long flags;
1540 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1542 struct xhci_bus_state *bus_state;
1543 bool reset_change = false;
1544 struct xhci_hub *rhub;
1545 struct xhci_port **ports;
1547 rhub = xhci_get_rhub(hcd);
1548 ports = rhub->ports;
1549 max_ports = rhub->num_ports;
1550 bus_state = &rhub->bus_state;
1552 /* Initial status is no changes */
1553 retval = (max_ports + 8) / 8;
1554 memset(buf, 0, retval);
1557 * Inform the usbcore about resume-in-progress by returning
1558 * a non-zero value even if there are no status changes.
1560 spin_lock_irqsave(&xhci->lock, flags);
1562 status = bus_state->resuming_ports;
1565 * SS devices are only visible to roothub after link training completes.
1566 * Keep polling roothubs for a grace period after xHC start
1568 if (xhci->run_graceperiod) {
1569 if (time_before(jiffies, xhci->run_graceperiod))
1572 xhci->run_graceperiod = 0;
1575 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1577 /* For each port, did anything change? If so, set that bit in buf. */
1578 for (i = 0; i < max_ports; i++) {
1579 temp = readl(ports[i]->addr);
1580 if (temp == ~(u32)0) {
1585 trace_xhci_hub_status_data(i, temp);
1587 if ((temp & mask) != 0 ||
1588 (bus_state->port_c_suspend & 1 << i) ||
1589 (ports[i]->resume_timestamp && time_after_eq(
1590 jiffies, ports[i]->resume_timestamp))) {
1591 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1594 if ((temp & PORT_RC))
1595 reset_change = true;
1599 if (!status && !reset_change) {
1600 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1601 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1603 spin_unlock_irqrestore(&xhci->lock, flags);
1604 return status ? retval : 0;
1609 int xhci_bus_suspend(struct usb_hcd *hcd)
1611 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1612 int max_ports, port_index;
1613 struct xhci_bus_state *bus_state;
1614 unsigned long flags;
1615 struct xhci_hub *rhub;
1616 struct xhci_port **ports;
1617 u32 portsc_buf[USB_MAXCHILDREN];
1620 rhub = xhci_get_rhub(hcd);
1621 ports = rhub->ports;
1622 max_ports = rhub->num_ports;
1623 bus_state = &rhub->bus_state;
1624 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1626 spin_lock_irqsave(&xhci->lock, flags);
1629 if (bus_state->resuming_ports || /* USB2 */
1630 bus_state->port_remote_wakeup) { /* USB3 */
1631 spin_unlock_irqrestore(&xhci->lock, flags);
1632 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1637 * Prepare ports for suspend, but don't write anything before all ports
1638 * are checked and we know bus suspend can proceed
1640 bus_state->bus_suspended = 0;
1641 port_index = max_ports;
1642 while (port_index--) {
1646 t1 = readl(ports[port_index]->addr);
1647 t2 = xhci_port_state_to_neutral(t1);
1648 portsc_buf[port_index] = 0;
1651 * Give a USB3 port in link training time to finish, but don't
1652 * prevent suspend as port might be stuck
1654 if ((hcd->speed >= HCD_USB3) && retries-- &&
1655 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1656 spin_unlock_irqrestore(&xhci->lock, flags);
1657 msleep(XHCI_PORT_POLLING_LFPS_TIME);
1658 spin_lock_irqsave(&xhci->lock, flags);
1659 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1660 hcd->self.busnum, port_index + 1);
1663 /* bail out if port detected a over-current condition */
1665 bus_state->bus_suspended = 0;
1666 spin_unlock_irqrestore(&xhci->lock, flags);
1667 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1670 /* suspend ports in U0, or bail out for new connect changes */
1671 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1672 if ((t1 & PORT_CSC) && wake_enabled) {
1673 bus_state->bus_suspended = 0;
1674 spin_unlock_irqrestore(&xhci->lock, flags);
1675 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1678 xhci_dbg(xhci, "port %d-%d not suspended\n",
1679 hcd->self.busnum, port_index + 1);
1680 t2 &= ~PORT_PLS_MASK;
1681 t2 |= PORT_LINK_STROBE | XDEV_U3;
1682 set_bit(port_index, &bus_state->bus_suspended);
1684 /* USB core sets remote wake mask for USB 3.0 hubs,
1685 * including the USB 3.0 roothub, but only if CONFIG_PM
1686 * is enabled, so also enable remote wake here.
1689 if (t1 & PORT_CONNECT) {
1690 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1691 t2 &= ~PORT_WKCONN_E;
1693 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1694 t2 &= ~PORT_WKDISC_E;
1697 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1698 (hcd->speed < HCD_USB3)) {
1699 if (usb_amd_pt_check_port(hcd->self.controller,
1701 t2 &= ~PORT_WAKE_BITS;
1704 t2 &= ~PORT_WAKE_BITS;
1706 t1 = xhci_port_state_to_neutral(t1);
1708 portsc_buf[port_index] = t2;
1711 /* write port settings, stopping and suspending ports if needed */
1712 port_index = max_ports;
1713 while (port_index--) {
1714 if (!portsc_buf[port_index])
1716 if (test_bit(port_index, &bus_state->bus_suspended)) {
1719 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1722 spin_unlock_irqrestore(&xhci->lock, flags);
1723 xhci_stop_device(xhci, slot_id, 1);
1724 spin_lock_irqsave(&xhci->lock, flags);
1727 writel(portsc_buf[port_index], ports[port_index]->addr);
1729 hcd->state = HC_STATE_SUSPENDED;
1730 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1731 spin_unlock_irqrestore(&xhci->lock, flags);
1733 if (bus_state->bus_suspended)
1734 usleep_range(5000, 10000);
1740 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1741 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1742 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1744 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1748 portsc = readl(port->addr);
1750 /* if any of these are set we are not stuck */
1751 if (portsc & (PORT_CONNECT | PORT_CAS))
1754 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1755 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1758 /* clear wakeup/change bits, and do a warm port reset */
1759 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1761 writel(portsc, port->addr);
1767 int xhci_bus_resume(struct usb_hcd *hcd)
1769 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1770 struct xhci_bus_state *bus_state;
1771 unsigned long flags;
1772 int max_ports, port_index;
1777 struct xhci_hub *rhub;
1778 struct xhci_port **ports;
1780 rhub = xhci_get_rhub(hcd);
1781 ports = rhub->ports;
1782 max_ports = rhub->num_ports;
1783 bus_state = &rhub->bus_state;
1785 if (time_before(jiffies, bus_state->next_statechange))
1788 spin_lock_irqsave(&xhci->lock, flags);
1789 if (!HCD_HW_ACCESSIBLE(hcd)) {
1790 spin_unlock_irqrestore(&xhci->lock, flags);
1794 /* delay the irqs */
1795 temp = readl(&xhci->op_regs->command);
1797 writel(temp, &xhci->op_regs->command);
1799 /* bus specific resume for ports we suspended at bus_suspend */
1800 if (hcd->speed >= HCD_USB3)
1801 next_state = XDEV_U0;
1803 next_state = XDEV_RESUME;
1805 port_index = max_ports;
1806 while (port_index--) {
1807 portsc = readl(ports[port_index]->addr);
1809 /* warm reset CAS limited ports stuck in polling/compliance */
1810 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1811 (hcd->speed >= HCD_USB3) &&
1812 xhci_port_missing_cas_quirk(ports[port_index])) {
1813 xhci_dbg(xhci, "reset stuck port %d-%d\n",
1814 hcd->self.busnum, port_index + 1);
1815 clear_bit(port_index, &bus_state->bus_suspended);
1818 /* resume if we suspended the link, and it is still suspended */
1819 if (test_bit(port_index, &bus_state->bus_suspended))
1820 switch (portsc & PORT_PLS_MASK) {
1822 portsc = xhci_port_state_to_neutral(portsc);
1823 portsc &= ~PORT_PLS_MASK;
1824 portsc |= PORT_LINK_STROBE | next_state;
1827 /* resume already initiated */
1830 /* not in a resumeable state, ignore it */
1831 clear_bit(port_index,
1832 &bus_state->bus_suspended);
1835 /* disable wake for all ports, write new link state if needed */
1836 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1837 writel(portsc, ports[port_index]->addr);
1840 /* USB2 specific resume signaling delay and U0 link state transition */
1841 if (hcd->speed < HCD_USB3) {
1842 if (bus_state->bus_suspended) {
1843 spin_unlock_irqrestore(&xhci->lock, flags);
1844 msleep(USB_RESUME_TIMEOUT);
1845 spin_lock_irqsave(&xhci->lock, flags);
1847 for_each_set_bit(port_index, &bus_state->bus_suspended,
1849 /* Clear PLC to poll it later for U0 transition */
1850 xhci_test_and_clear_bit(xhci, ports[port_index],
1852 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1856 /* poll for U0 link state complete, both USB2 and USB3 */
1857 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1858 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1859 PORT_PLC, 10 * 1000);
1861 xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1862 hcd->self.busnum, port_index + 1);
1865 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1866 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1868 xhci_ring_device(xhci, slot_id);
1870 (void) readl(&xhci->op_regs->command);
1872 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1873 /* re-enable irqs */
1874 temp = readl(&xhci->op_regs->command);
1876 writel(temp, &xhci->op_regs->command);
1877 temp = readl(&xhci->op_regs->command);
1879 spin_unlock_irqrestore(&xhci->lock, flags);
1883 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1885 struct xhci_hub *rhub = xhci_get_rhub(hcd);
1887 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1888 return rhub->bus_state.resuming_ports; /* USB2 ports only */
1891 #endif /* CONFIG_PM */