drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x1c,                           /* bLength 28, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  58         0x01, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  61         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  62         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  63         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  64         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  65 };
  66
  67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  68                                      u16 wLength)
  69 {
  70         int i, ssa_count;
  71         u32 temp;
  72         u16 desc_size, ssp_cap_size, ssa_size = 0;
  73         bool usb3_1 = false;
  74
  75         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  76         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  77
  78         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  79         if (xhci->usb3_rhub.min_rev >= 0x01) {
  80                 /* does xhci provide a PSI table for SSA speed attributes? */
  81                 if (xhci->usb3_rhub.psi_count) {
  82                         /* two SSA entries for each unique PSI ID, RX and TX */
  83                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  84                         ssa_size = ssa_count * sizeof(u32);
  85                         ssp_cap_size -= 16; /* skip copying the default SSA */
  86                 }
  87                 desc_size += ssp_cap_size;
  88                 usb3_1 = true;
  89         }
  90         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  91
  92         if (usb3_1) {
  93                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  94                 buf[4] += 1;
  95                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  96         }
  97
  98         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  99                 return wLength;
 100
 101         /* Indicate whether the host has LTM support. */
 102         temp = readl(&xhci->cap_regs->hcc_params);
 103         if (HCC_LTC(temp))
 104                 buf[8] |= USB_LTM_SUPPORT;
 105
 106         /* Set the U1 and U2 exit latencies. */
 107         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 108                 temp = readl(&xhci->cap_regs->hcs_params3);
 109                 buf[12] = HCS_U1_LATENCY(temp);
 110                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 111         }
 112
 113         /* If PSI table exists, add the custom speed attributes from it */
 114         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 115                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 116                 int offset;
 117
 118                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 119
 120                 if (wLength < desc_size)
 121                         return wLength;
 122                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 123
 124                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 125                 bm_attrib = (ssa_count - 1) & 0x1f;
 126                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 127                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 128
 129                 if (wLength < desc_size + ssa_size)
 130                         return wLength;
 131                 /*
 132                  * Create the Sublink Speed Attributes (SSA) array.
 133                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 134                  * but link type bits 7:6 differ for values 01b and 10b.
 135                  * xhci has also only one PSI entry for a symmetric link when
 136                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 137                  */
 138                 offset = desc_size;
 139                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 140                         psi = xhci->usb3_rhub.psi[i];
 141                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 142                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 143                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 144
 145                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 146                         for (; psi_exp < 3; psi_exp++)
 147                                 psi_mant /= 1000;
 148                         if (psi_mant >= 10)
 149                                 psi |= BIT(14);
 150
 151                         if ((psi & PLT_MASK) == PLT_SYM) {
 152                         /* Symmetric, create SSA RX and TX from one PSI entry */
 153                                 put_unaligned_le32(psi, &buf[offset]);
 154                                 psi |= 1 << 7;  /* turn entry to TX */
 155                                 offset += 4;
 156                                 if (offset >= desc_size + ssa_size)
 157                                         return desc_size + ssa_size;
 158                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 159                                 /* Asymetric RX, flip bits 7:6 for SSA */
 160                                 psi ^= PLT_MASK;
 161                         }
 162                         put_unaligned_le32(psi, &buf[offset]);
 163                         offset += 4;
 164                         if (offset >= desc_size + ssa_size)
 165                                 return desc_size + ssa_size;
 166                 }
 167         }
 168         /* ssa_size is 0 for other than usb 3.1 hosts */
 169         return desc_size + ssa_size;
 170 }
 171
 172 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 173                 struct usb_hub_descriptor *desc, int ports)
 174 {
 175         u16 temp;
 176
 177         desc->bHubContrCurrent = 0;
 178
 179         desc->bNbrPorts = ports;
 180         temp = 0;
 181         /* Bits 1:0 - support per-port power switching, or power always on */
 182         if (HCC_PPC(xhci->hcc_params))
 183                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 184         else
 185                 temp |= HUB_CHAR_NO_LPSM;
 186         /* Bit  2 - root hubs are not part of a compound device */
 187         /* Bits 4:3 - individual port over current protection */
 188         temp |= HUB_CHAR_INDV_PORT_OCPM;
 189         /* Bits 6:5 - no TTs in root ports */
 190         /* Bit  7 - no port indicators */
 191         desc->wHubCharacteristics = cpu_to_le16(temp);
 192 }
 193
 194 /* Fill in the USB 2.0 roothub descriptor */
 195 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 196                 struct usb_hub_descriptor *desc)
 197 {
 198         int ports;
 199         u16 temp;
 200         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 201         u32 portsc;
 202         unsigned int i;
 203
 204         ports = xhci->num_usb2_ports;
 205
 206         xhci_common_hub_descriptor(xhci, desc, ports);
 207         desc->bDescriptorType = USB_DT_HUB;
 208         temp = 1 + (ports / 8);
 209         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 210         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.8 says 20ms */
 211
 212         /* The Device Removable bits are reported on a byte granularity.
 213          * If the port doesn't exist within that byte, the bit is set to 0.
 214          */
 215         memset(port_removable, 0, sizeof(port_removable));
 216         for (i = 0; i < ports; i++) {
 217                 portsc = readl(xhci->usb2_ports[i]);
 218                 /* If a device is removable, PORTSC reports a 0, same as in the
 219                  * hub descriptor DeviceRemovable bits.
 220                  */
 221                 if (portsc & PORT_DEV_REMOVE)
 222                         /* This math is hairy because bit 0 of DeviceRemovable
 223                          * is reserved, and bit 1 is for port 1, etc.
 224                          */
 225                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 226         }
 227
 228         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 229          * ports on it.  The USB 2.0 specification says that there are two
 230          * variable length fields at the end of the hub descriptor:
 231          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 232          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 233          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 234          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 235          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 236          * set of ports that actually exist.
 237          */
 238         memset(desc->u.hs.DeviceRemovable, 0xff,
 239                         sizeof(desc->u.hs.DeviceRemovable));
 240         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 241                         sizeof(desc->u.hs.PortPwrCtrlMask));
 242
 243         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 244                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 245                                 sizeof(__u8));
 246 }
 247
 248 /* Fill in the USB 3.0 roothub descriptor */
 249 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 250                 struct usb_hub_descriptor *desc)
 251 {
 252         int ports;
 253         u16 port_removable;
 254         u32 portsc;
 255         unsigned int i;
 256
 257         ports = xhci->num_usb3_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261         desc->bPwrOn2PwrGood = 50;      /* usb 3.1 may fail if less than 100ms */
 262
 263         /* header decode latency should be zero for roothubs,
 264          * see section 4.23.5.2.
 265          */
 266         desc->u.ss.bHubHdrDecLat = 0;
 267         desc->u.ss.wHubDelay = 0;
 268
 269         port_removable = 0;
 270         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 271         for (i = 0; i < ports; i++) {
 272                 portsc = readl(xhci->usb3_ports[i]);
 273                 if (portsc & PORT_DEV_REMOVE)
 274                         port_removable |= 1 << (i + 1);
 275         }
 276
 277         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 278 }
 279
 280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 281                 struct usb_hub_descriptor *desc)
 282 {
 283
 284         if (hcd->speed >= HCD_USB3)
 285                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 286         else
 287                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 288
 289 }
 290
 291 static unsigned int xhci_port_speed(unsigned int port_status)
 292 {
 293         if (DEV_LOWSPEED(port_status))
 294                 return USB_PORT_STAT_LOW_SPEED;
 295         if (DEV_HIGHSPEED(port_status))
 296                 return USB_PORT_STAT_HIGH_SPEED;
 297         /*
 298          * FIXME: Yes, we should check for full speed, but the core uses that as
 299          * a default in portspeed() in usb/core/hub.c (which is the only place
 300          * USB_PORT_STAT_*_SPEED is used).
 301          */
 302         return 0;
 303 }
 304
 305 /*
 306  * These bits are Read Only (RO) and should be saved and written to the
 307  * registers: 0, 3, 10:13, 30
 308  * connect status, over-current status, port speed, and device removable.
 309  * connect status and port speed are also sticky - meaning they're in
 310  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 311  */
 312 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 313 /*
 314  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 315  * bits 5:8, 9, 14:15, 25:27
 316  * link state, port power, port indicator state, "wake on" enable state
 317  */
 318 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 319 /*
 320  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 321  * bit 4 (port reset)
 322  */
 323 #define XHCI_PORT_RW1S  ((1<<4))
 324 /*
 325  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 326  * bits 1, 17, 18, 19, 20, 21, 22, 23
 327  * port enable/disable, and
 328  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 329  * over-current, reset, link state, and L1 change
 330  */
 331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 332 /*
 333  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 334  * latched in
 335  */
 336 #define XHCI_PORT_RW    ((1<<16))
 337 /*
 338  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 339  * bits 2, 24, 28:31
 340  */
 341 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 342
 343 /*
 344  * Given a port state, this function returns a value that would result in the
 345  * port being in the same state, if the value was written to the port status
 346  * control register.
 347  * Save Read Only (RO) bits and save read/write bits where
 348  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 349  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 350  */
 351 u32 xhci_port_state_to_neutral(u32 state)
 352 {
 353         /* Save read-only status and port state */
 354         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 355 }
 356
 357 /*
 358  * find slot id based on port number.
 359  * @port: The one-based port number from one of the two split roothubs.
 360  */
 361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 362                 u16 port)
 363 {
 364         int slot_id;
 365         int i;
 366         enum usb_device_speed speed;
 367
 368         slot_id = 0;
 369         for (i = 0; i < MAX_HC_SLOTS; i++) {
 370                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 371                         continue;
 372                 speed = xhci->devs[i]->udev->speed;
 373                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 374                                 && xhci->devs[i]->fake_port == port) {
 375                         slot_id = i;
 376                         break;
 377                 }
 378         }
 379
 380         return slot_id;
 381 }
 382
 383 /*
 384  * Stop device
 385  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 386  * to complete.
 387  * suspend will set to 1, if suspend bit need to set in command.
 388  */
 389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 390 {
 391         struct xhci_virt_device *virt_dev;
 392         struct xhci_command *cmd;
 393         unsigned long flags;
 394         int ret;
 395         int i;
 396
 397         ret = 0;
 398         virt_dev = xhci->devs[slot_id];
 399         if (!virt_dev)
 400                 return -ENODEV;
 401
 402         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 403         if (!cmd) {
 404                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 405                 return -ENOMEM;
 406         }
 407
 408         spin_lock_irqsave(&xhci->lock, flags);
 409         for (i = LAST_EP_INDEX; i > 0; i--) {
 410                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 411                         struct xhci_command *command;
 412                         command = xhci_alloc_command(xhci, false, false,
 413                                                      GFP_NOWAIT);
 414                         if (!command) {
 415                                 spin_unlock_irqrestore(&xhci->lock, flags);
 416                                 ret = -ENOMEM;
 417                                 goto cmd_cleanup;
 418                         }
 419
 420                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 421                                                        i, suspend);
 422                         if (ret) {
 423                                 spin_unlock_irqrestore(&xhci->lock, flags);
 424                                 xhci_free_command(xhci, command);
 425                                 goto cmd_cleanup;
 426                         }
 427                 }
 428         }
 429         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 430         if (ret) {
 431                 spin_unlock_irqrestore(&xhci->lock, flags);
 432                 goto cmd_cleanup;
 433         }
 434
 435         xhci_ring_cmd_db(xhci);
 436         spin_unlock_irqrestore(&xhci->lock, flags);
 437
 438         /* Wait for last stop endpoint command to finish */
 439         wait_for_completion(cmd->completion);
 440
 441         if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
 442                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 443                 ret = -ETIME;
 444         }
 445
 446 cmd_cleanup:
 447         xhci_free_command(xhci, cmd);
 448         return ret;
 449 }
 450
 451 /*
 452  * Ring device, it rings the all doorbells unconditionally.
 453  */
 454 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 455 {
 456         int i, s;
 457         struct xhci_virt_ep *ep;
 458
 459         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 460                 ep = &xhci->devs[slot_id]->eps[i];
 461
 462                 if (ep->ep_state & EP_HAS_STREAMS) {
 463                         for (s = 1; s < ep->stream_info->num_streams; s++)
 464                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 465                 } else if (ep->ring && ep->ring->dequeue) {
 466                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 467                 }
 468         }
 469
 470         return;
 471 }
 472
 473 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 474                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 475 {
 476         /* Don't allow the USB core to disable SuperSpeed ports. */
 477         if (hcd->speed >= HCD_USB3) {
 478                 xhci_dbg(xhci, "Ignoring request to disable "
 479                                 "SuperSpeed port.\n");
 480                 return;
 481         }
 482
 483         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 484                 xhci_dbg(xhci,
 485                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 486                 return;
 487         }
 488
 489         /* Write 1 to disable the port */
 490         writel(port_status | PORT_PE, addr);
 491         port_status = readl(addr);
 492         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 493                         wIndex, port_status);
 494 }
 495
 496 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 497                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 498 {
 499         char *port_change_bit;
 500         u32 status;
 501
 502         switch (wValue) {
 503         case USB_PORT_FEAT_C_RESET:
 504                 status = PORT_RC;
 505                 port_change_bit = "reset";
 506                 break;
 507         case USB_PORT_FEAT_C_BH_PORT_RESET:
 508                 status = PORT_WRC;
 509                 port_change_bit = "warm(BH) reset";
 510                 break;
 511         case USB_PORT_FEAT_C_CONNECTION:
 512                 status = PORT_CSC;
 513                 port_change_bit = "connect";
 514                 break;
 515         case USB_PORT_FEAT_C_OVER_CURRENT:
 516                 status = PORT_OCC;
 517                 port_change_bit = "over-current";
 518                 break;
 519         case USB_PORT_FEAT_C_ENABLE:
 520                 status = PORT_PEC;
 521                 port_change_bit = "enable/disable";
 522                 break;
 523         case USB_PORT_FEAT_C_SUSPEND:
 524                 status = PORT_PLC;
 525                 port_change_bit = "suspend/resume";
 526                 break;
 527         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 528                 status = PORT_PLC;
 529                 port_change_bit = "link state";
 530                 break;
 531         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 532                 status = PORT_CEC;
 533                 port_change_bit = "config error";
 534                 break;
 535         default:
 536                 /* Should never happen */
 537                 return;
 538         }
 539         /* Change bits are all write 1 to clear */
 540         writel(port_status | status, addr);
 541         port_status = readl(addr);
 542         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 543                         port_change_bit, wIndex, port_status);
 544 }
 545
 546 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 547 {
 548         int max_ports;
 549         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 550
 551         if (hcd->speed >= HCD_USB3) {
 552                 max_ports = xhci->num_usb3_ports;
 553                 *port_array = xhci->usb3_ports;
 554         } else {
 555                 max_ports = xhci->num_usb2_ports;
 556                 *port_array = xhci->usb2_ports;
 557         }
 558
 559         return max_ports;
 560 }
 561
 562 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 563                                 int port_id, u32 link_state)
 564 {
 565         u32 temp;
 566
 567         temp = readl(port_array[port_id]);
 568         temp = xhci_port_state_to_neutral(temp);
 569         temp &= ~PORT_PLS_MASK;
 570         temp |= PORT_LINK_STROBE | link_state;
 571         writel(temp, port_array[port_id]);
 572 }
 573
 574 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 575                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 576 {
 577         u32 temp;
 578
 579         temp = readl(port_array[port_id]);
 580         temp = xhci_port_state_to_neutral(temp);
 581
 582         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 583                 temp |= PORT_WKCONN_E;
 584         else
 585                 temp &= ~PORT_WKCONN_E;
 586
 587         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 588                 temp |= PORT_WKDISC_E;
 589         else
 590                 temp &= ~PORT_WKDISC_E;
 591
 592         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 593                 temp |= PORT_WKOC_E;
 594         else
 595                 temp &= ~PORT_WKOC_E;
 596
 597         writel(temp, port_array[port_id]);
 598 }
 599
 600 /* Test and clear port RWC bit */
 601 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 602                                 int port_id, u32 port_bit)
 603 {
 604         u32 temp;
 605
 606         temp = readl(port_array[port_id]);
 607         if (temp & port_bit) {
 608                 temp = xhci_port_state_to_neutral(temp);
 609                 temp |= port_bit;
 610                 writel(temp, port_array[port_id]);
 611         }
 612 }
 613
 614 /* Updates Link Status for USB 2.1 port */
 615 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 616 {
 617         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 618                 *status |= USB_PORT_STAT_L1;
 619 }
 620
 621 /* Updates Link Status for super Speed port */
 622 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 623                 u32 *status, u32 status_reg)
 624 {
 625         u32 pls = status_reg & PORT_PLS_MASK;
 626
 627         /* When the CAS bit is set then warm reset
 628          * should be performed on port
 629          */
 630         if (status_reg & PORT_CAS) {
 631                 /* The CAS bit can be set while the port is
 632                  * in any link state.
 633                  * Only roothubs have CAS bit, so we
 634                  * pretend to be in compliance mode
 635                  * unless we're already in compliance
 636                  * or the inactive state.
 637                  */
 638                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 639                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 640                         pls = USB_SS_PORT_LS_COMP_MOD;
 641                 }
 642                 /* Return also connection bit -
 643                  * hub state machine resets port
 644                  * when this bit is set.
 645                  */
 646                 pls |= USB_PORT_STAT_CONNECTION;
 647         } else {
 648                 /*
 649                  * Resume state is an xHCI internal state.  Do not report it to
 650                  * usb core, instead, pretend to be U3, thus usb core knows
 651                  * it's not ready for transfer.
 652                  */
 653                 if (pls == XDEV_RESUME) {
 654                         *status |= USB_SS_PORT_LS_U3;
 655                         return;
 656                 }
 657
 658                 /*
 659                  * If CAS bit isn't set but the Port is already at
 660                  * Compliance Mode, fake a connection so the USB core
 661                  * notices the Compliance state and resets the port.
 662                  * This resolves an issue generated by the SN65LVPE502CP
 663                  * in which sometimes the port enters compliance mode
 664                  * caused by a delay on the host-device negotiation.
 665                  */
 666                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 667                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 668                         pls |= USB_PORT_STAT_CONNECTION;
 669         }
 670
 671         /* update status field */
 672         *status |= pls;
 673 }
 674
 675 /*
 676  * Function for Compliance Mode Quirk.
 677  *
 678  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 679  * the compliance mode timer is deleted. A port won't enter
 680  * compliance mode if it has previously entered U0.
 681  */
 682 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 683                                     u16 wIndex)
 684 {
 685         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 686         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 687
 688         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 689                 return;
 690
 691         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 692                 xhci->port_status_u0 |= 1 << wIndex;
 693                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 694                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 695                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 696                                 "All USB3 ports have entered U0 already!");
 697                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 698                                 "Compliance Mode Recovery Timer Deleted.");
 699                 }
 700         }
 701 }
 702
 703 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 704 {
 705         u32 ext_stat = 0;
 706         int speed_id;
 707
 708         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 709         speed_id = DEV_PORT_SPEED(raw_port_status);
 710         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 711         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 712
 713         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 714         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 715
 716         return ext_stat;
 717 }
 718
 719 /*
 720  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 721  * 3.0 hubs use.
 722  *
 723  * Possible side effects:
 724  *  - Mark a port as being done with device resume,
 725  *    and ring the endpoint doorbells.
 726  *  - Stop the Synopsys redriver Compliance Mode polling.
 727  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 728  */
 729 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 730                 struct xhci_bus_state *bus_state,
 731                 __le32 __iomem **port_array,
 732                 u16 wIndex, u32 raw_port_status,
 733                 unsigned long *flags)
 734         __releases(&xhci->lock)
 735         __acquires(&xhci->lock)
 736 {
 737         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 738         u32 status = 0;
 739         int slot_id;
 740
 741         /* wPortChange bits */
 742         if (raw_port_status & PORT_CSC)
 743                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 744         if (raw_port_status & PORT_PEC)
 745                 status |= USB_PORT_STAT_C_ENABLE << 16;
 746         if ((raw_port_status & PORT_OCC))
 747                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 748         if ((raw_port_status & PORT_RC))
 749                 status |= USB_PORT_STAT_C_RESET << 16;
 750         /* USB3.0 only */
 751         if (hcd->speed >= HCD_USB3) {
 752                 /* Port link change with port in resume state should not be
 753                  * reported to usbcore, as this is an internal state to be
 754                  * handled by xhci driver. Reporting PLC to usbcore may
 755                  * cause usbcore clearing PLC first and port change event
 756                  * irq won't be generated.
 757                  */
 758                 if ((raw_port_status & PORT_PLC) &&
 759                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 760                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 761                 if ((raw_port_status & PORT_WRC))
 762                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 763                 if ((raw_port_status & PORT_CEC))
 764                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 765
 766                 /* USB3 remote wake resume signaling completed */
 767                 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
 768                     (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
 769                     (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
 770                         bus_state->port_remote_wakeup &= ~(1 << wIndex);
 771                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 772                 }
 773         }
 774
 775         if (hcd->speed < HCD_USB3) {
 776                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 777                                 && (raw_port_status & PORT_POWER))
 778                         status |= USB_PORT_STAT_SUSPEND;
 779         }
 780         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 781                 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
 782                 if ((raw_port_status & PORT_RESET) ||
 783                                 !(raw_port_status & PORT_PE))
 784                         return 0xffffffff;
 785                 /* did port event handler already start resume timing? */
 786                 if (!bus_state->resume_done[wIndex]) {
 787                         /* If not, maybe we are in a host initated resume? */
 788                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 789                                 /* Host initated resume doesn't time the resume
 790                                  * signalling using resume_done[].
 791                                  * It manually sets RESUME state, sleeps 20ms
 792                                  * and sets U0 state. This should probably be
 793                                  * changed, but not right now.
 794                                  */
 795                         } else {
 796                                 /* port resume was discovered now and here,
 797                                  * start resume timing
 798                                  */
 799                                 unsigned long timeout = jiffies +
 800                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 801
 802                                 set_bit(wIndex, &bus_state->resuming_ports);
 803                                 bus_state->resume_done[wIndex] = timeout;
 804                                 mod_timer(&hcd->rh_timer, timeout);
 805                         }
 806                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 807                 } else if (time_after_eq(jiffies,
 808                                          bus_state->resume_done[wIndex])) {
 809                         int time_left;
 810
 811                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 812                                         wIndex + 1);
 813                         bus_state->resume_done[wIndex] = 0;
 814                         clear_bit(wIndex, &bus_state->resuming_ports);
 815
 816                         set_bit(wIndex, &bus_state->rexit_ports);
 817
 818                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 819                                                 PORT_PLC);
 820                         xhci_set_link_state(xhci, port_array, wIndex,
 821                                         XDEV_U0);
 822
 823                         spin_unlock_irqrestore(&xhci->lock, *flags);
 824                         time_left = wait_for_completion_timeout(
 825                                         &bus_state->rexit_done[wIndex],
 826                                         msecs_to_jiffies(
 827                                                 XHCI_MAX_REXIT_TIMEOUT_MS));
 828                         spin_lock_irqsave(&xhci->lock, *flags);
 829
 830                         if (time_left) {
 831                                 slot_id = xhci_find_slot_id_by_port(hcd,
 832                                                 xhci, wIndex + 1);
 833                                 if (!slot_id) {
 834                                         xhci_dbg(xhci, "slot_id is zero\n");
 835                                         return 0xffffffff;
 836                                 }
 837                                 xhci_ring_device(xhci, slot_id);
 838                         } else {
 839                                 int port_status = readl(port_array[wIndex]);
 840                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 841                                                 XHCI_MAX_REXIT_TIMEOUT_MS,
 842                                                 port_status);
 843                                 status |= USB_PORT_STAT_SUSPEND;
 844                                 clear_bit(wIndex, &bus_state->rexit_ports);
 845                         }
 846
 847                         bus_state->port_c_suspend |= 1 << wIndex;
 848                         bus_state->suspended_ports &= ~(1 << wIndex);
 849                 } else {
 850                         /*
 851                          * The resume has been signaling for less than
 852                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 853                          * let the usbcore check port status again and clear
 854                          * resume signaling later.
 855                          */
 856                         status |= USB_PORT_STAT_SUSPEND;
 857                 }
 858         }
 859         /*
 860          * Clear stale usb2 resume signalling variables in case port changed
 861          * state during resume signalling. For example on error
 862          */
 863         if ((bus_state->resume_done[wIndex] ||
 864              test_bit(wIndex, &bus_state->resuming_ports)) &&
 865             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 866             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 867                 bus_state->resume_done[wIndex] = 0;
 868                 clear_bit(wIndex, &bus_state->resuming_ports);
 869         }
 870
 871
 872         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 873             (raw_port_status & PORT_POWER)) {
 874                 if (bus_state->suspended_ports & (1 << wIndex)) {
 875                         bus_state->suspended_ports &= ~(1 << wIndex);
 876                         if (hcd->speed < HCD_USB3)
 877                                 bus_state->port_c_suspend |= 1 << wIndex;
 878                 }
 879                 bus_state->resume_done[wIndex] = 0;
 880                 clear_bit(wIndex, &bus_state->resuming_ports);
 881         }
 882         if (raw_port_status & PORT_CONNECT) {
 883                 status |= USB_PORT_STAT_CONNECTION;
 884                 status |= xhci_port_speed(raw_port_status);
 885         }
 886         if (raw_port_status & PORT_PE)
 887                 status |= USB_PORT_STAT_ENABLE;
 888         if (raw_port_status & PORT_OC)
 889                 status |= USB_PORT_STAT_OVERCURRENT;
 890         if (raw_port_status & PORT_RESET)
 891                 status |= USB_PORT_STAT_RESET;
 892         if (raw_port_status & PORT_POWER) {
 893                 if (hcd->speed >= HCD_USB3)
 894                         status |= USB_SS_PORT_STAT_POWER;
 895                 else
 896                         status |= USB_PORT_STAT_POWER;
 897         }
 898         /* Update Port Link State */
 899         if (hcd->speed >= HCD_USB3) {
 900                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
 901                 /*
 902                  * Verify if all USB3 Ports Have entered U0 already.
 903                  * Delete Compliance Mode Timer if so.
 904                  */
 905                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 906         } else {
 907                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 908         }
 909         if (bus_state->port_c_suspend & (1 << wIndex))
 910                 status |= USB_PORT_STAT_C_SUSPEND << 16;
 911
 912         return status;
 913 }
 914
 915 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 916                 u16 wIndex, char *buf, u16 wLength)
 917 {
 918         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 919         int max_ports;
 920         unsigned long flags;
 921         u32 temp, status;
 922         int retval = 0;
 923         __le32 __iomem **port_array;
 924         int slot_id;
 925         struct xhci_bus_state *bus_state;
 926         u16 link_state = 0;
 927         u16 wake_mask = 0;
 928         u16 timeout = 0;
 929
 930         max_ports = xhci_get_ports(hcd, &port_array);
 931         bus_state = &xhci->bus_state[hcd_index(hcd)];
 932
 933         spin_lock_irqsave(&xhci->lock, flags);
 934         switch (typeReq) {
 935         case GetHubStatus:
 936                 /* No power source, over-current reported per port */
 937                 memset(buf, 0, 4);
 938                 break;
 939         case GetHubDescriptor:
 940                 /* Check to make sure userspace is asking for the USB 3.0 hub
 941                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 942                  * endpoint, like external hubs do.
 943                  */
 944                 if (hcd->speed >= HCD_USB3 &&
 945                                 (wLength < USB_DT_SS_HUB_SIZE ||
 946                                  wValue != (USB_DT_SS_HUB << 8))) {
 947                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 948                                         "USB 3.0 roothub.\n");
 949                         goto error;
 950                 }
 951                 xhci_hub_descriptor(hcd, xhci,
 952                                 (struct usb_hub_descriptor *) buf);
 953                 break;
 954         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 955                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 956                         goto error;
 957
 958                 if (hcd->speed < HCD_USB3)
 959                         goto error;
 960
 961                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
 962                 spin_unlock_irqrestore(&xhci->lock, flags);
 963                 return retval;
 964         case GetPortStatus:
 965                 if (!wIndex || wIndex > max_ports)
 966                         goto error;
 967                 wIndex--;
 968                 temp = readl(port_array[wIndex]);
 969                 if (temp == 0xffffffff) {
 970                         retval = -ENODEV;
 971                         break;
 972                 }
 973                 status = xhci_get_port_status(hcd, bus_state, port_array,
 974                                 wIndex, temp, &flags);
 975                 if (status == 0xffffffff)
 976                         goto error;
 977
 978                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 979                                 wIndex, temp);
 980                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 981
 982                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 983                 /* if USB 3.1 extended port status return additional 4 bytes */
 984                 if (wValue == 0x02) {
 985                         u32 port_li;
 986
 987                         if (hcd->speed < HCD_USB31 || wLength != 8) {
 988                                 xhci_err(xhci, "get ext port status invalid parameter\n");
 989                                 retval = -EINVAL;
 990                                 break;
 991                         }
 992                         port_li = readl(port_array[wIndex] + PORTLI);
 993                         status = xhci_get_ext_port_status(temp, port_li);
 994                         put_unaligned_le32(status, &buf[4]);
 995                 }
 996                 break;
 997         case SetPortFeature:
 998                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 999                         link_state = (wIndex & 0xff00) >> 3;
1000                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1001                         wake_mask = wIndex & 0xff00;
1002                 /* The MSB of wIndex is the U1/U2 timeout */
1003                 timeout = (wIndex & 0xff00) >> 8;
1004                 wIndex &= 0xff;
1005                 if (!wIndex || wIndex > max_ports)
1006                         goto error;
1007                 wIndex--;
1008                 temp = readl(port_array[wIndex]);
1009                 if (temp == 0xffffffff) {
1010                         retval = -ENODEV;
1011                         break;
1012                 }
1013                 temp = xhci_port_state_to_neutral(temp);
1014                 /* FIXME: What new port features do we need to support? */
1015                 switch (wValue) {
1016                 case USB_PORT_FEAT_SUSPEND:
1017                         temp = readl(port_array[wIndex]);
1018                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1019                                 /* Resume the port to U0 first */
1020                                 xhci_set_link_state(xhci, port_array, wIndex,
1021                                                         XDEV_U0);
1022                                 spin_unlock_irqrestore(&xhci->lock, flags);
1023                                 msleep(10);
1024                                 spin_lock_irqsave(&xhci->lock, flags);
1025                         }
1026                         /* In spec software should not attempt to suspend
1027                          * a port unless the port reports that it is in the
1028                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1029                          */
1030                         temp = readl(port_array[wIndex]);
1031                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1032                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1033                                 xhci_warn(xhci, "USB core suspending device "
1034                                           "not in U0/U1/U2.\n");
1035                                 goto error;
1036                         }
1037
1038                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1039                                         wIndex + 1);
1040                         if (!slot_id) {
1041                                 xhci_warn(xhci, "slot_id is zero\n");
1042                                 goto error;
1043                         }
1044                         /* unlock to execute stop endpoint commands */
1045                         spin_unlock_irqrestore(&xhci->lock, flags);
1046                         xhci_stop_device(xhci, slot_id, 1);
1047                         spin_lock_irqsave(&xhci->lock, flags);
1048
1049                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1050
1051                         spin_unlock_irqrestore(&xhci->lock, flags);
1052                         msleep(10); /* wait device to enter */
1053                         spin_lock_irqsave(&xhci->lock, flags);
1054
1055                         temp = readl(port_array[wIndex]);
1056                         bus_state->suspended_ports |= 1 << wIndex;
1057                         break;
1058                 case USB_PORT_FEAT_LINK_STATE:
1059                         temp = readl(port_array[wIndex]);
1060
1061                         /* Disable port */
1062                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1063                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1064                                 temp = xhci_port_state_to_neutral(temp);
1065                                 /*
1066                                  * Clear all change bits, so that we get a new
1067                                  * connection event.
1068                                  */
1069                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1070                                         PORT_OCC | PORT_RC | PORT_PLC |
1071                                         PORT_CEC;
1072                                 writel(temp | PORT_PE, port_array[wIndex]);
1073                                 temp = readl(port_array[wIndex]);
1074                                 break;
1075                         }
1076
1077                         /* Put link in RxDetect (enable port) */
1078                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1079                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1080                                 xhci_set_link_state(xhci, port_array, wIndex,
1081                                                 link_state);
1082                                 temp = readl(port_array[wIndex]);
1083                                 break;
1084                         }
1085                         /* Port must be enabled */
1086                         if (!(temp & PORT_PE)) {
1087                                 retval = -ENODEV;
1088                                 break;
1089                         }
1090                         /* Can't set port link state above '3' (U3) */
1091                         if (link_state > USB_SS_PORT_LS_U3) {
1092                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1093                                          wIndex, link_state);
1094                                 goto error;
1095                         }
1096                         if (link_state == USB_SS_PORT_LS_U3) {
1097                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1098                                                 wIndex + 1);
1099                                 if (slot_id) {
1100                                         /* unlock to execute stop endpoint
1101                                          * commands */
1102                                         spin_unlock_irqrestore(&xhci->lock,
1103                                                                 flags);
1104                                         xhci_stop_device(xhci, slot_id, 1);
1105                                         spin_lock_irqsave(&xhci->lock, flags);
1106                                 }
1107                         }
1108
1109                         xhci_set_link_state(xhci, port_array, wIndex,
1110                                                 link_state);
1111
1112                         spin_unlock_irqrestore(&xhci->lock, flags);
1113                         msleep(20); /* wait device to enter */
1114                         spin_lock_irqsave(&xhci->lock, flags);
1115
1116                         temp = readl(port_array[wIndex]);
1117                         if (link_state == USB_SS_PORT_LS_U3)
1118                                 bus_state->suspended_ports |= 1 << wIndex;
1119                         break;
1120                 case USB_PORT_FEAT_POWER:
1121                         /*
1122                          * Turn on ports, even if there isn't per-port switching.
1123                          * HC will report connect events even before this is set.
1124                          * However, hub_wq will ignore the roothub events until
1125                          * the roothub is registered.
1126                          */
1127                         writel(temp | PORT_POWER, port_array[wIndex]);
1128
1129                         temp = readl(port_array[wIndex]);
1130                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
1131
1132                         spin_unlock_irqrestore(&xhci->lock, flags);
1133                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1134                                         wIndex);
1135                         if (temp)
1136                                 usb_acpi_set_power_state(hcd->self.root_hub,
1137                                                 wIndex, true);
1138                         spin_lock_irqsave(&xhci->lock, flags);
1139                         break;
1140                 case USB_PORT_FEAT_RESET:
1141                         temp = (temp | PORT_RESET);
1142                         writel(temp, port_array[wIndex]);
1143
1144                         temp = readl(port_array[wIndex]);
1145                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1146                         break;
1147                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1148                         xhci_set_remote_wake_mask(xhci, port_array,
1149                                         wIndex, wake_mask);
1150                         temp = readl(port_array[wIndex]);
1151                         xhci_dbg(xhci, "set port remote wake mask, "
1152                                         "actual port %d status  = 0x%x\n",
1153                                         wIndex, temp);
1154                         break;
1155                 case USB_PORT_FEAT_BH_PORT_RESET:
1156                         temp |= PORT_WR;
1157                         writel(temp, port_array[wIndex]);
1158
1159                         temp = readl(port_array[wIndex]);
1160                         break;
1161                 case USB_PORT_FEAT_U1_TIMEOUT:
1162                         if (hcd->speed < HCD_USB3)
1163                                 goto error;
1164                         temp = readl(port_array[wIndex] + PORTPMSC);
1165                         temp &= ~PORT_U1_TIMEOUT_MASK;
1166                         temp |= PORT_U1_TIMEOUT(timeout);
1167                         writel(temp, port_array[wIndex] + PORTPMSC);
1168                         break;
1169                 case USB_PORT_FEAT_U2_TIMEOUT:
1170                         if (hcd->speed < HCD_USB3)
1171                                 goto error;
1172                         temp = readl(port_array[wIndex] + PORTPMSC);
1173                         temp &= ~PORT_U2_TIMEOUT_MASK;
1174                         temp |= PORT_U2_TIMEOUT(timeout);
1175                         writel(temp, port_array[wIndex] + PORTPMSC);
1176                         break;
1177                 default:
1178                         goto error;
1179                 }
1180                 /* unblock any posted writes */
1181                 temp = readl(port_array[wIndex]);
1182                 break;
1183         case ClearPortFeature:
1184                 if (!wIndex || wIndex > max_ports)
1185                         goto error;
1186                 wIndex--;
1187                 temp = readl(port_array[wIndex]);
1188                 if (temp == 0xffffffff) {
1189                         retval = -ENODEV;
1190                         break;
1191                 }
1192                 /* FIXME: What new port features do we need to support? */
1193                 temp = xhci_port_state_to_neutral(temp);
1194                 switch (wValue) {
1195                 case USB_PORT_FEAT_SUSPEND:
1196                         temp = readl(port_array[wIndex]);
1197                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1198                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1199                         if (temp & PORT_RESET)
1200                                 goto error;
1201                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1202                                 if ((temp & PORT_PE) == 0)
1203                                         goto error;
1204
1205                                 set_bit(wIndex, &bus_state->resuming_ports);
1206                                 xhci_set_link_state(xhci, port_array, wIndex,
1207                                                         XDEV_RESUME);
1208                                 spin_unlock_irqrestore(&xhci->lock, flags);
1209                                 msleep(USB_RESUME_TIMEOUT);
1210                                 spin_lock_irqsave(&xhci->lock, flags);
1211                                 xhci_set_link_state(xhci, port_array, wIndex,
1212                                                         XDEV_U0);
1213                                 clear_bit(wIndex, &bus_state->resuming_ports);
1214                         }
1215                         bus_state->port_c_suspend |= 1 << wIndex;
1216
1217                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1218                                         wIndex + 1);
1219                         if (!slot_id) {
1220                                 xhci_dbg(xhci, "slot_id is zero\n");
1221                                 goto error;
1222                         }
1223                         xhci_ring_device(xhci, slot_id);
1224                         break;
1225                 case USB_PORT_FEAT_C_SUSPEND:
1226                         bus_state->port_c_suspend &= ~(1 << wIndex);
1227                 case USB_PORT_FEAT_C_RESET:
1228                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1229                 case USB_PORT_FEAT_C_CONNECTION:
1230                 case USB_PORT_FEAT_C_OVER_CURRENT:
1231                 case USB_PORT_FEAT_C_ENABLE:
1232                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1233                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1234                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1235                                         port_array[wIndex], temp);
1236                         break;
1237                 case USB_PORT_FEAT_ENABLE:
1238                         xhci_disable_port(hcd, xhci, wIndex,
1239                                         port_array[wIndex], temp);
1240                         break;
1241                 case USB_PORT_FEAT_POWER:
1242                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1243
1244                         spin_unlock_irqrestore(&xhci->lock, flags);
1245                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1246                                         wIndex);
1247                         if (temp)
1248                                 usb_acpi_set_power_state(hcd->self.root_hub,
1249                                                 wIndex, false);
1250                         spin_lock_irqsave(&xhci->lock, flags);
1251                         break;
1252                 default:
1253                         goto error;
1254                 }
1255                 break;
1256         default:
1257 error:
1258                 /* "stall" on error */
1259                 retval = -EPIPE;
1260         }
1261         spin_unlock_irqrestore(&xhci->lock, flags);
1262         return retval;
1263 }
1264
1265 /*
1266  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1267  * Ports are 0-indexed from the HCD point of view,
1268  * and 1-indexed from the USB core pointer of view.
1269  *
1270  * Note that the status change bits will be cleared as soon as a port status
1271  * change event is generated, so we use the saved status from that event.
1272  */
1273 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1274 {
1275         unsigned long flags;
1276         u32 temp, status;
1277         u32 mask;
1278         int i, retval;
1279         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1280         int max_ports;
1281         __le32 __iomem **port_array;
1282         struct xhci_bus_state *bus_state;
1283         bool reset_change = false;
1284
1285         max_ports = xhci_get_ports(hcd, &port_array);
1286         bus_state = &xhci->bus_state[hcd_index(hcd)];
1287
1288         /* Initial status is no changes */
1289         retval = (max_ports + 8) / 8;
1290         memset(buf, 0, retval);
1291
1292         /*
1293          * Inform the usbcore about resume-in-progress by returning
1294          * a non-zero value even if there are no status changes.
1295          */
1296         spin_lock_irqsave(&xhci->lock, flags);
1297
1298         status = bus_state->resuming_ports;
1299
1300         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1301
1302         /* For each port, did anything change?  If so, set that bit in buf. */
1303         for (i = 0; i < max_ports; i++) {
1304                 temp = readl(port_array[i]);
1305                 if (temp == 0xffffffff) {
1306                         retval = -ENODEV;
1307                         break;
1308                 }
1309                 if ((temp & mask) != 0 ||
1310                         (bus_state->port_c_suspend & 1 << i) ||
1311                         (bus_state->resume_done[i] && time_after_eq(
1312                             jiffies, bus_state->resume_done[i]))) {
1313                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1314                         status = 1;
1315                 }
1316                 if ((temp & PORT_RC))
1317                         reset_change = true;
1318         }
1319         if (!status && !reset_change) {
1320                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1321                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1322         }
1323         spin_unlock_irqrestore(&xhci->lock, flags);
1324         return status ? retval : 0;
1325 }
1326
1327 #ifdef CONFIG_PM
1328
1329 int xhci_bus_suspend(struct usb_hcd *hcd)
1330 {
1331         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1332         int max_ports, port_index;
1333         __le32 __iomem **port_array;
1334         struct xhci_bus_state *bus_state;
1335         unsigned long flags;
1336         u32 portsc_buf[USB_MAXCHILDREN];
1337         bool wake_enabled;
1338
1339         max_ports = xhci_get_ports(hcd, &port_array);
1340         bus_state = &xhci->bus_state[hcd_index(hcd)];
1341         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1342
1343         spin_lock_irqsave(&xhci->lock, flags);
1344
1345         if (wake_enabled) {
1346                 if (bus_state->resuming_ports ||        /* USB2 */
1347                     bus_state->port_remote_wakeup) {    /* USB3 */
1348                         spin_unlock_irqrestore(&xhci->lock, flags);
1349                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1350                         return -EBUSY;
1351                 }
1352         }
1353         /*
1354          * Prepare ports for suspend, but don't write anything before all ports
1355          * are checked and we know bus suspend can proceed
1356          */
1357         bus_state->bus_suspended = 0;
1358         port_index = max_ports;
1359         while (port_index--) {
1360                 u32 t1, t2;
1361
1362                 t1 = readl(port_array[port_index]);
1363                 t2 = xhci_port_state_to_neutral(t1);
1364                 portsc_buf[port_index] = 0;
1365
1366                 /* Bail out if a USB3 port has a new device in link training */
1367                 if ((hcd->speed >= HCD_USB3) &&
1368                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1369                         bus_state->bus_suspended = 0;
1370                         spin_unlock_irqrestore(&xhci->lock, flags);
1371                         xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1372                         return -EBUSY;
1373                 }
1374
1375                 /* suspend ports in U0, or bail out for new connect changes */
1376                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1377                         if ((t1 & PORT_CSC) && wake_enabled) {
1378                                 bus_state->bus_suspended = 0;
1379                                 spin_unlock_irqrestore(&xhci->lock, flags);
1380                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1381                                 return -EBUSY;
1382                         }
1383                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1384                         t2 &= ~PORT_PLS_MASK;
1385                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1386                         set_bit(port_index, &bus_state->bus_suspended);
1387                 }
1388                 /* USB core sets remote wake mask for USB 3.0 hubs,
1389                  * including the USB 3.0 roothub, but only if CONFIG_PM
1390                  * is enabled, so also enable remote wake here.
1391                  */
1392                 if (wake_enabled) {
1393                         if (t1 & PORT_CONNECT) {
1394                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1395                                 t2 &= ~PORT_WKCONN_E;
1396                         } else {
1397                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1398                                 t2 &= ~PORT_WKDISC_E;
1399                         }
1400                 } else
1401                         t2 &= ~PORT_WAKE_BITS;
1402
1403                 t1 = xhci_port_state_to_neutral(t1);
1404                 if (t1 != t2)
1405                         portsc_buf[port_index] = t2;
1406         }
1407
1408         /* write port settings, stopping and suspending ports if needed */
1409         port_index = max_ports;
1410         while (port_index--) {
1411                 if (!portsc_buf[port_index])
1412                         continue;
1413                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1414                         int slot_id;
1415
1416                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1417                                                             port_index + 1);
1418                         if (slot_id) {
1419                                 spin_unlock_irqrestore(&xhci->lock, flags);
1420                                 xhci_stop_device(xhci, slot_id, 1);
1421                                 spin_lock_irqsave(&xhci->lock, flags);
1422                         }
1423                 }
1424                 writel(portsc_buf[port_index], port_array[port_index]);
1425         }
1426         hcd->state = HC_STATE_SUSPENDED;
1427         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1428         spin_unlock_irqrestore(&xhci->lock, flags);
1429
1430         if (bus_state->bus_suspended)
1431                 usleep_range(5000, 10000);
1432
1433         return 0;
1434 }
1435
1436 /*
1437  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1438  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1439  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1440  */
1441 static bool xhci_port_missing_cas_quirk(int port_index,
1442                                              __le32 __iomem **port_array)
1443 {
1444         u32 portsc;
1445
1446         portsc = readl(port_array[port_index]);
1447
1448         /* if any of these are set we are not stuck */
1449         if (portsc & (PORT_CONNECT | PORT_CAS))
1450                 return false;
1451
1452         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1453             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1454                 return false;
1455
1456         /* clear wakeup/change bits, and do a warm port reset */
1457         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1458         portsc |= PORT_WR;
1459         writel(portsc, port_array[port_index]);
1460         /* flush write */
1461         readl(port_array[port_index]);
1462         return true;
1463 }
1464
1465 int xhci_bus_resume(struct usb_hcd *hcd)
1466 {
1467         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1468         int max_ports, port_index;
1469         __le32 __iomem **port_array;
1470         struct xhci_bus_state *bus_state;
1471         u32 temp;
1472         unsigned long flags;
1473         unsigned long port_was_suspended = 0;
1474         bool need_usb2_u3_exit = false;
1475         int slot_id;
1476         int sret;
1477
1478         max_ports = xhci_get_ports(hcd, &port_array);
1479         bus_state = &xhci->bus_state[hcd_index(hcd)];
1480
1481         if (time_before(jiffies, bus_state->next_statechange))
1482                 msleep(5);
1483
1484         spin_lock_irqsave(&xhci->lock, flags);
1485         if (!HCD_HW_ACCESSIBLE(hcd)) {
1486                 spin_unlock_irqrestore(&xhci->lock, flags);
1487                 return -ESHUTDOWN;
1488         }
1489
1490         /* delay the irqs */
1491         temp = readl(&xhci->op_regs->command);
1492         temp &= ~CMD_EIE;
1493         writel(temp, &xhci->op_regs->command);
1494
1495         port_index = max_ports;
1496         while (port_index--) {
1497                 /* Check whether need resume ports. If needed
1498                    resume port and disable remote wakeup */
1499                 u32 temp;
1500
1501                 temp = readl(port_array[port_index]);
1502
1503                 /* warm reset CAS limited ports stuck in polling/compliance */
1504                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1505                     (hcd->speed >= HCD_USB3) &&
1506                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1507                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1508                         continue;
1509                 }
1510                 if (DEV_SUPERSPEED_ANY(temp))
1511                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1512                 else
1513                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1514                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1515                     (temp & PORT_PLS_MASK)) {
1516                         set_bit(port_index, &port_was_suspended);
1517                         if (!DEV_SUPERSPEED_ANY(temp)) {
1518                                 xhci_set_link_state(xhci, port_array,
1519                                                 port_index, XDEV_RESUME);
1520                                 need_usb2_u3_exit = true;
1521                         }
1522                 } else
1523                         writel(temp, port_array[port_index]);
1524         }
1525
1526         if (need_usb2_u3_exit) {
1527                 spin_unlock_irqrestore(&xhci->lock, flags);
1528                 msleep(USB_RESUME_TIMEOUT);
1529                 spin_lock_irqsave(&xhci->lock, flags);
1530         }
1531
1532         port_index = max_ports;
1533         while (port_index--) {
1534                 if (!(port_was_suspended & BIT(port_index)))
1535                         continue;
1536                 /* Clear PLC to poll it later after XDEV_U0 */
1537                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1538                 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1539         }
1540
1541         port_index = max_ports;
1542         while (port_index--) {
1543                 if (!(port_was_suspended & BIT(port_index)))
1544                         continue;
1545                 /* Poll and Clear PLC */
1546                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1547                                       PORT_PLC, 10 * 1000);
1548                 if (sret)
1549                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1550                                   port_index);
1551                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1552                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1553                 if (slot_id)
1554                         xhci_ring_device(xhci, slot_id);
1555         }
1556
1557         (void) readl(&xhci->op_regs->command);
1558
1559         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1560         /* re-enable irqs */
1561         temp = readl(&xhci->op_regs->command);
1562         temp |= CMD_EIE;
1563         writel(temp, &xhci->op_regs->command);
1564         temp = readl(&xhci->op_regs->command);
1565
1566         spin_unlock_irqrestore(&xhci->lock, flags);
1567         return 0;
1568 }
1569
1570 #endif  /* CONFIG_PM */