drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         struct xhci_port_cap *port_cap = NULL;
  59         int i, ssa_count;
  60         u32 temp;
  61         u16 desc_size, ssp_cap_size, ssa_size = 0;
  62         bool usb3_1 = false;
  63
  64         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  65         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  66
  67         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  68         for (i = 0; i < xhci->num_port_caps; i++) {
  69                 if (xhci->port_caps[i].maj_rev == 0x03 &&
  70                     xhci->port_caps[i].min_rev >= 0x01) {
  71                         usb3_1 = true;
  72                         port_cap = &xhci->port_caps[i];
  73                         break;
  74                 }
  75         }
  76
  77         if (usb3_1) {
  78                 /* does xhci provide a PSI table for SSA speed attributes? */
  79                 if (port_cap->psi_count) {
  80                         /* two SSA entries for each unique PSI ID, RX and TX */
  81                         ssa_count = port_cap->psi_uid_count * 2;
  82                         ssa_size = ssa_count * sizeof(u32);
  83                         ssp_cap_size -= 16; /* skip copying the default SSA */
  84                 }
  85                 desc_size += ssp_cap_size;
  86         }
  87         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  88
  89         if (usb3_1) {
  90                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  91                 buf[4] += 1;
  92                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  93         }
  94
  95         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  96                 return wLength;
  97
  98         /* Indicate whether the host has LTM support. */
  99         temp = readl(&xhci->cap_regs->hcc_params);
 100         if (HCC_LTC(temp))
 101                 buf[8] |= USB_LTM_SUPPORT;
 102
 103         /* Set the U1 and U2 exit latencies. */
 104         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 105                 temp = readl(&xhci->cap_regs->hcs_params3);
 106                 buf[12] = HCS_U1_LATENCY(temp);
 107                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 108         }
 109
 110         /* If PSI table exists, add the custom speed attributes from it */
 111         if (usb3_1 && port_cap->psi_count) {
 112                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 113                 int offset;
 114
 115                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 116
 117                 if (wLength < desc_size)
 118                         return wLength;
 119                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 120
 121                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 122                 bm_attrib = (ssa_count - 1) & 0x1f;
 123                 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
 124                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 125
 126                 if (wLength < desc_size + ssa_size)
 127                         return wLength;
 128                 /*
 129                  * Create the Sublink Speed Attributes (SSA) array.
 130                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 131                  * but link type bits 7:6 differ for values 01b and 10b.
 132                  * xhci has also only one PSI entry for a symmetric link when
 133                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 134                  */
 135                 offset = desc_size;
 136                 for (i = 0; i < port_cap->psi_count; i++) {
 137                         psi = port_cap->psi[i];
 138                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 139                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 140                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 141
 142                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 143                         for (; psi_exp < 3; psi_exp++)
 144                                 psi_mant /= 1000;
 145                         if (psi_mant >= 10)
 146                                 psi |= BIT(14);
 147
 148                         if ((psi & PLT_MASK) == PLT_SYM) {
 149                         /* Symmetric, create SSA RX and TX from one PSI entry */
 150                                 put_unaligned_le32(psi, &buf[offset]);
 151                                 psi |= 1 << 7;  /* turn entry to TX */
 152                                 offset += 4;
 153                                 if (offset >= desc_size + ssa_size)
 154                                         return desc_size + ssa_size;
 155                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 156                                 /* Asymetric RX, flip bits 7:6 for SSA */
 157                                 psi ^= PLT_MASK;
 158                         }
 159                         put_unaligned_le32(psi, &buf[offset]);
 160                         offset += 4;
 161                         if (offset >= desc_size + ssa_size)
 162                                 return desc_size + ssa_size;
 163                 }
 164         }
 165         /* ssa_size is 0 for other than usb 3.1 hosts */
 166         return desc_size + ssa_size;
 167 }
 168
 169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 170                 struct usb_hub_descriptor *desc, int ports)
 171 {
 172         u16 temp;
 173
 174         desc->bHubContrCurrent = 0;
 175
 176         desc->bNbrPorts = ports;
 177         temp = 0;
 178         /* Bits 1:0 - support per-port power switching, or power always on */
 179         if (HCC_PPC(xhci->hcc_params))
 180                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 181         else
 182                 temp |= HUB_CHAR_NO_LPSM;
 183         /* Bit  2 - root hubs are not part of a compound device */
 184         /* Bits 4:3 - individual port over current protection */
 185         temp |= HUB_CHAR_INDV_PORT_OCPM;
 186         /* Bits 6:5 - no TTs in root ports */
 187         /* Bit  7 - no port indicators */
 188         desc->wHubCharacteristics = cpu_to_le16(temp);
 189 }
 190
 191 /* Fill in the USB 2.0 roothub descriptor */
 192 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 193                 struct usb_hub_descriptor *desc)
 194 {
 195         int ports;
 196         u16 temp;
 197         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 198         u32 portsc;
 199         unsigned int i;
 200         struct xhci_hub *rhub;
 201
 202         rhub = &xhci->usb2_rhub;
 203         ports = rhub->num_ports;
 204         xhci_common_hub_descriptor(xhci, desc, ports);
 205         desc->bDescriptorType = USB_DT_HUB;
 206         temp = 1 + (ports / 8);
 207         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 208         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.8 says 20ms */
 209
 210         /* The Device Removable bits are reported on a byte granularity.
 211          * If the port doesn't exist within that byte, the bit is set to 0.
 212          */
 213         memset(port_removable, 0, sizeof(port_removable));
 214         for (i = 0; i < ports; i++) {
 215                 portsc = readl(rhub->ports[i]->addr);
 216                 /* If a device is removable, PORTSC reports a 0, same as in the
 217                  * hub descriptor DeviceRemovable bits.
 218                  */
 219                 if (portsc & PORT_DEV_REMOVE)
 220                         /* This math is hairy because bit 0 of DeviceRemovable
 221                          * is reserved, and bit 1 is for port 1, etc.
 222                          */
 223                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 224         }
 225
 226         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 227          * ports on it.  The USB 2.0 specification says that there are two
 228          * variable length fields at the end of the hub descriptor:
 229          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 230          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 231          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 232          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 233          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 234          * set of ports that actually exist.
 235          */
 236         memset(desc->u.hs.DeviceRemovable, 0xff,
 237                         sizeof(desc->u.hs.DeviceRemovable));
 238         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 239                         sizeof(desc->u.hs.PortPwrCtrlMask));
 240
 241         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 242                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 243                                 sizeof(__u8));
 244 }
 245
 246 /* Fill in the USB 3.0 roothub descriptor */
 247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 248                 struct usb_hub_descriptor *desc)
 249 {
 250         int ports;
 251         u16 port_removable;
 252         u32 portsc;
 253         unsigned int i;
 254         struct xhci_hub *rhub;
 255
 256         rhub = &xhci->usb3_rhub;
 257         ports = rhub->num_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261         desc->bPwrOn2PwrGood = 50;      /* usb 3.1 may fail if less than 100ms */
 262
 263         /* header decode latency should be zero for roothubs,
 264          * see section 4.23.5.2.
 265          */
 266         desc->u.ss.bHubHdrDecLat = 0;
 267         desc->u.ss.wHubDelay = 0;
 268
 269         port_removable = 0;
 270         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 271         for (i = 0; i < ports; i++) {
 272                 portsc = readl(rhub->ports[i]->addr);
 273                 if (portsc & PORT_DEV_REMOVE)
 274                         port_removable |= 1 << (i + 1);
 275         }
 276
 277         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 278 }
 279
 280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 281                 struct usb_hub_descriptor *desc)
 282 {
 283
 284         if (hcd->speed >= HCD_USB3)
 285                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 286         else
 287                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 288
 289 }
 290
 291 static unsigned int xhci_port_speed(unsigned int port_status)
 292 {
 293         if (DEV_LOWSPEED(port_status))
 294                 return USB_PORT_STAT_LOW_SPEED;
 295         if (DEV_HIGHSPEED(port_status))
 296                 return USB_PORT_STAT_HIGH_SPEED;
 297         /*
 298          * FIXME: Yes, we should check for full speed, but the core uses that as
 299          * a default in portspeed() in usb/core/hub.c (which is the only place
 300          * USB_PORT_STAT_*_SPEED is used).
 301          */
 302         return 0;
 303 }
 304
 305 /*
 306  * These bits are Read Only (RO) and should be saved and written to the
 307  * registers: 0, 3, 10:13, 30
 308  * connect status, over-current status, port speed, and device removable.
 309  * connect status and port speed are also sticky - meaning they're in
 310  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 311  */
 312 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 313 /*
 314  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 315  * bits 5:8, 9, 14:15, 25:27
 316  * link state, port power, port indicator state, "wake on" enable state
 317  */
 318 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 319 /*
 320  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 321  * bit 4 (port reset)
 322  */
 323 #define XHCI_PORT_RW1S  ((1<<4))
 324 /*
 325  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 326  * bits 1, 17, 18, 19, 20, 21, 22, 23
 327  * port enable/disable, and
 328  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 329  * over-current, reset, link state, and L1 change
 330  */
 331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 332 /*
 333  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 334  * latched in
 335  */
 336 #define XHCI_PORT_RW    ((1<<16))
 337 /*
 338  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 339  * bits 2, 24, 28:31
 340  */
 341 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 342
 343 /*
 344  * Given a port state, this function returns a value that would result in the
 345  * port being in the same state, if the value was written to the port status
 346  * control register.
 347  * Save Read Only (RO) bits and save read/write bits where
 348  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 349  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 350  */
 351 u32 xhci_port_state_to_neutral(u32 state)
 352 {
 353         /* Save read-only status and port state */
 354         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 355 }
 356
 357 /*
 358  * find slot id based on port number.
 359  * @port: The one-based port number from one of the two split roothubs.
 360  */
 361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 362                 u16 port)
 363 {
 364         int slot_id;
 365         int i;
 366         enum usb_device_speed speed;
 367
 368         slot_id = 0;
 369         for (i = 0; i < MAX_HC_SLOTS; i++) {
 370                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 371                         continue;
 372                 speed = xhci->devs[i]->udev->speed;
 373                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 374                                 && xhci->devs[i]->fake_port == port) {
 375                         slot_id = i;
 376                         break;
 377                 }
 378         }
 379
 380         return slot_id;
 381 }
 382
 383 /*
 384  * Stop device
 385  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 386  * to complete.
 387  * suspend will set to 1, if suspend bit need to set in command.
 388  */
 389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 390 {
 391         struct xhci_virt_device *virt_dev;
 392         struct xhci_command *cmd;
 393         unsigned long flags;
 394         int ret;
 395         int i;
 396
 397         ret = 0;
 398         virt_dev = xhci->devs[slot_id];
 399         if (!virt_dev)
 400                 return -ENODEV;
 401
 402         trace_xhci_stop_device(virt_dev);
 403
 404         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 405         if (!cmd)
 406                 return -ENOMEM;
 407
 408         spin_lock_irqsave(&xhci->lock, flags);
 409         for (i = LAST_EP_INDEX; i > 0; i--) {
 410                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 411                         struct xhci_ep_ctx *ep_ctx;
 412                         struct xhci_command *command;
 413
 414                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 415
 416                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 417                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 418                                 continue;
 419
 420                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 421                         if (!command) {
 422                                 spin_unlock_irqrestore(&xhci->lock, flags);
 423                                 ret = -ENOMEM;
 424                                 goto cmd_cleanup;
 425                         }
 426
 427                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 428                                                        i, suspend);
 429                         if (ret) {
 430                                 spin_unlock_irqrestore(&xhci->lock, flags);
 431                                 xhci_free_command(xhci, command);
 432                                 goto cmd_cleanup;
 433                         }
 434                 }
 435         }
 436         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 437         if (ret) {
 438                 spin_unlock_irqrestore(&xhci->lock, flags);
 439                 goto cmd_cleanup;
 440         }
 441
 442         xhci_ring_cmd_db(xhci);
 443         spin_unlock_irqrestore(&xhci->lock, flags);
 444
 445         /* Wait for last stop endpoint command to finish */
 446         wait_for_completion(cmd->completion);
 447
 448         if (cmd->status == COMP_COMMAND_ABORTED ||
 449             cmd->status == COMP_COMMAND_RING_STOPPED) {
 450                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 451                 ret = -ETIME;
 452         }
 453
 454 cmd_cleanup:
 455         xhci_free_command(xhci, cmd);
 456         return ret;
 457 }
 458
 459 /*
 460  * Ring device, it rings the all doorbells unconditionally.
 461  */
 462 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 463 {
 464         int i, s;
 465         struct xhci_virt_ep *ep;
 466
 467         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 468                 ep = &xhci->devs[slot_id]->eps[i];
 469
 470                 if (ep->ep_state & EP_HAS_STREAMS) {
 471                         for (s = 1; s < ep->stream_info->num_streams; s++)
 472                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 473                 } else if (ep->ring && ep->ring->dequeue) {
 474                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 475                 }
 476         }
 477
 478         return;
 479 }
 480
 481 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 482                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 483 {
 484         /* Don't allow the USB core to disable SuperSpeed ports. */
 485         if (hcd->speed >= HCD_USB3) {
 486                 xhci_dbg(xhci, "Ignoring request to disable "
 487                                 "SuperSpeed port.\n");
 488                 return;
 489         }
 490
 491         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 492                 xhci_dbg(xhci,
 493                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 494                 return;
 495         }
 496
 497         /* Write 1 to disable the port */
 498         writel(port_status | PORT_PE, addr);
 499         port_status = readl(addr);
 500         xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
 501                  hcd->self.busnum, wIndex + 1, port_status);
 502 }
 503
 504 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 505                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 506 {
 507         char *port_change_bit;
 508         u32 status;
 509
 510         switch (wValue) {
 511         case USB_PORT_FEAT_C_RESET:
 512                 status = PORT_RC;
 513                 port_change_bit = "reset";
 514                 break;
 515         case USB_PORT_FEAT_C_BH_PORT_RESET:
 516                 status = PORT_WRC;
 517                 port_change_bit = "warm(BH) reset";
 518                 break;
 519         case USB_PORT_FEAT_C_CONNECTION:
 520                 status = PORT_CSC;
 521                 port_change_bit = "connect";
 522                 break;
 523         case USB_PORT_FEAT_C_OVER_CURRENT:
 524                 status = PORT_OCC;
 525                 port_change_bit = "over-current";
 526                 break;
 527         case USB_PORT_FEAT_C_ENABLE:
 528                 status = PORT_PEC;
 529                 port_change_bit = "enable/disable";
 530                 break;
 531         case USB_PORT_FEAT_C_SUSPEND:
 532                 status = PORT_PLC;
 533                 port_change_bit = "suspend/resume";
 534                 break;
 535         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 536                 status = PORT_PLC;
 537                 port_change_bit = "link state";
 538                 break;
 539         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 540                 status = PORT_CEC;
 541                 port_change_bit = "config error";
 542                 break;
 543         default:
 544                 /* Should never happen */
 545                 return;
 546         }
 547         /* Change bits are all write 1 to clear */
 548         writel(port_status | status, addr);
 549         port_status = readl(addr);
 550
 551         xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
 552                  wIndex + 1, port_change_bit, port_status);
 553 }
 554
 555 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 556 {
 557         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 558
 559         if (hcd->speed >= HCD_USB3)
 560                 return &xhci->usb3_rhub;
 561         return &xhci->usb2_rhub;
 562 }
 563
 564 /*
 565  * xhci_set_port_power() must be called with xhci->lock held.
 566  * It will release and re-aquire the lock while calling ACPI
 567  * method.
 568  */
 569 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 570                                 u16 index, bool on, unsigned long *flags)
 571         __must_hold(&xhci->lock)
 572 {
 573         struct xhci_hub *rhub;
 574         struct xhci_port *port;
 575         u32 temp;
 576
 577         rhub = xhci_get_rhub(hcd);
 578         port = rhub->ports[index];
 579         temp = readl(port->addr);
 580
 581         xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
 582                  hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
 583
 584         temp = xhci_port_state_to_neutral(temp);
 585
 586         if (on) {
 587                 /* Power on */
 588                 writel(temp | PORT_POWER, port->addr);
 589                 readl(port->addr);
 590         } else {
 591                 /* Power off */
 592                 writel(temp & ~PORT_POWER, port->addr);
 593         }
 594
 595         spin_unlock_irqrestore(&xhci->lock, *flags);
 596         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 597                                         index);
 598         if (temp)
 599                 usb_acpi_set_power_state(hcd->self.root_hub,
 600                         index, on);
 601         spin_lock_irqsave(&xhci->lock, *flags);
 602 }
 603
 604 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 605         u16 test_mode, u16 wIndex)
 606 {
 607         u32 temp;
 608         struct xhci_port *port;
 609
 610         /* xhci only supports test mode for usb2 ports */
 611         port = xhci->usb2_rhub.ports[wIndex];
 612         temp = readl(port->addr + PORTPMSC);
 613         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 614         writel(temp, port->addr + PORTPMSC);
 615         xhci->test_mode = test_mode;
 616         if (test_mode == USB_TEST_FORCE_ENABLE)
 617                 xhci_start(xhci);
 618 }
 619
 620 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 621                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 622         __must_hold(&xhci->lock)
 623 {
 624         int i, retval;
 625
 626         /* Disable all Device Slots */
 627         xhci_dbg(xhci, "Disable all slots\n");
 628         spin_unlock_irqrestore(&xhci->lock, *flags);
 629         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 630                 if (!xhci->devs[i])
 631                         continue;
 632
 633                 retval = xhci_disable_slot(xhci, i);
 634                 xhci_free_virt_device(xhci, i);
 635                 if (retval)
 636                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 637                                  i, retval);
 638         }
 639         spin_lock_irqsave(&xhci->lock, *flags);
 640         /* Put all ports to the Disable state by clear PP */
 641         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 642         /* Power off USB3 ports*/
 643         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 644                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 645         /* Power off USB2 ports*/
 646         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 647                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 648         /* Stop the controller */
 649         xhci_dbg(xhci, "Stop controller\n");
 650         retval = xhci_halt(xhci);
 651         if (retval)
 652                 return retval;
 653         /* Disable runtime PM for test mode */
 654         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 655         /* Set PORTPMSC.PTC field to enter selected test mode */
 656         /* Port is selected by wIndex. port_id = wIndex + 1 */
 657         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 658                                         test_mode, wIndex + 1);
 659         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 660         return retval;
 661 }
 662
 663 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 664 {
 665         int retval;
 666
 667         if (!xhci->test_mode) {
 668                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 669                 return 0;
 670         }
 671         if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
 672                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 673                 retval = xhci_halt(xhci);
 674                 if (retval)
 675                         return retval;
 676         }
 677         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 678         xhci->test_mode = 0;
 679         return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 680 }
 681
 682 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 683                          u32 link_state)
 684 {
 685         u32 temp;
 686         u32 portsc;
 687
 688         portsc = readl(port->addr);
 689         temp = xhci_port_state_to_neutral(portsc);
 690         temp &= ~PORT_PLS_MASK;
 691         temp |= PORT_LINK_STROBE | link_state;
 692         writel(temp, port->addr);
 693
 694         xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
 695                  port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
 696                  portsc, temp);
 697 }
 698
 699 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 700                                       struct xhci_port *port, u16 wake_mask)
 701 {
 702         u32 temp;
 703
 704         temp = readl(port->addr);
 705         temp = xhci_port_state_to_neutral(temp);
 706
 707         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 708                 temp |= PORT_WKCONN_E;
 709         else
 710                 temp &= ~PORT_WKCONN_E;
 711
 712         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 713                 temp |= PORT_WKDISC_E;
 714         else
 715                 temp &= ~PORT_WKDISC_E;
 716
 717         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 718                 temp |= PORT_WKOC_E;
 719         else
 720                 temp &= ~PORT_WKOC_E;
 721
 722         writel(temp, port->addr);
 723 }
 724
 725 /* Test and clear port RWC bit */
 726 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 727                              u32 port_bit)
 728 {
 729         u32 temp;
 730
 731         temp = readl(port->addr);
 732         if (temp & port_bit) {
 733                 temp = xhci_port_state_to_neutral(temp);
 734                 temp |= port_bit;
 735                 writel(temp, port->addr);
 736         }
 737 }
 738
 739 /* Updates Link Status for super Speed port */
 740 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 741                 u32 *status, u32 status_reg)
 742 {
 743         u32 pls = status_reg & PORT_PLS_MASK;
 744
 745         /* When the CAS bit is set then warm reset
 746          * should be performed on port
 747          */
 748         if (status_reg & PORT_CAS) {
 749                 /* The CAS bit can be set while the port is
 750                  * in any link state.
 751                  * Only roothubs have CAS bit, so we
 752                  * pretend to be in compliance mode
 753                  * unless we're already in compliance
 754                  * or the inactive state.
 755                  */
 756                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 757                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 758                         pls = USB_SS_PORT_LS_COMP_MOD;
 759                 }
 760                 /* Return also connection bit -
 761                  * hub state machine resets port
 762                  * when this bit is set.
 763                  */
 764                 pls |= USB_PORT_STAT_CONNECTION;
 765         } else {
 766                 /*
 767                  * Resume state is an xHCI internal state.  Do not report it to
 768                  * usb core, instead, pretend to be U3, thus usb core knows
 769                  * it's not ready for transfer.
 770                  */
 771                 if (pls == XDEV_RESUME) {
 772                         *status |= USB_SS_PORT_LS_U3;
 773                         return;
 774                 }
 775
 776                 /*
 777                  * If CAS bit isn't set but the Port is already at
 778                  * Compliance Mode, fake a connection so the USB core
 779                  * notices the Compliance state and resets the port.
 780                  * This resolves an issue generated by the SN65LVPE502CP
 781                  * in which sometimes the port enters compliance mode
 782                  * caused by a delay on the host-device negotiation.
 783                  */
 784                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 785                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 786                         pls |= USB_PORT_STAT_CONNECTION;
 787         }
 788
 789         /* update status field */
 790         *status |= pls;
 791 }
 792
 793 /*
 794  * Function for Compliance Mode Quirk.
 795  *
 796  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 797  * the compliance mode timer is deleted. A port won't enter
 798  * compliance mode if it has previously entered U0.
 799  */
 800 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 801                                     u16 wIndex)
 802 {
 803         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 804         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 805
 806         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 807                 return;
 808
 809         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 810                 xhci->port_status_u0 |= 1 << wIndex;
 811                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 812                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 813                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 814                                 "All USB3 ports have entered U0 already!");
 815                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 816                                 "Compliance Mode Recovery Timer Deleted.");
 817                 }
 818         }
 819 }
 820
 821 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
 822                                              u32 *status, u32 portsc,
 823                                              unsigned long *flags)
 824 {
 825         struct xhci_bus_state *bus_state;
 826         struct xhci_hcd *xhci;
 827         struct usb_hcd *hcd;
 828         int slot_id;
 829         u32 wIndex;
 830
 831         hcd = port->rhub->hcd;
 832         bus_state = &port->rhub->bus_state;
 833         xhci = hcd_to_xhci(hcd);
 834         wIndex = port->hcd_portnum;
 835
 836         if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
 837                 *status = 0xffffffff;
 838                 return -EINVAL;
 839         }
 840         /* did port event handler already start resume timing? */
 841         if (!bus_state->resume_done[wIndex]) {
 842                 /* If not, maybe we are in a host initated resume? */
 843                 if (test_bit(wIndex, &bus_state->resuming_ports)) {
 844                         /* Host initated resume doesn't time the resume
 845                          * signalling using resume_done[].
 846                          * It manually sets RESUME state, sleeps 20ms
 847                          * and sets U0 state. This should probably be
 848                          * changed, but not right now.
 849                          */
 850                 } else {
 851                         /* port resume was discovered now and here,
 852                          * start resume timing
 853                          */
 854                         unsigned long timeout = jiffies +
 855                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
 856
 857                         set_bit(wIndex, &bus_state->resuming_ports);
 858                         bus_state->resume_done[wIndex] = timeout;
 859                         mod_timer(&hcd->rh_timer, timeout);
 860                         usb_hcd_start_port_resume(&hcd->self, wIndex);
 861                 }
 862         /* Has resume been signalled for USB_RESUME_TIME yet? */
 863         } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
 864                 int time_left;
 865
 866                 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
 867                          hcd->self.busnum, wIndex + 1);
 868
 869                 bus_state->resume_done[wIndex] = 0;
 870                 clear_bit(wIndex, &bus_state->resuming_ports);
 871
 872                 set_bit(wIndex, &bus_state->rexit_ports);
 873
 874                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 875                 xhci_set_link_state(xhci, port, XDEV_U0);
 876
 877                 spin_unlock_irqrestore(&xhci->lock, *flags);
 878                 time_left = wait_for_completion_timeout(
 879                         &bus_state->rexit_done[wIndex],
 880                         msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
 881                 spin_lock_irqsave(&xhci->lock, *flags);
 882
 883                 if (time_left) {
 884                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 885                                                             wIndex + 1);
 886                         if (!slot_id) {
 887                                 xhci_dbg(xhci, "slot_id is zero\n");
 888                                 *status = 0xffffffff;
 889                                 return -ENODEV;
 890                         }
 891                         xhci_ring_device(xhci, slot_id);
 892                 } else {
 893                         int port_status = readl(port->addr);
 894
 895                         xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
 896                                   hcd->self.busnum, wIndex + 1, port_status);
 897                         *status |= USB_PORT_STAT_SUSPEND;
 898                         clear_bit(wIndex, &bus_state->rexit_ports);
 899                 }
 900
 901                 usb_hcd_end_port_resume(&hcd->self, wIndex);
 902                 bus_state->port_c_suspend |= 1 << wIndex;
 903                 bus_state->suspended_ports &= ~(1 << wIndex);
 904         } else {
 905                 /*
 906                  * The resume has been signaling for less than
 907                  * USB_RESUME_TIME. Report the port status as SUSPEND,
 908                  * let the usbcore check port status again and clear
 909                  * resume signaling later.
 910                  */
 911                 *status |= USB_PORT_STAT_SUSPEND;
 912         }
 913         return 0;
 914 }
 915
 916 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 917 {
 918         u32 ext_stat = 0;
 919         int speed_id;
 920
 921         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 922         speed_id = DEV_PORT_SPEED(raw_port_status);
 923         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 924         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 925
 926         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 927         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 928
 929         return ext_stat;
 930 }
 931
 932 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
 933                                       u32 portsc)
 934 {
 935         struct xhci_bus_state *bus_state;
 936         struct xhci_hcd *xhci;
 937         struct usb_hcd *hcd;
 938         u32 link_state;
 939         u32 portnum;
 940
 941         bus_state = &port->rhub->bus_state;
 942         xhci = hcd_to_xhci(port->rhub->hcd);
 943         hcd = port->rhub->hcd;
 944         link_state = portsc & PORT_PLS_MASK;
 945         portnum = port->hcd_portnum;
 946
 947         /* USB3 specific wPortChange bits
 948          *
 949          * Port link change with port in resume state should not be
 950          * reported to usbcore, as this is an internal state to be
 951          * handled by xhci driver. Reporting PLC to usbcore may
 952          * cause usbcore clearing PLC first and port change event
 953          * irq won't be generated.
 954          */
 955
 956         if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
 957                 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
 958         if (portsc & PORT_WRC)
 959                 *status |= USB_PORT_STAT_C_BH_RESET << 16;
 960         if (portsc & PORT_CEC)
 961                 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 962
 963         /* USB3 specific wPortStatus bits */
 964         if (portsc & PORT_POWER) {
 965                 *status |= USB_SS_PORT_STAT_POWER;
 966                 /* link state handling */
 967                 if (link_state == XDEV_U0)
 968                         bus_state->suspended_ports &= ~(1 << portnum);
 969         }
 970
 971         /* remote wake resume signaling complete */
 972         if (bus_state->port_remote_wakeup & (1 << portnum) &&
 973             link_state != XDEV_RESUME &&
 974             link_state != XDEV_RECOVERY) {
 975                 bus_state->port_remote_wakeup &= ~(1 << portnum);
 976                 usb_hcd_end_port_resume(&hcd->self, portnum);
 977         }
 978
 979         xhci_hub_report_usb3_link_state(xhci, status, portsc);
 980         xhci_del_comp_mod_timer(xhci, portsc, portnum);
 981 }
 982
 983 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
 984                                       u32 portsc, unsigned long *flags)
 985 {
 986         struct xhci_bus_state *bus_state;
 987         u32 link_state;
 988         u32 portnum;
 989         int ret;
 990
 991         bus_state = &port->rhub->bus_state;
 992         link_state = portsc & PORT_PLS_MASK;
 993         portnum = port->hcd_portnum;
 994
 995         /* USB2 wPortStatus bits */
 996         if (portsc & PORT_POWER) {
 997                 *status |= USB_PORT_STAT_POWER;
 998
 999                 /* link state is only valid if port is powered */
1000                 if (link_state == XDEV_U3)
1001                         *status |= USB_PORT_STAT_SUSPEND;
1002                 if (link_state == XDEV_U2)
1003                         *status |= USB_PORT_STAT_L1;
1004                 if (link_state == XDEV_U0) {
1005                         if (bus_state->resume_done[portnum])
1006                                 usb_hcd_end_port_resume(&port->rhub->hcd->self,
1007                                                         portnum);
1008                         bus_state->resume_done[portnum] = 0;
1009                         clear_bit(portnum, &bus_state->resuming_ports);
1010                         if (bus_state->suspended_ports & (1 << portnum)) {
1011                                 bus_state->suspended_ports &= ~(1 << portnum);
1012                                 bus_state->port_c_suspend |= 1 << portnum;
1013                         }
1014                 }
1015                 if (link_state == XDEV_RESUME) {
1016                         ret = xhci_handle_usb2_port_link_resume(port, status,
1017                                                                 portsc, flags);
1018                         if (ret)
1019                                 return;
1020                 }
1021         }
1022 }
1023
1024 /*
1025  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1026  * 3.0 hubs use.
1027  *
1028  * Possible side effects:
1029  *  - Mark a port as being done with device resume,
1030  *    and ring the endpoint doorbells.
1031  *  - Stop the Synopsys redriver Compliance Mode polling.
1032  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1033  */
1034 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1035                 struct xhci_bus_state *bus_state,
1036         u16 wIndex, u32 raw_port_status,
1037                 unsigned long *flags)
1038         __releases(&xhci->lock)
1039         __acquires(&xhci->lock)
1040 {
1041         u32 status = 0;
1042         struct xhci_hub *rhub;
1043         struct xhci_port *port;
1044
1045         rhub = xhci_get_rhub(hcd);
1046         port = rhub->ports[wIndex];
1047
1048         /* common wPortChange bits */
1049         if (raw_port_status & PORT_CSC)
1050                 status |= USB_PORT_STAT_C_CONNECTION << 16;
1051         if (raw_port_status & PORT_PEC)
1052                 status |= USB_PORT_STAT_C_ENABLE << 16;
1053         if ((raw_port_status & PORT_OCC))
1054                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1055         if ((raw_port_status & PORT_RC))
1056                 status |= USB_PORT_STAT_C_RESET << 16;
1057
1058         /* common wPortStatus bits */
1059         if (raw_port_status & PORT_CONNECT) {
1060                 status |= USB_PORT_STAT_CONNECTION;
1061                 status |= xhci_port_speed(raw_port_status);
1062         }
1063         if (raw_port_status & PORT_PE)
1064                 status |= USB_PORT_STAT_ENABLE;
1065         if (raw_port_status & PORT_OC)
1066                 status |= USB_PORT_STAT_OVERCURRENT;
1067         if (raw_port_status & PORT_RESET)
1068                 status |= USB_PORT_STAT_RESET;
1069
1070         /* USB2 and USB3 specific bits, including Port Link State */
1071         if (hcd->speed >= HCD_USB3)
1072                 xhci_get_usb3_port_status(port, &status, raw_port_status);
1073         else
1074                 xhci_get_usb2_port_status(port, &status, raw_port_status,
1075                                           flags);
1076         /*
1077          * Clear stale usb2 resume signalling variables in case port changed
1078          * state during resume signalling. For example on error
1079          */
1080         if ((bus_state->resume_done[wIndex] ||
1081              test_bit(wIndex, &bus_state->resuming_ports)) &&
1082             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1083             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1084                 bus_state->resume_done[wIndex] = 0;
1085                 clear_bit(wIndex, &bus_state->resuming_ports);
1086                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1087         }
1088
1089         if (bus_state->port_c_suspend & (1 << wIndex))
1090                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1091
1092         return status;
1093 }
1094
1095 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1096                 u16 wIndex, char *buf, u16 wLength)
1097 {
1098         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1099         int max_ports;
1100         unsigned long flags;
1101         u32 temp, status;
1102         int retval = 0;
1103         int slot_id;
1104         struct xhci_bus_state *bus_state;
1105         u16 link_state = 0;
1106         u16 wake_mask = 0;
1107         u16 timeout = 0;
1108         u16 test_mode = 0;
1109         struct xhci_hub *rhub;
1110         struct xhci_port **ports;
1111
1112         rhub = xhci_get_rhub(hcd);
1113         ports = rhub->ports;
1114         max_ports = rhub->num_ports;
1115         bus_state = &rhub->bus_state;
1116
1117         spin_lock_irqsave(&xhci->lock, flags);
1118         switch (typeReq) {
1119         case GetHubStatus:
1120                 /* No power source, over-current reported per port */
1121                 memset(buf, 0, 4);
1122                 break;
1123         case GetHubDescriptor:
1124                 /* Check to make sure userspace is asking for the USB 3.0 hub
1125                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1126                  * endpoint, like external hubs do.
1127                  */
1128                 if (hcd->speed >= HCD_USB3 &&
1129                                 (wLength < USB_DT_SS_HUB_SIZE ||
1130                                  wValue != (USB_DT_SS_HUB << 8))) {
1131                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1132                                         "USB 3.0 roothub.\n");
1133                         goto error;
1134                 }
1135                 xhci_hub_descriptor(hcd, xhci,
1136                                 (struct usb_hub_descriptor *) buf);
1137                 break;
1138         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1139                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1140                         goto error;
1141
1142                 if (hcd->speed < HCD_USB3)
1143                         goto error;
1144
1145                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1146                 spin_unlock_irqrestore(&xhci->lock, flags);
1147                 return retval;
1148         case GetPortStatus:
1149                 if (!wIndex || wIndex > max_ports)
1150                         goto error;
1151                 wIndex--;
1152                 temp = readl(ports[wIndex]->addr);
1153                 if (temp == ~(u32)0) {
1154                         xhci_hc_died(xhci);
1155                         retval = -ENODEV;
1156                         break;
1157                 }
1158                 trace_xhci_get_port_status(wIndex, temp);
1159                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1160                                               &flags);
1161                 if (status == 0xffffffff)
1162                         goto error;
1163
1164                 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1165                          hcd->self.busnum, wIndex + 1, temp, status);
1166
1167                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1168                 /* if USB 3.1 extended port status return additional 4 bytes */
1169                 if (wValue == 0x02) {
1170                         u32 port_li;
1171
1172                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1173                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1174                                 retval = -EINVAL;
1175                                 break;
1176                         }
1177                         port_li = readl(ports[wIndex]->addr + PORTLI);
1178                         status = xhci_get_ext_port_status(temp, port_li);
1179                         put_unaligned_le32(status, &buf[4]);
1180                 }
1181                 break;
1182         case SetPortFeature:
1183                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1184                         link_state = (wIndex & 0xff00) >> 3;
1185                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1186                         wake_mask = wIndex & 0xff00;
1187                 if (wValue == USB_PORT_FEAT_TEST)
1188                         test_mode = (wIndex & 0xff00) >> 8;
1189                 /* The MSB of wIndex is the U1/U2 timeout */
1190                 timeout = (wIndex & 0xff00) >> 8;
1191                 wIndex &= 0xff;
1192                 if (!wIndex || wIndex > max_ports)
1193                         goto error;
1194                 wIndex--;
1195                 temp = readl(ports[wIndex]->addr);
1196                 if (temp == ~(u32)0) {
1197                         xhci_hc_died(xhci);
1198                         retval = -ENODEV;
1199                         break;
1200                 }
1201                 temp = xhci_port_state_to_neutral(temp);
1202                 /* FIXME: What new port features do we need to support? */
1203                 switch (wValue) {
1204                 case USB_PORT_FEAT_SUSPEND:
1205                         temp = readl(ports[wIndex]->addr);
1206                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1207                                 /* Resume the port to U0 first */
1208                                 xhci_set_link_state(xhci, ports[wIndex],
1209                                                         XDEV_U0);
1210                                 spin_unlock_irqrestore(&xhci->lock, flags);
1211                                 msleep(10);
1212                                 spin_lock_irqsave(&xhci->lock, flags);
1213                         }
1214                         /* In spec software should not attempt to suspend
1215                          * a port unless the port reports that it is in the
1216                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1217                          */
1218                         temp = readl(ports[wIndex]->addr);
1219                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1220                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1221                                 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1222                                           hcd->self.busnum, wIndex + 1);
1223                                 goto error;
1224                         }
1225
1226                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1227                                         wIndex + 1);
1228                         if (!slot_id) {
1229                                 xhci_warn(xhci, "slot_id is zero\n");
1230                                 goto error;
1231                         }
1232                         /* unlock to execute stop endpoint commands */
1233                         spin_unlock_irqrestore(&xhci->lock, flags);
1234                         xhci_stop_device(xhci, slot_id, 1);
1235                         spin_lock_irqsave(&xhci->lock, flags);
1236
1237                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1238
1239                         spin_unlock_irqrestore(&xhci->lock, flags);
1240                         msleep(10); /* wait device to enter */
1241                         spin_lock_irqsave(&xhci->lock, flags);
1242
1243                         temp = readl(ports[wIndex]->addr);
1244                         bus_state->suspended_ports |= 1 << wIndex;
1245                         break;
1246                 case USB_PORT_FEAT_LINK_STATE:
1247                         temp = readl(ports[wIndex]->addr);
1248                         /* Disable port */
1249                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1250                                 xhci_dbg(xhci, "Disable port %d-%d\n",
1251                                          hcd->self.busnum, wIndex + 1);
1252                                 temp = xhci_port_state_to_neutral(temp);
1253                                 /*
1254                                  * Clear all change bits, so that we get a new
1255                                  * connection event.
1256                                  */
1257                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1258                                         PORT_OCC | PORT_RC | PORT_PLC |
1259                                         PORT_CEC;
1260                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1261                                 temp = readl(ports[wIndex]->addr);
1262                                 break;
1263                         }
1264
1265                         /* Put link in RxDetect (enable port) */
1266                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1267                                 xhci_dbg(xhci, "Enable port %d-%d\n",
1268                                          hcd->self.busnum, wIndex + 1);
1269                                 xhci_set_link_state(xhci, ports[wIndex],
1270                                                         link_state);
1271                                 temp = readl(ports[wIndex]->addr);
1272                                 break;
1273                         }
1274
1275                         /*
1276                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1277                          * root hub port's transition to compliance mode upon
1278                          * detecting LFPS timeout may be controlled by an
1279                          * Compliance Transition Enabled (CTE) flag (not
1280                          * software visible). This flag is set by writing 0xA
1281                          * to PORTSC PLS field which will allow transition to
1282                          * compliance mode the next time LFPS timeout is
1283                          * encountered. A warm reset will clear it.
1284                          *
1285                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1286                          * flag is set, otherwise, the compliance substate is
1287                          * automatically entered as on 1.0 and prior.
1288                          */
1289                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1290                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1291                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1292                                         break;
1293                                 }
1294
1295                                 if ((temp & PORT_CONNECT)) {
1296                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1297                                         goto error;
1298                                 }
1299
1300                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1301                                          hcd->self.busnum, wIndex + 1);
1302                                 xhci_set_link_state(xhci, ports[wIndex],
1303                                                 link_state);
1304
1305                                 temp = readl(ports[wIndex]->addr);
1306                                 break;
1307                         }
1308                         /* Port must be enabled */
1309                         if (!(temp & PORT_PE)) {
1310                                 retval = -ENODEV;
1311                                 break;
1312                         }
1313                         /* Can't set port link state above '3' (U3) */
1314                         if (link_state > USB_SS_PORT_LS_U3) {
1315                                 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1316                                           hcd->self.busnum, wIndex + 1,
1317                                           link_state);
1318                                 goto error;
1319                         }
1320
1321                         /*
1322                          * set link to U0, steps depend on current link state.
1323                          * U3: set link to U0 and wait for u3exit completion.
1324                          * U1/U2:  no PLC complete event, only set link to U0.
1325                          * Resume/Recovery: device initiated U0, only wait for
1326                          * completion
1327                          */
1328                         if (link_state == USB_SS_PORT_LS_U0) {
1329                                 u32 pls = temp & PORT_PLS_MASK;
1330                                 bool wait_u0 = false;
1331
1332                                 /* already in U0 */
1333                                 if (pls == XDEV_U0)
1334                                         break;
1335                                 if (pls == XDEV_U3 ||
1336                                     pls == XDEV_RESUME ||
1337                                     pls == XDEV_RECOVERY) {
1338                                         wait_u0 = true;
1339                                         reinit_completion(&bus_state->u3exit_done[wIndex]);
1340                                 }
1341                                 if (pls <= XDEV_U3) /* U1, U2, U3 */
1342                                         xhci_set_link_state(xhci, ports[wIndex],
1343                                                             USB_SS_PORT_LS_U0);
1344                                 if (!wait_u0) {
1345                                         if (pls > XDEV_U3)
1346                                                 goto error;
1347                                         break;
1348                                 }
1349                                 spin_unlock_irqrestore(&xhci->lock, flags);
1350                                 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1351                                                                  msecs_to_jiffies(500)))
1352                                         xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1353                                                  hcd->self.busnum, wIndex + 1);
1354                                 spin_lock_irqsave(&xhci->lock, flags);
1355                                 temp = readl(ports[wIndex]->addr);
1356                                 break;
1357                         }
1358
1359                         if (link_state == USB_SS_PORT_LS_U3) {
1360                                 int retries = 16;
1361                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1362                                                 wIndex + 1);
1363                                 if (slot_id) {
1364                                         /* unlock to execute stop endpoint
1365                                          * commands */
1366                                         spin_unlock_irqrestore(&xhci->lock,
1367                                                                 flags);
1368                                         xhci_stop_device(xhci, slot_id, 1);
1369                                         spin_lock_irqsave(&xhci->lock, flags);
1370                                 }
1371                                 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1372                                 spin_unlock_irqrestore(&xhci->lock, flags);
1373                                 while (retries--) {
1374                                         usleep_range(4000, 8000);
1375                                         temp = readl(ports[wIndex]->addr);
1376                                         if ((temp & PORT_PLS_MASK) == XDEV_U3)
1377                                                 break;
1378                                 }
1379                                 spin_lock_irqsave(&xhci->lock, flags);
1380                                 temp = readl(ports[wIndex]->addr);
1381                                 bus_state->suspended_ports |= 1 << wIndex;
1382                         }
1383                         break;
1384                 case USB_PORT_FEAT_POWER:
1385                         /*
1386                          * Turn on ports, even if there isn't per-port switching.
1387                          * HC will report connect events even before this is set.
1388                          * However, hub_wq will ignore the roothub events until
1389                          * the roothub is registered.
1390                          */
1391                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1392                         break;
1393                 case USB_PORT_FEAT_RESET:
1394                         temp = (temp | PORT_RESET);
1395                         writel(temp, ports[wIndex]->addr);
1396
1397                         temp = readl(ports[wIndex]->addr);
1398                         xhci_dbg(xhci, "set port reset, actual port %d-%d status  = 0x%x\n",
1399                                  hcd->self.busnum, wIndex + 1, temp);
1400                         break;
1401                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1402                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1403                                                   wake_mask);
1404                         temp = readl(ports[wIndex]->addr);
1405                         xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status  = 0x%x\n",
1406                                  hcd->self.busnum, wIndex + 1, temp);
1407                         break;
1408                 case USB_PORT_FEAT_BH_PORT_RESET:
1409                         temp |= PORT_WR;
1410                         writel(temp, ports[wIndex]->addr);
1411                         temp = readl(ports[wIndex]->addr);
1412                         break;
1413                 case USB_PORT_FEAT_U1_TIMEOUT:
1414                         if (hcd->speed < HCD_USB3)
1415                                 goto error;
1416                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1417                         temp &= ~PORT_U1_TIMEOUT_MASK;
1418                         temp |= PORT_U1_TIMEOUT(timeout);
1419                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1420                         break;
1421                 case USB_PORT_FEAT_U2_TIMEOUT:
1422                         if (hcd->speed < HCD_USB3)
1423                                 goto error;
1424                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1425                         temp &= ~PORT_U2_TIMEOUT_MASK;
1426                         temp |= PORT_U2_TIMEOUT(timeout);
1427                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1428                         break;
1429                 case USB_PORT_FEAT_TEST:
1430                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1431                         if (hcd->speed != HCD_USB2)
1432                                 goto error;
1433                         if (test_mode > USB_TEST_FORCE_ENABLE ||
1434                             test_mode < USB_TEST_J)
1435                                 goto error;
1436                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1437                                                       &flags);
1438                         break;
1439                 default:
1440                         goto error;
1441                 }
1442                 /* unblock any posted writes */
1443                 temp = readl(ports[wIndex]->addr);
1444                 break;
1445         case ClearPortFeature:
1446                 if (!wIndex || wIndex > max_ports)
1447                         goto error;
1448                 wIndex--;
1449                 temp = readl(ports[wIndex]->addr);
1450                 if (temp == ~(u32)0) {
1451                         xhci_hc_died(xhci);
1452                         retval = -ENODEV;
1453                         break;
1454                 }
1455                 /* FIXME: What new port features do we need to support? */
1456                 temp = xhci_port_state_to_neutral(temp);
1457                 switch (wValue) {
1458                 case USB_PORT_FEAT_SUSPEND:
1459                         temp = readl(ports[wIndex]->addr);
1460                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1461                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1462                         if (temp & PORT_RESET)
1463                                 goto error;
1464                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1465                                 if ((temp & PORT_PE) == 0)
1466                                         goto error;
1467
1468                                 set_bit(wIndex, &bus_state->resuming_ports);
1469                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1470                                 xhci_set_link_state(xhci, ports[wIndex],
1471                                                     XDEV_RESUME);
1472                                 spin_unlock_irqrestore(&xhci->lock, flags);
1473                                 msleep(USB_RESUME_TIMEOUT);
1474                                 spin_lock_irqsave(&xhci->lock, flags);
1475                                 xhci_set_link_state(xhci, ports[wIndex],
1476                                                         XDEV_U0);
1477                                 clear_bit(wIndex, &bus_state->resuming_ports);
1478                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1479                         }
1480                         bus_state->port_c_suspend |= 1 << wIndex;
1481
1482                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1483                                         wIndex + 1);
1484                         if (!slot_id) {
1485                                 xhci_dbg(xhci, "slot_id is zero\n");
1486                                 goto error;
1487                         }
1488                         xhci_ring_device(xhci, slot_id);
1489                         break;
1490                 case USB_PORT_FEAT_C_SUSPEND:
1491                         bus_state->port_c_suspend &= ~(1 << wIndex);
1492                         fallthrough;
1493                 case USB_PORT_FEAT_C_RESET:
1494                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1495                 case USB_PORT_FEAT_C_CONNECTION:
1496                 case USB_PORT_FEAT_C_OVER_CURRENT:
1497                 case USB_PORT_FEAT_C_ENABLE:
1498                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1499                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1500                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1501                                         ports[wIndex]->addr, temp);
1502                         break;
1503                 case USB_PORT_FEAT_ENABLE:
1504                         xhci_disable_port(hcd, xhci, wIndex,
1505                                         ports[wIndex]->addr, temp);
1506                         break;
1507                 case USB_PORT_FEAT_POWER:
1508                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1509                         break;
1510                 case USB_PORT_FEAT_TEST:
1511                         retval = xhci_exit_test_mode(xhci);
1512                         break;
1513                 default:
1514                         goto error;
1515                 }
1516                 break;
1517         default:
1518 error:
1519                 /* "stall" on error */
1520                 retval = -EPIPE;
1521         }
1522         spin_unlock_irqrestore(&xhci->lock, flags);
1523         return retval;
1524 }
1525
1526 /*
1527  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1528  * Ports are 0-indexed from the HCD point of view,
1529  * and 1-indexed from the USB core pointer of view.
1530  *
1531  * Note that the status change bits will be cleared as soon as a port status
1532  * change event is generated, so we use the saved status from that event.
1533  */
1534 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1535 {
1536         unsigned long flags;
1537         u32 temp, status;
1538         u32 mask;
1539         int i, retval;
1540         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1541         int max_ports;
1542         struct xhci_bus_state *bus_state;
1543         bool reset_change = false;
1544         struct xhci_hub *rhub;
1545         struct xhci_port **ports;
1546
1547         rhub = xhci_get_rhub(hcd);
1548         ports = rhub->ports;
1549         max_ports = rhub->num_ports;
1550         bus_state = &rhub->bus_state;
1551
1552         /* Initial status is no changes */
1553         retval = (max_ports + 8) / 8;
1554         memset(buf, 0, retval);
1555
1556         /*
1557          * Inform the usbcore about resume-in-progress by returning
1558          * a non-zero value even if there are no status changes.
1559          */
1560         spin_lock_irqsave(&xhci->lock, flags);
1561
1562         status = bus_state->resuming_ports;
1563
1564         /*
1565          * SS devices are only visible to roothub after link training completes.
1566          * Keep polling roothubs for a grace period after xHC start
1567          */
1568         if (xhci->run_graceperiod) {
1569                 if (time_before(jiffies, xhci->run_graceperiod))
1570                         status = 1;
1571                 else
1572                         xhci->run_graceperiod = 0;
1573         }
1574
1575         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1576
1577         /* For each port, did anything change?  If so, set that bit in buf. */
1578         for (i = 0; i < max_ports; i++) {
1579                 temp = readl(ports[i]->addr);
1580                 if (temp == ~(u32)0) {
1581                         xhci_hc_died(xhci);
1582                         retval = -ENODEV;
1583                         break;
1584                 }
1585                 trace_xhci_hub_status_data(i, temp);
1586
1587                 if ((temp & mask) != 0 ||
1588                         (bus_state->port_c_suspend & 1 << i) ||
1589                         (bus_state->resume_done[i] && time_after_eq(
1590                             jiffies, bus_state->resume_done[i]))) {
1591                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1592                         status = 1;
1593                 }
1594                 if ((temp & PORT_RC))
1595                         reset_change = true;
1596                 if (temp & PORT_OC)
1597                         status = 1;
1598         }
1599         if (!status && !reset_change) {
1600                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1601                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1602         }
1603         spin_unlock_irqrestore(&xhci->lock, flags);
1604         return status ? retval : 0;
1605 }
1606
1607 #ifdef CONFIG_PM
1608
1609 int xhci_bus_suspend(struct usb_hcd *hcd)
1610 {
1611         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1612         int max_ports, port_index;
1613         struct xhci_bus_state *bus_state;
1614         unsigned long flags;
1615         struct xhci_hub *rhub;
1616         struct xhci_port **ports;
1617         u32 portsc_buf[USB_MAXCHILDREN];
1618         bool wake_enabled;
1619
1620         rhub = xhci_get_rhub(hcd);
1621         ports = rhub->ports;
1622         max_ports = rhub->num_ports;
1623         bus_state = &rhub->bus_state;
1624         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1625
1626         spin_lock_irqsave(&xhci->lock, flags);
1627
1628         if (wake_enabled) {
1629                 if (bus_state->resuming_ports ||        /* USB2 */
1630                     bus_state->port_remote_wakeup) {    /* USB3 */
1631                         spin_unlock_irqrestore(&xhci->lock, flags);
1632                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1633                         return -EBUSY;
1634                 }
1635         }
1636         /*
1637          * Prepare ports for suspend, but don't write anything before all ports
1638          * are checked and we know bus suspend can proceed
1639          */
1640         bus_state->bus_suspended = 0;
1641         port_index = max_ports;
1642         while (port_index--) {
1643                 u32 t1, t2;
1644                 int retries = 10;
1645 retry:
1646                 t1 = readl(ports[port_index]->addr);
1647                 t2 = xhci_port_state_to_neutral(t1);
1648                 portsc_buf[port_index] = 0;
1649
1650                 /*
1651                  * Give a USB3 port in link training time to finish, but don't
1652                  * prevent suspend as port might be stuck
1653                  */
1654                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1655                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1656                         spin_unlock_irqrestore(&xhci->lock, flags);
1657                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1658                         spin_lock_irqsave(&xhci->lock, flags);
1659                         xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1660                                  hcd->self.busnum, port_index + 1);
1661                         goto retry;
1662                 }
1663                 /* bail out if port detected a over-current condition */
1664                 if (t1 & PORT_OC) {
1665                         bus_state->bus_suspended = 0;
1666                         spin_unlock_irqrestore(&xhci->lock, flags);
1667                         xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1668                         return -EBUSY;
1669                 }
1670                 /* suspend ports in U0, or bail out for new connect changes */
1671                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1672                         if ((t1 & PORT_CSC) && wake_enabled) {
1673                                 bus_state->bus_suspended = 0;
1674                                 spin_unlock_irqrestore(&xhci->lock, flags);
1675                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1676                                 return -EBUSY;
1677                         }
1678                         xhci_dbg(xhci, "port %d-%d not suspended\n",
1679                                  hcd->self.busnum, port_index + 1);
1680                         t2 &= ~PORT_PLS_MASK;
1681                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1682                         set_bit(port_index, &bus_state->bus_suspended);
1683                 }
1684                 /* USB core sets remote wake mask for USB 3.0 hubs,
1685                  * including the USB 3.0 roothub, but only if CONFIG_PM
1686                  * is enabled, so also enable remote wake here.
1687                  */
1688                 if (wake_enabled) {
1689                         if (t1 & PORT_CONNECT) {
1690                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1691                                 t2 &= ~PORT_WKCONN_E;
1692                         } else {
1693                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1694                                 t2 &= ~PORT_WKDISC_E;
1695                         }
1696
1697                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1698                             (hcd->speed < HCD_USB3)) {
1699                                 if (usb_amd_pt_check_port(hcd->self.controller,
1700                                                           port_index))
1701                                         t2 &= ~PORT_WAKE_BITS;
1702                         }
1703                 } else
1704                         t2 &= ~PORT_WAKE_BITS;
1705
1706                 t1 = xhci_port_state_to_neutral(t1);
1707                 if (t1 != t2)
1708                         portsc_buf[port_index] = t2;
1709         }
1710
1711         /* write port settings, stopping and suspending ports if needed */
1712         port_index = max_ports;
1713         while (port_index--) {
1714                 if (!portsc_buf[port_index])
1715                         continue;
1716                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1717                         int slot_id;
1718
1719                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1720                                                             port_index + 1);
1721                         if (slot_id) {
1722                                 spin_unlock_irqrestore(&xhci->lock, flags);
1723                                 xhci_stop_device(xhci, slot_id, 1);
1724                                 spin_lock_irqsave(&xhci->lock, flags);
1725                         }
1726                 }
1727                 writel(portsc_buf[port_index], ports[port_index]->addr);
1728         }
1729         hcd->state = HC_STATE_SUSPENDED;
1730         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1731         spin_unlock_irqrestore(&xhci->lock, flags);
1732
1733         if (bus_state->bus_suspended)
1734                 usleep_range(5000, 10000);
1735
1736         return 0;
1737 }
1738
1739 /*
1740  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1741  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1742  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1743  */
1744 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1745 {
1746         u32 portsc;
1747
1748         portsc = readl(port->addr);
1749
1750         /* if any of these are set we are not stuck */
1751         if (portsc & (PORT_CONNECT | PORT_CAS))
1752                 return false;
1753
1754         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1755             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1756                 return false;
1757
1758         /* clear wakeup/change bits, and do a warm port reset */
1759         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1760         portsc |= PORT_WR;
1761         writel(portsc, port->addr);
1762         /* flush write */
1763         readl(port->addr);
1764         return true;
1765 }
1766
1767 int xhci_bus_resume(struct usb_hcd *hcd)
1768 {
1769         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1770         struct xhci_bus_state *bus_state;
1771         unsigned long flags;
1772         int max_ports, port_index;
1773         int slot_id;
1774         int sret;
1775         u32 next_state;
1776         u32 temp, portsc;
1777         struct xhci_hub *rhub;
1778         struct xhci_port **ports;
1779
1780         rhub = xhci_get_rhub(hcd);
1781         ports = rhub->ports;
1782         max_ports = rhub->num_ports;
1783         bus_state = &rhub->bus_state;
1784
1785         if (time_before(jiffies, bus_state->next_statechange))
1786                 msleep(5);
1787
1788         spin_lock_irqsave(&xhci->lock, flags);
1789         if (!HCD_HW_ACCESSIBLE(hcd)) {
1790                 spin_unlock_irqrestore(&xhci->lock, flags);
1791                 return -ESHUTDOWN;
1792         }
1793
1794         /* delay the irqs */
1795         temp = readl(&xhci->op_regs->command);
1796         temp &= ~CMD_EIE;
1797         writel(temp, &xhci->op_regs->command);
1798
1799         /* bus specific resume for ports we suspended at bus_suspend */
1800         if (hcd->speed >= HCD_USB3)
1801                 next_state = XDEV_U0;
1802         else
1803                 next_state = XDEV_RESUME;
1804
1805         port_index = max_ports;
1806         while (port_index--) {
1807                 portsc = readl(ports[port_index]->addr);
1808
1809                 /* warm reset CAS limited ports stuck in polling/compliance */
1810                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1811                     (hcd->speed >= HCD_USB3) &&
1812                     xhci_port_missing_cas_quirk(ports[port_index])) {
1813                         xhci_dbg(xhci, "reset stuck port %d-%d\n",
1814                                  hcd->self.busnum, port_index + 1);
1815                         clear_bit(port_index, &bus_state->bus_suspended);
1816                         continue;
1817                 }
1818                 /* resume if we suspended the link, and it is still suspended */
1819                 if (test_bit(port_index, &bus_state->bus_suspended))
1820                         switch (portsc & PORT_PLS_MASK) {
1821                         case XDEV_U3:
1822                                 portsc = xhci_port_state_to_neutral(portsc);
1823                                 portsc &= ~PORT_PLS_MASK;
1824                                 portsc |= PORT_LINK_STROBE | next_state;
1825                                 break;
1826                         case XDEV_RESUME:
1827                                 /* resume already initiated */
1828                                 break;
1829                         default:
1830                                 /* not in a resumeable state, ignore it */
1831                                 clear_bit(port_index,
1832                                           &bus_state->bus_suspended);
1833                                 break;
1834                         }
1835                 /* disable wake for all ports, write new link state if needed */
1836                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1837                 writel(portsc, ports[port_index]->addr);
1838         }
1839
1840         /* USB2 specific resume signaling delay and U0 link state transition */
1841         if (hcd->speed < HCD_USB3) {
1842                 if (bus_state->bus_suspended) {
1843                         spin_unlock_irqrestore(&xhci->lock, flags);
1844                         msleep(USB_RESUME_TIMEOUT);
1845                         spin_lock_irqsave(&xhci->lock, flags);
1846                 }
1847                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1848                                  BITS_PER_LONG) {
1849                         /* Clear PLC to poll it later for U0 transition */
1850                         xhci_test_and_clear_bit(xhci, ports[port_index],
1851                                                 PORT_PLC);
1852                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1853                 }
1854         }
1855
1856         /* poll for U0 link state complete, both USB2 and USB3 */
1857         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1858                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1859                                       PORT_PLC, 10 * 1000);
1860                 if (sret) {
1861                         xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1862                                   hcd->self.busnum, port_index + 1);
1863                         continue;
1864                 }
1865                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1866                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1867                 if (slot_id)
1868                         xhci_ring_device(xhci, slot_id);
1869         }
1870         (void) readl(&xhci->op_regs->command);
1871
1872         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1873         /* re-enable irqs */
1874         temp = readl(&xhci->op_regs->command);
1875         temp |= CMD_EIE;
1876         writel(temp, &xhci->op_regs->command);
1877         temp = readl(&xhci->op_regs->command);
1878
1879         spin_unlock_irqrestore(&xhci->lock, flags);
1880         return 0;
1881 }
1882
1883 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1884 {
1885         struct xhci_hub *rhub = xhci_get_rhub(hcd);
1886
1887         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1888         return rhub->bus_state.resuming_ports;  /* USB2 ports only */
1889 }
1890
1891 #endif  /* CONFIG_PM */