drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x1c,                           /* bLength 28, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  58         0x01, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  61         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  62         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  63         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  64         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  65 };
  66
  67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  68                                      u16 wLength)
  69 {
  70         int i, ssa_count;
  71         u32 temp;
  72         u16 desc_size, ssp_cap_size, ssa_size = 0;
  73         bool usb3_1 = false;
  74
  75         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  76         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  77
  78         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  79         if (xhci->usb3_rhub.min_rev >= 0x01) {
  80                 /* does xhci provide a PSI table for SSA speed attributes? */
  81                 if (xhci->usb3_rhub.psi_count) {
  82                         /* two SSA entries for each unique PSI ID, RX and TX */
  83                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  84                         ssa_size = ssa_count * sizeof(u32);
  85                         ssp_cap_size -= 16; /* skip copying the default SSA */
  86                 }
  87                 desc_size += ssp_cap_size;
  88                 usb3_1 = true;
  89         }
  90         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  91
  92         if (usb3_1) {
  93                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  94                 buf[4] += 1;
  95                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  96         }
  97
  98         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  99                 return wLength;
 100
 101         /* Indicate whether the host has LTM support. */
 102         temp = readl(&xhci->cap_regs->hcc_params);
 103         if (HCC_LTC(temp))
 104                 buf[8] |= USB_LTM_SUPPORT;
 105
 106         /* Set the U1 and U2 exit latencies. */
 107         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 108                 temp = readl(&xhci->cap_regs->hcs_params3);
 109                 buf[12] = HCS_U1_LATENCY(temp);
 110                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 111         }
 112
 113         /* If PSI table exists, add the custom speed attributes from it */
 114         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 115                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 116                 int offset;
 117
 118                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 119
 120                 if (wLength < desc_size)
 121                         return wLength;
 122                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 123
 124                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 125                 bm_attrib = (ssa_count - 1) & 0x1f;
 126                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 127                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 128
 129                 if (wLength < desc_size + ssa_size)
 130                         return wLength;
 131                 /*
 132                  * Create the Sublink Speed Attributes (SSA) array.
 133                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 134                  * but link type bits 7:6 differ for values 01b and 10b.
 135                  * xhci has also only one PSI entry for a symmetric link when
 136                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 137                  */
 138                 offset = desc_size;
 139                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 140                         psi = xhci->usb3_rhub.psi[i];
 141                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 142                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 143                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 144
 145                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 146                         for (; psi_exp < 3; psi_exp++)
 147                                 psi_mant /= 1000;
 148                         if (psi_mant >= 10)
 149                                 psi |= BIT(14);
 150
 151                         if ((psi & PLT_MASK) == PLT_SYM) {
 152                         /* Symmetric, create SSA RX and TX from one PSI entry */
 153                                 put_unaligned_le32(psi, &buf[offset]);
 154                                 psi |= 1 << 7;  /* turn entry to TX */
 155                                 offset += 4;
 156                                 if (offset >= desc_size + ssa_size)
 157                                         return desc_size + ssa_size;
 158                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 159                                 /* Asymetric RX, flip bits 7:6 for SSA */
 160                                 psi ^= PLT_MASK;
 161                         }
 162                         put_unaligned_le32(psi, &buf[offset]);
 163                         offset += 4;
 164                         if (offset >= desc_size + ssa_size)
 165                                 return desc_size + ssa_size;
 166                 }
 167         }
 168         /* ssa_size is 0 for other than usb 3.1 hosts */
 169         return desc_size + ssa_size;
 170 }
 171
 172 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 173                 struct usb_hub_descriptor *desc, int ports)
 174 {
 175         u16 temp;
 176
 177         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 178         desc->bHubContrCurrent = 0;
 179
 180         desc->bNbrPorts = ports;
 181         temp = 0;
 182         /* Bits 1:0 - support per-port power switching, or power always on */
 183         if (HCC_PPC(xhci->hcc_params))
 184                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 185         else
 186                 temp |= HUB_CHAR_NO_LPSM;
 187         /* Bit  2 - root hubs are not part of a compound device */
 188         /* Bits 4:3 - individual port over current protection */
 189         temp |= HUB_CHAR_INDV_PORT_OCPM;
 190         /* Bits 6:5 - no TTs in root ports */
 191         /* Bit  7 - no port indicators */
 192         desc->wHubCharacteristics = cpu_to_le16(temp);
 193 }
 194
 195 /* Fill in the USB 2.0 roothub descriptor */
 196 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 197                 struct usb_hub_descriptor *desc)
 198 {
 199         int ports;
 200         u16 temp;
 201         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 202         u32 portsc;
 203         unsigned int i;
 204
 205         ports = xhci->num_usb2_ports;
 206
 207         xhci_common_hub_descriptor(xhci, desc, ports);
 208         desc->bDescriptorType = USB_DT_HUB;
 209         temp = 1 + (ports / 8);
 210         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 211
 212         /* The Device Removable bits are reported on a byte granularity.
 213          * If the port doesn't exist within that byte, the bit is set to 0.
 214          */
 215         memset(port_removable, 0, sizeof(port_removable));
 216         for (i = 0; i < ports; i++) {
 217                 portsc = readl(xhci->usb2_ports[i]);
 218                 /* If a device is removable, PORTSC reports a 0, same as in the
 219                  * hub descriptor DeviceRemovable bits.
 220                  */
 221                 if (portsc & PORT_DEV_REMOVE)
 222                         /* This math is hairy because bit 0 of DeviceRemovable
 223                          * is reserved, and bit 1 is for port 1, etc.
 224                          */
 225                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 226         }
 227
 228         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 229          * ports on it.  The USB 2.0 specification says that there are two
 230          * variable length fields at the end of the hub descriptor:
 231          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 232          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 233          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 234          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 235          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 236          * set of ports that actually exist.
 237          */
 238         memset(desc->u.hs.DeviceRemovable, 0xff,
 239                         sizeof(desc->u.hs.DeviceRemovable));
 240         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 241                         sizeof(desc->u.hs.PortPwrCtrlMask));
 242
 243         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 244                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 245                                 sizeof(__u8));
 246 }
 247
 248 /* Fill in the USB 3.0 roothub descriptor */
 249 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 250                 struct usb_hub_descriptor *desc)
 251 {
 252         int ports;
 253         u16 port_removable;
 254         u32 portsc;
 255         unsigned int i;
 256
 257         ports = xhci->num_usb3_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261
 262         /* header decode latency should be zero for roothubs,
 263          * see section 4.23.5.2.
 264          */
 265         desc->u.ss.bHubHdrDecLat = 0;
 266         desc->u.ss.wHubDelay = 0;
 267
 268         port_removable = 0;
 269         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 270         for (i = 0; i < ports; i++) {
 271                 portsc = readl(xhci->usb3_ports[i]);
 272                 if (portsc & PORT_DEV_REMOVE)
 273                         port_removable |= 1 << (i + 1);
 274         }
 275
 276         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 277 }
 278
 279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 280                 struct usb_hub_descriptor *desc)
 281 {
 282
 283         if (hcd->speed >= HCD_USB3)
 284                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 285         else
 286                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 287
 288 }
 289
 290 static unsigned int xhci_port_speed(unsigned int port_status)
 291 {
 292         if (DEV_LOWSPEED(port_status))
 293                 return USB_PORT_STAT_LOW_SPEED;
 294         if (DEV_HIGHSPEED(port_status))
 295                 return USB_PORT_STAT_HIGH_SPEED;
 296         /*
 297          * FIXME: Yes, we should check for full speed, but the core uses that as
 298          * a default in portspeed() in usb/core/hub.c (which is the only place
 299          * USB_PORT_STAT_*_SPEED is used).
 300          */
 301         return 0;
 302 }
 303
 304 /*
 305  * These bits are Read Only (RO) and should be saved and written to the
 306  * registers: 0, 3, 10:13, 30
 307  * connect status, over-current status, port speed, and device removable.
 308  * connect status and port speed are also sticky - meaning they're in
 309  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 310  */
 311 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 312 /*
 313  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 314  * bits 5:8, 9, 14:15, 25:27
 315  * link state, port power, port indicator state, "wake on" enable state
 316  */
 317 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 318 /*
 319  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 320  * bit 4 (port reset)
 321  */
 322 #define XHCI_PORT_RW1S  ((1<<4))
 323 /*
 324  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 325  * bits 1, 17, 18, 19, 20, 21, 22, 23
 326  * port enable/disable, and
 327  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 328  * over-current, reset, link state, and L1 change
 329  */
 330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 331 /*
 332  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 333  * latched in
 334  */
 335 #define XHCI_PORT_RW    ((1<<16))
 336 /*
 337  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 338  * bits 2, 24, 28:31
 339  */
 340 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 341
 342 /*
 343  * Given a port state, this function returns a value that would result in the
 344  * port being in the same state, if the value was written to the port status
 345  * control register.
 346  * Save Read Only (RO) bits and save read/write bits where
 347  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 348  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 349  */
 350 u32 xhci_port_state_to_neutral(u32 state)
 351 {
 352         /* Save read-only status and port state */
 353         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 354 }
 355
 356 /*
 357  * find slot id based on port number.
 358  * @port: The one-based port number from one of the two split roothubs.
 359  */
 360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 361                 u16 port)
 362 {
 363         int slot_id;
 364         int i;
 365         enum usb_device_speed speed;
 366
 367         slot_id = 0;
 368         for (i = 0; i < MAX_HC_SLOTS; i++) {
 369                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 370                         continue;
 371                 speed = xhci->devs[i]->udev->speed;
 372                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 373                                 && xhci->devs[i]->fake_port == port) {
 374                         slot_id = i;
 375                         break;
 376                 }
 377         }
 378
 379         return slot_id;
 380 }
 381
 382 /*
 383  * Stop device
 384  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 385  * to complete.
 386  * suspend will set to 1, if suspend bit need to set in command.
 387  */
 388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 389 {
 390         struct xhci_virt_device *virt_dev;
 391         struct xhci_command *cmd;
 392         unsigned long flags;
 393         int ret;
 394         int i;
 395
 396         ret = 0;
 397         virt_dev = xhci->devs[slot_id];
 398         if (!virt_dev)
 399                 return -ENODEV;
 400
 401         trace_xhci_stop_device(virt_dev);
 402
 403         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 404         if (!cmd)
 405                 return -ENOMEM;
 406
 407         spin_lock_irqsave(&xhci->lock, flags);
 408         for (i = LAST_EP_INDEX; i > 0; i--) {
 409                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 410                         struct xhci_ep_ctx *ep_ctx;
 411                         struct xhci_command *command;
 412
 413                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 414
 415                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 416                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 417                                 continue;
 418
 419                         command = xhci_alloc_command(xhci, false, false,
 420                                                      GFP_NOWAIT);
 421                         if (!command) {
 422                                 spin_unlock_irqrestore(&xhci->lock, flags);
 423                                 ret = -ENOMEM;
 424                                 goto cmd_cleanup;
 425                         }
 426
 427                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 428                                                        i, suspend);
 429                         if (ret) {
 430                                 spin_unlock_irqrestore(&xhci->lock, flags);
 431                                 xhci_free_command(xhci, command);
 432                                 goto cmd_cleanup;
 433                         }
 434                 }
 435         }
 436         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 437         if (ret) {
 438                 spin_unlock_irqrestore(&xhci->lock, flags);
 439                 goto cmd_cleanup;
 440         }
 441
 442         xhci_ring_cmd_db(xhci);
 443         spin_unlock_irqrestore(&xhci->lock, flags);
 444
 445         /* Wait for last stop endpoint command to finish */
 446         wait_for_completion(cmd->completion);
 447
 448         if (cmd->status == COMP_COMMAND_ABORTED ||
 449             cmd->status == COMP_COMMAND_RING_STOPPED) {
 450                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 451                 ret = -ETIME;
 452         }
 453
 454 cmd_cleanup:
 455         xhci_free_command(xhci, cmd);
 456         return ret;
 457 }
 458
 459 /*
 460  * Ring device, it rings the all doorbells unconditionally.
 461  */
 462 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 463 {
 464         int i, s;
 465         struct xhci_virt_ep *ep;
 466
 467         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 468                 ep = &xhci->devs[slot_id]->eps[i];
 469
 470                 if (ep->ep_state & EP_HAS_STREAMS) {
 471                         for (s = 1; s < ep->stream_info->num_streams; s++)
 472                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 473                 } else if (ep->ring && ep->ring->dequeue) {
 474                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 475                 }
 476         }
 477
 478         return;
 479 }
 480
 481 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 482                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 483 {
 484         /* Don't allow the USB core to disable SuperSpeed ports. */
 485         if (hcd->speed >= HCD_USB3) {
 486                 xhci_dbg(xhci, "Ignoring request to disable "
 487                                 "SuperSpeed port.\n");
 488                 return;
 489         }
 490
 491         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 492                 xhci_dbg(xhci,
 493                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 494                 return;
 495         }
 496
 497         /* Write 1 to disable the port */
 498         writel(port_status | PORT_PE, addr);
 499         port_status = readl(addr);
 500         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 501                         wIndex, port_status);
 502 }
 503
 504 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 505                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 506 {
 507         char *port_change_bit;
 508         u32 status;
 509
 510         switch (wValue) {
 511         case USB_PORT_FEAT_C_RESET:
 512                 status = PORT_RC;
 513                 port_change_bit = "reset";
 514                 break;
 515         case USB_PORT_FEAT_C_BH_PORT_RESET:
 516                 status = PORT_WRC;
 517                 port_change_bit = "warm(BH) reset";
 518                 break;
 519         case USB_PORT_FEAT_C_CONNECTION:
 520                 status = PORT_CSC;
 521                 port_change_bit = "connect";
 522                 break;
 523         case USB_PORT_FEAT_C_OVER_CURRENT:
 524                 status = PORT_OCC;
 525                 port_change_bit = "over-current";
 526                 break;
 527         case USB_PORT_FEAT_C_ENABLE:
 528                 status = PORT_PEC;
 529                 port_change_bit = "enable/disable";
 530                 break;
 531         case USB_PORT_FEAT_C_SUSPEND:
 532                 status = PORT_PLC;
 533                 port_change_bit = "suspend/resume";
 534                 break;
 535         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 536                 status = PORT_PLC;
 537                 port_change_bit = "link state";
 538                 break;
 539         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 540                 status = PORT_CEC;
 541                 port_change_bit = "config error";
 542                 break;
 543         default:
 544                 /* Should never happen */
 545                 return;
 546         }
 547         /* Change bits are all write 1 to clear */
 548         writel(port_status | status, addr);
 549         port_status = readl(addr);
 550         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 551                         port_change_bit, wIndex, port_status);
 552 }
 553
 554 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 555 {
 556         int max_ports;
 557         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 558
 559         if (hcd->speed >= HCD_USB3) {
 560                 max_ports = xhci->num_usb3_ports;
 561                 *port_array = xhci->usb3_ports;
 562         } else {
 563                 max_ports = xhci->num_usb2_ports;
 564                 *port_array = xhci->usb2_ports;
 565         }
 566
 567         return max_ports;
 568 }
 569
 570 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
 571 {
 572         __le32 __iomem **port_array;
 573
 574         xhci_get_ports(hcd, &port_array);
 575         return port_array[index];
 576 }
 577
 578 /*
 579  * xhci_set_port_power() must be called with xhci->lock held.
 580  * It will release and re-aquire the lock while calling ACPI
 581  * method.
 582  */
 583 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 584                                 u16 index, bool on, unsigned long *flags)
 585 {
 586         __le32 __iomem *addr;
 587         u32 temp;
 588
 589         addr = xhci_get_port_io_addr(hcd, index);
 590         temp = readl(addr);
 591         temp = xhci_port_state_to_neutral(temp);
 592         if (on) {
 593                 /* Power on */
 594                 writel(temp | PORT_POWER, addr);
 595                 temp = readl(addr);
 596                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 597                                                 index, temp);
 598         } else {
 599                 /* Power off */
 600                 writel(temp & ~PORT_POWER, addr);
 601         }
 602
 603         spin_unlock_irqrestore(&xhci->lock, *flags);
 604         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 605                                         index);
 606         if (temp)
 607                 usb_acpi_set_power_state(hcd->self.root_hub,
 608                         index, on);
 609         spin_lock_irqsave(&xhci->lock, *flags);
 610 }
 611
 612 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 613         u16 test_mode, u16 wIndex)
 614 {
 615         u32 temp;
 616         __le32 __iomem *addr;
 617
 618         /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
 619         addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
 620         temp = readl(addr + PORTPMSC);
 621         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 622         writel(temp, addr + PORTPMSC);
 623         xhci->test_mode = test_mode;
 624         if (test_mode == TEST_FORCE_EN)
 625                 xhci_start(xhci);
 626 }
 627
 628 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 629                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 630 {
 631         int i, retval;
 632
 633         /* Disable all Device Slots */
 634         xhci_dbg(xhci, "Disable all slots\n");
 635         spin_unlock_irqrestore(&xhci->lock, *flags);
 636         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 637                 if (!xhci->devs[i])
 638                         continue;
 639
 640                 retval = xhci_disable_slot(xhci, i);
 641                 if (retval)
 642                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 643                                  i, retval);
 644         }
 645         spin_lock_irqsave(&xhci->lock, *flags);
 646         /* Put all ports to the Disable state by clear PP */
 647         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 648         /* Power off USB3 ports*/
 649         for (i = 0; i < xhci->num_usb3_ports; i++)
 650                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 651         /* Power off USB2 ports*/
 652         for (i = 0; i < xhci->num_usb2_ports; i++)
 653                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 654         /* Stop the controller */
 655         xhci_dbg(xhci, "Stop controller\n");
 656         retval = xhci_halt(xhci);
 657         if (retval)
 658                 return retval;
 659         /* Disable runtime PM for test mode */
 660         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 661         /* Set PORTPMSC.PTC field to enter selected test mode */
 662         /* Port is selected by wIndex. port_id = wIndex + 1 */
 663         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 664                                         test_mode, wIndex + 1);
 665         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 666         return retval;
 667 }
 668
 669 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 670 {
 671         int retval;
 672
 673         if (!xhci->test_mode) {
 674                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 675                 return 0;
 676         }
 677         if (xhci->test_mode == TEST_FORCE_EN &&
 678                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 679                 retval = xhci_halt(xhci);
 680                 if (retval)
 681                         return retval;
 682         }
 683         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 684         xhci->test_mode = 0;
 685         return xhci_reset(xhci);
 686 }
 687
 688 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 689                                 int port_id, u32 link_state)
 690 {
 691         u32 temp;
 692
 693         temp = readl(port_array[port_id]);
 694         temp = xhci_port_state_to_neutral(temp);
 695         temp &= ~PORT_PLS_MASK;
 696         temp |= PORT_LINK_STROBE | link_state;
 697         writel(temp, port_array[port_id]);
 698 }
 699
 700 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 701                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 702 {
 703         u32 temp;
 704
 705         temp = readl(port_array[port_id]);
 706         temp = xhci_port_state_to_neutral(temp);
 707
 708         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 709                 temp |= PORT_WKCONN_E;
 710         else
 711                 temp &= ~PORT_WKCONN_E;
 712
 713         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 714                 temp |= PORT_WKDISC_E;
 715         else
 716                 temp &= ~PORT_WKDISC_E;
 717
 718         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 719                 temp |= PORT_WKOC_E;
 720         else
 721                 temp &= ~PORT_WKOC_E;
 722
 723         writel(temp, port_array[port_id]);
 724 }
 725
 726 /* Test and clear port RWC bit */
 727 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 728                                 int port_id, u32 port_bit)
 729 {
 730         u32 temp;
 731
 732         temp = readl(port_array[port_id]);
 733         if (temp & port_bit) {
 734                 temp = xhci_port_state_to_neutral(temp);
 735                 temp |= port_bit;
 736                 writel(temp, port_array[port_id]);
 737         }
 738 }
 739
 740 /* Updates Link Status for USB 2.1 port */
 741 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 742 {
 743         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 744                 *status |= USB_PORT_STAT_L1;
 745 }
 746
 747 /* Updates Link Status for super Speed port */
 748 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 749                 u32 *status, u32 status_reg)
 750 {
 751         u32 pls = status_reg & PORT_PLS_MASK;
 752
 753         /* When the CAS bit is set then warm reset
 754          * should be performed on port
 755          */
 756         if (status_reg & PORT_CAS) {
 757                 /* The CAS bit can be set while the port is
 758                  * in any link state.
 759                  * Only roothubs have CAS bit, so we
 760                  * pretend to be in compliance mode
 761                  * unless we're already in compliance
 762                  * or the inactive state.
 763                  */
 764                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 765                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 766                         pls = USB_SS_PORT_LS_COMP_MOD;
 767                 }
 768                 /* Return also connection bit -
 769                  * hub state machine resets port
 770                  * when this bit is set.
 771                  */
 772                 pls |= USB_PORT_STAT_CONNECTION;
 773         } else {
 774                 /*
 775                  * Resume state is an xHCI internal state.  Do not report it to
 776                  * usb core, instead, pretend to be U3, thus usb core knows
 777                  * it's not ready for transfer.
 778                  */
 779                 if (pls == XDEV_RESUME) {
 780                         *status |= USB_SS_PORT_LS_U3;
 781                         return;
 782                 }
 783
 784                 /*
 785                  * If CAS bit isn't set but the Port is already at
 786                  * Compliance Mode, fake a connection so the USB core
 787                  * notices the Compliance state and resets the port.
 788                  * This resolves an issue generated by the SN65LVPE502CP
 789                  * in which sometimes the port enters compliance mode
 790                  * caused by a delay on the host-device negotiation.
 791                  */
 792                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 793                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 794                         pls |= USB_PORT_STAT_CONNECTION;
 795         }
 796
 797         /* update status field */
 798         *status |= pls;
 799 }
 800
 801 /*
 802  * Function for Compliance Mode Quirk.
 803  *
 804  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 805  * the compliance mode timer is deleted. A port won't enter
 806  * compliance mode if it has previously entered U0.
 807  */
 808 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 809                                     u16 wIndex)
 810 {
 811         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 812         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 813
 814         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 815                 return;
 816
 817         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 818                 xhci->port_status_u0 |= 1 << wIndex;
 819                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 820                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 821                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 822                                 "All USB3 ports have entered U0 already!");
 823                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 824                                 "Compliance Mode Recovery Timer Deleted.");
 825                 }
 826         }
 827 }
 828
 829 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 830 {
 831         u32 ext_stat = 0;
 832         int speed_id;
 833
 834         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 835         speed_id = DEV_PORT_SPEED(raw_port_status);
 836         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 837         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 838
 839         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 840         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 841
 842         return ext_stat;
 843 }
 844
 845 /*
 846  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 847  * 3.0 hubs use.
 848  *
 849  * Possible side effects:
 850  *  - Mark a port as being done with device resume,
 851  *    and ring the endpoint doorbells.
 852  *  - Stop the Synopsys redriver Compliance Mode polling.
 853  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 854  */
 855 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 856                 struct xhci_bus_state *bus_state,
 857                 __le32 __iomem **port_array,
 858                 u16 wIndex, u32 raw_port_status,
 859                 unsigned long *flags)
 860         __releases(&xhci->lock)
 861         __acquires(&xhci->lock)
 862 {
 863         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 864         u32 status = 0;
 865         int slot_id;
 866
 867         /* wPortChange bits */
 868         if (raw_port_status & PORT_CSC)
 869                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 870         if (raw_port_status & PORT_PEC)
 871                 status |= USB_PORT_STAT_C_ENABLE << 16;
 872         if ((raw_port_status & PORT_OCC))
 873                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 874         if ((raw_port_status & PORT_RC))
 875                 status |= USB_PORT_STAT_C_RESET << 16;
 876         /* USB3.0 only */
 877         if (hcd->speed >= HCD_USB3) {
 878                 /* Port link change with port in resume state should not be
 879                  * reported to usbcore, as this is an internal state to be
 880                  * handled by xhci driver. Reporting PLC to usbcore may
 881                  * cause usbcore clearing PLC first and port change event
 882                  * irq won't be generated.
 883                  */
 884                 if ((raw_port_status & PORT_PLC) &&
 885                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 886                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 887                 if ((raw_port_status & PORT_WRC))
 888                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 889                 if ((raw_port_status & PORT_CEC))
 890                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 891
 892                 /* USB3 remote wake resume signaling completed */
 893                 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
 894                     (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
 895                     (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
 896                         bus_state->port_remote_wakeup &= ~(1 << wIndex);
 897                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 898                 }
 899         }
 900
 901         if (hcd->speed < HCD_USB3) {
 902                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 903                                 && (raw_port_status & PORT_POWER))
 904                         status |= USB_PORT_STAT_SUSPEND;
 905         }
 906         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 907                 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
 908                 if ((raw_port_status & PORT_RESET) ||
 909                                 !(raw_port_status & PORT_PE))
 910                         return 0xffffffff;
 911                 /* did port event handler already start resume timing? */
 912                 if (!bus_state->resume_done[wIndex]) {
 913                         /* If not, maybe we are in a host initated resume? */
 914                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 915                                 /* Host initated resume doesn't time the resume
 916                                  * signalling using resume_done[].
 917                                  * It manually sets RESUME state, sleeps 20ms
 918                                  * and sets U0 state. This should probably be
 919                                  * changed, but not right now.
 920                                  */
 921                         } else {
 922                                 /* port resume was discovered now and here,
 923                                  * start resume timing
 924                                  */
 925                                 unsigned long timeout = jiffies +
 926                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 927
 928                                 set_bit(wIndex, &bus_state->resuming_ports);
 929                                 bus_state->resume_done[wIndex] = timeout;
 930                                 mod_timer(&hcd->rh_timer, timeout);
 931                         }
 932                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 933                 } else if (time_after_eq(jiffies,
 934                                          bus_state->resume_done[wIndex])) {
 935                         int time_left;
 936
 937                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 938                                         wIndex + 1);
 939                         bus_state->resume_done[wIndex] = 0;
 940                         clear_bit(wIndex, &bus_state->resuming_ports);
 941
 942                         set_bit(wIndex, &bus_state->rexit_ports);
 943
 944                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 945                                                 PORT_PLC);
 946                         xhci_set_link_state(xhci, port_array, wIndex,
 947                                         XDEV_U0);
 948
 949                         spin_unlock_irqrestore(&xhci->lock, *flags);
 950                         time_left = wait_for_completion_timeout(
 951                                         &bus_state->rexit_done[wIndex],
 952                                         msecs_to_jiffies(
 953                                                 XHCI_MAX_REXIT_TIMEOUT_MS));
 954                         spin_lock_irqsave(&xhci->lock, *flags);
 955
 956                         if (time_left) {
 957                                 slot_id = xhci_find_slot_id_by_port(hcd,
 958                                                 xhci, wIndex + 1);
 959                                 if (!slot_id) {
 960                                         xhci_dbg(xhci, "slot_id is zero\n");
 961                                         return 0xffffffff;
 962                                 }
 963                                 xhci_ring_device(xhci, slot_id);
 964                         } else {
 965                                 int port_status = readl(port_array[wIndex]);
 966                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 967                                                 XHCI_MAX_REXIT_TIMEOUT_MS,
 968                                                 port_status);
 969                                 status |= USB_PORT_STAT_SUSPEND;
 970                                 clear_bit(wIndex, &bus_state->rexit_ports);
 971                         }
 972
 973                         bus_state->port_c_suspend |= 1 << wIndex;
 974                         bus_state->suspended_ports &= ~(1 << wIndex);
 975                 } else {
 976                         /*
 977                          * The resume has been signaling for less than
 978                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 979                          * let the usbcore check port status again and clear
 980                          * resume signaling later.
 981                          */
 982                         status |= USB_PORT_STAT_SUSPEND;
 983                 }
 984         }
 985         /*
 986          * Clear stale usb2 resume signalling variables in case port changed
 987          * state during resume signalling. For example on error
 988          */
 989         if ((bus_state->resume_done[wIndex] ||
 990              test_bit(wIndex, &bus_state->resuming_ports)) &&
 991             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 992             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 993                 bus_state->resume_done[wIndex] = 0;
 994                 clear_bit(wIndex, &bus_state->resuming_ports);
 995         }
 996
 997
 998         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 999             (raw_port_status & PORT_POWER)) {
1000                 if (bus_state->suspended_ports & (1 << wIndex)) {
1001                         bus_state->suspended_ports &= ~(1 << wIndex);
1002                         if (hcd->speed < HCD_USB3)
1003                                 bus_state->port_c_suspend |= 1 << wIndex;
1004                 }
1005                 bus_state->resume_done[wIndex] = 0;
1006                 clear_bit(wIndex, &bus_state->resuming_ports);
1007         }
1008         if (raw_port_status & PORT_CONNECT) {
1009                 status |= USB_PORT_STAT_CONNECTION;
1010                 status |= xhci_port_speed(raw_port_status);
1011         }
1012         if (raw_port_status & PORT_PE)
1013                 status |= USB_PORT_STAT_ENABLE;
1014         if (raw_port_status & PORT_OC)
1015                 status |= USB_PORT_STAT_OVERCURRENT;
1016         if (raw_port_status & PORT_RESET)
1017                 status |= USB_PORT_STAT_RESET;
1018         if (raw_port_status & PORT_POWER) {
1019                 if (hcd->speed >= HCD_USB3)
1020                         status |= USB_SS_PORT_STAT_POWER;
1021                 else
1022                         status |= USB_PORT_STAT_POWER;
1023         }
1024         /* Update Port Link State */
1025         if (hcd->speed >= HCD_USB3) {
1026                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1027                 /*
1028                  * Verify if all USB3 Ports Have entered U0 already.
1029                  * Delete Compliance Mode Timer if so.
1030                  */
1031                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1032         } else {
1033                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1034         }
1035         if (bus_state->port_c_suspend & (1 << wIndex))
1036                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1037
1038         return status;
1039 }
1040
1041 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1042                 u16 wIndex, char *buf, u16 wLength)
1043 {
1044         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1045         int max_ports;
1046         unsigned long flags;
1047         u32 temp, status;
1048         int retval = 0;
1049         __le32 __iomem **port_array;
1050         int slot_id;
1051         struct xhci_bus_state *bus_state;
1052         u16 link_state = 0;
1053         u16 wake_mask = 0;
1054         u16 timeout = 0;
1055         u16 test_mode = 0;
1056
1057         max_ports = xhci_get_ports(hcd, &port_array);
1058         bus_state = &xhci->bus_state[hcd_index(hcd)];
1059
1060         spin_lock_irqsave(&xhci->lock, flags);
1061         switch (typeReq) {
1062         case GetHubStatus:
1063                 /* No power source, over-current reported per port */
1064                 memset(buf, 0, 4);
1065                 break;
1066         case GetHubDescriptor:
1067                 /* Check to make sure userspace is asking for the USB 3.0 hub
1068                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1069                  * endpoint, like external hubs do.
1070                  */
1071                 if (hcd->speed >= HCD_USB3 &&
1072                                 (wLength < USB_DT_SS_HUB_SIZE ||
1073                                  wValue != (USB_DT_SS_HUB << 8))) {
1074                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1075                                         "USB 3.0 roothub.\n");
1076                         goto error;
1077                 }
1078                 xhci_hub_descriptor(hcd, xhci,
1079                                 (struct usb_hub_descriptor *) buf);
1080                 break;
1081         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1082                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1083                         goto error;
1084
1085                 if (hcd->speed < HCD_USB3)
1086                         goto error;
1087
1088                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1089                 spin_unlock_irqrestore(&xhci->lock, flags);
1090                 return retval;
1091         case GetPortStatus:
1092                 if (!wIndex || wIndex > max_ports)
1093                         goto error;
1094                 wIndex--;
1095                 temp = readl(port_array[wIndex]);
1096                 if (temp == ~(u32)0) {
1097                         xhci_hc_died(xhci);
1098                         retval = -ENODEV;
1099                         break;
1100                 }
1101                 status = xhci_get_port_status(hcd, bus_state, port_array,
1102                                 wIndex, temp, &flags);
1103                 if (status == 0xffffffff)
1104                         goto error;
1105
1106                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1107                                 wIndex, temp);
1108                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1109
1110                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1111                 /* if USB 3.1 extended port status return additional 4 bytes */
1112                 if (wValue == 0x02) {
1113                         u32 port_li;
1114
1115                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1116                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1117                                 retval = -EINVAL;
1118                                 break;
1119                         }
1120                         port_li = readl(port_array[wIndex] + PORTLI);
1121                         status = xhci_get_ext_port_status(temp, port_li);
1122                         put_unaligned_le32(status, &buf[4]);
1123                 }
1124                 break;
1125         case SetPortFeature:
1126                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1127                         link_state = (wIndex & 0xff00) >> 3;
1128                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1129                         wake_mask = wIndex & 0xff00;
1130                 if (wValue == USB_PORT_FEAT_TEST)
1131                         test_mode = (wIndex & 0xff00) >> 8;
1132                 /* The MSB of wIndex is the U1/U2 timeout */
1133                 timeout = (wIndex & 0xff00) >> 8;
1134                 wIndex &= 0xff;
1135                 if (!wIndex || wIndex > max_ports)
1136                         goto error;
1137                 wIndex--;
1138                 temp = readl(port_array[wIndex]);
1139                 if (temp == ~(u32)0) {
1140                         xhci_hc_died(xhci);
1141                         retval = -ENODEV;
1142                         break;
1143                 }
1144                 temp = xhci_port_state_to_neutral(temp);
1145                 /* FIXME: What new port features do we need to support? */
1146                 switch (wValue) {
1147                 case USB_PORT_FEAT_SUSPEND:
1148                         temp = readl(port_array[wIndex]);
1149                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1150                                 /* Resume the port to U0 first */
1151                                 xhci_set_link_state(xhci, port_array, wIndex,
1152                                                         XDEV_U0);
1153                                 spin_unlock_irqrestore(&xhci->lock, flags);
1154                                 msleep(10);
1155                                 spin_lock_irqsave(&xhci->lock, flags);
1156                         }
1157                         /* In spec software should not attempt to suspend
1158                          * a port unless the port reports that it is in the
1159                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1160                          */
1161                         temp = readl(port_array[wIndex]);
1162                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1163                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1164                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1165                                 goto error;
1166                         }
1167
1168                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1169                                         wIndex + 1);
1170                         if (!slot_id) {
1171                                 xhci_warn(xhci, "slot_id is zero\n");
1172                                 goto error;
1173                         }
1174                         /* unlock to execute stop endpoint commands */
1175                         spin_unlock_irqrestore(&xhci->lock, flags);
1176                         xhci_stop_device(xhci, slot_id, 1);
1177                         spin_lock_irqsave(&xhci->lock, flags);
1178
1179                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1180
1181                         spin_unlock_irqrestore(&xhci->lock, flags);
1182                         msleep(10); /* wait device to enter */
1183                         spin_lock_irqsave(&xhci->lock, flags);
1184
1185                         temp = readl(port_array[wIndex]);
1186                         bus_state->suspended_ports |= 1 << wIndex;
1187                         break;
1188                 case USB_PORT_FEAT_LINK_STATE:
1189                         temp = readl(port_array[wIndex]);
1190
1191                         /* Disable port */
1192                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1193                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1194                                 temp = xhci_port_state_to_neutral(temp);
1195                                 /*
1196                                  * Clear all change bits, so that we get a new
1197                                  * connection event.
1198                                  */
1199                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1200                                         PORT_OCC | PORT_RC | PORT_PLC |
1201                                         PORT_CEC;
1202                                 writel(temp | PORT_PE, port_array[wIndex]);
1203                                 temp = readl(port_array[wIndex]);
1204                                 break;
1205                         }
1206
1207                         /* Put link in RxDetect (enable port) */
1208                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1209                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1210                                 xhci_set_link_state(xhci, port_array, wIndex,
1211                                                 link_state);
1212                                 temp = readl(port_array[wIndex]);
1213                                 break;
1214                         }
1215
1216                         /*
1217                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1218                          * root hub port's transition to compliance mode upon
1219                          * detecting LFPS timeout may be controlled by an
1220                          * Compliance Transition Enabled (CTE) flag (not
1221                          * software visible). This flag is set by writing 0xA
1222                          * to PORTSC PLS field which will allow transition to
1223                          * compliance mode the next time LFPS timeout is
1224                          * encountered. A warm reset will clear it.
1225                          *
1226                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1227                          * flag is set, otherwise, the compliance substate is
1228                          * automatically entered as on 1.0 and prior.
1229                          */
1230                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1231                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1232                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1233                                         break;
1234                                 }
1235
1236                                 if ((temp & PORT_CONNECT)) {
1237                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1238                                         goto error;
1239                                 }
1240
1241                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1242                                                 wIndex);
1243                                 xhci_set_link_state(xhci, port_array, wIndex,
1244                                                 link_state);
1245                                 temp = readl(port_array[wIndex]);
1246                                 break;
1247                         }
1248                         /* Port must be enabled */
1249                         if (!(temp & PORT_PE)) {
1250                                 retval = -ENODEV;
1251                                 break;
1252                         }
1253                         /* Can't set port link state above '3' (U3) */
1254                         if (link_state > USB_SS_PORT_LS_U3) {
1255                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1256                                          wIndex, link_state);
1257                                 goto error;
1258                         }
1259                         if (link_state == USB_SS_PORT_LS_U3) {
1260                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1261                                                 wIndex + 1);
1262                                 if (slot_id) {
1263                                         /* unlock to execute stop endpoint
1264                                          * commands */
1265                                         spin_unlock_irqrestore(&xhci->lock,
1266                                                                 flags);
1267                                         xhci_stop_device(xhci, slot_id, 1);
1268                                         spin_lock_irqsave(&xhci->lock, flags);
1269                                 }
1270                         }
1271
1272                         xhci_set_link_state(xhci, port_array, wIndex,
1273                                                 link_state);
1274
1275                         spin_unlock_irqrestore(&xhci->lock, flags);
1276                         msleep(20); /* wait device to enter */
1277                         spin_lock_irqsave(&xhci->lock, flags);
1278
1279                         temp = readl(port_array[wIndex]);
1280                         if (link_state == USB_SS_PORT_LS_U3)
1281                                 bus_state->suspended_ports |= 1 << wIndex;
1282                         break;
1283                 case USB_PORT_FEAT_POWER:
1284                         /*
1285                          * Turn on ports, even if there isn't per-port switching.
1286                          * HC will report connect events even before this is set.
1287                          * However, hub_wq will ignore the roothub events until
1288                          * the roothub is registered.
1289                          */
1290                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1291                         break;
1292                 case USB_PORT_FEAT_RESET:
1293                         temp = (temp | PORT_RESET);
1294                         writel(temp, port_array[wIndex]);
1295
1296                         temp = readl(port_array[wIndex]);
1297                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1298                         break;
1299                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1300                         xhci_set_remote_wake_mask(xhci, port_array,
1301                                         wIndex, wake_mask);
1302                         temp = readl(port_array[wIndex]);
1303                         xhci_dbg(xhci, "set port remote wake mask, "
1304                                         "actual port %d status  = 0x%x\n",
1305                                         wIndex, temp);
1306                         break;
1307                 case USB_PORT_FEAT_BH_PORT_RESET:
1308                         temp |= PORT_WR;
1309                         writel(temp, port_array[wIndex]);
1310
1311                         temp = readl(port_array[wIndex]);
1312                         break;
1313                 case USB_PORT_FEAT_U1_TIMEOUT:
1314                         if (hcd->speed < HCD_USB3)
1315                                 goto error;
1316                         temp = readl(port_array[wIndex] + PORTPMSC);
1317                         temp &= ~PORT_U1_TIMEOUT_MASK;
1318                         temp |= PORT_U1_TIMEOUT(timeout);
1319                         writel(temp, port_array[wIndex] + PORTPMSC);
1320                         break;
1321                 case USB_PORT_FEAT_U2_TIMEOUT:
1322                         if (hcd->speed < HCD_USB3)
1323                                 goto error;
1324                         temp = readl(port_array[wIndex] + PORTPMSC);
1325                         temp &= ~PORT_U2_TIMEOUT_MASK;
1326                         temp |= PORT_U2_TIMEOUT(timeout);
1327                         writel(temp, port_array[wIndex] + PORTPMSC);
1328                         break;
1329                 case USB_PORT_FEAT_TEST:
1330                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1331                         if (hcd->speed != HCD_USB2)
1332                                 goto error;
1333                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1334                                 goto error;
1335                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1336                                                       &flags);
1337                         break;
1338                 default:
1339                         goto error;
1340                 }
1341                 /* unblock any posted writes */
1342                 temp = readl(port_array[wIndex]);
1343                 break;
1344         case ClearPortFeature:
1345                 if (!wIndex || wIndex > max_ports)
1346                         goto error;
1347                 wIndex--;
1348                 temp = readl(port_array[wIndex]);
1349                 if (temp == ~(u32)0) {
1350                         xhci_hc_died(xhci);
1351                         retval = -ENODEV;
1352                         break;
1353                 }
1354                 /* FIXME: What new port features do we need to support? */
1355                 temp = xhci_port_state_to_neutral(temp);
1356                 switch (wValue) {
1357                 case USB_PORT_FEAT_SUSPEND:
1358                         temp = readl(port_array[wIndex]);
1359                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1360                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1361                         if (temp & PORT_RESET)
1362                                 goto error;
1363                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1364                                 if ((temp & PORT_PE) == 0)
1365                                         goto error;
1366
1367                                 set_bit(wIndex, &bus_state->resuming_ports);
1368                                 xhci_set_link_state(xhci, port_array, wIndex,
1369                                                         XDEV_RESUME);
1370                                 spin_unlock_irqrestore(&xhci->lock, flags);
1371                                 msleep(USB_RESUME_TIMEOUT);
1372                                 spin_lock_irqsave(&xhci->lock, flags);
1373                                 xhci_set_link_state(xhci, port_array, wIndex,
1374                                                         XDEV_U0);
1375                                 clear_bit(wIndex, &bus_state->resuming_ports);
1376                         }
1377                         bus_state->port_c_suspend |= 1 << wIndex;
1378
1379                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1380                                         wIndex + 1);
1381                         if (!slot_id) {
1382                                 xhci_dbg(xhci, "slot_id is zero\n");
1383                                 goto error;
1384                         }
1385                         xhci_ring_device(xhci, slot_id);
1386                         break;
1387                 case USB_PORT_FEAT_C_SUSPEND:
1388                         bus_state->port_c_suspend &= ~(1 << wIndex);
1389                 case USB_PORT_FEAT_C_RESET:
1390                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1391                 case USB_PORT_FEAT_C_CONNECTION:
1392                 case USB_PORT_FEAT_C_OVER_CURRENT:
1393                 case USB_PORT_FEAT_C_ENABLE:
1394                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1395                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1396                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1397                                         port_array[wIndex], temp);
1398                         break;
1399                 case USB_PORT_FEAT_ENABLE:
1400                         xhci_disable_port(hcd, xhci, wIndex,
1401                                         port_array[wIndex], temp);
1402                         break;
1403                 case USB_PORT_FEAT_POWER:
1404                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1405                         break;
1406                 case USB_PORT_FEAT_TEST:
1407                         retval = xhci_exit_test_mode(xhci);
1408                         break;
1409                 default:
1410                         goto error;
1411                 }
1412                 break;
1413         default:
1414 error:
1415                 /* "stall" on error */
1416                 retval = -EPIPE;
1417         }
1418         spin_unlock_irqrestore(&xhci->lock, flags);
1419         return retval;
1420 }
1421
1422 /*
1423  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1424  * Ports are 0-indexed from the HCD point of view,
1425  * and 1-indexed from the USB core pointer of view.
1426  *
1427  * Note that the status change bits will be cleared as soon as a port status
1428  * change event is generated, so we use the saved status from that event.
1429  */
1430 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1431 {
1432         unsigned long flags;
1433         u32 temp, status;
1434         u32 mask;
1435         int i, retval;
1436         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1437         int max_ports;
1438         __le32 __iomem **port_array;
1439         struct xhci_bus_state *bus_state;
1440         bool reset_change = false;
1441
1442         max_ports = xhci_get_ports(hcd, &port_array);
1443         bus_state = &xhci->bus_state[hcd_index(hcd)];
1444
1445         /* Initial status is no changes */
1446         retval = (max_ports + 8) / 8;
1447         memset(buf, 0, retval);
1448
1449         /*
1450          * Inform the usbcore about resume-in-progress by returning
1451          * a non-zero value even if there are no status changes.
1452          */
1453         spin_lock_irqsave(&xhci->lock, flags);
1454
1455         status = bus_state->resuming_ports;
1456
1457         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1458
1459         /* For each port, did anything change?  If so, set that bit in buf. */
1460         for (i = 0; i < max_ports; i++) {
1461                 temp = readl(port_array[i]);
1462                 if (temp == ~(u32)0) {
1463                         xhci_hc_died(xhci);
1464                         retval = -ENODEV;
1465                         break;
1466                 }
1467                 if ((temp & mask) != 0 ||
1468                         (bus_state->port_c_suspend & 1 << i) ||
1469                         (bus_state->resume_done[i] && time_after_eq(
1470                             jiffies, bus_state->resume_done[i]))) {
1471                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1472                         status = 1;
1473                 }
1474                 if ((temp & PORT_RC))
1475                         reset_change = true;
1476         }
1477         if (!status && !reset_change) {
1478                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1479                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1480         }
1481         spin_unlock_irqrestore(&xhci->lock, flags);
1482         return status ? retval : 0;
1483 }
1484
1485 #ifdef CONFIG_PM
1486
1487 int xhci_bus_suspend(struct usb_hcd *hcd)
1488 {
1489         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1490         int max_ports, port_index;
1491         __le32 __iomem **port_array;
1492         struct xhci_bus_state *bus_state;
1493         unsigned long flags;
1494         u32 portsc_buf[USB_MAXCHILDREN];
1495         bool wake_enabled;
1496
1497         max_ports = xhci_get_ports(hcd, &port_array);
1498         bus_state = &xhci->bus_state[hcd_index(hcd)];
1499         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1500
1501         spin_lock_irqsave(&xhci->lock, flags);
1502
1503         if (wake_enabled) {
1504                 if (bus_state->resuming_ports ||        /* USB2 */
1505                     bus_state->port_remote_wakeup) {    /* USB3 */
1506                         spin_unlock_irqrestore(&xhci->lock, flags);
1507                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1508                         return -EBUSY;
1509                 }
1510         }
1511         /*
1512          * Prepare ports for suspend, but don't write anything before all ports
1513          * are checked and we know bus suspend can proceed
1514          */
1515         bus_state->bus_suspended = 0;
1516         port_index = max_ports;
1517         while (port_index--) {
1518                 u32 t1, t2;
1519
1520                 t1 = readl(port_array[port_index]);
1521                 t2 = xhci_port_state_to_neutral(t1);
1522                 portsc_buf[port_index] = 0;
1523
1524                 /* Bail out if a USB3 port has a new device in link training */
1525                 if ((hcd->speed >= HCD_USB3) &&
1526                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1527                         bus_state->bus_suspended = 0;
1528                         spin_unlock_irqrestore(&xhci->lock, flags);
1529                         xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1530                         return -EBUSY;
1531                 }
1532
1533                 /* suspend ports in U0, or bail out for new connect changes */
1534                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1535                         if ((t1 & PORT_CSC) && wake_enabled) {
1536                                 bus_state->bus_suspended = 0;
1537                                 spin_unlock_irqrestore(&xhci->lock, flags);
1538                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1539                                 return -EBUSY;
1540                         }
1541                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1542                         t2 &= ~PORT_PLS_MASK;
1543                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1544                         set_bit(port_index, &bus_state->bus_suspended);
1545                 }
1546                 /* USB core sets remote wake mask for USB 3.0 hubs,
1547                  * including the USB 3.0 roothub, but only if CONFIG_PM
1548                  * is enabled, so also enable remote wake here.
1549                  */
1550                 if (wake_enabled) {
1551                         if (t1 & PORT_CONNECT) {
1552                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1553                                 t2 &= ~PORT_WKCONN_E;
1554                         } else {
1555                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1556                                 t2 &= ~PORT_WKDISC_E;
1557                         }
1558
1559                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1560                             (hcd->speed < HCD_USB3)) {
1561                                 if (usb_amd_pt_check_port(hcd->self.controller,
1562                                                           port_index))
1563                                         t2 &= ~PORT_WAKE_BITS;
1564                         }
1565                 } else
1566                         t2 &= ~PORT_WAKE_BITS;
1567
1568                 t1 = xhci_port_state_to_neutral(t1);
1569                 if (t1 != t2)
1570                         portsc_buf[port_index] = t2;
1571         }
1572
1573         /* write port settings, stopping and suspending ports if needed */
1574         port_index = max_ports;
1575         while (port_index--) {
1576                 if (!portsc_buf[port_index])
1577                         continue;
1578                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1579                         int slot_id;
1580
1581                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1582                                                             port_index + 1);
1583                         if (slot_id) {
1584                                 spin_unlock_irqrestore(&xhci->lock, flags);
1585                                 xhci_stop_device(xhci, slot_id, 1);
1586                                 spin_lock_irqsave(&xhci->lock, flags);
1587                         }
1588                 }
1589                 writel(portsc_buf[port_index], port_array[port_index]);
1590         }
1591         hcd->state = HC_STATE_SUSPENDED;
1592         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1593         spin_unlock_irqrestore(&xhci->lock, flags);
1594
1595         if (bus_state->bus_suspended)
1596                 usleep_range(5000, 10000);
1597
1598         return 0;
1599 }
1600
1601 /*
1602  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1603  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1604  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1605  */
1606 static bool xhci_port_missing_cas_quirk(int port_index,
1607                                              __le32 __iomem **port_array)
1608 {
1609         u32 portsc;
1610
1611         portsc = readl(port_array[port_index]);
1612
1613         /* if any of these are set we are not stuck */
1614         if (portsc & (PORT_CONNECT | PORT_CAS))
1615                 return false;
1616
1617         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1618             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1619                 return false;
1620
1621         /* clear wakeup/change bits, and do a warm port reset */
1622         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1623         portsc |= PORT_WR;
1624         writel(portsc, port_array[port_index]);
1625         /* flush write */
1626         readl(port_array[port_index]);
1627         return true;
1628 }
1629
1630 int xhci_bus_resume(struct usb_hcd *hcd)
1631 {
1632         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1633         struct xhci_bus_state *bus_state;
1634         __le32 __iomem **port_array;
1635         unsigned long flags;
1636         int max_ports, port_index;
1637         int slot_id;
1638         int sret;
1639         u32 next_state;
1640         u32 temp, portsc;
1641
1642         max_ports = xhci_get_ports(hcd, &port_array);
1643         bus_state = &xhci->bus_state[hcd_index(hcd)];
1644
1645         if (time_before(jiffies, bus_state->next_statechange))
1646                 msleep(5);
1647
1648         spin_lock_irqsave(&xhci->lock, flags);
1649         if (!HCD_HW_ACCESSIBLE(hcd)) {
1650                 spin_unlock_irqrestore(&xhci->lock, flags);
1651                 return -ESHUTDOWN;
1652         }
1653
1654         /* delay the irqs */
1655         temp = readl(&xhci->op_regs->command);
1656         temp &= ~CMD_EIE;
1657         writel(temp, &xhci->op_regs->command);
1658
1659         /* bus specific resume for ports we suspended at bus_suspend */
1660         if (hcd->speed >= HCD_USB3)
1661                 next_state = XDEV_U0;
1662         else
1663                 next_state = XDEV_RESUME;
1664
1665         port_index = max_ports;
1666         while (port_index--) {
1667                 portsc = readl(port_array[port_index]);
1668
1669                 /* warm reset CAS limited ports stuck in polling/compliance */
1670                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1671                     (hcd->speed >= HCD_USB3) &&
1672                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1673                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1674                         clear_bit(port_index, &bus_state->bus_suspended);
1675                         continue;
1676                 }
1677                 /* resume if we suspended the link, and it is still suspended */
1678                 if (test_bit(port_index, &bus_state->bus_suspended))
1679                         switch (portsc & PORT_PLS_MASK) {
1680                         case XDEV_U3:
1681                                 portsc = xhci_port_state_to_neutral(portsc);
1682                                 portsc &= ~PORT_PLS_MASK;
1683                                 portsc |= PORT_LINK_STROBE | next_state;
1684                                 break;
1685                         case XDEV_RESUME:
1686                                 /* resume already initiated */
1687                                 break;
1688                         default:
1689                                 /* not in a resumeable state, ignore it */
1690                                 clear_bit(port_index,
1691                                           &bus_state->bus_suspended);
1692                                 break;
1693                         }
1694                 /* disable wake for all ports, write new link state if needed */
1695                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1696                 writel(portsc, port_array[port_index]);
1697         }
1698
1699         /* USB2 specific resume signaling delay and U0 link state transition */
1700         if (hcd->speed < HCD_USB3) {
1701                 if (bus_state->bus_suspended) {
1702                         spin_unlock_irqrestore(&xhci->lock, flags);
1703                         msleep(USB_RESUME_TIMEOUT);
1704                         spin_lock_irqsave(&xhci->lock, flags);
1705                 }
1706                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1707                                  BITS_PER_LONG) {
1708                         /* Clear PLC to poll it later for U0 transition */
1709                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1710                                                 PORT_PLC);
1711                         xhci_set_link_state(xhci, port_array, port_index,
1712                                             XDEV_U0);
1713                 }
1714         }
1715
1716         /* poll for U0 link state complete, both USB2 and USB3 */
1717         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1718                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1719                                       PORT_PLC, 10 * 1000);
1720                 if (sret) {
1721                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1722                                   port_index);
1723                         continue;
1724                 }
1725                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1726                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1727                 if (slot_id)
1728                         xhci_ring_device(xhci, slot_id);
1729         }
1730         (void) readl(&xhci->op_regs->command);
1731
1732         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1733         /* re-enable irqs */
1734         temp = readl(&xhci->op_regs->command);
1735         temp |= CMD_EIE;
1736         writel(temp, &xhci->op_regs->command);
1737         temp = readl(&xhci->op_regs->command);
1738
1739         spin_unlock_irqrestore(&xhci->lock, flags);
1740         return 0;
1741 }
1742
1743 #endif  /* CONFIG_PM */