drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x0c,                           /* bLength 12, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x00, 0x00, 0x00, 0x00,         /* bmAttributes, get from xhci psic */
  58         0x00, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Sublink Speed Attributes are added in xhci_create_usb3_bos_desc() */
  61 };
  62
  63 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  64                                      u16 wLength)
  65 {
  66         int i, ssa_count;
  67         u32 temp;
  68         u16 desc_size, ssp_cap_size, ssa_size = 0;
  69         bool usb3_1 = false;
  70
  71         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  72         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  73
  74         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  75         if (xhci->usb3_rhub.min_rev >= 0x01 && xhci->usb3_rhub.psi_uid_count) {
  76                 /* two SSA entries for each unique PSI ID, one RX and one TX */
  77                 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  78                 ssa_size = ssa_count * sizeof(u32);
  79                 desc_size += ssp_cap_size;
  80                 usb3_1 = true;
  81         }
  82         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  83
  84         if (usb3_1) {
  85                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  86                 buf[4] += 1;
  87                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  88         }
  89
  90         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  91                 return wLength;
  92
  93         /* Indicate whether the host has LTM support. */
  94         temp = readl(&xhci->cap_regs->hcc_params);
  95         if (HCC_LTC(temp))
  96                 buf[8] |= USB_LTM_SUPPORT;
  97
  98         /* Set the U1 and U2 exit latencies. */
  99         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 100                 temp = readl(&xhci->cap_regs->hcs_params3);
 101                 buf[12] = HCS_U1_LATENCY(temp);
 102                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 103         }
 104
 105         if (usb3_1) {
 106                 u32 ssp_cap_base, bm_attrib, psi;
 107                 int offset;
 108
 109                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 110
 111                 if (wLength < desc_size)
 112                         return wLength;
 113                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 114
 115                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 116                 bm_attrib = (ssa_count - 1) & 0x1f;
 117                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 118                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 119
 120                 if (wLength < desc_size + ssa_size)
 121                         return wLength;
 122                 /*
 123                  * Create the Sublink Speed Attributes (SSA) array.
 124                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 125                  * but link type bits 7:6 differ for values 01b and 10b.
 126                  * xhci has also only one PSI entry for a symmetric link when
 127                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 128                  */
 129                 offset = desc_size;
 130                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 131                         psi = xhci->usb3_rhub.psi[i];
 132                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 133                         if ((psi & PLT_MASK) == PLT_SYM) {
 134                         /* Symmetric, create SSA RX and TX from one PSI entry */
 135                                 put_unaligned_le32(psi, &buf[offset]);
 136                                 psi |= 1 << 7;  /* turn entry to TX */
 137                                 offset += 4;
 138                                 if (offset >= desc_size + ssa_size)
 139                                         return desc_size + ssa_size;
 140                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 141                                 /* Asymetric RX, flip bits 7:6 for SSA */
 142                                 psi ^= PLT_MASK;
 143                         }
 144                         put_unaligned_le32(psi, &buf[offset]);
 145                         offset += 4;
 146                         if (offset >= desc_size + ssa_size)
 147                                 return desc_size + ssa_size;
 148                 }
 149         }
 150         /* ssa_size is 0 for other than usb 3.1 hosts */
 151         return desc_size + ssa_size;
 152 }
 153
 154 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 155                 struct usb_hub_descriptor *desc, int ports)
 156 {
 157         u16 temp;
 158
 159         desc->bHubContrCurrent = 0;
 160
 161         desc->bNbrPorts = ports;
 162         temp = 0;
 163         /* Bits 1:0 - support per-port power switching, or power always on */
 164         if (HCC_PPC(xhci->hcc_params))
 165                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 166         else
 167                 temp |= HUB_CHAR_NO_LPSM;
 168         /* Bit  2 - root hubs are not part of a compound device */
 169         /* Bits 4:3 - individual port over current protection */
 170         temp |= HUB_CHAR_INDV_PORT_OCPM;
 171         /* Bits 6:5 - no TTs in root ports */
 172         /* Bit  7 - no port indicators */
 173         desc->wHubCharacteristics = cpu_to_le16(temp);
 174 }
 175
 176 /* Fill in the USB 2.0 roothub descriptor */
 177 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 178                 struct usb_hub_descriptor *desc)
 179 {
 180         int ports;
 181         u16 temp;
 182         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 183         u32 portsc;
 184         unsigned int i;
 185
 186         ports = xhci->num_usb2_ports;
 187
 188         xhci_common_hub_descriptor(xhci, desc, ports);
 189         desc->bDescriptorType = USB_DT_HUB;
 190         temp = 1 + (ports / 8);
 191         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 192         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.8 says 20ms */
 193
 194         /* The Device Removable bits are reported on a byte granularity.
 195          * If the port doesn't exist within that byte, the bit is set to 0.
 196          */
 197         memset(port_removable, 0, sizeof(port_removable));
 198         for (i = 0; i < ports; i++) {
 199                 portsc = readl(xhci->usb2_ports[i]);
 200                 /* If a device is removable, PORTSC reports a 0, same as in the
 201                  * hub descriptor DeviceRemovable bits.
 202                  */
 203                 if (portsc & PORT_DEV_REMOVE)
 204                         /* This math is hairy because bit 0 of DeviceRemovable
 205                          * is reserved, and bit 1 is for port 1, etc.
 206                          */
 207                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 208         }
 209
 210         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 211          * ports on it.  The USB 2.0 specification says that there are two
 212          * variable length fields at the end of the hub descriptor:
 213          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 214          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 215          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 216          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 217          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 218          * set of ports that actually exist.
 219          */
 220         memset(desc->u.hs.DeviceRemovable, 0xff,
 221                         sizeof(desc->u.hs.DeviceRemovable));
 222         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 223                         sizeof(desc->u.hs.PortPwrCtrlMask));
 224
 225         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 226                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 227                                 sizeof(__u8));
 228 }
 229
 230 /* Fill in the USB 3.0 roothub descriptor */
 231 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 232                 struct usb_hub_descriptor *desc)
 233 {
 234         int ports;
 235         u16 port_removable;
 236         u32 portsc;
 237         unsigned int i;
 238
 239         ports = xhci->num_usb3_ports;
 240         xhci_common_hub_descriptor(xhci, desc, ports);
 241         desc->bDescriptorType = USB_DT_SS_HUB;
 242         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 243         desc->bPwrOn2PwrGood = 50;      /* usb 3.1 may fail if less than 100ms */
 244
 245         /* header decode latency should be zero for roothubs,
 246          * see section 4.23.5.2.
 247          */
 248         desc->u.ss.bHubHdrDecLat = 0;
 249         desc->u.ss.wHubDelay = 0;
 250
 251         port_removable = 0;
 252         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 253         for (i = 0; i < ports; i++) {
 254                 portsc = readl(xhci->usb3_ports[i]);
 255                 if (portsc & PORT_DEV_REMOVE)
 256                         port_removable |= 1 << (i + 1);
 257         }
 258
 259         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 260 }
 261
 262 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 263                 struct usb_hub_descriptor *desc)
 264 {
 265
 266         if (hcd->speed >= HCD_USB3)
 267                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 268         else
 269                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 270
 271 }
 272
 273 static unsigned int xhci_port_speed(unsigned int port_status)
 274 {
 275         if (DEV_LOWSPEED(port_status))
 276                 return USB_PORT_STAT_LOW_SPEED;
 277         if (DEV_HIGHSPEED(port_status))
 278                 return USB_PORT_STAT_HIGH_SPEED;
 279         /*
 280          * FIXME: Yes, we should check for full speed, but the core uses that as
 281          * a default in portspeed() in usb/core/hub.c (which is the only place
 282          * USB_PORT_STAT_*_SPEED is used).
 283          */
 284         return 0;
 285 }
 286
 287 /*
 288  * These bits are Read Only (RO) and should be saved and written to the
 289  * registers: 0, 3, 10:13, 30
 290  * connect status, over-current status, port speed, and device removable.
 291  * connect status and port speed are also sticky - meaning they're in
 292  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 293  */
 294 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 295 /*
 296  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 297  * bits 5:8, 9, 14:15, 25:27
 298  * link state, port power, port indicator state, "wake on" enable state
 299  */
 300 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 301 /*
 302  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 303  * bit 4 (port reset)
 304  */
 305 #define XHCI_PORT_RW1S  ((1<<4))
 306 /*
 307  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 308  * bits 1, 17, 18, 19, 20, 21, 22, 23
 309  * port enable/disable, and
 310  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 311  * over-current, reset, link state, and L1 change
 312  */
 313 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 314 /*
 315  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 316  * latched in
 317  */
 318 #define XHCI_PORT_RW    ((1<<16))
 319 /*
 320  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 321  * bits 2, 24, 28:31
 322  */
 323 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 324
 325 /*
 326  * Given a port state, this function returns a value that would result in the
 327  * port being in the same state, if the value was written to the port status
 328  * control register.
 329  * Save Read Only (RO) bits and save read/write bits where
 330  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 331  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 332  */
 333 u32 xhci_port_state_to_neutral(u32 state)
 334 {
 335         /* Save read-only status and port state */
 336         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 337 }
 338
 339 /*
 340  * find slot id based on port number.
 341  * @port: The one-based port number from one of the two split roothubs.
 342  */
 343 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 344                 u16 port)
 345 {
 346         int slot_id;
 347         int i;
 348         enum usb_device_speed speed;
 349
 350         slot_id = 0;
 351         for (i = 0; i < MAX_HC_SLOTS; i++) {
 352                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 353                         continue;
 354                 speed = xhci->devs[i]->udev->speed;
 355                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 356                                 && xhci->devs[i]->fake_port == port) {
 357                         slot_id = i;
 358                         break;
 359                 }
 360         }
 361
 362         return slot_id;
 363 }
 364
 365 /*
 366  * Stop device
 367  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 368  * to complete.
 369  * suspend will set to 1, if suspend bit need to set in command.
 370  */
 371 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 372 {
 373         struct xhci_virt_device *virt_dev;
 374         struct xhci_command *cmd;
 375         unsigned long flags;
 376         int ret;
 377         int i;
 378
 379         ret = 0;
 380         virt_dev = xhci->devs[slot_id];
 381         if (!virt_dev)
 382                 return -ENODEV;
 383
 384         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 385         if (!cmd) {
 386                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 387                 return -ENOMEM;
 388         }
 389
 390         spin_lock_irqsave(&xhci->lock, flags);
 391         for (i = LAST_EP_INDEX; i > 0; i--) {
 392                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 393                         struct xhci_command *command;
 394                         command = xhci_alloc_command(xhci, false, false,
 395                                                      GFP_NOWAIT);
 396                         if (!command) {
 397                                 spin_unlock_irqrestore(&xhci->lock, flags);
 398                                 ret = -ENOMEM;
 399                                 goto cmd_cleanup;
 400                         }
 401
 402                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 403                                                        i, suspend);
 404                         if (ret) {
 405                                 spin_unlock_irqrestore(&xhci->lock, flags);
 406                                 xhci_free_command(xhci, command);
 407                                 goto cmd_cleanup;
 408                         }
 409                 }
 410         }
 411         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 412         if (ret) {
 413                 spin_unlock_irqrestore(&xhci->lock, flags);
 414                 goto cmd_cleanup;
 415         }
 416
 417         xhci_ring_cmd_db(xhci);
 418         spin_unlock_irqrestore(&xhci->lock, flags);
 419
 420         /* Wait for last stop endpoint command to finish */
 421         wait_for_completion(cmd->completion);
 422
 423         if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
 424                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 425                 ret = -ETIME;
 426         }
 427
 428 cmd_cleanup:
 429         xhci_free_command(xhci, cmd);
 430         return ret;
 431 }
 432
 433 /*
 434  * Ring device, it rings the all doorbells unconditionally.
 435  */
 436 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 437 {
 438         int i, s;
 439         struct xhci_virt_ep *ep;
 440
 441         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 442                 ep = &xhci->devs[slot_id]->eps[i];
 443
 444                 if (ep->ep_state & EP_HAS_STREAMS) {
 445                         for (s = 1; s < ep->stream_info->num_streams; s++)
 446                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 447                 } else if (ep->ring && ep->ring->dequeue) {
 448                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 449                 }
 450         }
 451
 452         return;
 453 }
 454
 455 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 456                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 457 {
 458         /* Don't allow the USB core to disable SuperSpeed ports. */
 459         if (hcd->speed >= HCD_USB3) {
 460                 xhci_dbg(xhci, "Ignoring request to disable "
 461                                 "SuperSpeed port.\n");
 462                 return;
 463         }
 464
 465         /* Write 1 to disable the port */
 466         writel(port_status | PORT_PE, addr);
 467         port_status = readl(addr);
 468         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 469                         wIndex, port_status);
 470 }
 471
 472 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 473                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 474 {
 475         char *port_change_bit;
 476         u32 status;
 477
 478         switch (wValue) {
 479         case USB_PORT_FEAT_C_RESET:
 480                 status = PORT_RC;
 481                 port_change_bit = "reset";
 482                 break;
 483         case USB_PORT_FEAT_C_BH_PORT_RESET:
 484                 status = PORT_WRC;
 485                 port_change_bit = "warm(BH) reset";
 486                 break;
 487         case USB_PORT_FEAT_C_CONNECTION:
 488                 status = PORT_CSC;
 489                 port_change_bit = "connect";
 490                 break;
 491         case USB_PORT_FEAT_C_OVER_CURRENT:
 492                 status = PORT_OCC;
 493                 port_change_bit = "over-current";
 494                 break;
 495         case USB_PORT_FEAT_C_ENABLE:
 496                 status = PORT_PEC;
 497                 port_change_bit = "enable/disable";
 498                 break;
 499         case USB_PORT_FEAT_C_SUSPEND:
 500                 status = PORT_PLC;
 501                 port_change_bit = "suspend/resume";
 502                 break;
 503         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 504                 status = PORT_PLC;
 505                 port_change_bit = "link state";
 506                 break;
 507         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 508                 status = PORT_CEC;
 509                 port_change_bit = "config error";
 510                 break;
 511         default:
 512                 /* Should never happen */
 513                 return;
 514         }
 515         /* Change bits are all write 1 to clear */
 516         writel(port_status | status, addr);
 517         port_status = readl(addr);
 518         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 519                         port_change_bit, wIndex, port_status);
 520 }
 521
 522 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 523 {
 524         int max_ports;
 525         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 526
 527         if (hcd->speed >= HCD_USB3) {
 528                 max_ports = xhci->num_usb3_ports;
 529                 *port_array = xhci->usb3_ports;
 530         } else {
 531                 max_ports = xhci->num_usb2_ports;
 532                 *port_array = xhci->usb2_ports;
 533         }
 534
 535         return max_ports;
 536 }
 537
 538 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 539                                 int port_id, u32 link_state)
 540 {
 541         u32 temp;
 542
 543         temp = readl(port_array[port_id]);
 544         temp = xhci_port_state_to_neutral(temp);
 545         temp &= ~PORT_PLS_MASK;
 546         temp |= PORT_LINK_STROBE | link_state;
 547         writel(temp, port_array[port_id]);
 548 }
 549
 550 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 551                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 552 {
 553         u32 temp;
 554
 555         temp = readl(port_array[port_id]);
 556         temp = xhci_port_state_to_neutral(temp);
 557
 558         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 559                 temp |= PORT_WKCONN_E;
 560         else
 561                 temp &= ~PORT_WKCONN_E;
 562
 563         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 564                 temp |= PORT_WKDISC_E;
 565         else
 566                 temp &= ~PORT_WKDISC_E;
 567
 568         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 569                 temp |= PORT_WKOC_E;
 570         else
 571                 temp &= ~PORT_WKOC_E;
 572
 573         writel(temp, port_array[port_id]);
 574 }
 575
 576 /* Test and clear port RWC bit */
 577 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 578                                 int port_id, u32 port_bit)
 579 {
 580         u32 temp;
 581
 582         temp = readl(port_array[port_id]);
 583         if (temp & port_bit) {
 584                 temp = xhci_port_state_to_neutral(temp);
 585                 temp |= port_bit;
 586                 writel(temp, port_array[port_id]);
 587         }
 588 }
 589
 590 /* Updates Link Status for USB 2.1 port */
 591 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 592 {
 593         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 594                 *status |= USB_PORT_STAT_L1;
 595 }
 596
 597 /* Updates Link Status for super Speed port */
 598 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 599                 u32 *status, u32 status_reg)
 600 {
 601         u32 pls = status_reg & PORT_PLS_MASK;
 602
 603         /* When the CAS bit is set then warm reset
 604          * should be performed on port
 605          */
 606         if (status_reg & PORT_CAS) {
 607                 /* The CAS bit can be set while the port is
 608                  * in any link state.
 609                  * Only roothubs have CAS bit, so we
 610                  * pretend to be in compliance mode
 611                  * unless we're already in compliance
 612                  * or the inactive state.
 613                  */
 614                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 615                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 616                         pls = USB_SS_PORT_LS_COMP_MOD;
 617                 }
 618                 /* Return also connection bit -
 619                  * hub state machine resets port
 620                  * when this bit is set.
 621                  */
 622                 pls |= USB_PORT_STAT_CONNECTION;
 623         } else {
 624                 /*
 625                  * Resume state is an xHCI internal state.  Do not report it to
 626                  * usb core, instead, pretend to be U3, thus usb core knows
 627                  * it's not ready for transfer.
 628                  */
 629                 if (pls == XDEV_RESUME) {
 630                         *status |= USB_SS_PORT_LS_U3;
 631                         return;
 632                 }
 633
 634                 /*
 635                  * If CAS bit isn't set but the Port is already at
 636                  * Compliance Mode, fake a connection so the USB core
 637                  * notices the Compliance state and resets the port.
 638                  * This resolves an issue generated by the SN65LVPE502CP
 639                  * in which sometimes the port enters compliance mode
 640                  * caused by a delay on the host-device negotiation.
 641                  */
 642                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 643                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 644                         pls |= USB_PORT_STAT_CONNECTION;
 645         }
 646
 647         /* update status field */
 648         *status |= pls;
 649 }
 650
 651 /*
 652  * Function for Compliance Mode Quirk.
 653  *
 654  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 655  * the compliance mode timer is deleted. A port won't enter
 656  * compliance mode if it has previously entered U0.
 657  */
 658 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 659                                     u16 wIndex)
 660 {
 661         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 662         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 663
 664         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 665                 return;
 666
 667         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 668                 xhci->port_status_u0 |= 1 << wIndex;
 669                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 670                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 671                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 672                                 "All USB3 ports have entered U0 already!");
 673                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 674                                 "Compliance Mode Recovery Timer Deleted.");
 675                 }
 676         }
 677 }
 678
 679 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 680 {
 681         u32 ext_stat = 0;
 682         int speed_id;
 683
 684         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 685         speed_id = DEV_PORT_SPEED(raw_port_status);
 686         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 687         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 688
 689         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 690         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 691
 692         return ext_stat;
 693 }
 694
 695 /*
 696  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 697  * 3.0 hubs use.
 698  *
 699  * Possible side effects:
 700  *  - Mark a port as being done with device resume,
 701  *    and ring the endpoint doorbells.
 702  *  - Stop the Synopsys redriver Compliance Mode polling.
 703  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 704  */
 705 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 706                 struct xhci_bus_state *bus_state,
 707                 __le32 __iomem **port_array,
 708                 u16 wIndex, u32 raw_port_status,
 709                 unsigned long *flags)
 710         __releases(&xhci->lock)
 711         __acquires(&xhci->lock)
 712 {
 713         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 714         u32 status = 0;
 715         int slot_id;
 716
 717         /* wPortChange bits */
 718         if (raw_port_status & PORT_CSC)
 719                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 720         if (raw_port_status & PORT_PEC)
 721                 status |= USB_PORT_STAT_C_ENABLE << 16;
 722         if ((raw_port_status & PORT_OCC))
 723                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 724         if ((raw_port_status & PORT_RC))
 725                 status |= USB_PORT_STAT_C_RESET << 16;
 726         /* USB3.0 only */
 727         if (hcd->speed >= HCD_USB3) {
 728                 /* Port link change with port in resume state should not be
 729                  * reported to usbcore, as this is an internal state to be
 730                  * handled by xhci driver. Reporting PLC to usbcore may
 731                  * cause usbcore clearing PLC first and port change event
 732                  * irq won't be generated.
 733                  */
 734                 if ((raw_port_status & PORT_PLC) &&
 735                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 736                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 737                 if ((raw_port_status & PORT_WRC))
 738                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 739                 if ((raw_port_status & PORT_CEC))
 740                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 741
 742                 /* USB3 remote wake resume signaling completed */
 743                 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
 744                     (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
 745                     (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
 746                         bus_state->port_remote_wakeup &= ~(1 << wIndex);
 747                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 748                 }
 749         }
 750
 751         if (hcd->speed < HCD_USB3) {
 752                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 753                                 && (raw_port_status & PORT_POWER))
 754                         status |= USB_PORT_STAT_SUSPEND;
 755         }
 756         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 757                 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
 758                 if ((raw_port_status & PORT_RESET) ||
 759                                 !(raw_port_status & PORT_PE))
 760                         return 0xffffffff;
 761                 /* did port event handler already start resume timing? */
 762                 if (!bus_state->resume_done[wIndex]) {
 763                         /* If not, maybe we are in a host initated resume? */
 764                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 765                                 /* Host initated resume doesn't time the resume
 766                                  * signalling using resume_done[].
 767                                  * It manually sets RESUME state, sleeps 20ms
 768                                  * and sets U0 state. This should probably be
 769                                  * changed, but not right now.
 770                                  */
 771                         } else {
 772                                 /* port resume was discovered now and here,
 773                                  * start resume timing
 774                                  */
 775                                 unsigned long timeout = jiffies +
 776                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 777
 778                                 set_bit(wIndex, &bus_state->resuming_ports);
 779                                 bus_state->resume_done[wIndex] = timeout;
 780                                 mod_timer(&hcd->rh_timer, timeout);
 781                         }
 782                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 783                 } else if (time_after_eq(jiffies,
 784                                          bus_state->resume_done[wIndex])) {
 785                         int time_left;
 786
 787                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 788                                         wIndex + 1);
 789                         bus_state->resume_done[wIndex] = 0;
 790                         clear_bit(wIndex, &bus_state->resuming_ports);
 791
 792                         set_bit(wIndex, &bus_state->rexit_ports);
 793
 794                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 795                                                 PORT_PLC);
 796                         xhci_set_link_state(xhci, port_array, wIndex,
 797                                         XDEV_U0);
 798
 799                         spin_unlock_irqrestore(&xhci->lock, *flags);
 800                         time_left = wait_for_completion_timeout(
 801                                         &bus_state->rexit_done[wIndex],
 802                                         msecs_to_jiffies(
 803                                                 XHCI_MAX_REXIT_TIMEOUT_MS));
 804                         spin_lock_irqsave(&xhci->lock, *flags);
 805
 806                         if (time_left) {
 807                                 slot_id = xhci_find_slot_id_by_port(hcd,
 808                                                 xhci, wIndex + 1);
 809                                 if (!slot_id) {
 810                                         xhci_dbg(xhci, "slot_id is zero\n");
 811                                         return 0xffffffff;
 812                                 }
 813                                 xhci_ring_device(xhci, slot_id);
 814                         } else {
 815                                 int port_status = readl(port_array[wIndex]);
 816                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 817                                                 XHCI_MAX_REXIT_TIMEOUT_MS,
 818                                                 port_status);
 819                                 status |= USB_PORT_STAT_SUSPEND;
 820                                 clear_bit(wIndex, &bus_state->rexit_ports);
 821                         }
 822
 823                         bus_state->port_c_suspend |= 1 << wIndex;
 824                         bus_state->suspended_ports &= ~(1 << wIndex);
 825                 } else {
 826                         /*
 827                          * The resume has been signaling for less than
 828                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 829                          * let the usbcore check port status again and clear
 830                          * resume signaling later.
 831                          */
 832                         status |= USB_PORT_STAT_SUSPEND;
 833                 }
 834         }
 835         /*
 836          * Clear stale usb2 resume signalling variables in case port changed
 837          * state during resume signalling. For example on error
 838          */
 839         if ((bus_state->resume_done[wIndex] ||
 840              test_bit(wIndex, &bus_state->resuming_ports)) &&
 841             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 842             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 843                 bus_state->resume_done[wIndex] = 0;
 844                 clear_bit(wIndex, &bus_state->resuming_ports);
 845         }
 846
 847
 848         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 849             (raw_port_status & PORT_POWER)) {
 850                 if (bus_state->suspended_ports & (1 << wIndex)) {
 851                         bus_state->suspended_ports &= ~(1 << wIndex);
 852                         if (hcd->speed < HCD_USB3)
 853                                 bus_state->port_c_suspend |= 1 << wIndex;
 854                 }
 855                 bus_state->resume_done[wIndex] = 0;
 856                 clear_bit(wIndex, &bus_state->resuming_ports);
 857         }
 858         if (raw_port_status & PORT_CONNECT) {
 859                 status |= USB_PORT_STAT_CONNECTION;
 860                 status |= xhci_port_speed(raw_port_status);
 861         }
 862         if (raw_port_status & PORT_PE)
 863                 status |= USB_PORT_STAT_ENABLE;
 864         if (raw_port_status & PORT_OC)
 865                 status |= USB_PORT_STAT_OVERCURRENT;
 866         if (raw_port_status & PORT_RESET)
 867                 status |= USB_PORT_STAT_RESET;
 868         if (raw_port_status & PORT_POWER) {
 869                 if (hcd->speed >= HCD_USB3)
 870                         status |= USB_SS_PORT_STAT_POWER;
 871                 else
 872                         status |= USB_PORT_STAT_POWER;
 873         }
 874         /* Update Port Link State */
 875         if (hcd->speed >= HCD_USB3) {
 876                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
 877                 /*
 878                  * Verify if all USB3 Ports Have entered U0 already.
 879                  * Delete Compliance Mode Timer if so.
 880                  */
 881                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 882         } else {
 883                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 884         }
 885         if (bus_state->port_c_suspend & (1 << wIndex))
 886                 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 887
 888         return status;
 889 }
 890
 891 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 892                 u16 wIndex, char *buf, u16 wLength)
 893 {
 894         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 895         int max_ports;
 896         unsigned long flags;
 897         u32 temp, status;
 898         int retval = 0;
 899         __le32 __iomem **port_array;
 900         int slot_id;
 901         struct xhci_bus_state *bus_state;
 902         u16 link_state = 0;
 903         u16 wake_mask = 0;
 904         u16 timeout = 0;
 905
 906         max_ports = xhci_get_ports(hcd, &port_array);
 907         bus_state = &xhci->bus_state[hcd_index(hcd)];
 908
 909         spin_lock_irqsave(&xhci->lock, flags);
 910         switch (typeReq) {
 911         case GetHubStatus:
 912                 /* No power source, over-current reported per port */
 913                 memset(buf, 0, 4);
 914                 break;
 915         case GetHubDescriptor:
 916                 /* Check to make sure userspace is asking for the USB 3.0 hub
 917                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 918                  * endpoint, like external hubs do.
 919                  */
 920                 if (hcd->speed >= HCD_USB3 &&
 921                                 (wLength < USB_DT_SS_HUB_SIZE ||
 922                                  wValue != (USB_DT_SS_HUB << 8))) {
 923                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 924                                         "USB 3.0 roothub.\n");
 925                         goto error;
 926                 }
 927                 xhci_hub_descriptor(hcd, xhci,
 928                                 (struct usb_hub_descriptor *) buf);
 929                 break;
 930         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 931                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 932                         goto error;
 933
 934                 if (hcd->speed < HCD_USB3)
 935                         goto error;
 936
 937                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
 938                 spin_unlock_irqrestore(&xhci->lock, flags);
 939                 return retval;
 940         case GetPortStatus:
 941                 if (!wIndex || wIndex > max_ports)
 942                         goto error;
 943                 wIndex--;
 944                 temp = readl(port_array[wIndex]);
 945                 if (temp == 0xffffffff) {
 946                         retval = -ENODEV;
 947                         break;
 948                 }
 949                 status = xhci_get_port_status(hcd, bus_state, port_array,
 950                                 wIndex, temp, &flags);
 951                 if (status == 0xffffffff)
 952                         goto error;
 953
 954                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 955                                 wIndex, temp);
 956                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 957
 958                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 959                 /* if USB 3.1 extended port status return additional 4 bytes */
 960                 if (wValue == 0x02) {
 961                         u32 port_li;
 962
 963                         if (hcd->speed < HCD_USB31 || wLength != 8) {
 964                                 xhci_err(xhci, "get ext port status invalid parameter\n");
 965                                 retval = -EINVAL;
 966                                 break;
 967                         }
 968                         port_li = readl(port_array[wIndex] + PORTLI);
 969                         status = xhci_get_ext_port_status(temp, port_li);
 970                         put_unaligned_le32(status, &buf[4]);
 971                 }
 972                 break;
 973         case SetPortFeature:
 974                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 975                         link_state = (wIndex & 0xff00) >> 3;
 976                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 977                         wake_mask = wIndex & 0xff00;
 978                 /* The MSB of wIndex is the U1/U2 timeout */
 979                 timeout = (wIndex & 0xff00) >> 8;
 980                 wIndex &= 0xff;
 981                 if (!wIndex || wIndex > max_ports)
 982                         goto error;
 983                 wIndex--;
 984                 temp = readl(port_array[wIndex]);
 985                 if (temp == 0xffffffff) {
 986                         retval = -ENODEV;
 987                         break;
 988                 }
 989                 temp = xhci_port_state_to_neutral(temp);
 990                 /* FIXME: What new port features do we need to support? */
 991                 switch (wValue) {
 992                 case USB_PORT_FEAT_SUSPEND:
 993                         temp = readl(port_array[wIndex]);
 994                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 995                                 /* Resume the port to U0 first */
 996                                 xhci_set_link_state(xhci, port_array, wIndex,
 997                                                         XDEV_U0);
 998                                 spin_unlock_irqrestore(&xhci->lock, flags);
 999                                 msleep(10);
1000                                 spin_lock_irqsave(&xhci->lock, flags);
1001                         }
1002                         /* In spec software should not attempt to suspend
1003                          * a port unless the port reports that it is in the
1004                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1005                          */
1006                         temp = readl(port_array[wIndex]);
1007                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1008                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1009                                 xhci_warn(xhci, "USB core suspending device "
1010                                           "not in U0/U1/U2.\n");
1011                                 goto error;
1012                         }
1013
1014                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1015                                         wIndex + 1);
1016                         if (!slot_id) {
1017                                 xhci_warn(xhci, "slot_id is zero\n");
1018                                 goto error;
1019                         }
1020                         /* unlock to execute stop endpoint commands */
1021                         spin_unlock_irqrestore(&xhci->lock, flags);
1022                         xhci_stop_device(xhci, slot_id, 1);
1023                         spin_lock_irqsave(&xhci->lock, flags);
1024
1025                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1026
1027                         spin_unlock_irqrestore(&xhci->lock, flags);
1028                         msleep(10); /* wait device to enter */
1029                         spin_lock_irqsave(&xhci->lock, flags);
1030
1031                         temp = readl(port_array[wIndex]);
1032                         bus_state->suspended_ports |= 1 << wIndex;
1033                         break;
1034                 case USB_PORT_FEAT_LINK_STATE:
1035                         temp = readl(port_array[wIndex]);
1036
1037                         /* Disable port */
1038                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1039                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1040                                 temp = xhci_port_state_to_neutral(temp);
1041                                 /*
1042                                  * Clear all change bits, so that we get a new
1043                                  * connection event.
1044                                  */
1045                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1046                                         PORT_OCC | PORT_RC | PORT_PLC |
1047                                         PORT_CEC;
1048                                 writel(temp | PORT_PE, port_array[wIndex]);
1049                                 temp = readl(port_array[wIndex]);
1050                                 break;
1051                         }
1052
1053                         /* Put link in RxDetect (enable port) */
1054                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1055                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1056                                 xhci_set_link_state(xhci, port_array, wIndex,
1057                                                 link_state);
1058                                 temp = readl(port_array[wIndex]);
1059                                 break;
1060                         }
1061                         /* Port must be enabled */
1062                         if (!(temp & PORT_PE)) {
1063                                 retval = -ENODEV;
1064                                 break;
1065                         }
1066                         /* Can't set port link state above '3' (U3) */
1067                         if (link_state > USB_SS_PORT_LS_U3) {
1068                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1069                                          wIndex, link_state);
1070                                 goto error;
1071                         }
1072                         if (link_state == USB_SS_PORT_LS_U3) {
1073                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1074                                                 wIndex + 1);
1075                                 if (slot_id) {
1076                                         /* unlock to execute stop endpoint
1077                                          * commands */
1078                                         spin_unlock_irqrestore(&xhci->lock,
1079                                                                 flags);
1080                                         xhci_stop_device(xhci, slot_id, 1);
1081                                         spin_lock_irqsave(&xhci->lock, flags);
1082                                 }
1083                         }
1084
1085                         xhci_set_link_state(xhci, port_array, wIndex,
1086                                                 link_state);
1087
1088                         spin_unlock_irqrestore(&xhci->lock, flags);
1089                         msleep(20); /* wait device to enter */
1090                         spin_lock_irqsave(&xhci->lock, flags);
1091
1092                         temp = readl(port_array[wIndex]);
1093                         if (link_state == USB_SS_PORT_LS_U3)
1094                                 bus_state->suspended_ports |= 1 << wIndex;
1095                         break;
1096                 case USB_PORT_FEAT_POWER:
1097                         /*
1098                          * Turn on ports, even if there isn't per-port switching.
1099                          * HC will report connect events even before this is set.
1100                          * However, hub_wq will ignore the roothub events until
1101                          * the roothub is registered.
1102                          */
1103                         writel(temp | PORT_POWER, port_array[wIndex]);
1104
1105                         temp = readl(port_array[wIndex]);
1106                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
1107
1108                         spin_unlock_irqrestore(&xhci->lock, flags);
1109                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1110                                         wIndex);
1111                         if (temp)
1112                                 usb_acpi_set_power_state(hcd->self.root_hub,
1113                                                 wIndex, true);
1114                         spin_lock_irqsave(&xhci->lock, flags);
1115                         break;
1116                 case USB_PORT_FEAT_RESET:
1117                         temp = (temp | PORT_RESET);
1118                         writel(temp, port_array[wIndex]);
1119
1120                         temp = readl(port_array[wIndex]);
1121                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1122                         break;
1123                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1124                         xhci_set_remote_wake_mask(xhci, port_array,
1125                                         wIndex, wake_mask);
1126                         temp = readl(port_array[wIndex]);
1127                         xhci_dbg(xhci, "set port remote wake mask, "
1128                                         "actual port %d status  = 0x%x\n",
1129                                         wIndex, temp);
1130                         break;
1131                 case USB_PORT_FEAT_BH_PORT_RESET:
1132                         temp |= PORT_WR;
1133                         writel(temp, port_array[wIndex]);
1134
1135                         temp = readl(port_array[wIndex]);
1136                         break;
1137                 case USB_PORT_FEAT_U1_TIMEOUT:
1138                         if (hcd->speed < HCD_USB3)
1139                                 goto error;
1140                         temp = readl(port_array[wIndex] + PORTPMSC);
1141                         temp &= ~PORT_U1_TIMEOUT_MASK;
1142                         temp |= PORT_U1_TIMEOUT(timeout);
1143                         writel(temp, port_array[wIndex] + PORTPMSC);
1144                         break;
1145                 case USB_PORT_FEAT_U2_TIMEOUT:
1146                         if (hcd->speed < HCD_USB3)
1147                                 goto error;
1148                         temp = readl(port_array[wIndex] + PORTPMSC);
1149                         temp &= ~PORT_U2_TIMEOUT_MASK;
1150                         temp |= PORT_U2_TIMEOUT(timeout);
1151                         writel(temp, port_array[wIndex] + PORTPMSC);
1152                         break;
1153                 default:
1154                         goto error;
1155                 }
1156                 /* unblock any posted writes */
1157                 temp = readl(port_array[wIndex]);
1158                 break;
1159         case ClearPortFeature:
1160                 if (!wIndex || wIndex > max_ports)
1161                         goto error;
1162                 wIndex--;
1163                 temp = readl(port_array[wIndex]);
1164                 if (temp == 0xffffffff) {
1165                         retval = -ENODEV;
1166                         break;
1167                 }
1168                 /* FIXME: What new port features do we need to support? */
1169                 temp = xhci_port_state_to_neutral(temp);
1170                 switch (wValue) {
1171                 case USB_PORT_FEAT_SUSPEND:
1172                         temp = readl(port_array[wIndex]);
1173                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1174                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1175                         if (temp & PORT_RESET)
1176                                 goto error;
1177                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1178                                 if ((temp & PORT_PE) == 0)
1179                                         goto error;
1180
1181                                 set_bit(wIndex, &bus_state->resuming_ports);
1182                                 xhci_set_link_state(xhci, port_array, wIndex,
1183                                                         XDEV_RESUME);
1184                                 spin_unlock_irqrestore(&xhci->lock, flags);
1185                                 msleep(USB_RESUME_TIMEOUT);
1186                                 spin_lock_irqsave(&xhci->lock, flags);
1187                                 xhci_set_link_state(xhci, port_array, wIndex,
1188                                                         XDEV_U0);
1189                                 clear_bit(wIndex, &bus_state->resuming_ports);
1190                         }
1191                         bus_state->port_c_suspend |= 1 << wIndex;
1192
1193                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1194                                         wIndex + 1);
1195                         if (!slot_id) {
1196                                 xhci_dbg(xhci, "slot_id is zero\n");
1197                                 goto error;
1198                         }
1199                         xhci_ring_device(xhci, slot_id);
1200                         break;
1201                 case USB_PORT_FEAT_C_SUSPEND:
1202                         bus_state->port_c_suspend &= ~(1 << wIndex);
1203                 case USB_PORT_FEAT_C_RESET:
1204                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1205                 case USB_PORT_FEAT_C_CONNECTION:
1206                 case USB_PORT_FEAT_C_OVER_CURRENT:
1207                 case USB_PORT_FEAT_C_ENABLE:
1208                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1209                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1210                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1211                                         port_array[wIndex], temp);
1212                         break;
1213                 case USB_PORT_FEAT_ENABLE:
1214                         xhci_disable_port(hcd, xhci, wIndex,
1215                                         port_array[wIndex], temp);
1216                         break;
1217                 case USB_PORT_FEAT_POWER:
1218                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1219
1220                         spin_unlock_irqrestore(&xhci->lock, flags);
1221                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1222                                         wIndex);
1223                         if (temp)
1224                                 usb_acpi_set_power_state(hcd->self.root_hub,
1225                                                 wIndex, false);
1226                         spin_lock_irqsave(&xhci->lock, flags);
1227                         break;
1228                 default:
1229                         goto error;
1230                 }
1231                 break;
1232         default:
1233 error:
1234                 /* "stall" on error */
1235                 retval = -EPIPE;
1236         }
1237         spin_unlock_irqrestore(&xhci->lock, flags);
1238         return retval;
1239 }
1240
1241 /*
1242  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1243  * Ports are 0-indexed from the HCD point of view,
1244  * and 1-indexed from the USB core pointer of view.
1245  *
1246  * Note that the status change bits will be cleared as soon as a port status
1247  * change event is generated, so we use the saved status from that event.
1248  */
1249 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1250 {
1251         unsigned long flags;
1252         u32 temp, status;
1253         u32 mask;
1254         int i, retval;
1255         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1256         int max_ports;
1257         __le32 __iomem **port_array;
1258         struct xhci_bus_state *bus_state;
1259         bool reset_change = false;
1260
1261         max_ports = xhci_get_ports(hcd, &port_array);
1262         bus_state = &xhci->bus_state[hcd_index(hcd)];
1263
1264         /* Initial status is no changes */
1265         retval = (max_ports + 8) / 8;
1266         memset(buf, 0, retval);
1267
1268         /*
1269          * Inform the usbcore about resume-in-progress by returning
1270          * a non-zero value even if there are no status changes.
1271          */
1272         spin_lock_irqsave(&xhci->lock, flags);
1273
1274         status = bus_state->resuming_ports;
1275
1276         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1277
1278         /* For each port, did anything change?  If so, set that bit in buf. */
1279         for (i = 0; i < max_ports; i++) {
1280                 temp = readl(port_array[i]);
1281                 if (temp == 0xffffffff) {
1282                         retval = -ENODEV;
1283                         break;
1284                 }
1285                 if ((temp & mask) != 0 ||
1286                         (bus_state->port_c_suspend & 1 << i) ||
1287                         (bus_state->resume_done[i] && time_after_eq(
1288                             jiffies, bus_state->resume_done[i]))) {
1289                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1290                         status = 1;
1291                 }
1292                 if ((temp & PORT_RC))
1293                         reset_change = true;
1294         }
1295         if (!status && !reset_change) {
1296                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1297                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1298         }
1299         spin_unlock_irqrestore(&xhci->lock, flags);
1300         return status ? retval : 0;
1301 }
1302
1303 #ifdef CONFIG_PM
1304
1305 int xhci_bus_suspend(struct usb_hcd *hcd)
1306 {
1307         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1308         int max_ports, port_index;
1309         __le32 __iomem **port_array;
1310         struct xhci_bus_state *bus_state;
1311         unsigned long flags;
1312         u32 portsc_buf[USB_MAXCHILDREN];
1313         bool wake_enabled;
1314
1315         max_ports = xhci_get_ports(hcd, &port_array);
1316         bus_state = &xhci->bus_state[hcd_index(hcd)];
1317         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1318
1319         spin_lock_irqsave(&xhci->lock, flags);
1320
1321         if (wake_enabled) {
1322                 if (bus_state->resuming_ports ||        /* USB2 */
1323                     bus_state->port_remote_wakeup) {    /* USB3 */
1324                         spin_unlock_irqrestore(&xhci->lock, flags);
1325                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1326                         return -EBUSY;
1327                 }
1328         }
1329         /*
1330          * Prepare ports for suspend, but don't write anything before all ports
1331          * are checked and we know bus suspend can proceed
1332          */
1333         bus_state->bus_suspended = 0;
1334         port_index = max_ports;
1335         while (port_index--) {
1336                 u32 t1, t2;
1337
1338                 t1 = readl(port_array[port_index]);
1339                 t2 = xhci_port_state_to_neutral(t1);
1340                 portsc_buf[port_index] = 0;
1341
1342                 /* Bail out if a USB3 port has a new device in link training */
1343                 if ((hcd->speed >= HCD_USB3) &&
1344                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1345                         bus_state->bus_suspended = 0;
1346                         spin_unlock_irqrestore(&xhci->lock, flags);
1347                         xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1348                         return -EBUSY;
1349                 }
1350
1351                 /* suspend ports in U0, or bail out for new connect changes */
1352                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1353                         if ((t1 & PORT_CSC) && wake_enabled) {
1354                                 bus_state->bus_suspended = 0;
1355                                 spin_unlock_irqrestore(&xhci->lock, flags);
1356                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1357                                 return -EBUSY;
1358                         }
1359                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1360                         t2 &= ~PORT_PLS_MASK;
1361                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1362                         set_bit(port_index, &bus_state->bus_suspended);
1363                 }
1364                 /* USB core sets remote wake mask for USB 3.0 hubs,
1365                  * including the USB 3.0 roothub, but only if CONFIG_PM
1366                  * is enabled, so also enable remote wake here.
1367                  */
1368                 if (wake_enabled) {
1369                         if (t1 & PORT_CONNECT) {
1370                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1371                                 t2 &= ~PORT_WKCONN_E;
1372                         } else {
1373                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1374                                 t2 &= ~PORT_WKDISC_E;
1375                         }
1376                 } else
1377                         t2 &= ~PORT_WAKE_BITS;
1378
1379                 t1 = xhci_port_state_to_neutral(t1);
1380                 if (t1 != t2)
1381                         portsc_buf[port_index] = t2;
1382         }
1383
1384         /* write port settings, stopping and suspending ports if needed */
1385         port_index = max_ports;
1386         while (port_index--) {
1387                 if (!portsc_buf[port_index])
1388                         continue;
1389                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1390                         int slot_id;
1391
1392                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1393                                                             port_index + 1);
1394                         if (slot_id) {
1395                                 spin_unlock_irqrestore(&xhci->lock, flags);
1396                                 xhci_stop_device(xhci, slot_id, 1);
1397                                 spin_lock_irqsave(&xhci->lock, flags);
1398                         }
1399                 }
1400                 writel(portsc_buf[port_index], port_array[port_index]);
1401         }
1402         hcd->state = HC_STATE_SUSPENDED;
1403         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1404         spin_unlock_irqrestore(&xhci->lock, flags);
1405
1406         if (bus_state->bus_suspended)
1407                 usleep_range(5000, 10000);
1408
1409         return 0;
1410 }
1411
1412 /*
1413  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1414  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1415  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1416  */
1417 static bool xhci_port_missing_cas_quirk(int port_index,
1418                                              __le32 __iomem **port_array)
1419 {
1420         u32 portsc;
1421
1422         portsc = readl(port_array[port_index]);
1423
1424         /* if any of these are set we are not stuck */
1425         if (portsc & (PORT_CONNECT | PORT_CAS))
1426                 return false;
1427
1428         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1429             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1430                 return false;
1431
1432         /* clear wakeup/change bits, and do a warm port reset */
1433         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1434         portsc |= PORT_WR;
1435         writel(portsc, port_array[port_index]);
1436         /* flush write */
1437         readl(port_array[port_index]);
1438         return true;
1439 }
1440
1441 int xhci_bus_resume(struct usb_hcd *hcd)
1442 {
1443         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1444         int max_ports, port_index;
1445         __le32 __iomem **port_array;
1446         struct xhci_bus_state *bus_state;
1447         u32 temp;
1448         unsigned long flags;
1449         unsigned long port_was_suspended = 0;
1450         bool need_usb2_u3_exit = false;
1451         int slot_id;
1452         int sret;
1453
1454         max_ports = xhci_get_ports(hcd, &port_array);
1455         bus_state = &xhci->bus_state[hcd_index(hcd)];
1456
1457         if (time_before(jiffies, bus_state->next_statechange))
1458                 msleep(5);
1459
1460         spin_lock_irqsave(&xhci->lock, flags);
1461         if (!HCD_HW_ACCESSIBLE(hcd)) {
1462                 spin_unlock_irqrestore(&xhci->lock, flags);
1463                 return -ESHUTDOWN;
1464         }
1465
1466         /* delay the irqs */
1467         temp = readl(&xhci->op_regs->command);
1468         temp &= ~CMD_EIE;
1469         writel(temp, &xhci->op_regs->command);
1470
1471         port_index = max_ports;
1472         while (port_index--) {
1473                 /* Check whether need resume ports. If needed
1474                    resume port and disable remote wakeup */
1475                 u32 temp;
1476
1477                 temp = readl(port_array[port_index]);
1478
1479                 /* warm reset CAS limited ports stuck in polling/compliance */
1480                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1481                     (hcd->speed >= HCD_USB3) &&
1482                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1483                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1484                         continue;
1485                 }
1486                 if (DEV_SUPERSPEED_ANY(temp))
1487                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1488                 else
1489                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1490                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1491                     (temp & PORT_PLS_MASK)) {
1492                         set_bit(port_index, &port_was_suspended);
1493                         if (!DEV_SUPERSPEED_ANY(temp)) {
1494                                 xhci_set_link_state(xhci, port_array,
1495                                                 port_index, XDEV_RESUME);
1496                                 need_usb2_u3_exit = true;
1497                         }
1498                 } else
1499                         writel(temp, port_array[port_index]);
1500         }
1501
1502         if (need_usb2_u3_exit) {
1503                 spin_unlock_irqrestore(&xhci->lock, flags);
1504                 msleep(USB_RESUME_TIMEOUT);
1505                 spin_lock_irqsave(&xhci->lock, flags);
1506         }
1507
1508         port_index = max_ports;
1509         while (port_index--) {
1510                 if (!(port_was_suspended & BIT(port_index)))
1511                         continue;
1512                 /* Clear PLC to poll it later after XDEV_U0 */
1513                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1514                 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1515         }
1516
1517         port_index = max_ports;
1518         while (port_index--) {
1519                 if (!(port_was_suspended & BIT(port_index)))
1520                         continue;
1521                 /* Poll and Clear PLC */
1522                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1523                                       PORT_PLC, 10 * 1000);
1524                 if (sret)
1525                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1526                                   port_index);
1527                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1528                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1529                 if (slot_id)
1530                         xhci_ring_device(xhci, slot_id);
1531         }
1532
1533         (void) readl(&xhci->op_regs->command);
1534
1535         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1536         /* re-enable irqs */
1537         temp = readl(&xhci->op_regs->command);
1538         temp |= CMD_EIE;
1539         writel(temp, &xhci->op_regs->command);
1540         temp = readl(&xhci->op_regs->command);
1541
1542         spin_unlock_irqrestore(&xhci->lock, flags);
1543         return 0;
1544 }
1545
1546 #endif  /* CONFIG_PM */