drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x1c,                           /* bLength 28, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  58         0x01, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  61         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  62         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  63         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  64         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  65 };
  66
  67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  68                                      u16 wLength)
  69 {
  70         int i, ssa_count;
  71         u32 temp;
  72         u16 desc_size, ssp_cap_size, ssa_size = 0;
  73         bool usb3_1 = false;
  74
  75         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  76         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  77
  78         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  79         if (xhci->usb3_rhub.min_rev >= 0x01) {
  80                 /* does xhci provide a PSI table for SSA speed attributes? */
  81                 if (xhci->usb3_rhub.psi_count) {
  82                         /* two SSA entries for each unique PSI ID, RX and TX */
  83                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  84                         ssa_size = ssa_count * sizeof(u32);
  85                         ssp_cap_size -= 16; /* skip copying the default SSA */
  86                 }
  87                 desc_size += ssp_cap_size;
  88                 usb3_1 = true;
  89         }
  90         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  91
  92         if (usb3_1) {
  93                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  94                 buf[4] += 1;
  95                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  96         }
  97
  98         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  99                 return wLength;
 100
 101         /* Indicate whether the host has LTM support. */
 102         temp = readl(&xhci->cap_regs->hcc_params);
 103         if (HCC_LTC(temp))
 104                 buf[8] |= USB_LTM_SUPPORT;
 105
 106         /* Set the U1 and U2 exit latencies. */
 107         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 108                 temp = readl(&xhci->cap_regs->hcs_params3);
 109                 buf[12] = HCS_U1_LATENCY(temp);
 110                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 111         }
 112
 113         /* If PSI table exists, add the custom speed attributes from it */
 114         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 115                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 116                 int offset;
 117
 118                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 119
 120                 if (wLength < desc_size)
 121                         return wLength;
 122                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 123
 124                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 125                 bm_attrib = (ssa_count - 1) & 0x1f;
 126                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 127                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 128
 129                 if (wLength < desc_size + ssa_size)
 130                         return wLength;
 131                 /*
 132                  * Create the Sublink Speed Attributes (SSA) array.
 133                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 134                  * but link type bits 7:6 differ for values 01b and 10b.
 135                  * xhci has also only one PSI entry for a symmetric link when
 136                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 137                  */
 138                 offset = desc_size;
 139                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 140                         psi = xhci->usb3_rhub.psi[i];
 141                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 142                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 143                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 144
 145                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 146                         for (; psi_exp < 3; psi_exp++)
 147                                 psi_mant /= 1000;
 148                         if (psi_mant >= 10)
 149                                 psi |= BIT(14);
 150
 151                         if ((psi & PLT_MASK) == PLT_SYM) {
 152                         /* Symmetric, create SSA RX and TX from one PSI entry */
 153                                 put_unaligned_le32(psi, &buf[offset]);
 154                                 psi |= 1 << 7;  /* turn entry to TX */
 155                                 offset += 4;
 156                                 if (offset >= desc_size + ssa_size)
 157                                         return desc_size + ssa_size;
 158                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 159                                 /* Asymetric RX, flip bits 7:6 for SSA */
 160                                 psi ^= PLT_MASK;
 161                         }
 162                         put_unaligned_le32(psi, &buf[offset]);
 163                         offset += 4;
 164                         if (offset >= desc_size + ssa_size)
 165                                 return desc_size + ssa_size;
 166                 }
 167         }
 168         /* ssa_size is 0 for other than usb 3.1 hosts */
 169         return desc_size + ssa_size;
 170 }
 171
 172 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 173                 struct usb_hub_descriptor *desc, int ports)
 174 {
 175         u16 temp;
 176
 177         desc->bHubContrCurrent = 0;
 178
 179         desc->bNbrPorts = ports;
 180         temp = 0;
 181         /* Bits 1:0 - support per-port power switching, or power always on */
 182         if (HCC_PPC(xhci->hcc_params))
 183                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 184         else
 185                 temp |= HUB_CHAR_NO_LPSM;
 186         /* Bit  2 - root hubs are not part of a compound device */
 187         /* Bits 4:3 - individual port over current protection */
 188         temp |= HUB_CHAR_INDV_PORT_OCPM;
 189         /* Bits 6:5 - no TTs in root ports */
 190         /* Bit  7 - no port indicators */
 191         desc->wHubCharacteristics = cpu_to_le16(temp);
 192 }
 193
 194 /* Fill in the USB 2.0 roothub descriptor */
 195 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 196                 struct usb_hub_descriptor *desc)
 197 {
 198         int ports;
 199         u16 temp;
 200         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 201         u32 portsc;
 202         unsigned int i;
 203
 204         ports = xhci->num_usb2_ports;
 205
 206         xhci_common_hub_descriptor(xhci, desc, ports);
 207         desc->bDescriptorType = USB_DT_HUB;
 208         temp = 1 + (ports / 8);
 209         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 210         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.8 says 20ms */
 211
 212         /* The Device Removable bits are reported on a byte granularity.
 213          * If the port doesn't exist within that byte, the bit is set to 0.
 214          */
 215         memset(port_removable, 0, sizeof(port_removable));
 216         for (i = 0; i < ports; i++) {
 217                 portsc = readl(xhci->usb2_ports[i]);
 218                 /* If a device is removable, PORTSC reports a 0, same as in the
 219                  * hub descriptor DeviceRemovable bits.
 220                  */
 221                 if (portsc & PORT_DEV_REMOVE)
 222                         /* This math is hairy because bit 0 of DeviceRemovable
 223                          * is reserved, and bit 1 is for port 1, etc.
 224                          */
 225                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 226         }
 227
 228         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 229          * ports on it.  The USB 2.0 specification says that there are two
 230          * variable length fields at the end of the hub descriptor:
 231          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 232          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 233          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 234          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 235          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 236          * set of ports that actually exist.
 237          */
 238         memset(desc->u.hs.DeviceRemovable, 0xff,
 239                         sizeof(desc->u.hs.DeviceRemovable));
 240         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 241                         sizeof(desc->u.hs.PortPwrCtrlMask));
 242
 243         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 244                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 245                                 sizeof(__u8));
 246 }
 247
 248 /* Fill in the USB 3.0 roothub descriptor */
 249 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 250                 struct usb_hub_descriptor *desc)
 251 {
 252         int ports;
 253         u16 port_removable;
 254         u32 portsc;
 255         unsigned int i;
 256
 257         ports = xhci->num_usb3_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261         desc->bPwrOn2PwrGood = 50;      /* usb 3.1 may fail if less than 100ms */
 262
 263         /* header decode latency should be zero for roothubs,
 264          * see section 4.23.5.2.
 265          */
 266         desc->u.ss.bHubHdrDecLat = 0;
 267         desc->u.ss.wHubDelay = 0;
 268
 269         port_removable = 0;
 270         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 271         for (i = 0; i < ports; i++) {
 272                 portsc = readl(xhci->usb3_ports[i]);
 273                 if (portsc & PORT_DEV_REMOVE)
 274                         port_removable |= 1 << (i + 1);
 275         }
 276
 277         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 278 }
 279
 280 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 281                 struct usb_hub_descriptor *desc)
 282 {
 283
 284         if (hcd->speed >= HCD_USB3)
 285                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 286         else
 287                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 288
 289 }
 290
 291 static unsigned int xhci_port_speed(unsigned int port_status)
 292 {
 293         if (DEV_LOWSPEED(port_status))
 294                 return USB_PORT_STAT_LOW_SPEED;
 295         if (DEV_HIGHSPEED(port_status))
 296                 return USB_PORT_STAT_HIGH_SPEED;
 297         /*
 298          * FIXME: Yes, we should check for full speed, but the core uses that as
 299          * a default in portspeed() in usb/core/hub.c (which is the only place
 300          * USB_PORT_STAT_*_SPEED is used).
 301          */
 302         return 0;
 303 }
 304
 305 /*
 306  * These bits are Read Only (RO) and should be saved and written to the
 307  * registers: 0, 3, 10:13, 30
 308  * connect status, over-current status, port speed, and device removable.
 309  * connect status and port speed are also sticky - meaning they're in
 310  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 311  */
 312 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 313 /*
 314  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 315  * bits 5:8, 9, 14:15, 25:27
 316  * link state, port power, port indicator state, "wake on" enable state
 317  */
 318 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 319 /*
 320  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 321  * bit 4 (port reset)
 322  */
 323 #define XHCI_PORT_RW1S  ((1<<4))
 324 /*
 325  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 326  * bits 1, 17, 18, 19, 20, 21, 22, 23
 327  * port enable/disable, and
 328  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 329  * over-current, reset, link state, and L1 change
 330  */
 331 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 332 /*
 333  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 334  * latched in
 335  */
 336 #define XHCI_PORT_RW    ((1<<16))
 337 /*
 338  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 339  * bits 2, 24, 28:31
 340  */
 341 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 342
 343 /*
 344  * Given a port state, this function returns a value that would result in the
 345  * port being in the same state, if the value was written to the port status
 346  * control register.
 347  * Save Read Only (RO) bits and save read/write bits where
 348  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 349  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 350  */
 351 u32 xhci_port_state_to_neutral(u32 state)
 352 {
 353         /* Save read-only status and port state */
 354         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 355 }
 356
 357 /*
 358  * find slot id based on port number.
 359  * @port: The one-based port number from one of the two split roothubs.
 360  */
 361 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 362                 u16 port)
 363 {
 364         int slot_id;
 365         int i;
 366         enum usb_device_speed speed;
 367
 368         slot_id = 0;
 369         for (i = 0; i < MAX_HC_SLOTS; i++) {
 370                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 371                         continue;
 372                 speed = xhci->devs[i]->udev->speed;
 373                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 374                                 && xhci->devs[i]->fake_port == port) {
 375                         slot_id = i;
 376                         break;
 377                 }
 378         }
 379
 380         return slot_id;
 381 }
 382
 383 /*
 384  * Stop device
 385  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 386  * to complete.
 387  * suspend will set to 1, if suspend bit need to set in command.
 388  */
 389 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 390 {
 391         struct xhci_virt_device *virt_dev;
 392         struct xhci_command *cmd;
 393         unsigned long flags;
 394         int ret;
 395         int i;
 396
 397         ret = 0;
 398         virt_dev = xhci->devs[slot_id];
 399         if (!virt_dev)
 400                 return -ENODEV;
 401
 402         trace_xhci_stop_device(virt_dev);
 403
 404         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 405         if (!cmd)
 406                 return -ENOMEM;
 407
 408         spin_lock_irqsave(&xhci->lock, flags);
 409         for (i = LAST_EP_INDEX; i > 0; i--) {
 410                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 411                         struct xhci_ep_ctx *ep_ctx;
 412                         struct xhci_command *command;
 413
 414                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 415
 416                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 417                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 418                                 continue;
 419
 420                         command = xhci_alloc_command(xhci, false, false,
 421                                                      GFP_NOWAIT);
 422                         if (!command) {
 423                                 spin_unlock_irqrestore(&xhci->lock, flags);
 424                                 ret = -ENOMEM;
 425                                 goto cmd_cleanup;
 426                         }
 427
 428                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 429                                                        i, suspend);
 430                         if (ret) {
 431                                 spin_unlock_irqrestore(&xhci->lock, flags);
 432                                 xhci_free_command(xhci, command);
 433                                 goto cmd_cleanup;
 434                         }
 435                 }
 436         }
 437         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 438         if (ret) {
 439                 spin_unlock_irqrestore(&xhci->lock, flags);
 440                 goto cmd_cleanup;
 441         }
 442
 443         xhci_ring_cmd_db(xhci);
 444         spin_unlock_irqrestore(&xhci->lock, flags);
 445
 446         /* Wait for last stop endpoint command to finish */
 447         wait_for_completion(cmd->completion);
 448
 449         if (cmd->status == COMP_COMMAND_ABORTED ||
 450             cmd->status == COMP_COMMAND_RING_STOPPED) {
 451                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 452                 ret = -ETIME;
 453         }
 454
 455 cmd_cleanup:
 456         xhci_free_command(xhci, cmd);
 457         return ret;
 458 }
 459
 460 /*
 461  * Ring device, it rings the all doorbells unconditionally.
 462  */
 463 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 464 {
 465         int i, s;
 466         struct xhci_virt_ep *ep;
 467
 468         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 469                 ep = &xhci->devs[slot_id]->eps[i];
 470
 471                 if (ep->ep_state & EP_HAS_STREAMS) {
 472                         for (s = 1; s < ep->stream_info->num_streams; s++)
 473                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 474                 } else if (ep->ring && ep->ring->dequeue) {
 475                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 476                 }
 477         }
 478
 479         return;
 480 }
 481
 482 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 483                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 484 {
 485         /* Don't allow the USB core to disable SuperSpeed ports. */
 486         if (hcd->speed >= HCD_USB3) {
 487                 xhci_dbg(xhci, "Ignoring request to disable "
 488                                 "SuperSpeed port.\n");
 489                 return;
 490         }
 491
 492         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 493                 xhci_dbg(xhci,
 494                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 495                 return;
 496         }
 497
 498         /* Write 1 to disable the port */
 499         writel(port_status | PORT_PE, addr);
 500         port_status = readl(addr);
 501         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 502                         wIndex, port_status);
 503 }
 504
 505 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 506                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 507 {
 508         char *port_change_bit;
 509         u32 status;
 510
 511         switch (wValue) {
 512         case USB_PORT_FEAT_C_RESET:
 513                 status = PORT_RC;
 514                 port_change_bit = "reset";
 515                 break;
 516         case USB_PORT_FEAT_C_BH_PORT_RESET:
 517                 status = PORT_WRC;
 518                 port_change_bit = "warm(BH) reset";
 519                 break;
 520         case USB_PORT_FEAT_C_CONNECTION:
 521                 status = PORT_CSC;
 522                 port_change_bit = "connect";
 523                 break;
 524         case USB_PORT_FEAT_C_OVER_CURRENT:
 525                 status = PORT_OCC;
 526                 port_change_bit = "over-current";
 527                 break;
 528         case USB_PORT_FEAT_C_ENABLE:
 529                 status = PORT_PEC;
 530                 port_change_bit = "enable/disable";
 531                 break;
 532         case USB_PORT_FEAT_C_SUSPEND:
 533                 status = PORT_PLC;
 534                 port_change_bit = "suspend/resume";
 535                 break;
 536         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 537                 status = PORT_PLC;
 538                 port_change_bit = "link state";
 539                 break;
 540         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 541                 status = PORT_CEC;
 542                 port_change_bit = "config error";
 543                 break;
 544         default:
 545                 /* Should never happen */
 546                 return;
 547         }
 548         /* Change bits are all write 1 to clear */
 549         writel(port_status | status, addr);
 550         port_status = readl(addr);
 551         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 552                         port_change_bit, wIndex, port_status);
 553 }
 554
 555 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 556 {
 557         int max_ports;
 558         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 559
 560         if (hcd->speed >= HCD_USB3) {
 561                 max_ports = xhci->num_usb3_ports;
 562                 *port_array = xhci->usb3_ports;
 563         } else {
 564                 max_ports = xhci->num_usb2_ports;
 565                 *port_array = xhci->usb2_ports;
 566         }
 567
 568         return max_ports;
 569 }
 570
 571 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
 572 {
 573         __le32 __iomem **port_array;
 574
 575         xhci_get_ports(hcd, &port_array);
 576         return port_array[index];
 577 }
 578
 579 /*
 580  * xhci_set_port_power() must be called with xhci->lock held.
 581  * It will release and re-aquire the lock while calling ACPI
 582  * method.
 583  */
 584 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 585                                 u16 index, bool on, unsigned long *flags)
 586 {
 587         __le32 __iomem *addr;
 588         u32 temp;
 589
 590         addr = xhci_get_port_io_addr(hcd, index);
 591         temp = readl(addr);
 592         temp = xhci_port_state_to_neutral(temp);
 593         if (on) {
 594                 /* Power on */
 595                 writel(temp | PORT_POWER, addr);
 596                 temp = readl(addr);
 597                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 598                                                 index, temp);
 599         } else {
 600                 /* Power off */
 601                 writel(temp & ~PORT_POWER, addr);
 602         }
 603
 604         spin_unlock_irqrestore(&xhci->lock, *flags);
 605         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 606                                         index);
 607         if (temp)
 608                 usb_acpi_set_power_state(hcd->self.root_hub,
 609                         index, on);
 610         spin_lock_irqsave(&xhci->lock, *flags);
 611 }
 612
 613 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 614         u16 test_mode, u16 wIndex)
 615 {
 616         u32 temp;
 617         __le32 __iomem *addr;
 618
 619         /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
 620         addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
 621         temp = readl(addr + PORTPMSC);
 622         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 623         writel(temp, addr + PORTPMSC);
 624         xhci->test_mode = test_mode;
 625         if (test_mode == TEST_FORCE_EN)
 626                 xhci_start(xhci);
 627 }
 628
 629 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 630                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 631 {
 632         int i, retval;
 633
 634         /* Disable all Device Slots */
 635         xhci_dbg(xhci, "Disable all slots\n");
 636         spin_unlock_irqrestore(&xhci->lock, *flags);
 637         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 638                 if (!xhci->devs[i])
 639                         continue;
 640
 641                 retval = xhci_disable_slot(xhci, i);
 642                 if (retval)
 643                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 644                                  i, retval);
 645         }
 646         spin_lock_irqsave(&xhci->lock, *flags);
 647         /* Put all ports to the Disable state by clear PP */
 648         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 649         /* Power off USB3 ports*/
 650         for (i = 0; i < xhci->num_usb3_ports; i++)
 651                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 652         /* Power off USB2 ports*/
 653         for (i = 0; i < xhci->num_usb2_ports; i++)
 654                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 655         /* Stop the controller */
 656         xhci_dbg(xhci, "Stop controller\n");
 657         retval = xhci_halt(xhci);
 658         if (retval)
 659                 return retval;
 660         /* Disable runtime PM for test mode */
 661         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 662         /* Set PORTPMSC.PTC field to enter selected test mode */
 663         /* Port is selected by wIndex. port_id = wIndex + 1 */
 664         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 665                                         test_mode, wIndex + 1);
 666         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 667         return retval;
 668 }
 669
 670 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 671 {
 672         int retval;
 673
 674         if (!xhci->test_mode) {
 675                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 676                 return 0;
 677         }
 678         if (xhci->test_mode == TEST_FORCE_EN &&
 679                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 680                 retval = xhci_halt(xhci);
 681                 if (retval)
 682                         return retval;
 683         }
 684         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 685         xhci->test_mode = 0;
 686         return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 687 }
 688
 689 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 690                                 int port_id, u32 link_state)
 691 {
 692         u32 temp;
 693
 694         temp = readl(port_array[port_id]);
 695         temp = xhci_port_state_to_neutral(temp);
 696         temp &= ~PORT_PLS_MASK;
 697         temp |= PORT_LINK_STROBE | link_state;
 698         writel(temp, port_array[port_id]);
 699 }
 700
 701 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 702                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 703 {
 704         u32 temp;
 705
 706         temp = readl(port_array[port_id]);
 707         temp = xhci_port_state_to_neutral(temp);
 708
 709         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 710                 temp |= PORT_WKCONN_E;
 711         else
 712                 temp &= ~PORT_WKCONN_E;
 713
 714         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 715                 temp |= PORT_WKDISC_E;
 716         else
 717                 temp &= ~PORT_WKDISC_E;
 718
 719         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 720                 temp |= PORT_WKOC_E;
 721         else
 722                 temp &= ~PORT_WKOC_E;
 723
 724         writel(temp, port_array[port_id]);
 725 }
 726
 727 /* Test and clear port RWC bit */
 728 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 729                                 int port_id, u32 port_bit)
 730 {
 731         u32 temp;
 732
 733         temp = readl(port_array[port_id]);
 734         if (temp & port_bit) {
 735                 temp = xhci_port_state_to_neutral(temp);
 736                 temp |= port_bit;
 737                 writel(temp, port_array[port_id]);
 738         }
 739 }
 740
 741 /* Updates Link Status for USB 2.1 port */
 742 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 743 {
 744         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 745                 *status |= USB_PORT_STAT_L1;
 746 }
 747
 748 /* Updates Link Status for super Speed port */
 749 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 750                 u32 *status, u32 status_reg)
 751 {
 752         u32 pls = status_reg & PORT_PLS_MASK;
 753
 754         /* When the CAS bit is set then warm reset
 755          * should be performed on port
 756          */
 757         if (status_reg & PORT_CAS) {
 758                 /* The CAS bit can be set while the port is
 759                  * in any link state.
 760                  * Only roothubs have CAS bit, so we
 761                  * pretend to be in compliance mode
 762                  * unless we're already in compliance
 763                  * or the inactive state.
 764                  */
 765                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 766                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 767                         pls = USB_SS_PORT_LS_COMP_MOD;
 768                 }
 769                 /* Return also connection bit -
 770                  * hub state machine resets port
 771                  * when this bit is set.
 772                  */
 773                 pls |= USB_PORT_STAT_CONNECTION;
 774         } else {
 775                 /*
 776                  * Resume state is an xHCI internal state.  Do not report it to
 777                  * usb core, instead, pretend to be U3, thus usb core knows
 778                  * it's not ready for transfer.
 779                  */
 780                 if (pls == XDEV_RESUME) {
 781                         *status |= USB_SS_PORT_LS_U3;
 782                         return;
 783                 }
 784
 785                 /*
 786                  * If CAS bit isn't set but the Port is already at
 787                  * Compliance Mode, fake a connection so the USB core
 788                  * notices the Compliance state and resets the port.
 789                  * This resolves an issue generated by the SN65LVPE502CP
 790                  * in which sometimes the port enters compliance mode
 791                  * caused by a delay on the host-device negotiation.
 792                  */
 793                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 794                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 795                         pls |= USB_PORT_STAT_CONNECTION;
 796         }
 797
 798         /* update status field */
 799         *status |= pls;
 800 }
 801
 802 /*
 803  * Function for Compliance Mode Quirk.
 804  *
 805  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 806  * the compliance mode timer is deleted. A port won't enter
 807  * compliance mode if it has previously entered U0.
 808  */
 809 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 810                                     u16 wIndex)
 811 {
 812         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 813         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 814
 815         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 816                 return;
 817
 818         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 819                 xhci->port_status_u0 |= 1 << wIndex;
 820                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 821                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 822                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 823                                 "All USB3 ports have entered U0 already!");
 824                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 825                                 "Compliance Mode Recovery Timer Deleted.");
 826                 }
 827         }
 828 }
 829
 830 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 831 {
 832         u32 ext_stat = 0;
 833         int speed_id;
 834
 835         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 836         speed_id = DEV_PORT_SPEED(raw_port_status);
 837         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 838         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 839
 840         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 841         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 842
 843         return ext_stat;
 844 }
 845
 846 /*
 847  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 848  * 3.0 hubs use.
 849  *
 850  * Possible side effects:
 851  *  - Mark a port as being done with device resume,
 852  *    and ring the endpoint doorbells.
 853  *  - Stop the Synopsys redriver Compliance Mode polling.
 854  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 855  */
 856 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 857                 struct xhci_bus_state *bus_state,
 858                 __le32 __iomem **port_array,
 859                 u16 wIndex, u32 raw_port_status,
 860                 unsigned long *flags)
 861         __releases(&xhci->lock)
 862         __acquires(&xhci->lock)
 863 {
 864         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 865         u32 status = 0;
 866         int slot_id;
 867
 868         /* wPortChange bits */
 869         if (raw_port_status & PORT_CSC)
 870                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 871         if (raw_port_status & PORT_PEC)
 872                 status |= USB_PORT_STAT_C_ENABLE << 16;
 873         if ((raw_port_status & PORT_OCC))
 874                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 875         if ((raw_port_status & PORT_RC))
 876                 status |= USB_PORT_STAT_C_RESET << 16;
 877         /* USB3.0 only */
 878         if (hcd->speed >= HCD_USB3) {
 879                 /* Port link change with port in resume state should not be
 880                  * reported to usbcore, as this is an internal state to be
 881                  * handled by xhci driver. Reporting PLC to usbcore may
 882                  * cause usbcore clearing PLC first and port change event
 883                  * irq won't be generated.
 884                  */
 885                 if ((raw_port_status & PORT_PLC) &&
 886                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 887                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 888                 if ((raw_port_status & PORT_WRC))
 889                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 890                 if ((raw_port_status & PORT_CEC))
 891                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 892
 893                 /* USB3 remote wake resume signaling completed */
 894                 if (bus_state->port_remote_wakeup & (1 << wIndex) &&
 895                     (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME &&
 896                     (raw_port_status & PORT_PLS_MASK) != XDEV_RECOVERY) {
 897                         bus_state->port_remote_wakeup &= ~(1 << wIndex);
 898                         usb_hcd_end_port_resume(&hcd->self, wIndex);
 899                 }
 900         }
 901
 902         if (hcd->speed < HCD_USB3) {
 903                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 904                                 && (raw_port_status & PORT_POWER))
 905                         status |= USB_PORT_STAT_SUSPEND;
 906         }
 907         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 908                 !DEV_SUPERSPEED_ANY(raw_port_status) && hcd->speed < HCD_USB3) {
 909                 if ((raw_port_status & PORT_RESET) ||
 910                                 !(raw_port_status & PORT_PE))
 911                         return 0xffffffff;
 912                 /* did port event handler already start resume timing? */
 913                 if (!bus_state->resume_done[wIndex]) {
 914                         /* If not, maybe we are in a host initated resume? */
 915                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 916                                 /* Host initated resume doesn't time the resume
 917                                  * signalling using resume_done[].
 918                                  * It manually sets RESUME state, sleeps 20ms
 919                                  * and sets U0 state. This should probably be
 920                                  * changed, but not right now.
 921                                  */
 922                         } else {
 923                                 /* port resume was discovered now and here,
 924                                  * start resume timing
 925                                  */
 926                                 unsigned long timeout = jiffies +
 927                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 928
 929                                 set_bit(wIndex, &bus_state->resuming_ports);
 930                                 bus_state->resume_done[wIndex] = timeout;
 931                                 mod_timer(&hcd->rh_timer, timeout);
 932                         }
 933                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 934                 } else if (time_after_eq(jiffies,
 935                                          bus_state->resume_done[wIndex])) {
 936                         int time_left;
 937
 938                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 939                                         wIndex + 1);
 940                         bus_state->resume_done[wIndex] = 0;
 941                         clear_bit(wIndex, &bus_state->resuming_ports);
 942
 943                         set_bit(wIndex, &bus_state->rexit_ports);
 944
 945                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 946                                                 PORT_PLC);
 947                         xhci_set_link_state(xhci, port_array, wIndex,
 948                                         XDEV_U0);
 949
 950                         spin_unlock_irqrestore(&xhci->lock, *flags);
 951                         time_left = wait_for_completion_timeout(
 952                                         &bus_state->rexit_done[wIndex],
 953                                         msecs_to_jiffies(
 954                                                 XHCI_MAX_REXIT_TIMEOUT_MS));
 955                         spin_lock_irqsave(&xhci->lock, *flags);
 956
 957                         if (time_left) {
 958                                 slot_id = xhci_find_slot_id_by_port(hcd,
 959                                                 xhci, wIndex + 1);
 960                                 if (!slot_id) {
 961                                         xhci_dbg(xhci, "slot_id is zero\n");
 962                                         return 0xffffffff;
 963                                 }
 964                                 xhci_ring_device(xhci, slot_id);
 965                         } else {
 966                                 int port_status = readl(port_array[wIndex]);
 967                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 968                                                 XHCI_MAX_REXIT_TIMEOUT_MS,
 969                                                 port_status);
 970                                 status |= USB_PORT_STAT_SUSPEND;
 971                                 clear_bit(wIndex, &bus_state->rexit_ports);
 972                         }
 973
 974                         bus_state->port_c_suspend |= 1 << wIndex;
 975                         bus_state->suspended_ports &= ~(1 << wIndex);
 976                 } else {
 977                         /*
 978                          * The resume has been signaling for less than
 979                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 980                          * let the usbcore check port status again and clear
 981                          * resume signaling later.
 982                          */
 983                         status |= USB_PORT_STAT_SUSPEND;
 984                 }
 985         }
 986         /*
 987          * Clear stale usb2 resume signalling variables in case port changed
 988          * state during resume signalling. For example on error
 989          */
 990         if ((bus_state->resume_done[wIndex] ||
 991              test_bit(wIndex, &bus_state->resuming_ports)) &&
 992             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 993             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 994                 bus_state->resume_done[wIndex] = 0;
 995                 clear_bit(wIndex, &bus_state->resuming_ports);
 996         }
 997
 998
 999         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
1000             (raw_port_status & PORT_POWER)) {
1001                 if (bus_state->suspended_ports & (1 << wIndex)) {
1002                         bus_state->suspended_ports &= ~(1 << wIndex);
1003                         if (hcd->speed < HCD_USB3)
1004                                 bus_state->port_c_suspend |= 1 << wIndex;
1005                 }
1006                 bus_state->resume_done[wIndex] = 0;
1007                 clear_bit(wIndex, &bus_state->resuming_ports);
1008         }
1009         if (raw_port_status & PORT_CONNECT) {
1010                 status |= USB_PORT_STAT_CONNECTION;
1011                 status |= xhci_port_speed(raw_port_status);
1012         }
1013         if (raw_port_status & PORT_PE)
1014                 status |= USB_PORT_STAT_ENABLE;
1015         if (raw_port_status & PORT_OC)
1016                 status |= USB_PORT_STAT_OVERCURRENT;
1017         if (raw_port_status & PORT_RESET)
1018                 status |= USB_PORT_STAT_RESET;
1019         if (raw_port_status & PORT_POWER) {
1020                 if (hcd->speed >= HCD_USB3)
1021                         status |= USB_SS_PORT_STAT_POWER;
1022                 else
1023                         status |= USB_PORT_STAT_POWER;
1024         }
1025         /* Update Port Link State */
1026         if (hcd->speed >= HCD_USB3) {
1027                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1028                 /*
1029                  * Verify if all USB3 Ports Have entered U0 already.
1030                  * Delete Compliance Mode Timer if so.
1031                  */
1032                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1033         } else {
1034                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1035         }
1036         if (bus_state->port_c_suspend & (1 << wIndex))
1037                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1038
1039         return status;
1040 }
1041
1042 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1043                 u16 wIndex, char *buf, u16 wLength)
1044 {
1045         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1046         int max_ports;
1047         unsigned long flags;
1048         u32 temp, status;
1049         int retval = 0;
1050         __le32 __iomem **port_array;
1051         int slot_id;
1052         struct xhci_bus_state *bus_state;
1053         u16 link_state = 0;
1054         u16 wake_mask = 0;
1055         u16 timeout = 0;
1056         u16 test_mode = 0;
1057
1058         max_ports = xhci_get_ports(hcd, &port_array);
1059         bus_state = &xhci->bus_state[hcd_index(hcd)];
1060
1061         spin_lock_irqsave(&xhci->lock, flags);
1062         switch (typeReq) {
1063         case GetHubStatus:
1064                 /* No power source, over-current reported per port */
1065                 memset(buf, 0, 4);
1066                 break;
1067         case GetHubDescriptor:
1068                 /* Check to make sure userspace is asking for the USB 3.0 hub
1069                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1070                  * endpoint, like external hubs do.
1071                  */
1072                 if (hcd->speed >= HCD_USB3 &&
1073                                 (wLength < USB_DT_SS_HUB_SIZE ||
1074                                  wValue != (USB_DT_SS_HUB << 8))) {
1075                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1076                                         "USB 3.0 roothub.\n");
1077                         goto error;
1078                 }
1079                 xhci_hub_descriptor(hcd, xhci,
1080                                 (struct usb_hub_descriptor *) buf);
1081                 break;
1082         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1083                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1084                         goto error;
1085
1086                 if (hcd->speed < HCD_USB3)
1087                         goto error;
1088
1089                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1090                 spin_unlock_irqrestore(&xhci->lock, flags);
1091                 return retval;
1092         case GetPortStatus:
1093                 if (!wIndex || wIndex > max_ports)
1094                         goto error;
1095                 wIndex--;
1096                 temp = readl(port_array[wIndex]);
1097                 if (temp == ~(u32)0) {
1098                         xhci_hc_died(xhci);
1099                         retval = -ENODEV;
1100                         break;
1101                 }
1102                 status = xhci_get_port_status(hcd, bus_state, port_array,
1103                                 wIndex, temp, &flags);
1104                 if (status == 0xffffffff)
1105                         goto error;
1106
1107                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1108                                 wIndex, temp);
1109                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1110
1111                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1112                 /* if USB 3.1 extended port status return additional 4 bytes */
1113                 if (wValue == 0x02) {
1114                         u32 port_li;
1115
1116                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1117                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1118                                 retval = -EINVAL;
1119                                 break;
1120                         }
1121                         port_li = readl(port_array[wIndex] + PORTLI);
1122                         status = xhci_get_ext_port_status(temp, port_li);
1123                         put_unaligned_le32(status, &buf[4]);
1124                 }
1125                 break;
1126         case SetPortFeature:
1127                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1128                         link_state = (wIndex & 0xff00) >> 3;
1129                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1130                         wake_mask = wIndex & 0xff00;
1131                 if (wValue == USB_PORT_FEAT_TEST)
1132                         test_mode = (wIndex & 0xff00) >> 8;
1133                 /* The MSB of wIndex is the U1/U2 timeout */
1134                 timeout = (wIndex & 0xff00) >> 8;
1135                 wIndex &= 0xff;
1136                 if (!wIndex || wIndex > max_ports)
1137                         goto error;
1138                 wIndex--;
1139                 temp = readl(port_array[wIndex]);
1140                 if (temp == ~(u32)0) {
1141                         xhci_hc_died(xhci);
1142                         retval = -ENODEV;
1143                         break;
1144                 }
1145                 temp = xhci_port_state_to_neutral(temp);
1146                 /* FIXME: What new port features do we need to support? */
1147                 switch (wValue) {
1148                 case USB_PORT_FEAT_SUSPEND:
1149                         temp = readl(port_array[wIndex]);
1150                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1151                                 /* Resume the port to U0 first */
1152                                 xhci_set_link_state(xhci, port_array, wIndex,
1153                                                         XDEV_U0);
1154                                 spin_unlock_irqrestore(&xhci->lock, flags);
1155                                 msleep(10);
1156                                 spin_lock_irqsave(&xhci->lock, flags);
1157                         }
1158                         /* In spec software should not attempt to suspend
1159                          * a port unless the port reports that it is in the
1160                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1161                          */
1162                         temp = readl(port_array[wIndex]);
1163                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1164                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1165                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1166                                 goto error;
1167                         }
1168
1169                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1170                                         wIndex + 1);
1171                         if (!slot_id) {
1172                                 xhci_warn(xhci, "slot_id is zero\n");
1173                                 goto error;
1174                         }
1175                         /* unlock to execute stop endpoint commands */
1176                         spin_unlock_irqrestore(&xhci->lock, flags);
1177                         xhci_stop_device(xhci, slot_id, 1);
1178                         spin_lock_irqsave(&xhci->lock, flags);
1179
1180                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1181
1182                         spin_unlock_irqrestore(&xhci->lock, flags);
1183                         msleep(10); /* wait device to enter */
1184                         spin_lock_irqsave(&xhci->lock, flags);
1185
1186                         temp = readl(port_array[wIndex]);
1187                         bus_state->suspended_ports |= 1 << wIndex;
1188                         break;
1189                 case USB_PORT_FEAT_LINK_STATE:
1190                         temp = readl(port_array[wIndex]);
1191
1192                         /* Disable port */
1193                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1194                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1195                                 temp = xhci_port_state_to_neutral(temp);
1196                                 /*
1197                                  * Clear all change bits, so that we get a new
1198                                  * connection event.
1199                                  */
1200                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1201                                         PORT_OCC | PORT_RC | PORT_PLC |
1202                                         PORT_CEC;
1203                                 writel(temp | PORT_PE, port_array[wIndex]);
1204                                 temp = readl(port_array[wIndex]);
1205                                 break;
1206                         }
1207
1208                         /* Put link in RxDetect (enable port) */
1209                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1210                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1211                                 xhci_set_link_state(xhci, port_array, wIndex,
1212                                                 link_state);
1213                                 temp = readl(port_array[wIndex]);
1214                                 break;
1215                         }
1216
1217                         /*
1218                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1219                          * root hub port's transition to compliance mode upon
1220                          * detecting LFPS timeout may be controlled by an
1221                          * Compliance Transition Enabled (CTE) flag (not
1222                          * software visible). This flag is set by writing 0xA
1223                          * to PORTSC PLS field which will allow transition to
1224                          * compliance mode the next time LFPS timeout is
1225                          * encountered. A warm reset will clear it.
1226                          *
1227                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1228                          * flag is set, otherwise, the compliance substate is
1229                          * automatically entered as on 1.0 and prior.
1230                          */
1231                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1232                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1233                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1234                                         break;
1235                                 }
1236
1237                                 if ((temp & PORT_CONNECT)) {
1238                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1239                                         goto error;
1240                                 }
1241
1242                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1243                                                 wIndex);
1244                                 xhci_set_link_state(xhci, port_array, wIndex,
1245                                                 link_state);
1246                                 temp = readl(port_array[wIndex]);
1247                                 break;
1248                         }
1249                         /* Port must be enabled */
1250                         if (!(temp & PORT_PE)) {
1251                                 retval = -ENODEV;
1252                                 break;
1253                         }
1254                         /* Can't set port link state above '3' (U3) */
1255                         if (link_state > USB_SS_PORT_LS_U3) {
1256                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1257                                          wIndex, link_state);
1258                                 goto error;
1259                         }
1260                         if (link_state == USB_SS_PORT_LS_U3) {
1261                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1262                                                 wIndex + 1);
1263                                 if (slot_id) {
1264                                         /* unlock to execute stop endpoint
1265                                          * commands */
1266                                         spin_unlock_irqrestore(&xhci->lock,
1267                                                                 flags);
1268                                         xhci_stop_device(xhci, slot_id, 1);
1269                                         spin_lock_irqsave(&xhci->lock, flags);
1270                                 }
1271                         }
1272
1273                         xhci_set_link_state(xhci, port_array, wIndex,
1274                                                 link_state);
1275
1276                         spin_unlock_irqrestore(&xhci->lock, flags);
1277                         msleep(20); /* wait device to enter */
1278                         spin_lock_irqsave(&xhci->lock, flags);
1279
1280                         temp = readl(port_array[wIndex]);
1281                         if (link_state == USB_SS_PORT_LS_U3)
1282                                 bus_state->suspended_ports |= 1 << wIndex;
1283                         break;
1284                 case USB_PORT_FEAT_POWER:
1285                         /*
1286                          * Turn on ports, even if there isn't per-port switching.
1287                          * HC will report connect events even before this is set.
1288                          * However, hub_wq will ignore the roothub events until
1289                          * the roothub is registered.
1290                          */
1291                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1292                         break;
1293                 case USB_PORT_FEAT_RESET:
1294                         temp = (temp | PORT_RESET);
1295                         writel(temp, port_array[wIndex]);
1296
1297                         temp = readl(port_array[wIndex]);
1298                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1299                         break;
1300                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1301                         xhci_set_remote_wake_mask(xhci, port_array,
1302                                         wIndex, wake_mask);
1303                         temp = readl(port_array[wIndex]);
1304                         xhci_dbg(xhci, "set port remote wake mask, "
1305                                         "actual port %d status  = 0x%x\n",
1306                                         wIndex, temp);
1307                         break;
1308                 case USB_PORT_FEAT_BH_PORT_RESET:
1309                         temp |= PORT_WR;
1310                         writel(temp, port_array[wIndex]);
1311
1312                         temp = readl(port_array[wIndex]);
1313                         break;
1314                 case USB_PORT_FEAT_U1_TIMEOUT:
1315                         if (hcd->speed < HCD_USB3)
1316                                 goto error;
1317                         temp = readl(port_array[wIndex] + PORTPMSC);
1318                         temp &= ~PORT_U1_TIMEOUT_MASK;
1319                         temp |= PORT_U1_TIMEOUT(timeout);
1320                         writel(temp, port_array[wIndex] + PORTPMSC);
1321                         break;
1322                 case USB_PORT_FEAT_U2_TIMEOUT:
1323                         if (hcd->speed < HCD_USB3)
1324                                 goto error;
1325                         temp = readl(port_array[wIndex] + PORTPMSC);
1326                         temp &= ~PORT_U2_TIMEOUT_MASK;
1327                         temp |= PORT_U2_TIMEOUT(timeout);
1328                         writel(temp, port_array[wIndex] + PORTPMSC);
1329                         break;
1330                 case USB_PORT_FEAT_TEST:
1331                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1332                         if (hcd->speed != HCD_USB2)
1333                                 goto error;
1334                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1335                                 goto error;
1336                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1337                                                       &flags);
1338                         break;
1339                 default:
1340                         goto error;
1341                 }
1342                 /* unblock any posted writes */
1343                 temp = readl(port_array[wIndex]);
1344                 break;
1345         case ClearPortFeature:
1346                 if (!wIndex || wIndex > max_ports)
1347                         goto error;
1348                 wIndex--;
1349                 temp = readl(port_array[wIndex]);
1350                 if (temp == ~(u32)0) {
1351                         xhci_hc_died(xhci);
1352                         retval = -ENODEV;
1353                         break;
1354                 }
1355                 /* FIXME: What new port features do we need to support? */
1356                 temp = xhci_port_state_to_neutral(temp);
1357                 switch (wValue) {
1358                 case USB_PORT_FEAT_SUSPEND:
1359                         temp = readl(port_array[wIndex]);
1360                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1361                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1362                         if (temp & PORT_RESET)
1363                                 goto error;
1364                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1365                                 if ((temp & PORT_PE) == 0)
1366                                         goto error;
1367
1368                                 set_bit(wIndex, &bus_state->resuming_ports);
1369                                 xhci_set_link_state(xhci, port_array, wIndex,
1370                                                         XDEV_RESUME);
1371                                 spin_unlock_irqrestore(&xhci->lock, flags);
1372                                 msleep(USB_RESUME_TIMEOUT);
1373                                 spin_lock_irqsave(&xhci->lock, flags);
1374                                 xhci_set_link_state(xhci, port_array, wIndex,
1375                                                         XDEV_U0);
1376                                 clear_bit(wIndex, &bus_state->resuming_ports);
1377                         }
1378                         bus_state->port_c_suspend |= 1 << wIndex;
1379
1380                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1381                                         wIndex + 1);
1382                         if (!slot_id) {
1383                                 xhci_dbg(xhci, "slot_id is zero\n");
1384                                 goto error;
1385                         }
1386                         xhci_ring_device(xhci, slot_id);
1387                         break;
1388                 case USB_PORT_FEAT_C_SUSPEND:
1389                         bus_state->port_c_suspend &= ~(1 << wIndex);
1390                 case USB_PORT_FEAT_C_RESET:
1391                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1392                 case USB_PORT_FEAT_C_CONNECTION:
1393                 case USB_PORT_FEAT_C_OVER_CURRENT:
1394                 case USB_PORT_FEAT_C_ENABLE:
1395                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1396                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1397                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1398                                         port_array[wIndex], temp);
1399                         break;
1400                 case USB_PORT_FEAT_ENABLE:
1401                         xhci_disable_port(hcd, xhci, wIndex,
1402                                         port_array[wIndex], temp);
1403                         break;
1404                 case USB_PORT_FEAT_POWER:
1405                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1406                         break;
1407                 case USB_PORT_FEAT_TEST:
1408                         retval = xhci_exit_test_mode(xhci);
1409                         break;
1410                 default:
1411                         goto error;
1412                 }
1413                 break;
1414         default:
1415 error:
1416                 /* "stall" on error */
1417                 retval = -EPIPE;
1418         }
1419         spin_unlock_irqrestore(&xhci->lock, flags);
1420         return retval;
1421 }
1422
1423 /*
1424  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1425  * Ports are 0-indexed from the HCD point of view,
1426  * and 1-indexed from the USB core pointer of view.
1427  *
1428  * Note that the status change bits will be cleared as soon as a port status
1429  * change event is generated, so we use the saved status from that event.
1430  */
1431 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1432 {
1433         unsigned long flags;
1434         u32 temp, status;
1435         u32 mask;
1436         int i, retval;
1437         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1438         int max_ports;
1439         __le32 __iomem **port_array;
1440         struct xhci_bus_state *bus_state;
1441         bool reset_change = false;
1442
1443         max_ports = xhci_get_ports(hcd, &port_array);
1444         bus_state = &xhci->bus_state[hcd_index(hcd)];
1445
1446         /* Initial status is no changes */
1447         retval = (max_ports + 8) / 8;
1448         memset(buf, 0, retval);
1449
1450         /*
1451          * Inform the usbcore about resume-in-progress by returning
1452          * a non-zero value even if there are no status changes.
1453          */
1454         spin_lock_irqsave(&xhci->lock, flags);
1455
1456         status = bus_state->resuming_ports;
1457
1458         /*
1459          * SS devices are only visible to roothub after link training completes.
1460          * Keep polling roothubs for a grace period after xHC start
1461          */
1462         if (xhci->run_graceperiod) {
1463                 if (time_before(jiffies, xhci->run_graceperiod))
1464                         status = 1;
1465                 else
1466                         xhci->run_graceperiod = 0;
1467         }
1468
1469         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1470
1471         /* For each port, did anything change?  If so, set that bit in buf. */
1472         for (i = 0; i < max_ports; i++) {
1473                 temp = readl(port_array[i]);
1474                 if (temp == ~(u32)0) {
1475                         xhci_hc_died(xhci);
1476                         retval = -ENODEV;
1477                         break;
1478                 }
1479                 if ((temp & mask) != 0 ||
1480                         (bus_state->port_c_suspend & 1 << i) ||
1481                         (bus_state->resume_done[i] && time_after_eq(
1482                             jiffies, bus_state->resume_done[i]))) {
1483                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1484                         status = 1;
1485                 }
1486                 if ((temp & PORT_RC))
1487                         reset_change = true;
1488         }
1489         if (!status && !reset_change) {
1490                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1491                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1492         }
1493         spin_unlock_irqrestore(&xhci->lock, flags);
1494         return status ? retval : 0;
1495 }
1496
1497 #ifdef CONFIG_PM
1498
1499 int xhci_bus_suspend(struct usb_hcd *hcd)
1500 {
1501         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1502         int max_ports, port_index;
1503         __le32 __iomem **port_array;
1504         struct xhci_bus_state *bus_state;
1505         unsigned long flags;
1506         u32 portsc_buf[USB_MAXCHILDREN];
1507         bool wake_enabled;
1508
1509         max_ports = xhci_get_ports(hcd, &port_array);
1510         bus_state = &xhci->bus_state[hcd_index(hcd)];
1511         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1512
1513         spin_lock_irqsave(&xhci->lock, flags);
1514
1515         if (wake_enabled) {
1516                 if (bus_state->resuming_ports ||        /* USB2 */
1517                     bus_state->port_remote_wakeup) {    /* USB3 */
1518                         spin_unlock_irqrestore(&xhci->lock, flags);
1519                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1520                         return -EBUSY;
1521                 }
1522         }
1523         /*
1524          * Prepare ports for suspend, but don't write anything before all ports
1525          * are checked and we know bus suspend can proceed
1526          */
1527         bus_state->bus_suspended = 0;
1528         port_index = max_ports;
1529         while (port_index--) {
1530                 u32 t1, t2;
1531
1532                 t1 = readl(port_array[port_index]);
1533                 t2 = xhci_port_state_to_neutral(t1);
1534                 portsc_buf[port_index] = 0;
1535
1536                 /* Bail out if a USB3 port has a new device in link training */
1537                 if ((hcd->speed >= HCD_USB3) &&
1538                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1539                         bus_state->bus_suspended = 0;
1540                         spin_unlock_irqrestore(&xhci->lock, flags);
1541                         xhci_dbg(xhci, "Bus suspend bailout, port in polling\n");
1542                         return -EBUSY;
1543                 }
1544
1545                 /* suspend ports in U0, or bail out for new connect changes */
1546                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1547                         if ((t1 & PORT_CSC) && wake_enabled) {
1548                                 bus_state->bus_suspended = 0;
1549                                 spin_unlock_irqrestore(&xhci->lock, flags);
1550                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1551                                 return -EBUSY;
1552                         }
1553                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1554                         t2 &= ~PORT_PLS_MASK;
1555                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1556                         set_bit(port_index, &bus_state->bus_suspended);
1557                 }
1558                 /* USB core sets remote wake mask for USB 3.0 hubs,
1559                  * including the USB 3.0 roothub, but only if CONFIG_PM
1560                  * is enabled, so also enable remote wake here.
1561                  */
1562                 if (wake_enabled) {
1563                         if (t1 & PORT_CONNECT) {
1564                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1565                                 t2 &= ~PORT_WKCONN_E;
1566                         } else {
1567                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1568                                 t2 &= ~PORT_WKDISC_E;
1569                         }
1570
1571                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1572                             (hcd->speed < HCD_USB3)) {
1573                                 if (usb_amd_pt_check_port(hcd->self.controller,
1574                                                           port_index))
1575                                         t2 &= ~PORT_WAKE_BITS;
1576                         }
1577                 } else
1578                         t2 &= ~PORT_WAKE_BITS;
1579
1580                 t1 = xhci_port_state_to_neutral(t1);
1581                 if (t1 != t2)
1582                         portsc_buf[port_index] = t2;
1583         }
1584
1585         /* write port settings, stopping and suspending ports if needed */
1586         port_index = max_ports;
1587         while (port_index--) {
1588                 if (!portsc_buf[port_index])
1589                         continue;
1590                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1591                         int slot_id;
1592
1593                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1594                                                             port_index + 1);
1595                         if (slot_id) {
1596                                 spin_unlock_irqrestore(&xhci->lock, flags);
1597                                 xhci_stop_device(xhci, slot_id, 1);
1598                                 spin_lock_irqsave(&xhci->lock, flags);
1599                         }
1600                 }
1601                 writel(portsc_buf[port_index], port_array[port_index]);
1602         }
1603         hcd->state = HC_STATE_SUSPENDED;
1604         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1605         spin_unlock_irqrestore(&xhci->lock, flags);
1606
1607         if (bus_state->bus_suspended)
1608                 usleep_range(5000, 10000);
1609
1610         return 0;
1611 }
1612
1613 /*
1614  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1615  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1616  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1617  */
1618 static bool xhci_port_missing_cas_quirk(int port_index,
1619                                              __le32 __iomem **port_array)
1620 {
1621         u32 portsc;
1622
1623         portsc = readl(port_array[port_index]);
1624
1625         /* if any of these are set we are not stuck */
1626         if (portsc & (PORT_CONNECT | PORT_CAS))
1627                 return false;
1628
1629         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1630             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1631                 return false;
1632
1633         /* clear wakeup/change bits, and do a warm port reset */
1634         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1635         portsc |= PORT_WR;
1636         writel(portsc, port_array[port_index]);
1637         /* flush write */
1638         readl(port_array[port_index]);
1639         return true;
1640 }
1641
1642 int xhci_bus_resume(struct usb_hcd *hcd)
1643 {
1644         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1645         struct xhci_bus_state *bus_state;
1646         __le32 __iomem **port_array;
1647         unsigned long flags;
1648         int max_ports, port_index;
1649         int slot_id;
1650         int sret;
1651         u32 next_state;
1652         u32 temp, portsc;
1653
1654         max_ports = xhci_get_ports(hcd, &port_array);
1655         bus_state = &xhci->bus_state[hcd_index(hcd)];
1656
1657         if (time_before(jiffies, bus_state->next_statechange))
1658                 msleep(5);
1659
1660         spin_lock_irqsave(&xhci->lock, flags);
1661         if (!HCD_HW_ACCESSIBLE(hcd)) {
1662                 spin_unlock_irqrestore(&xhci->lock, flags);
1663                 return -ESHUTDOWN;
1664         }
1665
1666         /* delay the irqs */
1667         temp = readl(&xhci->op_regs->command);
1668         temp &= ~CMD_EIE;
1669         writel(temp, &xhci->op_regs->command);
1670
1671         /* bus specific resume for ports we suspended at bus_suspend */
1672         if (hcd->speed >= HCD_USB3)
1673                 next_state = XDEV_U0;
1674         else
1675                 next_state = XDEV_RESUME;
1676
1677         port_index = max_ports;
1678         while (port_index--) {
1679                 portsc = readl(port_array[port_index]);
1680
1681                 /* warm reset CAS limited ports stuck in polling/compliance */
1682                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1683                     (hcd->speed >= HCD_USB3) &&
1684                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1685                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1686                         clear_bit(port_index, &bus_state->bus_suspended);
1687                         continue;
1688                 }
1689                 /* resume if we suspended the link, and it is still suspended */
1690                 if (test_bit(port_index, &bus_state->bus_suspended))
1691                         switch (portsc & PORT_PLS_MASK) {
1692                         case XDEV_U3:
1693                                 portsc = xhci_port_state_to_neutral(portsc);
1694                                 portsc &= ~PORT_PLS_MASK;
1695                                 portsc |= PORT_LINK_STROBE | next_state;
1696                                 break;
1697                         case XDEV_RESUME:
1698                                 /* resume already initiated */
1699                                 break;
1700                         default:
1701                                 /* not in a resumeable state, ignore it */
1702                                 clear_bit(port_index,
1703                                           &bus_state->bus_suspended);
1704                                 break;
1705                         }
1706                 /* disable wake for all ports, write new link state if needed */
1707                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1708                 writel(portsc, port_array[port_index]);
1709         }
1710
1711         /* USB2 specific resume signaling delay and U0 link state transition */
1712         if (hcd->speed < HCD_USB3) {
1713                 if (bus_state->bus_suspended) {
1714                         spin_unlock_irqrestore(&xhci->lock, flags);
1715                         msleep(USB_RESUME_TIMEOUT);
1716                         spin_lock_irqsave(&xhci->lock, flags);
1717                 }
1718                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1719                                  BITS_PER_LONG) {
1720                         /* Clear PLC to poll it later for U0 transition */
1721                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1722                                                 PORT_PLC);
1723                         xhci_set_link_state(xhci, port_array, port_index,
1724                                             XDEV_U0);
1725                 }
1726         }
1727
1728         /* poll for U0 link state complete, both USB2 and USB3 */
1729         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1730                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1731                                       PORT_PLC, 10 * 1000);
1732                 if (sret) {
1733                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1734                                   port_index);
1735                         continue;
1736                 }
1737                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1738                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1739                 if (slot_id)
1740                         xhci_ring_device(xhci, slot_id);
1741         }
1742         (void) readl(&xhci->op_regs->command);
1743
1744         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1745         /* re-enable irqs */
1746         temp = readl(&xhci->op_regs->command);
1747         temp |= CMD_EIE;
1748         writel(temp, &xhci->op_regs->command);
1749         temp = readl(&xhci->op_regs->command);
1750
1751         spin_unlock_irqrestore(&xhci->lock, flags);
1752         return 0;
1753 }
1754
1755 #endif  /* CONFIG_PM */