1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
14 #include <linux/bitfield.h>
17 #include "xhci-trace.h"
19 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
20 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
21 PORT_RC | PORT_PLC | PORT_PE)
23 /* Default sublink speed attribute of each lane */
24 static u32 ssp_cap_default_ssa[] = {
25 0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
26 0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
27 0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
28 0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
29 0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
30 0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
31 0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
32 0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf,
38 struct usb_bos_descriptor *bos;
39 struct usb_ss_cap_descriptor *ss_cap;
40 struct usb_ssp_cap_descriptor *ssp_cap;
41 struct xhci_port_cap *port_cap = NULL;
52 bos = (struct usb_bos_descriptor *)buf;
53 bos->bLength = USB_DT_BOS_SIZE;
54 bos->bDescriptorType = USB_DT_BOS;
55 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
56 USB_DT_USB_SS_CAP_SIZE);
57 bos->bNumDeviceCaps = 1;
59 /* Create the descriptor for port with the highest revision */
60 for (i = 0; i < xhci->num_port_caps; i++) {
61 u8 major = xhci->port_caps[i].maj_rev;
62 u8 minor = xhci->port_caps[i].min_rev;
63 u16 rev = (major << 8) | minor;
65 if (i == 0 || bcdUSB < rev) {
67 port_cap = &xhci->port_caps[i];
71 if (bcdUSB >= 0x0310) {
72 if (port_cap->psi_count) {
75 for (i = 0; i < port_cap->psi_count; i++) {
76 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM)
80 ssac = port_cap->psi_count + num_sym_ssa - 1;
81 ssic = port_cap->psi_uid_count - 1;
88 ssic = (ssac + 1) / 2 - 1;
91 bos->bNumDeviceCaps++;
92 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
93 USB_DT_USB_SS_CAP_SIZE +
94 USB_DT_USB_SSP_CAP_SIZE(ssac));
97 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
100 /* SuperSpeed USB Device Capability */
101 ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE];
102 ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE;
103 ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
104 ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE;
105 ss_cap->bmAttributes = 0; /* set later */
106 ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION);
107 ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION;
108 ss_cap->bU1devExitLat = 0; /* set later */
109 ss_cap->bU2DevExitLat = 0; /* set later */
111 reg = readl(&xhci->cap_regs->hcc_params);
113 ss_cap->bmAttributes |= USB_LTM_SUPPORT;
115 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
116 reg = readl(&xhci->cap_regs->hcs_params3);
117 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg);
118 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg));
121 if (wLength < le16_to_cpu(bos->wTotalLength))
125 return le16_to_cpu(bos->wTotalLength);
127 ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE +
128 USB_DT_USB_SS_CAP_SIZE];
129 ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac);
130 ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
131 ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE;
132 ssp_cap->bReserved = 0;
133 ssp_cap->wReserved = 0;
134 ssp_cap->bmAttributes =
135 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) |
136 FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic));
138 if (!port_cap->psi_count) {
139 for (i = 0; i < ssac + 1; i++)
140 ssp_cap->bmSublinkSpeedAttr[i] =
141 cpu_to_le32(ssp_cap_default_ssa[i]);
148 for (i = 0; i < port_cap->psi_count; i++) {
159 psi = port_cap->psi[i];
160 ssid = XHCI_EXT_PORT_PSIV(psi);
161 lp = XHCI_EXT_PORT_LP(psi);
162 psie = XHCI_EXT_PORT_PSIE(psi);
163 psim = XHCI_EXT_PORT_PSIM(psi);
164 plt = psi & PLT_MASK;
167 lane_mantissa = psim;
169 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
170 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++)
173 if (!min_rate || psim < min_rate) {
178 /* Some host controllers don't set the link protocol for SSP */
180 lp = USB_SSP_SUBLINK_SPEED_LP_SSP;
183 * PSIM and PSIE represent the total speed of PSI. The BOS
184 * descriptor SSP sublink speed attribute lane mantissa
185 * describes the lane speed. E.g. PSIM and PSIE for gen2x2
186 * is 20Gbps, but the BOS descriptor lane speed mantissa is
187 * 10Gbps. Check and modify the mantissa value to match the
190 if (bcdUSB == 0x0320 && plt == PLT_SYM) {
192 * The PSI dword for gen1x2 and gen2x1 share the same
193 * values. But the lane speed for gen1x2 is 5Gbps while
194 * gen2x1 is 10Gbps. If the previous PSI dword SSID is
195 * 5 and the PSIE and PSIM match with SSID 6, let's
196 * assume that the controller follows the default speed
197 * id with SSID 6 for gen1x2.
199 if (ssid == 6 && psie == 3 && psim == 10 && i) {
200 u32 prev = port_cap->psi[i - 1];
202 if ((prev & PLT_MASK) == PLT_SYM &&
203 XHCI_EXT_PORT_PSIV(prev) == 5 &&
204 XHCI_EXT_PORT_PSIE(prev) == 3 &&
205 XHCI_EXT_PORT_PSIM(prev) == 10) {
206 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
211 if (psie == 3 && psim > 10) {
212 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
217 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) |
218 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) |
219 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) |
220 FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa));
224 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
225 USB_SSP_SUBLINK_SPEED_ST_SYM_RX);
226 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
228 attr &= ~USB_SSP_SUBLINK_SPEED_ST;
229 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
230 USB_SSP_SUBLINK_SPEED_ST_SYM_TX);
231 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
234 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
235 USB_SSP_SUBLINK_SPEED_ST_ASYM_RX);
236 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
239 attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
240 USB_SSP_SUBLINK_SPEED_ST_ASYM_TX);
241 ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
246 ssp_cap->wFunctionalitySupport =
247 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID,
249 FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |
250 FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));
252 return le16_to_cpu(bos->wTotalLength);
255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
256 struct usb_hub_descriptor *desc, int ports)
260 desc->bHubContrCurrent = 0;
262 desc->bNbrPorts = ports;
264 /* Bits 1:0 - support per-port power switching, or power always on */
265 if (HCC_PPC(xhci->hcc_params))
266 temp |= HUB_CHAR_INDV_PORT_LPSM;
268 temp |= HUB_CHAR_NO_LPSM;
269 /* Bit 2 - root hubs are not part of a compound device */
270 /* Bits 4:3 - individual port over current protection */
271 temp |= HUB_CHAR_INDV_PORT_OCPM;
272 /* Bits 6:5 - no TTs in root ports */
273 /* Bit 7 - no port indicators */
274 desc->wHubCharacteristics = cpu_to_le16(temp);
277 /* Fill in the USB 2.0 roothub descriptor */
278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
279 struct usb_hub_descriptor *desc)
283 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
286 struct xhci_hub *rhub;
288 rhub = &xhci->usb2_rhub;
289 ports = rhub->num_ports;
290 xhci_common_hub_descriptor(xhci, desc, ports);
291 desc->bDescriptorType = USB_DT_HUB;
292 temp = 1 + (ports / 8);
293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
294 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.8 says 20ms */
296 /* The Device Removable bits are reported on a byte granularity.
297 * If the port doesn't exist within that byte, the bit is set to 0.
299 memset(port_removable, 0, sizeof(port_removable));
300 for (i = 0; i < ports; i++) {
301 portsc = readl(rhub->ports[i]->addr);
302 /* If a device is removable, PORTSC reports a 0, same as in the
303 * hub descriptor DeviceRemovable bits.
305 if (portsc & PORT_DEV_REMOVE)
306 /* This math is hairy because bit 0 of DeviceRemovable
307 * is reserved, and bit 1 is for port 1, etc.
309 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
312 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
313 * ports on it. The USB 2.0 specification says that there are two
314 * variable length fields at the end of the hub descriptor:
315 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
316 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
317 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
318 * 0xFF, so we initialize the both arrays (DeviceRemovable and
319 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
320 * set of ports that actually exist.
322 memset(desc->u.hs.DeviceRemovable, 0xff,
323 sizeof(desc->u.hs.DeviceRemovable));
324 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
325 sizeof(desc->u.hs.PortPwrCtrlMask));
327 for (i = 0; i < (ports + 1 + 7) / 8; i++)
328 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
332 /* Fill in the USB 3.0 roothub descriptor */
333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
334 struct usb_hub_descriptor *desc)
340 struct xhci_hub *rhub;
342 rhub = &xhci->usb3_rhub;
343 ports = rhub->num_ports;
344 xhci_common_hub_descriptor(xhci, desc, ports);
345 desc->bDescriptorType = USB_DT_SS_HUB;
346 desc->bDescLength = USB_DT_SS_HUB_SIZE;
347 desc->bPwrOn2PwrGood = 50; /* usb 3.1 may fail if less than 100ms */
349 /* header decode latency should be zero for roothubs,
350 * see section 4.23.5.2.
352 desc->u.ss.bHubHdrDecLat = 0;
353 desc->u.ss.wHubDelay = 0;
356 /* bit 0 is reserved, bit 1 is for port 1, etc. */
357 for (i = 0; i < ports; i++) {
358 portsc = readl(rhub->ports[i]->addr);
359 if (portsc & PORT_DEV_REMOVE)
360 port_removable |= 1 << (i + 1);
363 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
367 struct usb_hub_descriptor *desc)
370 if (hcd->speed >= HCD_USB3)
371 xhci_usb3_hub_descriptor(hcd, xhci, desc);
373 xhci_usb2_hub_descriptor(hcd, xhci, desc);
377 static unsigned int xhci_port_speed(unsigned int port_status)
379 if (DEV_LOWSPEED(port_status))
380 return USB_PORT_STAT_LOW_SPEED;
381 if (DEV_HIGHSPEED(port_status))
382 return USB_PORT_STAT_HIGH_SPEED;
384 * FIXME: Yes, we should check for full speed, but the core uses that as
385 * a default in portspeed() in usb/core/hub.c (which is the only place
386 * USB_PORT_STAT_*_SPEED is used).
392 * These bits are Read Only (RO) and should be saved and written to the
393 * registers: 0, 3, 10:13, 30
394 * connect status, over-current status, port speed, and device removable.
395 * connect status and port speed are also sticky - meaning they're in
396 * the AUX well and they aren't changed by a hot, warm, or cold reset.
398 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
400 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
401 * bits 5:8, 9, 14:15, 25:27
402 * link state, port power, port indicator state, "wake on" enable state
404 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
406 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
409 #define XHCI_PORT_RW1S ((1<<4))
411 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
412 * bits 1, 17, 18, 19, 20, 21, 22, 23
413 * port enable/disable, and
414 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
415 * over-current, reset, link state, and L1 change
417 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
419 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
422 #define XHCI_PORT_RW ((1<<16))
424 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
427 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
430 * Given a port state, this function returns a value that would result in the
431 * port being in the same state, if the value was written to the port status
433 * Save Read Only (RO) bits and save read/write bits where
434 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
435 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
437 u32 xhci_port_state_to_neutral(u32 state)
439 /* Save read-only status and port state */
440 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
444 * find slot id based on port number.
445 * @port: The one-based port number from one of the two split roothubs.
447 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
452 enum usb_device_speed speed;
455 for (i = 0; i < MAX_HC_SLOTS; i++) {
456 if (!xhci->devs[i] || !xhci->devs[i]->udev)
458 speed = xhci->devs[i]->udev->speed;
459 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
460 && xhci->devs[i]->fake_port == port) {
471 * It issues stop endpoint command for EP 0 to 30. And wait the last command
473 * suspend will set to 1, if suspend bit need to set in command.
475 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
477 struct xhci_virt_device *virt_dev;
478 struct xhci_command *cmd;
484 virt_dev = xhci->devs[slot_id];
488 trace_xhci_stop_device(virt_dev);
490 cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
494 spin_lock_irqsave(&xhci->lock, flags);
495 for (i = LAST_EP_INDEX; i > 0; i--) {
496 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
497 struct xhci_ep_ctx *ep_ctx;
498 struct xhci_command *command;
500 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
502 /* Check ep is running, required by AMD SNPS 3.1 xHC */
503 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
506 command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
508 spin_unlock_irqrestore(&xhci->lock, flags);
513 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
516 spin_unlock_irqrestore(&xhci->lock, flags);
517 xhci_free_command(xhci, command);
522 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
524 spin_unlock_irqrestore(&xhci->lock, flags);
528 xhci_ring_cmd_db(xhci);
529 spin_unlock_irqrestore(&xhci->lock, flags);
531 /* Wait for last stop endpoint command to finish */
532 wait_for_completion(cmd->completion);
534 if (cmd->status == COMP_COMMAND_ABORTED ||
535 cmd->status == COMP_COMMAND_RING_STOPPED) {
536 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
541 xhci_free_command(xhci, cmd);
546 * Ring device, it rings the all doorbells unconditionally.
548 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
551 struct xhci_virt_ep *ep;
553 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
554 ep = &xhci->devs[slot_id]->eps[i];
556 if (ep->ep_state & EP_HAS_STREAMS) {
557 for (s = 1; s < ep->stream_info->num_streams; s++)
558 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
559 } else if (ep->ring && ep->ring->dequeue) {
560 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
567 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
568 u16 wIndex, __le32 __iomem *addr, u32 port_status)
570 /* Don't allow the USB core to disable SuperSpeed ports. */
571 if (hcd->speed >= HCD_USB3) {
572 xhci_dbg(xhci, "Ignoring request to disable "
573 "SuperSpeed port.\n");
577 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
579 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
583 /* Write 1 to disable the port */
584 writel(port_status | PORT_PE, addr);
585 port_status = readl(addr);
586 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
587 hcd->self.busnum, wIndex + 1, port_status);
590 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
591 u16 wIndex, __le32 __iomem *addr, u32 port_status)
593 char *port_change_bit;
597 case USB_PORT_FEAT_C_RESET:
599 port_change_bit = "reset";
601 case USB_PORT_FEAT_C_BH_PORT_RESET:
603 port_change_bit = "warm(BH) reset";
605 case USB_PORT_FEAT_C_CONNECTION:
607 port_change_bit = "connect";
609 case USB_PORT_FEAT_C_OVER_CURRENT:
611 port_change_bit = "over-current";
613 case USB_PORT_FEAT_C_ENABLE:
615 port_change_bit = "enable/disable";
617 case USB_PORT_FEAT_C_SUSPEND:
619 port_change_bit = "suspend/resume";
621 case USB_PORT_FEAT_C_PORT_LINK_STATE:
623 port_change_bit = "link state";
625 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
627 port_change_bit = "config error";
630 /* Should never happen */
633 /* Change bits are all write 1 to clear */
634 writel(port_status | status, addr);
635 port_status = readl(addr);
637 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
638 wIndex + 1, port_change_bit, port_status);
641 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
643 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
645 if (hcd->speed >= HCD_USB3)
646 return &xhci->usb3_rhub;
647 return &xhci->usb2_rhub;
651 * xhci_set_port_power() must be called with xhci->lock held.
652 * It will release and re-aquire the lock while calling ACPI
655 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
656 u16 index, bool on, unsigned long *flags)
657 __must_hold(&xhci->lock)
659 struct xhci_hub *rhub;
660 struct xhci_port *port;
663 rhub = xhci_get_rhub(hcd);
664 port = rhub->ports[index];
665 temp = readl(port->addr);
667 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
668 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
670 temp = xhci_port_state_to_neutral(temp);
674 writel(temp | PORT_POWER, port->addr);
678 writel(temp & ~PORT_POWER, port->addr);
681 spin_unlock_irqrestore(&xhci->lock, *flags);
682 temp = usb_acpi_power_manageable(hcd->self.root_hub,
685 usb_acpi_set_power_state(hcd->self.root_hub,
687 spin_lock_irqsave(&xhci->lock, *flags);
690 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
691 u16 test_mode, u16 wIndex)
694 struct xhci_port *port;
696 /* xhci only supports test mode for usb2 ports */
697 port = xhci->usb2_rhub.ports[wIndex];
698 temp = readl(port->addr + PORTPMSC);
699 temp |= test_mode << PORT_TEST_MODE_SHIFT;
700 writel(temp, port->addr + PORTPMSC);
701 xhci->test_mode = test_mode;
702 if (test_mode == USB_TEST_FORCE_ENABLE)
706 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
707 u16 test_mode, u16 wIndex, unsigned long *flags)
708 __must_hold(&xhci->lock)
712 /* Disable all Device Slots */
713 xhci_dbg(xhci, "Disable all slots\n");
714 spin_unlock_irqrestore(&xhci->lock, *flags);
715 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
719 retval = xhci_disable_slot(xhci, i);
720 xhci_free_virt_device(xhci, i);
722 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
725 spin_lock_irqsave(&xhci->lock, *flags);
726 /* Put all ports to the Disable state by clear PP */
727 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
728 /* Power off USB3 ports*/
729 for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
730 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
731 /* Power off USB2 ports*/
732 for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
733 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
734 /* Stop the controller */
735 xhci_dbg(xhci, "Stop controller\n");
736 retval = xhci_halt(xhci);
739 /* Disable runtime PM for test mode */
740 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
741 /* Set PORTPMSC.PTC field to enter selected test mode */
742 /* Port is selected by wIndex. port_id = wIndex + 1 */
743 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
744 test_mode, wIndex + 1);
745 xhci_port_set_test_mode(xhci, test_mode, wIndex);
749 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
753 if (!xhci->test_mode) {
754 xhci_err(xhci, "Not in test mode, do nothing.\n");
757 if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
758 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
759 retval = xhci_halt(xhci);
763 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
765 return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
768 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
774 portsc = readl(port->addr);
775 temp = xhci_port_state_to_neutral(portsc);
776 temp &= ~PORT_PLS_MASK;
777 temp |= PORT_LINK_STROBE | link_state;
778 writel(temp, port->addr);
780 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
781 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
785 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
786 struct xhci_port *port, u16 wake_mask)
790 temp = readl(port->addr);
791 temp = xhci_port_state_to_neutral(temp);
793 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
794 temp |= PORT_WKCONN_E;
796 temp &= ~PORT_WKCONN_E;
798 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
799 temp |= PORT_WKDISC_E;
801 temp &= ~PORT_WKDISC_E;
803 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
806 temp &= ~PORT_WKOC_E;
808 writel(temp, port->addr);
811 /* Test and clear port RWC bit */
812 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
817 temp = readl(port->addr);
818 if (temp & port_bit) {
819 temp = xhci_port_state_to_neutral(temp);
821 writel(temp, port->addr);
825 /* Updates Link Status for super Speed port */
826 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
827 u32 *status, u32 status_reg)
829 u32 pls = status_reg & PORT_PLS_MASK;
831 /* When the CAS bit is set then warm reset
832 * should be performed on port
834 if (status_reg & PORT_CAS) {
835 /* The CAS bit can be set while the port is
837 * Only roothubs have CAS bit, so we
838 * pretend to be in compliance mode
839 * unless we're already in compliance
840 * or the inactive state.
842 if (pls != USB_SS_PORT_LS_COMP_MOD &&
843 pls != USB_SS_PORT_LS_SS_INACTIVE) {
844 pls = USB_SS_PORT_LS_COMP_MOD;
846 /* Return also connection bit -
847 * hub state machine resets port
848 * when this bit is set.
850 pls |= USB_PORT_STAT_CONNECTION;
853 * Resume state is an xHCI internal state. Do not report it to
854 * usb core, instead, pretend to be U3, thus usb core knows
855 * it's not ready for transfer.
857 if (pls == XDEV_RESUME) {
858 *status |= USB_SS_PORT_LS_U3;
863 * If CAS bit isn't set but the Port is already at
864 * Compliance Mode, fake a connection so the USB core
865 * notices the Compliance state and resets the port.
866 * This resolves an issue generated by the SN65LVPE502CP
867 * in which sometimes the port enters compliance mode
868 * caused by a delay on the host-device negotiation.
870 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
871 (pls == USB_SS_PORT_LS_COMP_MOD))
872 pls |= USB_PORT_STAT_CONNECTION;
875 /* update status field */
880 * Function for Compliance Mode Quirk.
882 * This Function verifies if all xhc USB3 ports have entered U0, if so,
883 * the compliance mode timer is deleted. A port won't enter
884 * compliance mode if it has previously entered U0.
886 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
889 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
890 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
892 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
895 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
896 xhci->port_status_u0 |= 1 << wIndex;
897 if (xhci->port_status_u0 == all_ports_seen_u0) {
898 del_timer_sync(&xhci->comp_mode_recovery_timer);
899 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
900 "All USB3 ports have entered U0 already!");
901 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
902 "Compliance Mode Recovery Timer Deleted.");
907 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
908 u32 *status, u32 portsc,
909 unsigned long *flags)
911 struct xhci_bus_state *bus_state;
912 struct xhci_hcd *xhci;
917 hcd = port->rhub->hcd;
918 bus_state = &port->rhub->bus_state;
919 xhci = hcd_to_xhci(hcd);
920 wIndex = port->hcd_portnum;
922 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
923 *status = 0xffffffff;
926 /* did port event handler already start resume timing? */
927 if (!bus_state->resume_done[wIndex]) {
928 /* If not, maybe we are in a host initated resume? */
929 if (test_bit(wIndex, &bus_state->resuming_ports)) {
930 /* Host initated resume doesn't time the resume
931 * signalling using resume_done[].
932 * It manually sets RESUME state, sleeps 20ms
933 * and sets U0 state. This should probably be
934 * changed, but not right now.
937 /* port resume was discovered now and here,
938 * start resume timing
940 unsigned long timeout = jiffies +
941 msecs_to_jiffies(USB_RESUME_TIMEOUT);
943 set_bit(wIndex, &bus_state->resuming_ports);
944 bus_state->resume_done[wIndex] = timeout;
945 mod_timer(&hcd->rh_timer, timeout);
946 usb_hcd_start_port_resume(&hcd->self, wIndex);
948 /* Has resume been signalled for USB_RESUME_TIME yet? */
949 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
952 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
953 hcd->self.busnum, wIndex + 1);
955 bus_state->resume_done[wIndex] = 0;
956 clear_bit(wIndex, &bus_state->resuming_ports);
958 set_bit(wIndex, &bus_state->rexit_ports);
960 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
961 xhci_set_link_state(xhci, port, XDEV_U0);
963 spin_unlock_irqrestore(&xhci->lock, *flags);
964 time_left = wait_for_completion_timeout(
965 &bus_state->rexit_done[wIndex],
966 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
967 spin_lock_irqsave(&xhci->lock, *flags);
970 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
973 xhci_dbg(xhci, "slot_id is zero\n");
974 *status = 0xffffffff;
977 xhci_ring_device(xhci, slot_id);
979 int port_status = readl(port->addr);
981 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
982 hcd->self.busnum, wIndex + 1, port_status);
983 *status |= USB_PORT_STAT_SUSPEND;
984 clear_bit(wIndex, &bus_state->rexit_ports);
987 usb_hcd_end_port_resume(&hcd->self, wIndex);
988 bus_state->port_c_suspend |= 1 << wIndex;
989 bus_state->suspended_ports &= ~(1 << wIndex);
992 * The resume has been signaling for less than
993 * USB_RESUME_TIME. Report the port status as SUSPEND,
994 * let the usbcore check port status again and clear
995 * resume signaling later.
997 *status |= USB_PORT_STAT_SUSPEND;
1002 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
1007 /* only support rx and tx lane counts of 1 in usb3.1 spec */
1008 speed_id = DEV_PORT_SPEED(raw_port_status);
1009 ext_stat |= speed_id; /* bits 3:0, RX speed id */
1010 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
1012 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
1013 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
1018 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
1021 struct xhci_bus_state *bus_state;
1022 struct xhci_hcd *xhci;
1023 struct usb_hcd *hcd;
1027 bus_state = &port->rhub->bus_state;
1028 xhci = hcd_to_xhci(port->rhub->hcd);
1029 hcd = port->rhub->hcd;
1030 link_state = portsc & PORT_PLS_MASK;
1031 portnum = port->hcd_portnum;
1033 /* USB3 specific wPortChange bits
1035 * Port link change with port in resume state should not be
1036 * reported to usbcore, as this is an internal state to be
1037 * handled by xhci driver. Reporting PLC to usbcore may
1038 * cause usbcore clearing PLC first and port change event
1039 * irq won't be generated.
1042 if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
1043 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
1044 if (portsc & PORT_WRC)
1045 *status |= USB_PORT_STAT_C_BH_RESET << 16;
1046 if (portsc & PORT_CEC)
1047 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
1049 /* USB3 specific wPortStatus bits */
1050 if (portsc & PORT_POWER) {
1051 *status |= USB_SS_PORT_STAT_POWER;
1052 /* link state handling */
1053 if (link_state == XDEV_U0)
1054 bus_state->suspended_ports &= ~(1 << portnum);
1057 /* remote wake resume signaling complete */
1058 if (bus_state->port_remote_wakeup & (1 << portnum) &&
1059 link_state != XDEV_RESUME &&
1060 link_state != XDEV_RECOVERY) {
1061 bus_state->port_remote_wakeup &= ~(1 << portnum);
1062 usb_hcd_end_port_resume(&hcd->self, portnum);
1065 xhci_hub_report_usb3_link_state(xhci, status, portsc);
1066 xhci_del_comp_mod_timer(xhci, portsc, portnum);
1069 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
1070 u32 portsc, unsigned long *flags)
1072 struct xhci_bus_state *bus_state;
1077 bus_state = &port->rhub->bus_state;
1078 link_state = portsc & PORT_PLS_MASK;
1079 portnum = port->hcd_portnum;
1081 /* USB2 wPortStatus bits */
1082 if (portsc & PORT_POWER) {
1083 *status |= USB_PORT_STAT_POWER;
1085 /* link state is only valid if port is powered */
1086 if (link_state == XDEV_U3)
1087 *status |= USB_PORT_STAT_SUSPEND;
1088 if (link_state == XDEV_U2)
1089 *status |= USB_PORT_STAT_L1;
1090 if (link_state == XDEV_U0) {
1091 if (bus_state->resume_done[portnum])
1092 usb_hcd_end_port_resume(&port->rhub->hcd->self,
1094 bus_state->resume_done[portnum] = 0;
1095 clear_bit(portnum, &bus_state->resuming_ports);
1096 if (bus_state->suspended_ports & (1 << portnum)) {
1097 bus_state->suspended_ports &= ~(1 << portnum);
1098 bus_state->port_c_suspend |= 1 << portnum;
1101 if (link_state == XDEV_RESUME) {
1102 ret = xhci_handle_usb2_port_link_resume(port, status,
1111 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1114 * Possible side effects:
1115 * - Mark a port as being done with device resume,
1116 * and ring the endpoint doorbells.
1117 * - Stop the Synopsys redriver Compliance Mode polling.
1118 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1120 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1121 struct xhci_bus_state *bus_state,
1122 u16 wIndex, u32 raw_port_status,
1123 unsigned long *flags)
1124 __releases(&xhci->lock)
1125 __acquires(&xhci->lock)
1128 struct xhci_hub *rhub;
1129 struct xhci_port *port;
1131 rhub = xhci_get_rhub(hcd);
1132 port = rhub->ports[wIndex];
1134 /* common wPortChange bits */
1135 if (raw_port_status & PORT_CSC)
1136 status |= USB_PORT_STAT_C_CONNECTION << 16;
1137 if (raw_port_status & PORT_PEC)
1138 status |= USB_PORT_STAT_C_ENABLE << 16;
1139 if ((raw_port_status & PORT_OCC))
1140 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1141 if ((raw_port_status & PORT_RC))
1142 status |= USB_PORT_STAT_C_RESET << 16;
1144 /* common wPortStatus bits */
1145 if (raw_port_status & PORT_CONNECT) {
1146 status |= USB_PORT_STAT_CONNECTION;
1147 status |= xhci_port_speed(raw_port_status);
1149 if (raw_port_status & PORT_PE)
1150 status |= USB_PORT_STAT_ENABLE;
1151 if (raw_port_status & PORT_OC)
1152 status |= USB_PORT_STAT_OVERCURRENT;
1153 if (raw_port_status & PORT_RESET)
1154 status |= USB_PORT_STAT_RESET;
1156 /* USB2 and USB3 specific bits, including Port Link State */
1157 if (hcd->speed >= HCD_USB3)
1158 xhci_get_usb3_port_status(port, &status, raw_port_status);
1160 xhci_get_usb2_port_status(port, &status, raw_port_status,
1163 * Clear stale usb2 resume signalling variables in case port changed
1164 * state during resume signalling. For example on error
1166 if ((bus_state->resume_done[wIndex] ||
1167 test_bit(wIndex, &bus_state->resuming_ports)) &&
1168 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1169 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1170 bus_state->resume_done[wIndex] = 0;
1171 clear_bit(wIndex, &bus_state->resuming_ports);
1172 usb_hcd_end_port_resume(&hcd->self, wIndex);
1175 if (bus_state->port_c_suspend & (1 << wIndex))
1176 status |= USB_PORT_STAT_C_SUSPEND << 16;
1181 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1182 u16 wIndex, char *buf, u16 wLength)
1184 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1186 unsigned long flags;
1190 struct xhci_bus_state *bus_state;
1195 struct xhci_hub *rhub;
1196 struct xhci_port **ports;
1198 rhub = xhci_get_rhub(hcd);
1199 ports = rhub->ports;
1200 max_ports = rhub->num_ports;
1201 bus_state = &rhub->bus_state;
1203 spin_lock_irqsave(&xhci->lock, flags);
1206 /* No power source, over-current reported per port */
1209 case GetHubDescriptor:
1210 /* Check to make sure userspace is asking for the USB 3.0 hub
1211 * descriptor for the USB 3.0 roothub. If not, we stall the
1212 * endpoint, like external hubs do.
1214 if (hcd->speed >= HCD_USB3 &&
1215 (wLength < USB_DT_SS_HUB_SIZE ||
1216 wValue != (USB_DT_SS_HUB << 8))) {
1217 xhci_dbg(xhci, "Wrong hub descriptor type for "
1218 "USB 3.0 roothub.\n");
1221 xhci_hub_descriptor(hcd, xhci,
1222 (struct usb_hub_descriptor *) buf);
1224 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1225 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1228 if (hcd->speed < HCD_USB3)
1231 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength);
1232 spin_unlock_irqrestore(&xhci->lock, flags);
1235 if (!wIndex || wIndex > max_ports)
1238 temp = readl(ports[wIndex]->addr);
1239 if (temp == ~(u32)0) {
1244 trace_xhci_get_port_status(wIndex, temp);
1245 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1247 if (status == 0xffffffff)
1250 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1251 hcd->self.busnum, wIndex + 1, temp, status);
1253 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1254 /* if USB 3.1 extended port status return additional 4 bytes */
1255 if (wValue == 0x02) {
1258 if (hcd->speed < HCD_USB31 || wLength != 8) {
1259 xhci_err(xhci, "get ext port status invalid parameter\n");
1263 port_li = readl(ports[wIndex]->addr + PORTLI);
1264 status = xhci_get_ext_port_status(temp, port_li);
1265 put_unaligned_le32(status, &buf[4]);
1268 case SetPortFeature:
1269 if (wValue == USB_PORT_FEAT_LINK_STATE)
1270 link_state = (wIndex & 0xff00) >> 3;
1271 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1272 wake_mask = wIndex & 0xff00;
1273 if (wValue == USB_PORT_FEAT_TEST)
1274 test_mode = (wIndex & 0xff00) >> 8;
1275 /* The MSB of wIndex is the U1/U2 timeout */
1276 timeout = (wIndex & 0xff00) >> 8;
1278 if (!wIndex || wIndex > max_ports)
1281 temp = readl(ports[wIndex]->addr);
1282 if (temp == ~(u32)0) {
1287 temp = xhci_port_state_to_neutral(temp);
1288 /* FIXME: What new port features do we need to support? */
1290 case USB_PORT_FEAT_SUSPEND:
1291 temp = readl(ports[wIndex]->addr);
1292 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1293 /* Resume the port to U0 first */
1294 xhci_set_link_state(xhci, ports[wIndex],
1296 spin_unlock_irqrestore(&xhci->lock, flags);
1298 spin_lock_irqsave(&xhci->lock, flags);
1300 /* In spec software should not attempt to suspend
1301 * a port unless the port reports that it is in the
1302 * enabled (PED = ‘1’,PLS < ‘3’) state.
1304 temp = readl(ports[wIndex]->addr);
1305 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1306 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1307 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1308 hcd->self.busnum, wIndex + 1);
1312 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1315 xhci_warn(xhci, "slot_id is zero\n");
1318 /* unlock to execute stop endpoint commands */
1319 spin_unlock_irqrestore(&xhci->lock, flags);
1320 xhci_stop_device(xhci, slot_id, 1);
1321 spin_lock_irqsave(&xhci->lock, flags);
1323 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1325 spin_unlock_irqrestore(&xhci->lock, flags);
1326 msleep(10); /* wait device to enter */
1327 spin_lock_irqsave(&xhci->lock, flags);
1329 temp = readl(ports[wIndex]->addr);
1330 bus_state->suspended_ports |= 1 << wIndex;
1332 case USB_PORT_FEAT_LINK_STATE:
1333 temp = readl(ports[wIndex]->addr);
1335 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1336 xhci_dbg(xhci, "Disable port %d-%d\n",
1337 hcd->self.busnum, wIndex + 1);
1338 temp = xhci_port_state_to_neutral(temp);
1340 * Clear all change bits, so that we get a new
1343 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1344 PORT_OCC | PORT_RC | PORT_PLC |
1346 writel(temp | PORT_PE, ports[wIndex]->addr);
1347 temp = readl(ports[wIndex]->addr);
1351 /* Put link in RxDetect (enable port) */
1352 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1353 xhci_dbg(xhci, "Enable port %d-%d\n",
1354 hcd->self.busnum, wIndex + 1);
1355 xhci_set_link_state(xhci, ports[wIndex],
1357 temp = readl(ports[wIndex]->addr);
1362 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1363 * root hub port's transition to compliance mode upon
1364 * detecting LFPS timeout may be controlled by an
1365 * Compliance Transition Enabled (CTE) flag (not
1366 * software visible). This flag is set by writing 0xA
1367 * to PORTSC PLS field which will allow transition to
1368 * compliance mode the next time LFPS timeout is
1369 * encountered. A warm reset will clear it.
1371 * The CTE flag is only supported if the HCCPARAMS2 CTC
1372 * flag is set, otherwise, the compliance substate is
1373 * automatically entered as on 1.0 and prior.
1375 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1376 if (!HCC2_CTC(xhci->hcc_params2)) {
1377 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1381 if ((temp & PORT_CONNECT)) {
1382 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1386 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1387 hcd->self.busnum, wIndex + 1);
1388 xhci_set_link_state(xhci, ports[wIndex],
1391 temp = readl(ports[wIndex]->addr);
1394 /* Port must be enabled */
1395 if (!(temp & PORT_PE)) {
1399 /* Can't set port link state above '3' (U3) */
1400 if (link_state > USB_SS_PORT_LS_U3) {
1401 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1402 hcd->self.busnum, wIndex + 1,
1408 * set link to U0, steps depend on current link state.
1409 * U3: set link to U0 and wait for u3exit completion.
1410 * U1/U2: no PLC complete event, only set link to U0.
1411 * Resume/Recovery: device initiated U0, only wait for
1414 if (link_state == USB_SS_PORT_LS_U0) {
1415 u32 pls = temp & PORT_PLS_MASK;
1416 bool wait_u0 = false;
1421 if (pls == XDEV_U3 ||
1422 pls == XDEV_RESUME ||
1423 pls == XDEV_RECOVERY) {
1425 reinit_completion(&bus_state->u3exit_done[wIndex]);
1427 if (pls <= XDEV_U3) /* U1, U2, U3 */
1428 xhci_set_link_state(xhci, ports[wIndex],
1435 spin_unlock_irqrestore(&xhci->lock, flags);
1436 if (!wait_for_completion_timeout(&bus_state->u3exit_done[wIndex],
1437 msecs_to_jiffies(100)))
1438 xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1439 hcd->self.busnum, wIndex + 1);
1440 spin_lock_irqsave(&xhci->lock, flags);
1441 temp = readl(ports[wIndex]->addr);
1445 if (link_state == USB_SS_PORT_LS_U3) {
1447 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1450 /* unlock to execute stop endpoint
1452 spin_unlock_irqrestore(&xhci->lock,
1454 xhci_stop_device(xhci, slot_id, 1);
1455 spin_lock_irqsave(&xhci->lock, flags);
1457 xhci_set_link_state(xhci, ports[wIndex], USB_SS_PORT_LS_U3);
1458 spin_unlock_irqrestore(&xhci->lock, flags);
1460 usleep_range(4000, 8000);
1461 temp = readl(ports[wIndex]->addr);
1462 if ((temp & PORT_PLS_MASK) == XDEV_U3)
1465 spin_lock_irqsave(&xhci->lock, flags);
1466 temp = readl(ports[wIndex]->addr);
1467 bus_state->suspended_ports |= 1 << wIndex;
1470 case USB_PORT_FEAT_POWER:
1472 * Turn on ports, even if there isn't per-port switching.
1473 * HC will report connect events even before this is set.
1474 * However, hub_wq will ignore the roothub events until
1475 * the roothub is registered.
1477 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1479 case USB_PORT_FEAT_RESET:
1480 temp = (temp | PORT_RESET);
1481 writel(temp, ports[wIndex]->addr);
1483 temp = readl(ports[wIndex]->addr);
1484 xhci_dbg(xhci, "set port reset, actual port %d-%d status = 0x%x\n",
1485 hcd->self.busnum, wIndex + 1, temp);
1487 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1488 xhci_set_remote_wake_mask(xhci, ports[wIndex],
1490 temp = readl(ports[wIndex]->addr);
1491 xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status = 0x%x\n",
1492 hcd->self.busnum, wIndex + 1, temp);
1494 case USB_PORT_FEAT_BH_PORT_RESET:
1496 writel(temp, ports[wIndex]->addr);
1497 temp = readl(ports[wIndex]->addr);
1499 case USB_PORT_FEAT_U1_TIMEOUT:
1500 if (hcd->speed < HCD_USB3)
1502 temp = readl(ports[wIndex]->addr + PORTPMSC);
1503 temp &= ~PORT_U1_TIMEOUT_MASK;
1504 temp |= PORT_U1_TIMEOUT(timeout);
1505 writel(temp, ports[wIndex]->addr + PORTPMSC);
1507 case USB_PORT_FEAT_U2_TIMEOUT:
1508 if (hcd->speed < HCD_USB3)
1510 temp = readl(ports[wIndex]->addr + PORTPMSC);
1511 temp &= ~PORT_U2_TIMEOUT_MASK;
1512 temp |= PORT_U2_TIMEOUT(timeout);
1513 writel(temp, ports[wIndex]->addr + PORTPMSC);
1515 case USB_PORT_FEAT_TEST:
1516 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1517 if (hcd->speed != HCD_USB2)
1519 if (test_mode > USB_TEST_FORCE_ENABLE ||
1520 test_mode < USB_TEST_J)
1522 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1528 /* unblock any posted writes */
1529 temp = readl(ports[wIndex]->addr);
1531 case ClearPortFeature:
1532 if (!wIndex || wIndex > max_ports)
1535 temp = readl(ports[wIndex]->addr);
1536 if (temp == ~(u32)0) {
1541 /* FIXME: What new port features do we need to support? */
1542 temp = xhci_port_state_to_neutral(temp);
1544 case USB_PORT_FEAT_SUSPEND:
1545 temp = readl(ports[wIndex]->addr);
1546 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1547 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1548 if (temp & PORT_RESET)
1550 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1551 if ((temp & PORT_PE) == 0)
1554 set_bit(wIndex, &bus_state->resuming_ports);
1555 usb_hcd_start_port_resume(&hcd->self, wIndex);
1556 xhci_set_link_state(xhci, ports[wIndex],
1558 spin_unlock_irqrestore(&xhci->lock, flags);
1559 msleep(USB_RESUME_TIMEOUT);
1560 spin_lock_irqsave(&xhci->lock, flags);
1561 xhci_set_link_state(xhci, ports[wIndex],
1563 clear_bit(wIndex, &bus_state->resuming_ports);
1564 usb_hcd_end_port_resume(&hcd->self, wIndex);
1566 bus_state->port_c_suspend |= 1 << wIndex;
1568 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1571 xhci_dbg(xhci, "slot_id is zero\n");
1574 xhci_ring_device(xhci, slot_id);
1576 case USB_PORT_FEAT_C_SUSPEND:
1577 bus_state->port_c_suspend &= ~(1 << wIndex);
1579 case USB_PORT_FEAT_C_RESET:
1580 case USB_PORT_FEAT_C_BH_PORT_RESET:
1581 case USB_PORT_FEAT_C_CONNECTION:
1582 case USB_PORT_FEAT_C_OVER_CURRENT:
1583 case USB_PORT_FEAT_C_ENABLE:
1584 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1585 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1586 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1587 ports[wIndex]->addr, temp);
1589 case USB_PORT_FEAT_ENABLE:
1590 xhci_disable_port(hcd, xhci, wIndex,
1591 ports[wIndex]->addr, temp);
1593 case USB_PORT_FEAT_POWER:
1594 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1596 case USB_PORT_FEAT_TEST:
1597 retval = xhci_exit_test_mode(xhci);
1605 /* "stall" on error */
1608 spin_unlock_irqrestore(&xhci->lock, flags);
1613 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1614 * Ports are 0-indexed from the HCD point of view,
1615 * and 1-indexed from the USB core pointer of view.
1617 * Note that the status change bits will be cleared as soon as a port status
1618 * change event is generated, so we use the saved status from that event.
1620 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1622 unsigned long flags;
1626 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1628 struct xhci_bus_state *bus_state;
1629 bool reset_change = false;
1630 struct xhci_hub *rhub;
1631 struct xhci_port **ports;
1633 rhub = xhci_get_rhub(hcd);
1634 ports = rhub->ports;
1635 max_ports = rhub->num_ports;
1636 bus_state = &rhub->bus_state;
1638 /* Initial status is no changes */
1639 retval = (max_ports + 8) / 8;
1640 memset(buf, 0, retval);
1643 * Inform the usbcore about resume-in-progress by returning
1644 * a non-zero value even if there are no status changes.
1646 spin_lock_irqsave(&xhci->lock, flags);
1648 status = bus_state->resuming_ports;
1650 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1652 /* For each port, did anything change? If so, set that bit in buf. */
1653 for (i = 0; i < max_ports; i++) {
1654 temp = readl(ports[i]->addr);
1655 if (temp == ~(u32)0) {
1660 trace_xhci_hub_status_data(i, temp);
1662 if ((temp & mask) != 0 ||
1663 (bus_state->port_c_suspend & 1 << i) ||
1664 (bus_state->resume_done[i] && time_after_eq(
1665 jiffies, bus_state->resume_done[i]))) {
1666 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1669 if ((temp & PORT_RC))
1670 reset_change = true;
1674 if (!status && !reset_change) {
1675 xhci_dbg(xhci, "%s: stopping usb%d port polling\n",
1676 __func__, hcd->self.busnum);
1677 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1679 spin_unlock_irqrestore(&xhci->lock, flags);
1680 return status ? retval : 0;
1685 int xhci_bus_suspend(struct usb_hcd *hcd)
1687 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1688 int max_ports, port_index;
1689 struct xhci_bus_state *bus_state;
1690 unsigned long flags;
1691 struct xhci_hub *rhub;
1692 struct xhci_port **ports;
1693 u32 portsc_buf[USB_MAXCHILDREN];
1696 rhub = xhci_get_rhub(hcd);
1697 ports = rhub->ports;
1698 max_ports = rhub->num_ports;
1699 bus_state = &rhub->bus_state;
1700 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1702 spin_lock_irqsave(&xhci->lock, flags);
1705 if (bus_state->resuming_ports || /* USB2 */
1706 bus_state->port_remote_wakeup) { /* USB3 */
1707 spin_unlock_irqrestore(&xhci->lock, flags);
1708 xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n",
1714 * Prepare ports for suspend, but don't write anything before all ports
1715 * are checked and we know bus suspend can proceed
1717 bus_state->bus_suspended = 0;
1718 port_index = max_ports;
1719 while (port_index--) {
1723 t1 = readl(ports[port_index]->addr);
1724 t2 = xhci_port_state_to_neutral(t1);
1725 portsc_buf[port_index] = 0;
1728 * Give a USB3 port in link training time to finish, but don't
1729 * prevent suspend as port might be stuck
1731 if ((hcd->speed >= HCD_USB3) && retries-- &&
1732 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1733 spin_unlock_irqrestore(&xhci->lock, flags);
1734 msleep(XHCI_PORT_POLLING_LFPS_TIME);
1735 spin_lock_irqsave(&xhci->lock, flags);
1736 xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1737 hcd->self.busnum, port_index + 1);
1740 /* bail out if port detected a over-current condition */
1742 bus_state->bus_suspended = 0;
1743 spin_unlock_irqrestore(&xhci->lock, flags);
1744 xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1747 /* suspend ports in U0, or bail out for new connect changes */
1748 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1749 if ((t1 & PORT_CSC) && wake_enabled) {
1750 bus_state->bus_suspended = 0;
1751 spin_unlock_irqrestore(&xhci->lock, flags);
1752 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1755 xhci_dbg(xhci, "port %d-%d not suspended\n",
1756 hcd->self.busnum, port_index + 1);
1757 t2 &= ~PORT_PLS_MASK;
1758 t2 |= PORT_LINK_STROBE | XDEV_U3;
1759 set_bit(port_index, &bus_state->bus_suspended);
1761 /* USB core sets remote wake mask for USB 3.0 hubs,
1762 * including the USB 3.0 roothub, but only if CONFIG_PM
1763 * is enabled, so also enable remote wake here.
1766 if (t1 & PORT_CONNECT) {
1767 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1768 t2 &= ~PORT_WKCONN_E;
1770 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1771 t2 &= ~PORT_WKDISC_E;
1774 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1775 (hcd->speed < HCD_USB3)) {
1776 if (usb_amd_pt_check_port(hcd->self.controller,
1778 t2 &= ~PORT_WAKE_BITS;
1781 t2 &= ~PORT_WAKE_BITS;
1783 t1 = xhci_port_state_to_neutral(t1);
1785 portsc_buf[port_index] = t2;
1788 /* write port settings, stopping and suspending ports if needed */
1789 port_index = max_ports;
1790 while (port_index--) {
1791 if (!portsc_buf[port_index])
1793 if (test_bit(port_index, &bus_state->bus_suspended)) {
1796 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1799 spin_unlock_irqrestore(&xhci->lock, flags);
1800 xhci_stop_device(xhci, slot_id, 1);
1801 spin_lock_irqsave(&xhci->lock, flags);
1804 writel(portsc_buf[port_index], ports[port_index]->addr);
1806 hcd->state = HC_STATE_SUSPENDED;
1807 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1808 spin_unlock_irqrestore(&xhci->lock, flags);
1810 if (bus_state->bus_suspended)
1811 usleep_range(5000, 10000);
1817 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1818 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1819 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1821 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1825 portsc = readl(port->addr);
1827 /* if any of these are set we are not stuck */
1828 if (portsc & (PORT_CONNECT | PORT_CAS))
1831 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1832 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1835 /* clear wakeup/change bits, and do a warm port reset */
1836 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1838 writel(portsc, port->addr);
1844 int xhci_bus_resume(struct usb_hcd *hcd)
1846 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1847 struct xhci_bus_state *bus_state;
1848 unsigned long flags;
1849 int max_ports, port_index;
1854 struct xhci_hub *rhub;
1855 struct xhci_port **ports;
1857 rhub = xhci_get_rhub(hcd);
1858 ports = rhub->ports;
1859 max_ports = rhub->num_ports;
1860 bus_state = &rhub->bus_state;
1862 if (time_before(jiffies, bus_state->next_statechange))
1865 spin_lock_irqsave(&xhci->lock, flags);
1866 if (!HCD_HW_ACCESSIBLE(hcd)) {
1867 spin_unlock_irqrestore(&xhci->lock, flags);
1871 /* delay the irqs */
1872 temp = readl(&xhci->op_regs->command);
1874 writel(temp, &xhci->op_regs->command);
1876 /* bus specific resume for ports we suspended at bus_suspend */
1877 if (hcd->speed >= HCD_USB3)
1878 next_state = XDEV_U0;
1880 next_state = XDEV_RESUME;
1882 port_index = max_ports;
1883 while (port_index--) {
1884 portsc = readl(ports[port_index]->addr);
1886 /* warm reset CAS limited ports stuck in polling/compliance */
1887 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1888 (hcd->speed >= HCD_USB3) &&
1889 xhci_port_missing_cas_quirk(ports[port_index])) {
1890 xhci_dbg(xhci, "reset stuck port %d-%d\n",
1891 hcd->self.busnum, port_index + 1);
1892 clear_bit(port_index, &bus_state->bus_suspended);
1895 /* resume if we suspended the link, and it is still suspended */
1896 if (test_bit(port_index, &bus_state->bus_suspended))
1897 switch (portsc & PORT_PLS_MASK) {
1899 portsc = xhci_port_state_to_neutral(portsc);
1900 portsc &= ~PORT_PLS_MASK;
1901 portsc |= PORT_LINK_STROBE | next_state;
1904 /* resume already initiated */
1907 /* not in a resumeable state, ignore it */
1908 clear_bit(port_index,
1909 &bus_state->bus_suspended);
1912 /* disable wake for all ports, write new link state if needed */
1913 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1914 writel(portsc, ports[port_index]->addr);
1917 /* USB2 specific resume signaling delay and U0 link state transition */
1918 if (hcd->speed < HCD_USB3) {
1919 if (bus_state->bus_suspended) {
1920 spin_unlock_irqrestore(&xhci->lock, flags);
1921 msleep(USB_RESUME_TIMEOUT);
1922 spin_lock_irqsave(&xhci->lock, flags);
1924 for_each_set_bit(port_index, &bus_state->bus_suspended,
1926 /* Clear PLC to poll it later for U0 transition */
1927 xhci_test_and_clear_bit(xhci, ports[port_index],
1929 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1933 /* poll for U0 link state complete, both USB2 and USB3 */
1934 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1935 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1936 PORT_PLC, 10 * 1000);
1938 xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1939 hcd->self.busnum, port_index + 1);
1942 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1943 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1945 xhci_ring_device(xhci, slot_id);
1947 (void) readl(&xhci->op_regs->command);
1949 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1950 /* re-enable irqs */
1951 temp = readl(&xhci->op_regs->command);
1953 writel(temp, &xhci->op_regs->command);
1954 temp = readl(&xhci->op_regs->command);
1956 spin_unlock_irqrestore(&xhci->lock, flags);
1960 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1962 struct xhci_hub *rhub = xhci_get_rhub(hcd);
1964 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1965 return rhub->bus_state.resuming_ports; /* USB2 ports only */
1968 #endif /* CONFIG_PM */