2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/pci.h>
14 #include <linux/delay.h>
15 #include <linux/export.h>
16 #include <linux/acpi.h>
17 #include <linux/dmi.h>
18 #include "pci-quirks.h"
19 #include "xhci-ext-caps.h"
22 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
23 #define UHCI_USBCMD 0 /* command register */
24 #define UHCI_USBINTR 4 /* interrupt register */
25 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
26 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
27 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
28 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
29 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
30 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
31 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
33 #define OHCI_CONTROL 0x04
34 #define OHCI_CMDSTATUS 0x08
35 #define OHCI_INTRSTATUS 0x0c
36 #define OHCI_INTRENABLE 0x10
37 #define OHCI_INTRDISABLE 0x14
38 #define OHCI_FMINTERVAL 0x34
39 #define OHCI_HCFS (3 << 6) /* hc functional state */
40 #define OHCI_HCR (1 << 0) /* host controller reset */
41 #define OHCI_OCR (1 << 3) /* ownership change request */
42 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
43 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
44 #define OHCI_INTR_OC (1 << 30) /* ownership change */
46 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
47 #define EHCI_USBCMD 0 /* command register */
48 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
49 #define EHCI_USBSTS 4 /* status register */
50 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
51 #define EHCI_USBINTR 8 /* interrupt register */
52 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */
53 #define EHCI_USBLEGSUP 0 /* legacy support register */
54 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
55 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
56 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
57 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
60 #define AB_REG_BAR_LOW 0xe0
61 #define AB_REG_BAR_HIGH 0xe1
62 #define AB_REG_BAR_SB700 0xf0
63 #define AB_INDX(addr) ((addr) + 0x00)
64 #define AB_DATA(addr) ((addr) + 0x04)
68 #define NB_PCIE_INDX_ADDR 0xe0
69 #define NB_PCIE_INDX_DATA 0xe4
70 #define PCIE_P_CNTL 0x10040
71 #define BIF_NB 0x10002
72 #define NB_PIF0_PWRDOWN_0 0x01100012
73 #define NB_PIF0_PWRDOWN_1 0x01100013
75 #define USB_INTEL_XUSB2PR 0xD0
76 #define USB_INTEL_USB2PRM 0xD4
77 #define USB_INTEL_USB3_PSSEN 0xD8
78 #define USB_INTEL_USB3PRM 0xDC
80 /* ASMEDIA quirk use */
81 #define ASMT_DATA_WRITE0_REG 0xF8
82 #define ASMT_DATA_WRITE1_REG 0xFC
83 #define ASMT_CONTROL_REG 0xE0
84 #define ASMT_CONTROL_WRITE_BIT 0x02
85 #define ASMT_WRITEREG_CMD 0x10423
86 #define ASMT_FLOWCTL_ADDR 0xFA30
87 #define ASMT_FLOWCTL_DATA 0xBA
88 #define ASMT_PSEUDO_DATA 0
91 * amd_chipset_gen values represent AMD different chipset generations
93 enum amd_chipset_gen {
105 struct amd_chipset_type {
106 enum amd_chipset_gen gen;
110 static struct amd_chipset_info {
111 struct pci_dev *nb_dev;
112 struct pci_dev *smbus_dev;
114 struct amd_chipset_type sb_type;
120 static DEFINE_SPINLOCK(amd_lock);
123 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
125 * AMD FCH/SB generation and revision is identified by SMBus controller
126 * vendor, device and revision IDs.
128 * Returns: 1 if it is an AMD chipset, 0 otherwise.
130 static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
133 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN;
135 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
136 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
137 if (pinfo->smbus_dev) {
138 rev = pinfo->smbus_dev->revision;
139 if (rev >= 0x10 && rev <= 0x1f)
140 pinfo->sb_type.gen = AMD_CHIPSET_SB600;
141 else if (rev >= 0x30 && rev <= 0x3f)
142 pinfo->sb_type.gen = AMD_CHIPSET_SB700;
143 else if (rev >= 0x40 && rev <= 0x4f)
144 pinfo->sb_type.gen = AMD_CHIPSET_SB800;
146 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
147 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
149 if (pinfo->smbus_dev) {
150 rev = pinfo->smbus_dev->revision;
151 if (rev >= 0x11 && rev <= 0x14)
152 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2;
153 else if (rev >= 0x15 && rev <= 0x18)
154 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON;
155 else if (rev >= 0x39 && rev <= 0x3a)
156 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE;
158 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
160 if (pinfo->smbus_dev) {
161 rev = pinfo->smbus_dev->revision;
162 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN;
164 pinfo->sb_type.gen = NOT_AMD_CHIPSET;
169 pinfo->sb_type.rev = rev;
173 void sb800_prefetch(struct device *dev, int on)
176 struct pci_dev *pdev = to_pci_dev(dev);
178 pci_read_config_word(pdev, 0x50, &misc);
180 pci_write_config_word(pdev, 0x50, misc & 0xfcff);
182 pci_write_config_word(pdev, 0x50, misc | 0x0300);
184 EXPORT_SYMBOL_GPL(sb800_prefetch);
186 int usb_amd_find_chipset_info(void)
189 struct amd_chipset_info info;
190 int need_pll_quirk = 0;
192 spin_lock_irqsave(&amd_lock, flags);
194 /* probe only once */
195 if (amd_chipset.probe_count > 0) {
196 amd_chipset.probe_count++;
197 spin_unlock_irqrestore(&amd_lock, flags);
198 return amd_chipset.probe_result;
200 memset(&info, 0, sizeof(info));
201 spin_unlock_irqrestore(&amd_lock, flags);
203 if (!amd_chipset_sb_type_init(&info)) {
207 switch (info.sb_type.gen) {
208 case AMD_CHIPSET_SB700:
209 need_pll_quirk = info.sb_type.rev <= 0x3B;
211 case AMD_CHIPSET_SB800:
212 case AMD_CHIPSET_HUDSON2:
213 case AMD_CHIPSET_BOLTON:
221 if (!need_pll_quirk) {
222 if (info.smbus_dev) {
223 pci_dev_put(info.smbus_dev);
224 info.smbus_dev = NULL;
229 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
233 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
237 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
244 need_pll_quirk = info.probe_result = 1;
245 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
249 spin_lock_irqsave(&amd_lock, flags);
250 if (amd_chipset.probe_count > 0) {
251 /* race - someone else was faster - drop devices */
253 /* Mark that we where here */
254 amd_chipset.probe_count++;
255 need_pll_quirk = amd_chipset.probe_result;
257 spin_unlock_irqrestore(&amd_lock, flags);
259 pci_dev_put(info.nb_dev);
260 pci_dev_put(info.smbus_dev);
263 /* no race - commit the result */
266 spin_unlock_irqrestore(&amd_lock, flags);
269 return need_pll_quirk;
271 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
273 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
275 /* Make sure amd chipset type has already been initialized */
276 usb_amd_find_chipset_info();
277 if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE ||
278 amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) {
279 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
284 EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
286 bool usb_amd_hang_symptom_quirk(void)
290 usb_amd_find_chipset_info();
291 rev = amd_chipset.sb_type.rev;
292 /* SB600 and old version of SB700 have hang symptom bug */
293 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 ||
294 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
295 rev >= 0x3a && rev <= 0x3b);
297 EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk);
299 bool usb_amd_prefetch_quirk(void)
301 usb_amd_find_chipset_info();
302 /* SB800 needs pre-fetch fix */
303 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800;
305 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk);
308 * The hardware normally enables the A-link power management feature, which
309 * lets the system lower the power consumption in idle states.
311 * This USB quirk prevents the link going into that lower power state
312 * during isochronous transfers.
314 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
315 * some AMD platforms may stutter or have breaks occasionally.
317 static void usb_amd_quirk_pll(int disable)
319 u32 addr, addr_low, addr_high, val;
320 u32 bit = disable ? 0 : 1;
323 spin_lock_irqsave(&amd_lock, flags);
326 amd_chipset.isoc_reqs++;
327 if (amd_chipset.isoc_reqs > 1) {
328 spin_unlock_irqrestore(&amd_lock, flags);
332 amd_chipset.isoc_reqs--;
333 if (amd_chipset.isoc_reqs > 0) {
334 spin_unlock_irqrestore(&amd_lock, flags);
339 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 ||
340 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 ||
341 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) {
342 outb_p(AB_REG_BAR_LOW, 0xcd6);
343 addr_low = inb_p(0xcd7);
344 outb_p(AB_REG_BAR_HIGH, 0xcd6);
345 addr_high = inb_p(0xcd7);
346 addr = addr_high << 8 | addr_low;
348 outl_p(0x30, AB_INDX(addr));
349 outl_p(0x40, AB_DATA(addr));
350 outl_p(0x34, AB_INDX(addr));
351 val = inl_p(AB_DATA(addr));
352 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
353 amd_chipset.sb_type.rev <= 0x3b) {
354 pci_read_config_dword(amd_chipset.smbus_dev,
355 AB_REG_BAR_SB700, &addr);
356 outl(AX_INDXC, AB_INDX(addr));
357 outl(0x40, AB_DATA(addr));
358 outl(AX_DATAC, AB_INDX(addr));
359 val = inl(AB_DATA(addr));
361 spin_unlock_irqrestore(&amd_lock, flags);
367 val |= (1 << 4) | (1 << 9);
370 val &= ~((1 << 4) | (1 << 9));
372 outl_p(val, AB_DATA(addr));
374 if (!amd_chipset.nb_dev) {
375 spin_unlock_irqrestore(&amd_lock, flags);
379 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
381 pci_write_config_dword(amd_chipset.nb_dev,
382 NB_PCIE_INDX_ADDR, addr);
383 pci_read_config_dword(amd_chipset.nb_dev,
384 NB_PCIE_INDX_DATA, &val);
386 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
387 val |= bit | (bit << 3) | (bit << 12);
388 val |= ((!bit) << 4) | ((!bit) << 9);
389 pci_write_config_dword(amd_chipset.nb_dev,
390 NB_PCIE_INDX_DATA, val);
393 pci_write_config_dword(amd_chipset.nb_dev,
394 NB_PCIE_INDX_ADDR, addr);
395 pci_read_config_dword(amd_chipset.nb_dev,
396 NB_PCIE_INDX_DATA, &val);
400 pci_write_config_dword(amd_chipset.nb_dev,
401 NB_PCIE_INDX_DATA, val);
402 } else if (amd_chipset.nb_type == 2) {
403 addr = NB_PIF0_PWRDOWN_0;
404 pci_write_config_dword(amd_chipset.nb_dev,
405 NB_PCIE_INDX_ADDR, addr);
406 pci_read_config_dword(amd_chipset.nb_dev,
407 NB_PCIE_INDX_DATA, &val);
413 pci_write_config_dword(amd_chipset.nb_dev,
414 NB_PCIE_INDX_DATA, val);
416 addr = NB_PIF0_PWRDOWN_1;
417 pci_write_config_dword(amd_chipset.nb_dev,
418 NB_PCIE_INDX_ADDR, addr);
419 pci_read_config_dword(amd_chipset.nb_dev,
420 NB_PCIE_INDX_DATA, &val);
426 pci_write_config_dword(amd_chipset.nb_dev,
427 NB_PCIE_INDX_DATA, val);
430 spin_unlock_irqrestore(&amd_lock, flags);
434 void usb_amd_quirk_pll_disable(void)
436 usb_amd_quirk_pll(1);
438 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
440 static int usb_asmedia_wait_write(struct pci_dev *pdev)
442 unsigned long retry_count;
445 for (retry_count = 1000; retry_count > 0; --retry_count) {
447 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
450 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
454 if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
460 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
464 void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
466 if (usb_asmedia_wait_write(pdev) != 0)
469 /* send command and address to device */
470 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
471 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
472 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
474 if (usb_asmedia_wait_write(pdev) != 0)
477 /* send data to device */
478 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
479 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
480 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
482 EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
484 void usb_amd_quirk_pll_enable(void)
486 usb_amd_quirk_pll(0);
488 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
490 void usb_amd_dev_put(void)
492 struct pci_dev *nb, *smbus;
495 spin_lock_irqsave(&amd_lock, flags);
497 amd_chipset.probe_count--;
498 if (amd_chipset.probe_count > 0) {
499 spin_unlock_irqrestore(&amd_lock, flags);
503 /* save them to pci_dev_put outside of spinlock */
504 nb = amd_chipset.nb_dev;
505 smbus = amd_chipset.smbus_dev;
507 amd_chipset.nb_dev = NULL;
508 amd_chipset.smbus_dev = NULL;
509 amd_chipset.nb_type = 0;
510 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
511 amd_chipset.isoc_reqs = 0;
512 amd_chipset.probe_result = 0;
514 spin_unlock_irqrestore(&amd_lock, flags);
519 EXPORT_SYMBOL_GPL(usb_amd_dev_put);
522 * Make sure the controller is completely inactive, unable to
523 * generate interrupts or do DMA.
525 void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
527 /* Turn off PIRQ enable and SMI enable. (This also turns off the
528 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
530 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
532 /* Reset the HC - this will force us to get a
533 * new notification of any already connected
534 * ports due to the virtual disconnect that it
537 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
540 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
541 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
543 /* Just to be safe, disable interrupt requests and
544 * make sure the controller is stopped.
546 outw(0, base + UHCI_USBINTR);
547 outw(0, base + UHCI_USBCMD);
549 EXPORT_SYMBOL_GPL(uhci_reset_hc);
552 * Initialize a controller that was newly discovered or has just been
553 * resumed. In either case we can't be sure of its previous state.
555 * Returns: 1 if the controller was reset, 0 otherwise.
557 int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
560 unsigned int cmd, intr;
563 * When restarting a suspended controller, we expect all the
564 * settings to be the same as we left them:
566 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
567 * Controller is stopped and configured with EGSM set;
568 * No interrupts enabled except possibly Resume Detect.
570 * If any of these conditions are violated we do a complete reset.
572 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
573 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
574 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
579 cmd = inw(base + UHCI_USBCMD);
580 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
581 !(cmd & UHCI_USBCMD_EGSM)) {
582 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
587 intr = inw(base + UHCI_USBINTR);
588 if (intr & (~UHCI_USBINTR_RESUME)) {
589 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
596 dev_dbg(&pdev->dev, "Performing full reset\n");
597 uhci_reset_hc(pdev, base);
600 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
602 static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
605 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
608 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
609 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
611 static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
613 unsigned long base = 0;
616 if (!pio_enabled(pdev))
619 for (i = 0; i < PCI_ROM_RESOURCE; i++)
620 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
621 base = pci_resource_start(pdev, i);
626 uhci_check_and_reset_hc(pdev, base);
629 static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
631 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
634 static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
639 bool no_fminterval = false;
642 if (!mmio_resource_enabled(pdev, 0))
645 base = pci_ioremap_bar(pdev, 0);
650 * ULi M5237 OHCI controller locks the whole system when accessing
651 * the OHCI_FMINTERVAL offset.
653 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)
654 no_fminterval = true;
656 control = readl(base + OHCI_CONTROL);
658 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
660 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
662 #define OHCI_CTRL_MASK OHCI_CTRL_RWC
664 if (control & OHCI_CTRL_IR) {
665 int wait_time = 500; /* arbitrary; 5 seconds */
666 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
667 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
668 while (wait_time > 0 &&
669 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
675 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n",
676 readl(base + OHCI_CONTROL));
680 /* disable interrupts */
681 writel((u32) ~0, base + OHCI_INTRDISABLE);
683 /* Reset the USB bus, if the controller isn't already in RESET */
684 if (control & OHCI_HCFS) {
685 /* Go into RESET, preserving RWC (and possibly IR) */
686 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
687 readl(base + OHCI_CONTROL);
689 /* drive bus reset for at least 50 ms (7.1.7.5) */
693 /* software reset of the controller, preserving HcFmInterval */
695 fminterval = readl(base + OHCI_FMINTERVAL);
697 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
699 /* reset requires max 10 us delay */
700 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
701 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
707 writel(fminterval, base + OHCI_FMINTERVAL);
709 /* Now the controller is safely in SUSPEND and nothing can wake it up */
713 static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
715 /* Pegatron Lucid (ExoPC) */
717 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
718 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
722 /* Pegatron Lucid (Ordissimo AIRIS) */
724 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
725 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
729 /* Pegatron Lucid (Ordissimo) */
731 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
732 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
738 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"),
739 DMI_MATCH(DMI_BOARD_NAME, "E210"),
740 DMI_MATCH(DMI_BIOS_VERSION, "6.00"),
746 static void ehci_bios_handoff(struct pci_dev *pdev,
747 void __iomem *op_reg_base,
750 int try_handoff = 1, tried_handoff = 0;
753 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying
754 * the handoff on its unused controller. Skip it.
756 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021).
758 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a ||
759 pdev->device == 0x27cc)) {
760 if (dmi_check_system(ehci_dmi_nohandoff_table))
764 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
765 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
768 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
769 * but that seems dubious in general (the BIOS left it off intentionally)
770 * and is known to prevent some systems from booting. so we won't do this
771 * unless maybe we can determine when we're on a system that needs SMI forced.
773 /* BIOS workaround (?): be sure the pre-Linux code
776 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
777 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
778 val | EHCI_USBLEGCTLSTS_SOOE);
781 /* some systems get upset if this semaphore is
782 * set for any other reason than forcing a BIOS
785 pci_write_config_byte(pdev, offset + 3, 1);
788 /* if boot firmware now owns EHCI, spin till it hands it over. */
791 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
795 pci_read_config_dword(pdev, offset, &cap);
799 if (cap & EHCI_USBLEGSUP_BIOS) {
800 /* well, possibly buggy BIOS... try to shut it down,
801 * and hope nothing goes too wrong
805 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n",
807 pci_write_config_byte(pdev, offset + 2, 0);
810 /* just in case, always disable EHCI SMIs */
811 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
813 /* If the BIOS ever owned the controller then we can't expect
814 * any power sessions to remain intact.
817 writel(0, op_reg_base + EHCI_CONFIGFLAG);
820 static void quirk_usb_disable_ehci(struct pci_dev *pdev)
822 void __iomem *base, *op_reg_base;
823 u32 hcc_params, cap, val;
824 u8 offset, cap_length;
825 int wait_time, count = 256/4;
827 if (!mmio_resource_enabled(pdev, 0))
830 base = pci_ioremap_bar(pdev, 0);
834 cap_length = readb(base);
835 op_reg_base = base + cap_length;
837 /* EHCI 0.96 and later may have "extended capabilities"
838 * spec section 5.1 explains the bios handoff, e.g. for
839 * booting from USB disk or using a usb keyboard
841 hcc_params = readl(base + EHCI_HCC_PARAMS);
842 offset = (hcc_params >> 8) & 0xff;
843 while (offset && --count) {
844 pci_read_config_dword(pdev, offset, &cap);
846 switch (cap & 0xff) {
848 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
850 case 0: /* Illegal reserved cap, set cap=0 so we exit */
851 cap = 0; /* then fallthrough... */
854 "EHCI: unrecognized capability %02x\n",
857 offset = (cap >> 8) & 0xff;
860 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
863 * halt EHCI & disable its interrupts in any case
865 val = readl(op_reg_base + EHCI_USBSTS);
866 if ((val & EHCI_USBSTS_HALTED) == 0) {
867 val = readl(op_reg_base + EHCI_USBCMD);
868 val &= ~EHCI_USBCMD_RUN;
869 writel(val, op_reg_base + EHCI_USBCMD);
873 writel(0x3f, op_reg_base + EHCI_USBSTS);
876 val = readl(op_reg_base + EHCI_USBSTS);
877 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
880 } while (wait_time > 0);
882 writel(0, op_reg_base + EHCI_USBINTR);
883 writel(0x3f, op_reg_base + EHCI_USBSTS);
889 * handshake - spin reading a register until handshake completes
890 * @ptr: address of hc register to be read
891 * @mask: bits to look at in result of read
892 * @done: value of those bits when handshake succeeds
893 * @wait_usec: timeout in microseconds
894 * @delay_usec: delay in microseconds to wait between polling
896 * Polls a register every delay_usec microseconds.
897 * Returns 0 when the mask bits have the value done.
898 * Returns -ETIMEDOUT if this condition is not true after
899 * wait_usec microseconds have passed.
901 static int handshake(void __iomem *ptr, u32 mask, u32 done,
902 int wait_usec, int delay_usec)
912 wait_usec -= delay_usec;
913 } while (wait_usec > 0);
918 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
919 * share some number of ports. These ports can be switched between either
920 * controller. Not all of the ports under the EHCI host controller may be
923 * The ports should be switched over to xHCI before PCI probes for any device
924 * start. This avoids active devices under EHCI being disconnected during the
925 * port switchover, which could cause loss of data on USB storage devices, or
926 * failed boot when the root file system is on a USB mass storage device and is
927 * enumerated under EHCI first.
929 * We write into the xHC's PCI configuration space in some Intel-specific
930 * registers to switch the ports over. The USB 3.0 terminations and the USB
931 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
932 * terminations before switching the USB 2.0 wires over, so that USB 3.0
933 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
935 void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
938 bool ehci_found = false;
939 struct pci_dev *companion = NULL;
941 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of
942 * switching ports from EHCI to xHCI
944 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY &&
945 xhci_pdev->subsystem_device == 0x90a8)
948 /* make sure an intel EHCI controller exists */
949 for_each_pci_dev(companion) {
950 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
951 companion->vendor == PCI_VENDOR_ID_INTEL) {
960 /* Don't switchover the ports if the user hasn't compiled the xHCI
961 * driver. Otherwise they will see "dead" USB ports that don't power
964 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
965 dev_warn(&xhci_pdev->dev,
966 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n");
967 dev_warn(&xhci_pdev->dev,
968 "USB 3.0 devices will work at USB 2.0 speeds.\n");
969 usb_disable_xhci_ports(xhci_pdev);
973 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
974 * Indicate the ports that can be changed from OS.
976 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
979 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
982 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
983 * Register, to turn on SuperSpeed terminations for the
986 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
989 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
991 dev_dbg(&xhci_pdev->dev,
992 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n",
995 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
996 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
999 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
1002 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
1005 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
1006 * switch the USB 2.0 power and data lines over to the xHCI
1009 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1012 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1014 dev_dbg(&xhci_pdev->dev,
1015 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n",
1018 EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
1020 void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
1022 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
1023 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
1025 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
1028 * PCI Quirks for xHCI.
1030 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
1031 * It signals to the BIOS that the OS wants control of the host controller,
1032 * and then waits 1 second for the BIOS to hand over control.
1033 * If we timeout, assume the BIOS is broken and take control anyway.
1035 static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
1039 void __iomem *op_reg_base;
1042 int len = pci_resource_len(pdev, 0);
1044 if (!mmio_resource_enabled(pdev, 0))
1047 base = ioremap_nocache(pci_resource_start(pdev, 0), len);
1052 * Find the Legacy Support Capability register -
1053 * this is optional for xHCI host controllers.
1055 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY);
1057 if (!ext_cap_offset)
1060 if ((ext_cap_offset + sizeof(val)) > len) {
1061 /* We're reading garbage from the controller */
1062 dev_warn(&pdev->dev, "xHCI controller failing to respond");
1065 val = readl(base + ext_cap_offset);
1067 /* Auto handoff never worked for these devices. Force it and continue */
1068 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ||
1069 (pdev->vendor == PCI_VENDOR_ID_RENESAS
1070 && pdev->device == 0x0014)) {
1071 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED;
1072 writel(val, base + ext_cap_offset);
1075 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
1076 if (val & XHCI_HC_BIOS_OWNED) {
1077 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
1079 /* Wait for 1 second with 10 microsecond polling interval */
1080 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
1083 /* Assume a buggy BIOS and take HC ownership anyway */
1085 dev_warn(&pdev->dev,
1086 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n",
1088 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
1092 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1093 /* Mask off (turn off) any enabled SMIs */
1094 val &= XHCI_LEGACY_DISABLE_SMI;
1095 /* Mask all SMI events bits, RW1C */
1096 val |= XHCI_LEGACY_SMI_EVENTS;
1097 /* Disable any BIOS SMIs and clear all SMI events*/
1098 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1101 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
1102 usb_enable_intel_xhci_ports(pdev);
1104 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
1106 /* Wait for the host controller to be ready before writing any
1107 * operational or runtime registers. Wait 5 seconds and no more.
1109 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
1111 /* Assume a buggy HC and start HC initialization anyway */
1113 val = readl(op_reg_base + XHCI_STS_OFFSET);
1114 dev_warn(&pdev->dev,
1115 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",
1119 /* Send the halt and disable interrupts command */
1120 val = readl(op_reg_base + XHCI_CMD_OFFSET);
1121 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
1122 writel(val, op_reg_base + XHCI_CMD_OFFSET);
1124 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
1125 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
1126 XHCI_MAX_HALT_USEC, 125);
1128 val = readl(op_reg_base + XHCI_STS_OFFSET);
1129 dev_warn(&pdev->dev,
1130 "xHCI HW did not halt within %d usec status = 0x%x\n",
1131 XHCI_MAX_HALT_USEC, val);
1138 static void quirk_usb_early_handoff(struct pci_dev *pdev)
1140 /* Skip Netlogic mips SoC's internal PCI USB controller.
1141 * This device does not need/support EHCI/OHCI handoff
1143 if (pdev->vendor == 0x184e) /* vendor Netlogic */
1145 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
1146 pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
1147 pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
1148 pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
1151 if (pci_enable_device(pdev) < 0) {
1152 dev_warn(&pdev->dev,
1153 "Can't enable PCI device, BIOS handoff failed.\n");
1156 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
1157 quirk_usb_handoff_uhci(pdev);
1158 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
1159 quirk_usb_handoff_ohci(pdev);
1160 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
1161 quirk_usb_disable_ehci(pdev);
1162 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
1163 quirk_usb_handoff_xhci(pdev);
1164 pci_disable_device(pdev);
1166 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1167 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);