1 // SPDX-License-Identifier: GPL-2.0
3 * OHCI HCD(Host Controller Driver) for USB.
5 *(C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6 *(C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 *(C) Copyright 2002 Hewlett-Packard Company
9 * Bus glue for Toshiba Mobile IO(TMIO) Controller's OHCI core
10 * (C) Copyright 2005 Chris Humbert <mahadri-usb@drigon.com>
11 * (C) Copyright 2007, 2008 Dmitry Baryshkov <dbaryshkov@gmail.com>
13 * This is known to work with the following variants:
14 * TC6393XB revision 3 (32kB SRAM)
16 * The TMIO's OHCI core DMAs through a small internal buffer that
17 * is directly addressable by the CPU.
19 * Written from sparse documentation from Toshiba and Sharp's driver
21 * usb-ohci-tc6393.c(C) Copyright 2004 Lineo Solutions, Inc.
24 #include <linux/platform_device.h>
25 #include <linux/mfd/core.h>
26 #include <linux/mfd/tmio.h>
27 #include <linux/dma-mapping.h>
29 /*-------------------------------------------------------------------------*/
32 * USB Host Controller Configuration Register
34 #define CCR_REVID 0x08 /* b Revision ID */
35 #define CCR_BASE 0x10 /* l USB Control Register Base Address Low */
36 #define CCR_ILME 0x40 /* b Internal Local Memory Enable */
37 #define CCR_PM 0x4c /* w Power Management */
38 #define CCR_INTC 0x50 /* b INT Control */
39 #define CCR_LMW1L 0x54 /* w Local Memory Window 1 LMADRS Low */
40 #define CCR_LMW1H 0x56 /* w Local Memory Window 1 LMADRS High */
41 #define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
42 #define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
43 #define CCR_LMW2L 0x5C /* w Local Memory Window 2 LMADRS Low */
44 #define CCR_LMW2H 0x5E /* w Local Memory Window 2 LMADRS High */
45 #define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
46 #define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
47 #define CCR_MISC 0xFC /* b MISC */
49 #define CCR_PM_GKEN 0x0001
50 #define CCR_PM_CKRNEN 0x0002
51 #define CCR_PM_USBPW1 0x0004
52 #define CCR_PM_USBPW2 0x0008
53 #define CCR_PM_USBPW3 0x0010
54 #define CCR_PM_PMEE 0x0100
55 #define CCR_PM_PMES 0x8000
57 /*-------------------------------------------------------------------------*/
61 spinlock_t lock; /* protects RMW cycles */
64 #define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1))
66 /*-------------------------------------------------------------------------*/
68 static void tmio_write_pm(struct platform_device *dev)
70 struct usb_hcd *hcd = platform_get_drvdata(dev);
71 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
75 spin_lock_irqsave(&tmio->lock, flags);
77 pm = CCR_PM_GKEN | CCR_PM_CKRNEN |
78 CCR_PM_PMEE | CCR_PM_PMES;
80 tmio_iowrite16(pm, tmio->ccr + CCR_PM);
81 spin_unlock_irqrestore(&tmio->lock, flags);
84 static void tmio_stop_hc(struct platform_device *dev)
86 struct usb_hcd *hcd = platform_get_drvdata(dev);
87 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
88 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
91 pm = CCR_PM_GKEN | CCR_PM_CKRNEN;
92 switch (ohci->num_ports) {
94 dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ohci->num_ports);
105 tmio_iowrite8(0, tmio->ccr + CCR_INTC);
106 tmio_iowrite8(0, tmio->ccr + CCR_ILME);
107 tmio_iowrite16(0, tmio->ccr + CCR_BASE);
108 tmio_iowrite16(0, tmio->ccr + CCR_BASE + 2);
109 tmio_iowrite16(pm, tmio->ccr + CCR_PM);
112 static void tmio_start_hc(struct platform_device *dev)
114 struct usb_hcd *hcd = platform_get_drvdata(dev);
115 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
116 unsigned long base = hcd->rsrc_start;
119 tmio_iowrite16(base, tmio->ccr + CCR_BASE);
120 tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2);
121 tmio_iowrite8(1, tmio->ccr + CCR_ILME);
122 tmio_iowrite8(2, tmio->ccr + CCR_INTC);
124 dev_info(&dev->dev, "revision %d @ 0x%08llx, irq %d\n",
125 tmio_ioread8(tmio->ccr + CCR_REVID),
126 (u64) hcd->rsrc_start, hcd->irq);
129 static int ohci_tmio_start(struct usb_hcd *hcd)
131 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
134 if ((ret = ohci_init(ohci)) < 0)
137 if ((ret = ohci_run(ohci)) < 0) {
138 dev_err(hcd->self.controller, "can't start %s\n",
147 static const struct hc_driver ohci_tmio_hc_driver = {
148 .description = hcd_name,
149 .product_desc = "TMIO OHCI USB Host Controller",
150 .hcd_priv_size = sizeof(struct ohci_hcd) + sizeof (struct tmio_hcd),
152 /* generic hardware linkage */
154 .flags = HCD_USB11 | HCD_MEMORY,
156 /* basic lifecycle operations */
157 .start = ohci_tmio_start,
159 .shutdown = ohci_shutdown,
161 /* managing i/o requests and associated device resources */
162 .urb_enqueue = ohci_urb_enqueue,
163 .urb_dequeue = ohci_urb_dequeue,
164 .endpoint_disable = ohci_endpoint_disable,
166 /* scheduling support */
167 .get_frame_number = ohci_get_frame,
169 /* root hub support */
170 .hub_status_data = ohci_hub_status_data,
171 .hub_control = ohci_hub_control,
173 .bus_suspend = ohci_bus_suspend,
174 .bus_resume = ohci_bus_resume,
176 .start_port_reset = ohci_start_port_reset,
179 /*-------------------------------------------------------------------------*/
180 static struct platform_driver ohci_hcd_tmio_driver;
182 static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
184 const struct mfd_cell *cell = mfd_get_cell(dev);
185 struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
186 struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1);
187 struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2);
188 int irq = platform_get_irq(dev, 0);
189 struct tmio_hcd *tmio;
190 struct ohci_hcd *ohci;
197 if (!cell || !regs || !config || !sram)
203 hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev_name(&dev->dev));
206 goto err_usb_create_hcd;
209 hcd->rsrc_start = regs->start;
210 hcd->rsrc_len = resource_size(regs);
212 tmio = hcd_to_tmio(hcd);
214 spin_lock_init(&tmio->lock);
216 tmio->ccr = ioremap(config->start, resource_size(config));
219 goto err_ioremap_ccr;
222 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
225 goto err_ioremap_regs;
229 ret = cell->enable(dev);
235 ohci = hcd_to_ohci(hcd);
238 ret = usb_hcd_setup_local_mem(hcd, sram->start, sram->start,
239 resource_size(sram));
243 ret = usb_add_hcd(hcd, irq, 0);
247 device_wakeup_enable(hcd->self.controller);
268 static int ohci_hcd_tmio_drv_remove(struct platform_device *dev)
270 struct usb_hcd *hcd = platform_get_drvdata(dev);
271 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
272 const struct mfd_cell *cell = mfd_get_cell(dev);
286 static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state)
288 const struct mfd_cell *cell = mfd_get_cell(dev);
289 struct usb_hcd *hcd = platform_get_drvdata(dev);
290 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
291 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
296 if (time_before(jiffies, ohci->next_statechange))
298 ohci->next_statechange = jiffies;
300 spin_lock_irqsave(&tmio->lock, flags);
302 misc = tmio_ioread8(tmio->ccr + CCR_MISC);
303 misc |= 1 << 3; /* USSUSP */
304 tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
306 spin_unlock_irqrestore(&tmio->lock, flags);
309 ret = cell->suspend(dev);
316 static int ohci_hcd_tmio_drv_resume(struct platform_device *dev)
318 const struct mfd_cell *cell = mfd_get_cell(dev);
319 struct usb_hcd *hcd = platform_get_drvdata(dev);
320 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
321 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
326 if (time_before(jiffies, ohci->next_statechange))
328 ohci->next_statechange = jiffies;
331 ret = cell->resume(dev);
338 spin_lock_irqsave(&tmio->lock, flags);
340 misc = tmio_ioread8(tmio->ccr + CCR_MISC);
341 misc &= ~(1 << 3); /* USSUSP */
342 tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
344 spin_unlock_irqrestore(&tmio->lock, flags);
346 ohci_resume(hcd, false);
351 #define ohci_hcd_tmio_drv_suspend NULL
352 #define ohci_hcd_tmio_drv_resume NULL
355 static struct platform_driver ohci_hcd_tmio_driver = {
356 .probe = ohci_hcd_tmio_drv_probe,
357 .remove = ohci_hcd_tmio_drv_remove,
358 .shutdown = usb_hcd_platform_shutdown,
359 .suspend = ohci_hcd_tmio_drv_suspend,
360 .resume = ohci_hcd_tmio_drv_resume,