1 // SPDX-License-Identifier: GPL-2.0+
3 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
5 * Copyright (C) 2005-2007 AMD (https://www.amd.com)
6 * Author: Thomas Dahlmann
10 * This file does the core driver implementation for the UDC that is based
11 * on Synopsys device controller IP (different than HS OTG IP) that is either
12 * connected through PCI bus or integrated to SoC platforms.
16 #define UDC_MOD_DESCRIPTION "Synopsys USB Device Controller"
17 #define UDC_DRIVER_VERSION_STRING "01.00.0206"
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/kernel.h>
22 #include <linux/delay.h>
23 #include <linux/ioport.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/timer.h>
28 #include <linux/list.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioctl.h>
32 #include <linux/dmapool.h>
33 #include <linux/prefetch.h>
34 #include <linux/moduleparam.h>
35 #include <asm/byteorder.h>
36 #include <asm/unaligned.h>
37 #include "amd5536udc.h"
39 static void udc_setup_endpoints(struct udc *dev);
40 static void udc_soft_reset(struct udc *dev);
41 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
42 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
45 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
46 static const char name[] = "udc";
48 /* structure to hold endpoint function pointers */
49 static const struct usb_ep_ops udc_ep_ops;
51 /* received setup data */
52 static union udc_setup_data setup_data;
54 /* pointer to device object */
55 static struct udc *udc;
57 /* irq spin lock for soft reset */
58 static DEFINE_SPINLOCK(udc_irq_spinlock);
60 static DEFINE_SPINLOCK(udc_stall_spinlock);
63 * slave mode: pending bytes in rx fifo after nyet,
64 * used if EPIN irq came but no req was available
66 static unsigned int udc_rxfifo_pending;
68 /* count soft resets after suspend to avoid loop */
69 static int soft_reset_occured;
70 static int soft_reset_after_usbreset_occured;
73 static struct timer_list udc_timer;
74 static int stop_timer;
76 /* set_rde -- Is used to control enabling of RX DMA. Problem is
77 * that UDC has only one bit (RDE) to enable/disable RX DMA for
78 * all OUT endpoints. So we have to handle race conditions like
79 * when OUT data reaches the fifo but no request was queued yet.
80 * This cannot be solved by letting the RX DMA disabled until a
81 * request gets queued because there may be other OUT packets
82 * in the FIFO (important for not blocking control traffic).
83 * The value of set_rde controls the corresponding timer.
85 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
86 * set_rde 0 == do not touch RDE, do no start the RDE timer
87 * set_rde 1 == timer function will look whether FIFO has data
88 * set_rde 2 == set by timer function to enable RX DMA on next call
90 static int set_rde = -1;
92 static DECLARE_COMPLETION(on_exit);
93 static struct timer_list udc_pollstall_timer;
94 static int stop_pollstall_timer;
95 static DECLARE_COMPLETION(on_pollstall_exit);
97 /* endpoint names used for print */
98 static const char ep0_string[] = "ep0in";
101 const struct usb_ep_caps caps;
103 #define EP_INFO(_name, _caps) \
110 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_IN)),
112 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
113 EP_INFO("ep2in-bulk",
114 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
115 EP_INFO("ep3in-bulk",
116 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
117 EP_INFO("ep4in-bulk",
118 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
119 EP_INFO("ep5in-bulk",
120 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
121 EP_INFO("ep6in-bulk",
122 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
123 EP_INFO("ep7in-bulk",
124 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
125 EP_INFO("ep8in-bulk",
126 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
127 EP_INFO("ep9in-bulk",
128 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
129 EP_INFO("ep10in-bulk",
130 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
131 EP_INFO("ep11in-bulk",
132 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
133 EP_INFO("ep12in-bulk",
134 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
135 EP_INFO("ep13in-bulk",
136 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
137 EP_INFO("ep14in-bulk",
138 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
139 EP_INFO("ep15in-bulk",
140 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
142 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_OUT)),
143 EP_INFO("ep1out-bulk",
144 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
145 EP_INFO("ep2out-bulk",
146 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
147 EP_INFO("ep3out-bulk",
148 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
149 EP_INFO("ep4out-bulk",
150 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
151 EP_INFO("ep5out-bulk",
152 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
153 EP_INFO("ep6out-bulk",
154 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
155 EP_INFO("ep7out-bulk",
156 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
157 EP_INFO("ep8out-bulk",
158 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
159 EP_INFO("ep9out-bulk",
160 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
161 EP_INFO("ep10out-bulk",
162 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
163 EP_INFO("ep11out-bulk",
164 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
165 EP_INFO("ep12out-bulk",
166 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
167 EP_INFO("ep13out-bulk",
168 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
169 EP_INFO("ep14out-bulk",
170 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
171 EP_INFO("ep15out-bulk",
172 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
177 /* buffer fill mode */
178 static int use_dma_bufferfill_mode;
179 /* tx buffer size for high speed */
180 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
182 /*---------------------------------------------------------------------------*/
183 /* Prints UDC device registers and endpoint irq registers */
184 static void print_regs(struct udc *dev)
186 DBG(dev, "------- Device registers -------\n");
187 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
188 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
189 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
191 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
192 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
194 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
195 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
197 DBG(dev, "USE DMA = %d\n", use_dma);
198 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
199 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
200 "WITHOUT desc. update)\n");
201 dev_info(dev->dev, "DMA mode (%s)\n", "PPBNDU");
202 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
203 DBG(dev, "DMA mode = PPBDU (packet per buffer "
204 "WITH desc. update)\n");
205 dev_info(dev->dev, "DMA mode (%s)\n", "PPBDU");
207 if (use_dma && use_dma_bufferfill_mode) {
208 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
209 dev_info(dev->dev, "DMA mode (%s)\n", "BF");
212 dev_info(dev->dev, "FIFO mode\n");
213 DBG(dev, "-------------------------------------------------------\n");
216 /* Masks unused interrupts */
217 int udc_mask_unused_interrupts(struct udc *dev)
221 /* mask all dev interrupts */
222 tmp = AMD_BIT(UDC_DEVINT_SVC) |
223 AMD_BIT(UDC_DEVINT_ENUM) |
224 AMD_BIT(UDC_DEVINT_US) |
225 AMD_BIT(UDC_DEVINT_UR) |
226 AMD_BIT(UDC_DEVINT_ES) |
227 AMD_BIT(UDC_DEVINT_SI) |
228 AMD_BIT(UDC_DEVINT_SOF)|
229 AMD_BIT(UDC_DEVINT_SC);
230 writel(tmp, &dev->regs->irqmsk);
232 /* mask all ep interrupts */
233 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
237 EXPORT_SYMBOL_GPL(udc_mask_unused_interrupts);
239 /* Enables endpoint 0 interrupts */
240 static int udc_enable_ep0_interrupts(struct udc *dev)
244 DBG(dev, "udc_enable_ep0_interrupts()\n");
247 tmp = readl(&dev->regs->ep_irqmsk);
248 /* enable ep0 irq's */
249 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
250 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
251 writel(tmp, &dev->regs->ep_irqmsk);
256 /* Enables device interrupts for SET_INTF and SET_CONFIG */
257 int udc_enable_dev_setup_interrupts(struct udc *dev)
261 DBG(dev, "enable device interrupts for setup data\n");
264 tmp = readl(&dev->regs->irqmsk);
266 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
267 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
268 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
269 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
270 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
271 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
272 writel(tmp, &dev->regs->irqmsk);
276 EXPORT_SYMBOL_GPL(udc_enable_dev_setup_interrupts);
278 /* Calculates fifo start of endpoint based on preceding endpoints */
279 static int udc_set_txfifo_addr(struct udc_ep *ep)
285 if (!ep || !(ep->in))
289 ep->txfifo = dev->txfifo;
292 for (i = 0; i < ep->num; i++) {
293 if (dev->ep[i].regs) {
295 tmp = readl(&dev->ep[i].regs->bufin_framenum);
296 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
303 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
304 static u32 cnak_pending;
306 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
308 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
309 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
310 cnak_pending |= 1 << (num);
313 cnak_pending = cnak_pending & (~(1 << (num)));
317 /* Enables endpoint, is called by gadget driver */
319 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
324 unsigned long iflags;
329 || usbep->name == ep0_string
331 || desc->bDescriptorType != USB_DT_ENDPOINT)
334 ep = container_of(usbep, struct udc_ep, ep);
337 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
339 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
342 spin_lock_irqsave(&dev->lock, iflags);
347 /* set traffic type */
348 tmp = readl(&dev->ep[ep->num].regs->ctl);
349 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
350 writel(tmp, &dev->ep[ep->num].regs->ctl);
352 /* set max packet size */
353 maxpacket = usb_endpoint_maxp(desc);
354 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
355 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
356 ep->ep.maxpacket = maxpacket;
357 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
362 /* ep ix in UDC CSR register space */
363 udc_csr_epix = ep->num;
365 /* set buffer size (tx fifo entries) */
366 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
367 /* double buffering: fifo size = 2 x max packet size */
370 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
373 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
375 /* calc. tx fifo base addr */
376 udc_set_txfifo_addr(ep);
379 tmp = readl(&ep->regs->ctl);
380 tmp |= AMD_BIT(UDC_EPCTL_F);
381 writel(tmp, &ep->regs->ctl);
385 /* ep ix in UDC CSR register space */
386 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
388 /* set max packet size UDC CSR */
389 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
390 tmp = AMD_ADDBITS(tmp, maxpacket,
392 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
394 if (use_dma && !ep->in) {
395 /* alloc and init BNA dummy request */
396 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
397 ep->bna_occurred = 0;
400 if (ep->num != UDC_EP0OUT_IX)
401 dev->data_ep_enabled = 1;
405 tmp = readl(&dev->csr->ne[udc_csr_epix]);
407 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
409 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
411 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
413 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
415 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
417 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
419 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
421 writel(tmp, &dev->csr->ne[udc_csr_epix]);
424 tmp = readl(&dev->regs->ep_irqmsk);
425 tmp &= AMD_UNMASK_BIT(ep->num);
426 writel(tmp, &dev->regs->ep_irqmsk);
429 * clear NAK by writing CNAK
430 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
432 if (!use_dma || ep->in) {
433 tmp = readl(&ep->regs->ctl);
434 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
435 writel(tmp, &ep->regs->ctl);
437 UDC_QUEUE_CNAK(ep, ep->num);
439 tmp = desc->bEndpointAddress;
440 DBG(dev, "%s enabled\n", usbep->name);
442 spin_unlock_irqrestore(&dev->lock, iflags);
446 /* Resets endpoint */
447 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
451 VDBG(ep->dev, "ep-%d reset\n", ep->num);
453 ep->ep.ops = &udc_ep_ops;
454 INIT_LIST_HEAD(&ep->queue);
456 usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
458 tmp = readl(&ep->regs->ctl);
459 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
460 writel(tmp, &ep->regs->ctl);
463 /* disable interrupt */
464 tmp = readl(®s->ep_irqmsk);
465 tmp |= AMD_BIT(ep->num);
466 writel(tmp, ®s->ep_irqmsk);
469 /* unset P and IN bit of potential former DMA */
470 tmp = readl(&ep->regs->ctl);
471 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
472 writel(tmp, &ep->regs->ctl);
474 tmp = readl(&ep->regs->sts);
475 tmp |= AMD_BIT(UDC_EPSTS_IN);
476 writel(tmp, &ep->regs->sts);
479 tmp = readl(&ep->regs->ctl);
480 tmp |= AMD_BIT(UDC_EPCTL_F);
481 writel(tmp, &ep->regs->ctl);
484 /* reset desc pointer */
485 writel(0, &ep->regs->desptr);
488 /* Disables endpoint, is called by gadget driver */
489 static int udc_ep_disable(struct usb_ep *usbep)
491 struct udc_ep *ep = NULL;
492 unsigned long iflags;
497 ep = container_of(usbep, struct udc_ep, ep);
498 if (usbep->name == ep0_string || !ep->ep.desc)
501 DBG(ep->dev, "Disable ep-%d\n", ep->num);
503 spin_lock_irqsave(&ep->dev->lock, iflags);
504 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
506 ep_init(ep->dev->regs, ep);
507 spin_unlock_irqrestore(&ep->dev->lock, iflags);
512 /* Allocates request packet, called by gadget driver */
513 static struct usb_request *
514 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
516 struct udc_request *req;
517 struct udc_data_dma *dma_desc;
523 ep = container_of(usbep, struct udc_ep, ep);
525 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
526 req = kzalloc(sizeof(struct udc_request), gfp);
530 req->req.dma = DMA_DONT_USE;
531 INIT_LIST_HEAD(&req->queue);
534 /* ep0 in requests are allocated from data pool here */
535 dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
542 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
545 (unsigned long)req->td_phys);
546 /* prevent from using desc. - set HOST BUSY */
547 dma_desc->status = AMD_ADDBITS(dma_desc->status,
548 UDC_DMA_STP_STS_BS_HOST_BUSY,
550 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
551 req->td_data = dma_desc;
552 req->td_data_last = NULL;
559 /* frees pci pool descriptors of a DMA chain */
560 static void udc_free_dma_chain(struct udc *dev, struct udc_request *req)
562 struct udc_data_dma *td = req->td_data;
565 dma_addr_t addr_next = 0x00;
566 dma_addr_t addr = (dma_addr_t)td->next;
568 DBG(dev, "free chain req = %p\n", req);
570 /* do not free first desc., will be done by free for request */
571 for (i = 1; i < req->chain_len; i++) {
572 td = phys_to_virt(addr);
573 addr_next = (dma_addr_t)td->next;
574 dma_pool_free(dev->data_requests, td, addr);
579 /* Frees request packet, called by gadget driver */
581 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
584 struct udc_request *req;
586 if (!usbep || !usbreq)
589 ep = container_of(usbep, struct udc_ep, ep);
590 req = container_of(usbreq, struct udc_request, req);
591 VDBG(ep->dev, "free_req req=%p\n", req);
592 BUG_ON(!list_empty(&req->queue));
594 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
596 /* free dma chain if created */
597 if (req->chain_len > 1)
598 udc_free_dma_chain(ep->dev, req);
600 dma_pool_free(ep->dev->data_requests, req->td_data,
606 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
607 static void udc_init_bna_dummy(struct udc_request *req)
611 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
612 /* set next pointer to itself */
613 req->td_data->next = req->td_phys;
616 = AMD_ADDBITS(req->td_data->status,
617 UDC_DMA_STP_STS_BS_DMA_DONE,
620 pr_debug("bna desc = %p, sts = %08x\n",
621 req->td_data, req->td_data->status);
626 /* Allocate BNA dummy descriptor */
627 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
629 struct udc_request *req = NULL;
630 struct usb_request *_req = NULL;
632 /* alloc the dummy request */
633 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
635 req = container_of(_req, struct udc_request, req);
636 ep->bna_dummy_req = req;
637 udc_init_bna_dummy(req);
642 /* Write data to TX fifo for IN packets */
644 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
650 unsigned remaining = 0;
655 req_buf = req->buf + req->actual;
657 remaining = req->length - req->actual;
659 buf = (u32 *) req_buf;
661 bytes = ep->ep.maxpacket;
662 if (bytes > remaining)
666 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
667 writel(*(buf + i), ep->txfifo);
669 /* remaining bytes must be written by byte access */
670 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
671 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
675 /* dummy write confirm */
676 writel(0, &ep->regs->confirm);
679 /* Read dwords from RX fifo for OUT transfers */
680 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
684 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
686 for (i = 0; i < dwords; i++)
687 *(buf + i) = readl(dev->rxfifo);
691 /* Read bytes from RX fifo for OUT transfers */
692 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
697 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
700 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
701 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
703 /* remaining bytes must be read by byte access */
704 if (bytes % UDC_DWORD_BYTES) {
705 tmp = readl(dev->rxfifo);
706 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
707 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
708 tmp = tmp >> UDC_BITS_PER_BYTE;
715 /* Read data from RX fifo for OUT transfers */
717 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
722 unsigned finished = 0;
724 /* received number bytes */
725 bytes = readl(&ep->regs->sts);
726 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
728 buf_space = req->req.length - req->req.actual;
729 buf = req->req.buf + req->req.actual;
730 if (bytes > buf_space) {
731 if ((buf_space % ep->ep.maxpacket) != 0) {
733 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
734 ep->ep.name, bytes, buf_space);
735 req->req.status = -EOVERFLOW;
739 req->req.actual += bytes;
742 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
743 || ((req->req.actual == req->req.length) && !req->req.zero))
746 /* read rx fifo bytes */
747 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
748 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
753 /* Creates or re-inits a DMA chain */
754 static int udc_create_dma_chain(
756 struct udc_request *req,
757 unsigned long buf_len, gfp_t gfp_flags
760 unsigned long bytes = req->req.length;
763 struct udc_data_dma *td = NULL;
764 struct udc_data_dma *last = NULL;
765 unsigned long txbytes;
766 unsigned create_new_chain = 0;
769 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
771 dma_addr = DMA_DONT_USE;
773 /* unset L bit in first desc for OUT */
775 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
777 /* alloc only new desc's if not already available */
778 len = req->req.length / ep->ep.maxpacket;
779 if (req->req.length % ep->ep.maxpacket)
782 if (len > req->chain_len) {
783 /* shorter chain already allocated before */
784 if (req->chain_len > 1)
785 udc_free_dma_chain(ep->dev, req);
786 req->chain_len = len;
787 create_new_chain = 1;
791 /* gen. required number of descriptors and buffers */
792 for (i = buf_len; i < bytes; i += buf_len) {
793 /* create or determine next desc. */
794 if (create_new_chain) {
795 td = dma_pool_alloc(ep->dev->data_requests,
796 gfp_flags, &dma_addr);
801 } else if (i == buf_len) {
803 td = (struct udc_data_dma *)phys_to_virt(
807 td = (struct udc_data_dma *)phys_to_virt(last->next);
812 td->bufptr = req->req.dma + i; /* assign buffer */
817 if ((bytes - i) >= buf_len) {
824 /* link td and assign tx bytes */
826 if (create_new_chain)
827 req->td_data->next = dma_addr;
830 * req->td_data->next = virt_to_phys(td);
835 req->td_data->status =
836 AMD_ADDBITS(req->td_data->status,
838 UDC_DMA_IN_STS_TXBYTES);
840 td->status = AMD_ADDBITS(td->status,
842 UDC_DMA_IN_STS_TXBYTES);
845 if (create_new_chain)
846 last->next = dma_addr;
849 * last->next = virt_to_phys(td);
853 td->status = AMD_ADDBITS(td->status,
855 UDC_DMA_IN_STS_TXBYTES);
862 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
863 /* last desc. points to itself */
864 req->td_data_last = td;
870 /* create/re-init a DMA descriptor or a DMA descriptor chain */
871 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
876 VDBG(ep->dev, "prep_dma\n");
877 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
878 ep->num, req->td_data);
880 /* set buffer pointer */
881 req->td_data->bufptr = req->req.dma;
884 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
886 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
889 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
891 if (retval == -ENOMEM)
892 DBG(ep->dev, "Out of DMA memory\n");
896 if (req->req.length == ep->ep.maxpacket) {
898 req->td_data->status =
899 AMD_ADDBITS(req->td_data->status,
901 UDC_DMA_IN_STS_TXBYTES);
909 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
910 "maxpacket=%d ep%d\n",
911 use_dma_ppb, req->req.length,
912 ep->ep.maxpacket, ep->num);
914 * if bytes < max packet then tx bytes must
915 * be written in packet per buffer mode
917 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
918 || ep->num == UDC_EP0OUT_IX
919 || ep->num == UDC_EP0IN_IX) {
921 req->td_data->status =
922 AMD_ADDBITS(req->td_data->status,
924 UDC_DMA_IN_STS_TXBYTES);
925 /* reset frame num */
926 req->td_data->status =
927 AMD_ADDBITS(req->td_data->status,
929 UDC_DMA_IN_STS_FRAMENUM);
932 req->td_data->status =
933 AMD_ADDBITS(req->td_data->status,
934 UDC_DMA_STP_STS_BS_HOST_BUSY,
937 VDBG(ep->dev, "OUT set host ready\n");
939 req->td_data->status =
940 AMD_ADDBITS(req->td_data->status,
941 UDC_DMA_STP_STS_BS_HOST_READY,
944 /* clear NAK by writing CNAK */
946 tmp = readl(&ep->regs->ctl);
947 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
948 writel(tmp, &ep->regs->ctl);
950 UDC_QUEUE_CNAK(ep, ep->num);
958 /* Completes request packet ... caller MUST hold lock */
960 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
961 __releases(ep->dev->lock)
962 __acquires(ep->dev->lock)
967 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
972 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
977 /* set new status if pending */
978 if (req->req.status == -EINPROGRESS)
979 req->req.status = sts;
981 /* remove from ep queue */
982 list_del_init(&req->queue);
984 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
985 &req->req, req->req.length, ep->ep.name, sts);
987 spin_unlock(&dev->lock);
988 usb_gadget_giveback_request(&ep->ep, &req->req);
989 spin_lock(&dev->lock);
993 /* Iterates to the end of a DMA chain and returns last descriptor */
994 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
996 struct udc_data_dma *td;
999 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
1000 td = phys_to_virt(td->next);
1006 /* Iterates to the end of a DMA chain and counts bytes received */
1007 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
1009 struct udc_data_dma *td;
1013 /* received number bytes */
1014 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
1016 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
1017 td = phys_to_virt(td->next);
1018 /* received number bytes */
1020 count += AMD_GETBITS(td->status,
1021 UDC_DMA_OUT_STS_RXBYTES);
1029 /* Enabling RX DMA */
1030 static void udc_set_rde(struct udc *dev)
1034 VDBG(dev, "udc_set_rde()\n");
1035 /* stop RDE timer */
1036 if (timer_pending(&udc_timer)) {
1038 mod_timer(&udc_timer, jiffies - 1);
1041 tmp = readl(&dev->regs->ctl);
1042 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1043 writel(tmp, &dev->regs->ctl);
1046 /* Queues a request packet, called by gadget driver */
1048 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1052 unsigned long iflags;
1054 struct udc_request *req;
1058 /* check the inputs */
1059 req = container_of(usbreq, struct udc_request, req);
1061 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1062 || !list_empty(&req->queue))
1065 ep = container_of(usbep, struct udc_ep, ep);
1066 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1069 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1072 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1075 /* map dma (usually done before) */
1077 VDBG(dev, "DMA map req %p\n", req);
1078 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1083 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1084 usbep->name, usbreq, usbreq->length,
1085 req->td_data, usbreq->buf);
1087 spin_lock_irqsave(&dev->lock, iflags);
1089 usbreq->status = -EINPROGRESS;
1092 /* on empty queue just do first transfer */
1093 if (list_empty(&ep->queue)) {
1095 if (usbreq->length == 0) {
1096 /* IN zlp's are handled by hardware */
1097 complete_req(ep, req, 0);
1098 VDBG(dev, "%s: zlp\n", ep->ep.name);
1100 * if set_config or set_intf is waiting for ack by zlp
1103 if (dev->set_cfg_not_acked) {
1104 tmp = readl(&dev->regs->ctl);
1105 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1106 writel(tmp, &dev->regs->ctl);
1107 dev->set_cfg_not_acked = 0;
1109 /* setup command is ACK'ed now by zlp */
1110 if (dev->waiting_zlp_ack_ep0in) {
1111 /* clear NAK by writing CNAK in EP0_IN */
1112 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1113 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1114 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1115 dev->ep[UDC_EP0IN_IX].naking = 0;
1116 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1118 dev->waiting_zlp_ack_ep0in = 0;
1123 retval = prep_dma(ep, req, GFP_ATOMIC);
1126 /* write desc pointer to enable DMA */
1128 /* set HOST READY */
1129 req->td_data->status =
1130 AMD_ADDBITS(req->td_data->status,
1131 UDC_DMA_IN_STS_BS_HOST_READY,
1135 /* disabled rx dma while descriptor update */
1137 /* stop RDE timer */
1138 if (timer_pending(&udc_timer)) {
1140 mod_timer(&udc_timer, jiffies - 1);
1143 tmp = readl(&dev->regs->ctl);
1144 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1145 writel(tmp, &dev->regs->ctl);
1149 * if BNA occurred then let BNA dummy desc.
1150 * point to current desc.
1152 if (ep->bna_occurred) {
1153 VDBG(dev, "copy to BNA dummy desc.\n");
1154 memcpy(ep->bna_dummy_req->td_data,
1156 sizeof(struct udc_data_dma));
1159 /* write desc pointer */
1160 writel(req->td_phys, &ep->regs->desptr);
1162 /* clear NAK by writing CNAK */
1164 tmp = readl(&ep->regs->ctl);
1165 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1166 writel(tmp, &ep->regs->ctl);
1168 UDC_QUEUE_CNAK(ep, ep->num);
1173 tmp = readl(&dev->regs->ep_irqmsk);
1174 tmp &= AMD_UNMASK_BIT(ep->num);
1175 writel(tmp, &dev->regs->ep_irqmsk);
1177 } else if (ep->in) {
1179 tmp = readl(&dev->regs->ep_irqmsk);
1180 tmp &= AMD_UNMASK_BIT(ep->num);
1181 writel(tmp, &dev->regs->ep_irqmsk);
1184 } else if (ep->dma) {
1187 * prep_dma not used for OUT ep's, this is not possible
1188 * for PPB modes, because of chain creation reasons
1191 retval = prep_dma(ep, req, GFP_ATOMIC);
1196 VDBG(dev, "list_add\n");
1197 /* add request to ep queue */
1200 list_add_tail(&req->queue, &ep->queue);
1202 /* open rxfifo if out data queued */
1207 if (ep->num != UDC_EP0OUT_IX)
1208 dev->data_ep_queued = 1;
1210 /* stop OUT naking */
1212 if (!use_dma && udc_rxfifo_pending) {
1213 DBG(dev, "udc_queue(): pending bytes in "
1214 "rxfifo after nyet\n");
1216 * read pending bytes afer nyet:
1219 if (udc_rxfifo_read(ep, req)) {
1221 complete_req(ep, req, 0);
1223 udc_rxfifo_pending = 0;
1230 spin_unlock_irqrestore(&dev->lock, iflags);
1234 /* Empty request queue of an endpoint; caller holds spinlock */
1235 void empty_req_queue(struct udc_ep *ep)
1237 struct udc_request *req;
1240 while (!list_empty(&ep->queue)) {
1241 req = list_entry(ep->queue.next,
1244 complete_req(ep, req, -ESHUTDOWN);
1247 EXPORT_SYMBOL_GPL(empty_req_queue);
1249 /* Dequeues a request packet, called by gadget driver */
1250 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1253 struct udc_request *req;
1255 unsigned long iflags;
1257 ep = container_of(usbep, struct udc_ep, ep);
1258 if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1259 && ep->num != UDC_EP0OUT_IX)))
1262 req = container_of(usbreq, struct udc_request, req);
1264 spin_lock_irqsave(&ep->dev->lock, iflags);
1265 halted = ep->halted;
1267 /* request in processing or next one */
1268 if (ep->queue.next == &req->queue) {
1269 if (ep->dma && req->dma_going) {
1271 ep->cancel_transfer = 1;
1275 /* stop potential receive DMA */
1276 tmp = readl(&udc->regs->ctl);
1277 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1280 * Cancel transfer later in ISR
1281 * if descriptor was touched.
1283 dma_sts = AMD_GETBITS(req->td_data->status,
1284 UDC_DMA_OUT_STS_BS);
1285 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1286 ep->cancel_transfer = 1;
1288 udc_init_bna_dummy(ep->req);
1289 writel(ep->bna_dummy_req->td_phys,
1292 writel(tmp, &udc->regs->ctl);
1296 complete_req(ep, req, -ECONNRESET);
1297 ep->halted = halted;
1299 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1303 /* Halt or clear halt of endpoint */
1305 udc_set_halt(struct usb_ep *usbep, int halt)
1309 unsigned long iflags;
1315 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1317 ep = container_of(usbep, struct udc_ep, ep);
1318 if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1320 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1323 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1324 /* halt or clear halt */
1327 ep->dev->stall_ep0in = 1;
1331 * rxfifo empty not taken into acount
1333 tmp = readl(&ep->regs->ctl);
1334 tmp |= AMD_BIT(UDC_EPCTL_S);
1335 writel(tmp, &ep->regs->ctl);
1338 /* setup poll timer */
1339 if (!timer_pending(&udc_pollstall_timer)) {
1340 udc_pollstall_timer.expires = jiffies +
1341 HZ * UDC_POLLSTALL_TIMER_USECONDS
1343 if (!stop_pollstall_timer) {
1344 DBG(ep->dev, "start polltimer\n");
1345 add_timer(&udc_pollstall_timer);
1350 /* ep is halted by set_halt() before */
1352 tmp = readl(&ep->regs->ctl);
1353 /* clear stall bit */
1354 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1355 /* clear NAK by writing CNAK */
1356 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1357 writel(tmp, &ep->regs->ctl);
1359 UDC_QUEUE_CNAK(ep, ep->num);
1362 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1366 /* gadget interface */
1367 static const struct usb_ep_ops udc_ep_ops = {
1368 .enable = udc_ep_enable,
1369 .disable = udc_ep_disable,
1371 .alloc_request = udc_alloc_request,
1372 .free_request = udc_free_request,
1375 .dequeue = udc_dequeue,
1377 .set_halt = udc_set_halt,
1378 /* fifo ops not implemented */
1381 /*-------------------------------------------------------------------------*/
1383 /* Get frame counter (not implemented) */
1384 static int udc_get_frame(struct usb_gadget *gadget)
1389 /* Initiates a remote wakeup */
1390 static int udc_remote_wakeup(struct udc *dev)
1392 unsigned long flags;
1395 DBG(dev, "UDC initiates remote wakeup\n");
1397 spin_lock_irqsave(&dev->lock, flags);
1399 tmp = readl(&dev->regs->ctl);
1400 tmp |= AMD_BIT(UDC_DEVCTL_RES);
1401 writel(tmp, &dev->regs->ctl);
1402 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
1403 writel(tmp, &dev->regs->ctl);
1405 spin_unlock_irqrestore(&dev->lock, flags);
1409 /* Remote wakeup gadget interface */
1410 static int udc_wakeup(struct usb_gadget *gadget)
1416 dev = container_of(gadget, struct udc, gadget);
1417 udc_remote_wakeup(dev);
1422 static int amd5536_udc_start(struct usb_gadget *g,
1423 struct usb_gadget_driver *driver);
1424 static int amd5536_udc_stop(struct usb_gadget *g);
1426 static const struct usb_gadget_ops udc_ops = {
1427 .wakeup = udc_wakeup,
1428 .get_frame = udc_get_frame,
1429 .udc_start = amd5536_udc_start,
1430 .udc_stop = amd5536_udc_stop,
1433 /* Setups endpoint parameters, adds endpoints to linked list */
1434 static void make_ep_lists(struct udc *dev)
1436 /* make gadget ep lists */
1437 INIT_LIST_HEAD(&dev->gadget.ep_list);
1438 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1439 &dev->gadget.ep_list);
1440 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1441 &dev->gadget.ep_list);
1442 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1443 &dev->gadget.ep_list);
1446 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1447 if (dev->gadget.speed == USB_SPEED_FULL)
1448 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1449 else if (dev->gadget.speed == USB_SPEED_HIGH)
1450 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1451 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1454 /* Inits UDC context */
1455 void udc_basic_init(struct udc *dev)
1459 DBG(dev, "udc_basic_init()\n");
1461 dev->gadget.speed = USB_SPEED_UNKNOWN;
1463 /* stop RDE timer */
1464 if (timer_pending(&udc_timer)) {
1466 mod_timer(&udc_timer, jiffies - 1);
1468 /* stop poll stall timer */
1469 if (timer_pending(&udc_pollstall_timer))
1470 mod_timer(&udc_pollstall_timer, jiffies - 1);
1472 tmp = readl(&dev->regs->ctl);
1473 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1474 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1475 writel(tmp, &dev->regs->ctl);
1477 /* enable dynamic CSR programming */
1478 tmp = readl(&dev->regs->cfg);
1479 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1480 /* set self powered */
1481 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1482 /* set remote wakeupable */
1483 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1484 writel(tmp, &dev->regs->cfg);
1488 dev->data_ep_enabled = 0;
1489 dev->data_ep_queued = 0;
1491 EXPORT_SYMBOL_GPL(udc_basic_init);
1493 /* init registers at driver load time */
1494 static int startup_registers(struct udc *dev)
1498 /* init controller by soft reset */
1499 udc_soft_reset(dev);
1501 /* mask not needed interrupts */
1502 udc_mask_unused_interrupts(dev);
1504 /* put into initial config */
1505 udc_basic_init(dev);
1506 /* link up all endpoints */
1507 udc_setup_endpoints(dev);
1510 tmp = readl(&dev->regs->cfg);
1512 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1514 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1515 writel(tmp, &dev->regs->cfg);
1520 /* Sets initial endpoint parameters */
1521 static void udc_setup_endpoints(struct udc *dev)
1527 DBG(dev, "udc_setup_endpoints()\n");
1529 /* read enum speed */
1530 tmp = readl(&dev->regs->sts);
1531 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1532 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1533 dev->gadget.speed = USB_SPEED_HIGH;
1534 else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1535 dev->gadget.speed = USB_SPEED_FULL;
1537 /* set basic ep parameters */
1538 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1541 ep->ep.name = ep_info[tmp].name;
1542 ep->ep.caps = ep_info[tmp].caps;
1544 /* txfifo size is calculated at enable time */
1545 ep->txfifo = dev->txfifo;
1548 if (tmp < UDC_EPIN_NUM) {
1549 ep->fifo_depth = UDC_TXFIFO_SIZE;
1552 ep->fifo_depth = UDC_RXFIFO_SIZE;
1556 ep->regs = &dev->ep_regs[tmp];
1558 * ep will be reset only if ep was not enabled before to avoid
1559 * disabling ep interrupts when ENUM interrupt occurs but ep is
1560 * not enabled by gadget driver
1563 ep_init(dev->regs, ep);
1567 * ep->dma is not really used, just to indicate that
1568 * DMA is active: remove this
1569 * dma regs = dev control regs
1571 ep->dma = &dev->regs->ctl;
1573 /* nak OUT endpoints until enable - not for ep0 */
1574 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1575 && tmp > UDC_EPIN_NUM) {
1577 reg = readl(&dev->ep[tmp].regs->ctl);
1578 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1579 writel(reg, &dev->ep[tmp].regs->ctl);
1580 dev->ep[tmp].naking = 1;
1585 /* EP0 max packet */
1586 if (dev->gadget.speed == USB_SPEED_FULL) {
1587 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1588 UDC_FS_EP0IN_MAX_PKT_SIZE);
1589 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1590 UDC_FS_EP0OUT_MAX_PKT_SIZE);
1591 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1592 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1593 UDC_EP0IN_MAX_PKT_SIZE);
1594 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1595 UDC_EP0OUT_MAX_PKT_SIZE);
1599 * with suspend bug workaround, ep0 params for gadget driver
1600 * are set at gadget driver bind() call
1602 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1603 dev->ep[UDC_EP0IN_IX].halted = 0;
1604 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1606 /* init cfg/alt/int */
1607 dev->cur_config = 0;
1612 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1613 static void usb_connect(struct udc *dev)
1615 /* Return if already connected */
1619 dev_info(dev->dev, "USB Connect\n");
1623 /* put into initial config */
1624 udc_basic_init(dev);
1626 /* enable device setup interrupts */
1627 udc_enable_dev_setup_interrupts(dev);
1631 * Calls gadget with disconnect event and resets the UDC and makes
1632 * initial bringup to be ready for ep0 events
1634 static void usb_disconnect(struct udc *dev)
1638 /* Return if already disconnected */
1639 if (!dev->connected)
1642 dev_info(dev->dev, "USB Disconnect\n");
1646 /* mask interrupts */
1647 udc_mask_unused_interrupts(dev);
1650 spin_unlock(&dev->lock);
1651 dev->driver->disconnect(&dev->gadget);
1652 spin_lock(&dev->lock);
1655 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1656 empty_req_queue(&dev->ep[tmp]);
1660 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
1662 if (!soft_reset_occured) {
1663 /* init controller by soft reset */
1664 udc_soft_reset(dev);
1665 soft_reset_occured++;
1668 /* re-enable dev interrupts */
1669 udc_enable_dev_setup_interrupts(dev);
1670 /* back to full speed ? */
1671 if (use_fullspeed) {
1672 tmp = readl(&dev->regs->cfg);
1673 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1674 writel(tmp, &dev->regs->cfg);
1678 /* Reset the UDC core */
1679 static void udc_soft_reset(struct udc *dev)
1681 unsigned long flags;
1683 DBG(dev, "Soft reset\n");
1685 * reset possible waiting interrupts, because int.
1686 * status is lost after soft reset,
1687 * ep int. status reset
1689 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1690 /* device int. status reset */
1691 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1693 /* Don't do this for Broadcom UDC since this is a reserved
1696 if (dev->chiprev != UDC_BCM_REV) {
1697 spin_lock_irqsave(&udc_irq_spinlock, flags);
1698 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1699 readl(&dev->regs->cfg);
1700 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1704 /* RDE timer callback to set RDE bit */
1705 static void udc_timer_function(struct timer_list *unused)
1709 spin_lock_irq(&udc_irq_spinlock);
1713 * open the fifo if fifo was filled on last timer call
1717 /* set RDE to receive setup data */
1718 tmp = readl(&udc->regs->ctl);
1719 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1720 writel(tmp, &udc->regs->ctl);
1722 } else if (readl(&udc->regs->sts)
1723 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1725 * if fifo empty setup polling, do not just
1728 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1730 add_timer(&udc_timer);
1733 * fifo contains data now, setup timer for opening
1734 * the fifo when timer expires to be able to receive
1735 * setup packets, when data packets gets queued by
1736 * gadget layer then timer will forced to expire with
1737 * set_rde=0 (RDE is set in udc_queue())
1740 /* debug: lhadmot_timer_start = 221070 */
1741 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1743 add_timer(&udc_timer);
1747 set_rde = -1; /* RDE was set by udc_queue() */
1748 spin_unlock_irq(&udc_irq_spinlock);
1754 /* Handle halt state, used in stall poll timer */
1755 static void udc_handle_halt_state(struct udc_ep *ep)
1758 /* set stall as long not halted */
1759 if (ep->halted == 1) {
1760 tmp = readl(&ep->regs->ctl);
1761 /* STALL cleared ? */
1762 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1764 * FIXME: MSC spec requires that stall remains
1765 * even on receivng of CLEAR_FEATURE HALT. So
1766 * we would set STALL again here to be compliant.
1767 * But with current mass storage drivers this does
1768 * not work (would produce endless host retries).
1769 * So we clear halt on CLEAR_FEATURE.
1771 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1772 tmp |= AMD_BIT(UDC_EPCTL_S);
1773 writel(tmp, &ep->regs->ctl);*/
1775 /* clear NAK by writing CNAK */
1776 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1777 writel(tmp, &ep->regs->ctl);
1779 UDC_QUEUE_CNAK(ep, ep->num);
1784 /* Stall timer callback to poll S bit and set it again after */
1785 static void udc_pollstall_timer_function(struct timer_list *unused)
1790 spin_lock_irq(&udc_stall_spinlock);
1792 * only one IN and OUT endpoints are handled
1795 ep = &udc->ep[UDC_EPIN_IX];
1796 udc_handle_halt_state(ep);
1799 /* OUT poll stall */
1800 ep = &udc->ep[UDC_EPOUT_IX];
1801 udc_handle_halt_state(ep);
1805 /* setup timer again when still halted */
1806 if (!stop_pollstall_timer && halted) {
1807 udc_pollstall_timer.expires = jiffies +
1808 HZ * UDC_POLLSTALL_TIMER_USECONDS
1810 add_timer(&udc_pollstall_timer);
1812 spin_unlock_irq(&udc_stall_spinlock);
1814 if (stop_pollstall_timer)
1815 complete(&on_pollstall_exit);
1818 /* Inits endpoint 0 so that SETUP packets are processed */
1819 static void activate_control_endpoints(struct udc *dev)
1823 DBG(dev, "activate_control_endpoints\n");
1826 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1827 tmp |= AMD_BIT(UDC_EPCTL_F);
1828 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1830 /* set ep0 directions */
1831 dev->ep[UDC_EP0IN_IX].in = 1;
1832 dev->ep[UDC_EP0OUT_IX].in = 0;
1834 /* set buffer size (tx fifo entries) of EP0_IN */
1835 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1836 if (dev->gadget.speed == USB_SPEED_FULL)
1837 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1838 UDC_EPIN_BUFF_SIZE);
1839 else if (dev->gadget.speed == USB_SPEED_HIGH)
1840 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1841 UDC_EPIN_BUFF_SIZE);
1842 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1844 /* set max packet size of EP0_IN */
1845 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1846 if (dev->gadget.speed == USB_SPEED_FULL)
1847 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1848 UDC_EP_MAX_PKT_SIZE);
1849 else if (dev->gadget.speed == USB_SPEED_HIGH)
1850 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1851 UDC_EP_MAX_PKT_SIZE);
1852 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1854 /* set max packet size of EP0_OUT */
1855 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1856 if (dev->gadget.speed == USB_SPEED_FULL)
1857 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1858 UDC_EP_MAX_PKT_SIZE);
1859 else if (dev->gadget.speed == USB_SPEED_HIGH)
1860 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1861 UDC_EP_MAX_PKT_SIZE);
1862 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1864 /* set max packet size of EP0 in UDC CSR */
1865 tmp = readl(&dev->csr->ne[0]);
1866 if (dev->gadget.speed == USB_SPEED_FULL)
1867 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1868 UDC_CSR_NE_MAX_PKT);
1869 else if (dev->gadget.speed == USB_SPEED_HIGH)
1870 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1871 UDC_CSR_NE_MAX_PKT);
1872 writel(tmp, &dev->csr->ne[0]);
1875 dev->ep[UDC_EP0OUT_IX].td->status |=
1876 AMD_BIT(UDC_DMA_OUT_STS_L);
1877 /* write dma desc address */
1878 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1879 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1880 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1881 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1882 /* stop RDE timer */
1883 if (timer_pending(&udc_timer)) {
1885 mod_timer(&udc_timer, jiffies - 1);
1887 /* stop pollstall timer */
1888 if (timer_pending(&udc_pollstall_timer))
1889 mod_timer(&udc_pollstall_timer, jiffies - 1);
1891 tmp = readl(&dev->regs->ctl);
1892 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1893 | AMD_BIT(UDC_DEVCTL_RDE)
1894 | AMD_BIT(UDC_DEVCTL_TDE);
1895 if (use_dma_bufferfill_mode)
1896 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1897 else if (use_dma_ppb_du)
1898 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1899 writel(tmp, &dev->regs->ctl);
1902 /* clear NAK by writing CNAK for EP0IN */
1903 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1904 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1905 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1906 dev->ep[UDC_EP0IN_IX].naking = 0;
1907 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1909 /* clear NAK by writing CNAK for EP0OUT */
1910 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1911 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1912 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1913 dev->ep[UDC_EP0OUT_IX].naking = 0;
1914 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1917 /* Make endpoint 0 ready for control traffic */
1918 static int setup_ep0(struct udc *dev)
1920 activate_control_endpoints(dev);
1921 /* enable ep0 interrupts */
1922 udc_enable_ep0_interrupts(dev);
1923 /* enable device setup interrupts */
1924 udc_enable_dev_setup_interrupts(dev);
1929 /* Called by gadget driver to register itself */
1930 static int amd5536_udc_start(struct usb_gadget *g,
1931 struct usb_gadget_driver *driver)
1933 struct udc *dev = to_amd5536_udc(g);
1936 dev->driver = driver;
1938 /* Some gadget drivers use both ep0 directions.
1939 * NOTE: to gadget driver, ep0 is just one endpoint...
1941 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1942 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1944 /* get ready for ep0 traffic */
1948 tmp = readl(&dev->regs->ctl);
1949 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1950 writel(tmp, &dev->regs->ctl);
1957 /* shutdown requests and disconnect from gadget */
1959 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1960 __releases(dev->lock)
1961 __acquires(dev->lock)
1965 /* empty queues and init hardware */
1966 udc_basic_init(dev);
1968 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1969 empty_req_queue(&dev->ep[tmp]);
1971 udc_setup_endpoints(dev);
1974 /* Called by gadget driver to unregister itself */
1975 static int amd5536_udc_stop(struct usb_gadget *g)
1977 struct udc *dev = to_amd5536_udc(g);
1978 unsigned long flags;
1981 spin_lock_irqsave(&dev->lock, flags);
1982 udc_mask_unused_interrupts(dev);
1983 shutdown(dev, NULL);
1984 spin_unlock_irqrestore(&dev->lock, flags);
1989 tmp = readl(&dev->regs->ctl);
1990 tmp |= AMD_BIT(UDC_DEVCTL_SD);
1991 writel(tmp, &dev->regs->ctl);
1996 /* Clear pending NAK bits */
1997 static void udc_process_cnak_queue(struct udc *dev)
2003 DBG(dev, "CNAK pending queue processing\n");
2004 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2005 if (cnak_pending & (1 << tmp)) {
2006 DBG(dev, "CNAK pending for ep%d\n", tmp);
2007 /* clear NAK by writing CNAK */
2008 reg = readl(&dev->ep[tmp].regs->ctl);
2009 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2010 writel(reg, &dev->ep[tmp].regs->ctl);
2011 dev->ep[tmp].naking = 0;
2012 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2015 /* ... and ep0out */
2016 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2017 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2018 /* clear NAK by writing CNAK */
2019 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2020 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2021 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2022 dev->ep[UDC_EP0OUT_IX].naking = 0;
2023 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2024 dev->ep[UDC_EP0OUT_IX].num);
2028 /* Enabling RX DMA after setup packet */
2029 static void udc_ep0_set_rde(struct udc *dev)
2033 * only enable RXDMA when no data endpoint enabled
2036 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2040 * setup timer for enabling RDE (to not enable
2041 * RXFIFO DMA for data endpoints to early)
2043 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2045 jiffies + HZ/UDC_RDE_TIMER_DIV;
2048 add_timer(&udc_timer);
2055 /* Interrupt handler for data OUT traffic */
2056 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2058 irqreturn_t ret_val = IRQ_NONE;
2061 struct udc_request *req;
2063 struct udc_data_dma *td = NULL;
2066 VDBG(dev, "ep%d irq\n", ep_ix);
2067 ep = &dev->ep[ep_ix];
2069 tmp = readl(&ep->regs->sts);
2072 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2073 DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2074 ep->num, readl(&ep->regs->desptr));
2076 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2077 if (!ep->cancel_transfer)
2078 ep->bna_occurred = 1;
2080 ep->cancel_transfer = 0;
2081 ret_val = IRQ_HANDLED;
2086 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2087 dev_err(dev->dev, "HE ep%dout occurred\n", ep->num);
2090 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2091 ret_val = IRQ_HANDLED;
2095 if (!list_empty(&ep->queue)) {
2098 req = list_entry(ep->queue.next,
2099 struct udc_request, queue);
2102 udc_rxfifo_pending = 1;
2104 VDBG(dev, "req = %p\n", req);
2109 if (req && udc_rxfifo_read(ep, req)) {
2110 ret_val = IRQ_HANDLED;
2113 complete_req(ep, req, 0);
2115 if (!list_empty(&ep->queue) && !ep->halted) {
2116 req = list_entry(ep->queue.next,
2117 struct udc_request, queue);
2123 } else if (!ep->cancel_transfer && req) {
2124 ret_val = IRQ_HANDLED;
2126 /* check for DMA done */
2128 dma_done = AMD_GETBITS(req->td_data->status,
2129 UDC_DMA_OUT_STS_BS);
2130 /* packet per buffer mode - rx bytes */
2133 * if BNA occurred then recover desc. from
2136 if (ep->bna_occurred) {
2137 VDBG(dev, "Recover desc. from BNA dummy\n");
2138 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2139 sizeof(struct udc_data_dma));
2140 ep->bna_occurred = 0;
2141 udc_init_bna_dummy(ep->req);
2143 td = udc_get_last_dma_desc(req);
2144 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2146 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2147 /* buffer fill mode - rx bytes */
2149 /* received number bytes */
2150 count = AMD_GETBITS(req->td_data->status,
2151 UDC_DMA_OUT_STS_RXBYTES);
2152 VDBG(dev, "rx bytes=%u\n", count);
2153 /* packet per buffer mode - rx bytes */
2155 VDBG(dev, "req->td_data=%p\n", req->td_data);
2156 VDBG(dev, "last desc = %p\n", td);
2157 /* received number bytes */
2158 if (use_dma_ppb_du) {
2159 /* every desc. counts bytes */
2160 count = udc_get_ppbdu_rxbytes(req);
2162 /* last desc. counts bytes */
2163 count = AMD_GETBITS(td->status,
2164 UDC_DMA_OUT_STS_RXBYTES);
2165 if (!count && req->req.length
2166 == UDC_DMA_MAXPACKET) {
2168 * on 64k packets the RXBYTES
2171 count = UDC_DMA_MAXPACKET;
2174 VDBG(dev, "last desc rx bytes=%u\n", count);
2177 tmp = req->req.length - req->req.actual;
2179 if ((tmp % ep->ep.maxpacket) != 0) {
2180 DBG(dev, "%s: rx %db, space=%db\n",
2181 ep->ep.name, count, tmp);
2182 req->req.status = -EOVERFLOW;
2186 req->req.actual += count;
2188 /* complete request */
2189 complete_req(ep, req, 0);
2192 if (!list_empty(&ep->queue) && !ep->halted) {
2193 req = list_entry(ep->queue.next,
2197 * DMA may be already started by udc_queue()
2198 * called by gadget drivers completion
2199 * routine. This happens when queue
2200 * holds one request only.
2202 if (req->dma_going == 0) {
2204 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2206 /* write desc pointer */
2207 writel(req->td_phys,
2215 * implant BNA dummy descriptor to allow
2216 * RXFIFO opening by RDE
2218 if (ep->bna_dummy_req) {
2219 /* write desc pointer */
2220 writel(ep->bna_dummy_req->td_phys,
2222 ep->bna_occurred = 0;
2226 * schedule timer for setting RDE if queue
2227 * remains empty to allow ep0 packets pass
2231 && !timer_pending(&udc_timer)) {
2234 + HZ*UDC_RDE_TIMER_SECONDS;
2237 add_timer(&udc_timer);
2239 if (ep->num != UDC_EP0OUT_IX)
2240 dev->data_ep_queued = 0;
2245 * RX DMA must be reenabled for each desc in PPBDU mode
2246 * and must be enabled for PPBNDU mode in case of BNA
2251 } else if (ep->cancel_transfer) {
2252 ret_val = IRQ_HANDLED;
2253 ep->cancel_transfer = 0;
2256 /* check pending CNAKS */
2258 /* CNAk processing when rxfifo empty only */
2259 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2260 udc_process_cnak_queue(dev);
2263 /* clear OUT bits in ep status */
2264 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2269 /* Interrupt handler for data IN traffic */
2270 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2272 irqreturn_t ret_val = IRQ_NONE;
2276 struct udc_request *req;
2277 struct udc_data_dma *td;
2280 ep = &dev->ep[ep_ix];
2282 epsts = readl(&ep->regs->sts);
2285 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2287 "BNA ep%din occurred - DESPTR = %08lx\n",
2289 (unsigned long) readl(&ep->regs->desptr));
2292 writel(epsts, &ep->regs->sts);
2293 ret_val = IRQ_HANDLED;
2298 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2300 "HE ep%dn occurred - DESPTR = %08lx\n",
2301 ep->num, (unsigned long) readl(&ep->regs->desptr));
2304 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2305 ret_val = IRQ_HANDLED;
2309 /* DMA completion */
2310 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2311 VDBG(dev, "TDC set- completion\n");
2312 ret_val = IRQ_HANDLED;
2313 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2314 req = list_entry(ep->queue.next,
2315 struct udc_request, queue);
2317 * length bytes transferred
2318 * check dma done of last desc. in PPBDU mode
2320 if (use_dma_ppb_du) {
2321 td = udc_get_last_dma_desc(req);
2323 req->req.actual = req->req.length;
2325 /* assume all bytes transferred */
2326 req->req.actual = req->req.length;
2329 if (req->req.actual == req->req.length) {
2331 complete_req(ep, req, 0);
2333 /* further request available ? */
2334 if (list_empty(&ep->queue)) {
2335 /* disable interrupt */
2336 tmp = readl(&dev->regs->ep_irqmsk);
2337 tmp |= AMD_BIT(ep->num);
2338 writel(tmp, &dev->regs->ep_irqmsk);
2342 ep->cancel_transfer = 0;
2346 * status reg has IN bit set and TDC not set (if TDC was handled,
2347 * IN must not be handled (UDC defect) ?
2349 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2350 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2351 ret_val = IRQ_HANDLED;
2352 if (!list_empty(&ep->queue)) {
2354 req = list_entry(ep->queue.next,
2355 struct udc_request, queue);
2359 udc_txfifo_write(ep, &req->req);
2360 len = req->req.length - req->req.actual;
2361 if (len > ep->ep.maxpacket)
2362 len = ep->ep.maxpacket;
2363 req->req.actual += len;
2364 if (req->req.actual == req->req.length
2365 || (len != ep->ep.maxpacket)) {
2367 complete_req(ep, req, 0);
2370 } else if (req && !req->dma_going) {
2371 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2378 * unset L bit of first desc.
2381 if (use_dma_ppb && req->req.length >
2383 req->td_data->status &=
2388 /* write desc pointer */
2389 writel(req->td_phys, &ep->regs->desptr);
2391 /* set HOST READY */
2392 req->td_data->status =
2394 req->td_data->status,
2395 UDC_DMA_IN_STS_BS_HOST_READY,
2398 /* set poll demand bit */
2399 tmp = readl(&ep->regs->ctl);
2400 tmp |= AMD_BIT(UDC_EPCTL_P);
2401 writel(tmp, &ep->regs->ctl);
2405 } else if (!use_dma && ep->in) {
2406 /* disable interrupt */
2408 &dev->regs->ep_irqmsk);
2409 tmp |= AMD_BIT(ep->num);
2411 &dev->regs->ep_irqmsk);
2414 /* clear status bits */
2415 writel(epsts, &ep->regs->sts);
2422 /* Interrupt handler for Control OUT traffic */
2423 static irqreturn_t udc_control_out_isr(struct udc *dev)
2424 __releases(dev->lock)
2425 __acquires(dev->lock)
2427 irqreturn_t ret_val = IRQ_NONE;
2429 int setup_supported;
2433 struct udc_ep *ep_tmp;
2435 ep = &dev->ep[UDC_EP0OUT_IX];
2438 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2440 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2441 /* check BNA and clear if set */
2442 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2443 VDBG(dev, "ep0: BNA set\n");
2444 writel(AMD_BIT(UDC_EPSTS_BNA),
2445 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2446 ep->bna_occurred = 1;
2447 ret_val = IRQ_HANDLED;
2451 /* type of data: SETUP or DATA 0 bytes */
2452 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2453 VDBG(dev, "data_typ = %x\n", tmp);
2456 if (tmp == UDC_EPSTS_OUT_SETUP) {
2457 ret_val = IRQ_HANDLED;
2459 ep->dev->stall_ep0in = 0;
2460 dev->waiting_zlp_ack_ep0in = 0;
2462 /* set NAK for EP0_IN */
2463 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2464 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2465 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2466 dev->ep[UDC_EP0IN_IX].naking = 1;
2467 /* get setup data */
2470 /* clear OUT bits in ep status */
2471 writel(UDC_EPSTS_OUT_CLEAR,
2472 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2474 setup_data.data[0] =
2475 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2476 setup_data.data[1] =
2477 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2478 /* set HOST READY */
2479 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2480 UDC_DMA_STP_STS_BS_HOST_READY;
2483 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2486 /* determine direction of control data */
2487 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2488 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2490 udc_ep0_set_rde(dev);
2493 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2495 * implant BNA dummy descriptor to allow RXFIFO opening
2498 if (ep->bna_dummy_req) {
2499 /* write desc pointer */
2500 writel(ep->bna_dummy_req->td_phys,
2501 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2502 ep->bna_occurred = 0;
2506 dev->ep[UDC_EP0OUT_IX].naking = 1;
2508 * setup timer for enabling RDE (to not enable
2509 * RXFIFO DMA for data to early)
2512 if (!timer_pending(&udc_timer)) {
2513 udc_timer.expires = jiffies +
2514 HZ/UDC_RDE_TIMER_DIV;
2516 add_timer(&udc_timer);
2521 * mass storage reset must be processed here because
2522 * next packet may be a CLEAR_FEATURE HALT which would not
2523 * clear the stall bit when no STALL handshake was received
2524 * before (autostall can cause this)
2526 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2527 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2528 DBG(dev, "MSC Reset\n");
2531 * only one IN and OUT endpoints are handled
2533 ep_tmp = &udc->ep[UDC_EPIN_IX];
2534 udc_set_halt(&ep_tmp->ep, 0);
2535 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2536 udc_set_halt(&ep_tmp->ep, 0);
2539 /* call gadget with setup data received */
2540 spin_unlock(&dev->lock);
2541 setup_supported = dev->driver->setup(&dev->gadget,
2542 &setup_data.request);
2543 spin_lock(&dev->lock);
2545 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2546 /* ep0 in returns data (not zlp) on IN phase */
2547 if (setup_supported >= 0 && setup_supported <
2548 UDC_EP0IN_MAXPACKET) {
2549 /* clear NAK by writing CNAK in EP0_IN */
2550 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2551 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2552 dev->ep[UDC_EP0IN_IX].naking = 0;
2553 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2555 /* if unsupported request then stall */
2556 } else if (setup_supported < 0) {
2557 tmp |= AMD_BIT(UDC_EPCTL_S);
2558 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2560 dev->waiting_zlp_ack_ep0in = 1;
2563 /* clear NAK by writing CNAK in EP0_OUT */
2565 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2566 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2567 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2568 dev->ep[UDC_EP0OUT_IX].naking = 0;
2569 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2573 /* clear OUT bits in ep status */
2574 writel(UDC_EPSTS_OUT_CLEAR,
2575 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2578 /* data packet 0 bytes */
2579 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2580 /* clear OUT bits in ep status */
2581 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2583 /* get setup data: only 0 packet */
2585 /* no req if 0 packet, just reactivate */
2586 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2589 /* set HOST READY */
2590 dev->ep[UDC_EP0OUT_IX].td->status =
2592 dev->ep[UDC_EP0OUT_IX].td->status,
2593 UDC_DMA_OUT_STS_BS_HOST_READY,
2594 UDC_DMA_OUT_STS_BS);
2596 udc_ep0_set_rde(dev);
2597 ret_val = IRQ_HANDLED;
2601 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2602 /* re-program desc. pointer for possible ZLPs */
2603 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2604 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2606 udc_ep0_set_rde(dev);
2610 /* received number bytes */
2611 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2612 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2613 /* out data for fifo mode not working */
2616 /* 0 packet or real data ? */
2618 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2620 /* dummy read confirm */
2621 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2622 ret_val = IRQ_HANDLED;
2627 /* check pending CNAKS */
2629 /* CNAk processing when rxfifo empty only */
2630 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2631 udc_process_cnak_queue(dev);
2638 /* Interrupt handler for Control IN traffic */
2639 static irqreturn_t udc_control_in_isr(struct udc *dev)
2641 irqreturn_t ret_val = IRQ_NONE;
2644 struct udc_request *req;
2647 ep = &dev->ep[UDC_EP0IN_IX];
2650 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2652 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2653 /* DMA completion */
2654 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2655 VDBG(dev, "isr: TDC clear\n");
2656 ret_val = IRQ_HANDLED;
2659 writel(AMD_BIT(UDC_EPSTS_TDC),
2660 &dev->ep[UDC_EP0IN_IX].regs->sts);
2662 /* status reg has IN bit set ? */
2663 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2664 ret_val = IRQ_HANDLED;
2668 writel(AMD_BIT(UDC_EPSTS_IN),
2669 &dev->ep[UDC_EP0IN_IX].regs->sts);
2671 if (dev->stall_ep0in) {
2672 DBG(dev, "stall ep0in\n");
2674 tmp = readl(&ep->regs->ctl);
2675 tmp |= AMD_BIT(UDC_EPCTL_S);
2676 writel(tmp, &ep->regs->ctl);
2678 if (!list_empty(&ep->queue)) {
2680 req = list_entry(ep->queue.next,
2681 struct udc_request, queue);
2684 /* write desc pointer */
2685 writel(req->td_phys, &ep->regs->desptr);
2686 /* set HOST READY */
2687 req->td_data->status =
2689 req->td_data->status,
2690 UDC_DMA_STP_STS_BS_HOST_READY,
2691 UDC_DMA_STP_STS_BS);
2693 /* set poll demand bit */
2695 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2696 tmp |= AMD_BIT(UDC_EPCTL_P);
2698 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2700 /* all bytes will be transferred */
2701 req->req.actual = req->req.length;
2704 complete_req(ep, req, 0);
2708 udc_txfifo_write(ep, &req->req);
2710 /* lengh bytes transferred */
2711 len = req->req.length - req->req.actual;
2712 if (len > ep->ep.maxpacket)
2713 len = ep->ep.maxpacket;
2715 req->req.actual += len;
2716 if (req->req.actual == req->req.length
2717 || (len != ep->ep.maxpacket)) {
2719 complete_req(ep, req, 0);
2726 dev->stall_ep0in = 0;
2729 writel(AMD_BIT(UDC_EPSTS_IN),
2730 &dev->ep[UDC_EP0IN_IX].regs->sts);
2738 /* Interrupt handler for global device events */
2739 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2740 __releases(dev->lock)
2741 __acquires(dev->lock)
2743 irqreturn_t ret_val = IRQ_NONE;
2750 /* SET_CONFIG irq ? */
2751 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2752 ret_val = IRQ_HANDLED;
2754 /* read config value */
2755 tmp = readl(&dev->regs->sts);
2756 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2757 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2758 dev->cur_config = cfg;
2759 dev->set_cfg_not_acked = 1;
2761 /* make usb request for gadget driver */
2762 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2763 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2764 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2766 /* programm the NE registers */
2767 for (i = 0; i < UDC_EP_NUM; i++) {
2771 /* ep ix in UDC CSR register space */
2772 udc_csr_epix = ep->num;
2777 /* ep ix in UDC CSR register space */
2778 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2781 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2783 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2786 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2788 /* clear stall bits */
2790 tmp = readl(&ep->regs->ctl);
2791 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2792 writel(tmp, &ep->regs->ctl);
2794 /* call gadget zero with setup data received */
2795 spin_unlock(&dev->lock);
2796 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2797 spin_lock(&dev->lock);
2799 } /* SET_INTERFACE ? */
2800 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2801 ret_val = IRQ_HANDLED;
2803 dev->set_cfg_not_acked = 1;
2804 /* read interface and alt setting values */
2805 tmp = readl(&dev->regs->sts);
2806 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2807 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2809 /* make usb request for gadget driver */
2810 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2811 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2812 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2813 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2814 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2816 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2817 dev->cur_alt, dev->cur_intf);
2819 /* programm the NE registers */
2820 for (i = 0; i < UDC_EP_NUM; i++) {
2824 /* ep ix in UDC CSR register space */
2825 udc_csr_epix = ep->num;
2830 /* ep ix in UDC CSR register space */
2831 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2836 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2838 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2840 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2842 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2845 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2847 /* clear stall bits */
2849 tmp = readl(&ep->regs->ctl);
2850 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2851 writel(tmp, &ep->regs->ctl);
2854 /* call gadget zero with setup data received */
2855 spin_unlock(&dev->lock);
2856 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2857 spin_lock(&dev->lock);
2860 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2861 DBG(dev, "USB Reset interrupt\n");
2862 ret_val = IRQ_HANDLED;
2864 /* allow soft reset when suspend occurs */
2865 soft_reset_occured = 0;
2867 dev->waiting_zlp_ack_ep0in = 0;
2868 dev->set_cfg_not_acked = 0;
2870 /* mask not needed interrupts */
2871 udc_mask_unused_interrupts(dev);
2873 /* call gadget to resume and reset configs etc. */
2874 spin_unlock(&dev->lock);
2875 if (dev->sys_suspended && dev->driver->resume) {
2876 dev->driver->resume(&dev->gadget);
2877 dev->sys_suspended = 0;
2879 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2880 spin_lock(&dev->lock);
2882 /* disable ep0 to empty req queue */
2883 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2884 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2886 /* soft reset when rxfifo not empty */
2887 tmp = readl(&dev->regs->sts);
2888 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2889 && !soft_reset_after_usbreset_occured) {
2890 udc_soft_reset(dev);
2891 soft_reset_after_usbreset_occured++;
2895 * DMA reset to kill potential old DMA hw hang,
2896 * POLL bit is already reset by ep_init() through
2899 DBG(dev, "DMA machine reset\n");
2900 tmp = readl(&dev->regs->cfg);
2901 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2902 writel(tmp, &dev->regs->cfg);
2904 /* put into initial config */
2905 udc_basic_init(dev);
2907 /* enable device setup interrupts */
2908 udc_enable_dev_setup_interrupts(dev);
2910 /* enable suspend interrupt */
2911 tmp = readl(&dev->regs->irqmsk);
2912 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2913 writel(tmp, &dev->regs->irqmsk);
2916 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2917 DBG(dev, "USB Suspend interrupt\n");
2918 ret_val = IRQ_HANDLED;
2919 if (dev->driver->suspend) {
2920 spin_unlock(&dev->lock);
2921 dev->sys_suspended = 1;
2922 dev->driver->suspend(&dev->gadget);
2923 spin_lock(&dev->lock);
2926 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2927 DBG(dev, "ENUM interrupt\n");
2928 ret_val = IRQ_HANDLED;
2929 soft_reset_after_usbreset_occured = 0;
2931 /* disable ep0 to empty req queue */
2932 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2933 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2935 /* link up all endpoints */
2936 udc_setup_endpoints(dev);
2937 dev_info(dev->dev, "Connect: %s\n",
2938 usb_speed_string(dev->gadget.speed));
2941 activate_control_endpoints(dev);
2943 /* enable ep0 interrupts */
2944 udc_enable_ep0_interrupts(dev);
2946 /* session valid change interrupt */
2947 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2948 DBG(dev, "USB SVC interrupt\n");
2949 ret_val = IRQ_HANDLED;
2951 /* check that session is not valid to detect disconnect */
2952 tmp = readl(&dev->regs->sts);
2953 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2954 /* disable suspend interrupt */
2955 tmp = readl(&dev->regs->irqmsk);
2956 tmp |= AMD_BIT(UDC_DEVINT_US);
2957 writel(tmp, &dev->regs->irqmsk);
2958 DBG(dev, "USB Disconnect (session valid low)\n");
2959 /* cleanup on disconnect */
2960 usb_disconnect(udc);
2968 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
2969 irqreturn_t udc_irq(int irq, void *pdev)
2971 struct udc *dev = pdev;
2975 irqreturn_t ret_val = IRQ_NONE;
2977 spin_lock(&dev->lock);
2979 /* check for ep irq */
2980 reg = readl(&dev->regs->ep_irqsts);
2982 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
2983 ret_val |= udc_control_out_isr(dev);
2984 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
2985 ret_val |= udc_control_in_isr(dev);
2991 for (i = 1; i < UDC_EP_NUM; i++) {
2993 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
2996 /* clear irq status */
2997 writel(ep_irq, &dev->regs->ep_irqsts);
2999 /* irq for out ep ? */
3000 if (i > UDC_EPIN_NUM)
3001 ret_val |= udc_data_out_isr(dev, i);
3003 ret_val |= udc_data_in_isr(dev, i);
3009 /* check for dev irq */
3010 reg = readl(&dev->regs->irqsts);
3013 writel(reg, &dev->regs->irqsts);
3014 ret_val |= udc_dev_isr(dev, reg);
3018 spin_unlock(&dev->lock);
3021 EXPORT_SYMBOL_GPL(udc_irq);
3023 /* Tears down device */
3024 void gadget_release(struct device *pdev)
3026 struct amd5536udc *dev = dev_get_drvdata(pdev);
3029 EXPORT_SYMBOL_GPL(gadget_release);
3031 /* Cleanup on device remove */
3032 void udc_remove(struct udc *dev)
3036 if (timer_pending(&udc_timer))
3037 wait_for_completion(&on_exit);
3038 del_timer_sync(&udc_timer);
3039 /* remove pollstall timer */
3040 stop_pollstall_timer++;
3041 if (timer_pending(&udc_pollstall_timer))
3042 wait_for_completion(&on_pollstall_exit);
3043 del_timer_sync(&udc_pollstall_timer);
3046 EXPORT_SYMBOL_GPL(udc_remove);
3048 /* free all the dma pools */
3049 void free_dma_pools(struct udc *dev)
3051 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td,
3052 dev->ep[UDC_EP0OUT_IX].td_phys);
3053 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3054 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3055 dma_pool_destroy(dev->stp_requests);
3056 dma_pool_destroy(dev->data_requests);
3058 EXPORT_SYMBOL_GPL(free_dma_pools);
3060 /* create dma pools on init */
3061 int init_dma_pools(struct udc *dev)
3063 struct udc_stp_dma *td_stp;
3064 struct udc_data_dma *td_data;
3067 /* consistent DMA mode setting ? */
3069 use_dma_bufferfill_mode = 0;
3072 use_dma_bufferfill_mode = 1;
3076 dev->data_requests = dma_pool_create("data_requests", dev->dev,
3077 sizeof(struct udc_data_dma), 0, 0);
3078 if (!dev->data_requests) {
3079 DBG(dev, "can't get request data pool\n");
3083 /* EP0 in dma regs = dev control regs */
3084 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3086 /* dma desc for setup data */
3087 dev->stp_requests = dma_pool_create("setup requests", dev->dev,
3088 sizeof(struct udc_stp_dma), 0, 0);
3089 if (!dev->stp_requests) {
3090 DBG(dev, "can't get stp request pool\n");
3092 goto err_create_dma_pool;
3095 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3096 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3101 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3103 /* data: 0 packets !? */
3104 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3105 &dev->ep[UDC_EP0OUT_IX].td_phys);
3108 goto err_alloc_phys;
3110 dev->ep[UDC_EP0OUT_IX].td = td_data;
3114 dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3115 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3117 dma_pool_destroy(dev->stp_requests);
3118 dev->stp_requests = NULL;
3119 err_create_dma_pool:
3120 dma_pool_destroy(dev->data_requests);
3121 dev->data_requests = NULL;
3124 EXPORT_SYMBOL_GPL(init_dma_pools);
3127 int udc_probe(struct udc *dev)
3133 /* device struct setup */
3134 dev->gadget.ops = &udc_ops;
3136 dev_set_name(&dev->gadget.dev, "gadget");
3137 dev->gadget.name = name;
3138 dev->gadget.max_speed = USB_SPEED_HIGH;
3140 /* init registers, interrupts, ... */
3141 startup_registers(dev);
3143 dev_info(dev->dev, "%s\n", mod_desc);
3145 snprintf(tmp, sizeof(tmp), "%d", dev->irq);
3147 /* Print this device info for AMD chips only*/
3148 if (dev->chiprev == UDC_HSA0_REV ||
3149 dev->chiprev == UDC_HSB1_REV) {
3150 dev_info(dev->dev, "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3151 tmp, dev->phys_addr, dev->chiprev,
3152 (dev->chiprev == UDC_HSA0_REV) ?
3154 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3155 if (dev->chiprev == UDC_HSA0_REV) {
3156 dev_err(dev->dev, "chip revision is A0; too old\n");
3161 "driver version: %s(for Geode5536 B1)\n", tmp);
3166 retval = usb_add_gadget_udc_release(udc->dev, &dev->gadget,
3172 timer_setup(&udc_timer, udc_timer_function, 0);
3173 timer_setup(&udc_pollstall_timer, udc_pollstall_timer_function, 0);
3176 reg = readl(&dev->regs->ctl);
3177 reg |= AMD_BIT(UDC_DEVCTL_SD);
3178 writel(reg, &dev->regs->ctl);
3180 /* print dev register info */
3188 EXPORT_SYMBOL_GPL(udc_probe);
3190 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3191 MODULE_AUTHOR("Thomas Dahlmann");
3192 MODULE_LICENSE("GPL");