2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <linux/list.h>
15 #include <linux/interrupt.h>
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18 #include <linux/gpio.h>
19 #include <linux/irq.h>
21 /* GPIO port for VBUS detecting */
22 static int vbus_gpio_port = -1; /* GPIO port number (-1:Not used) */
24 #define PCH_VBUS_PERIOD 3000 /* VBUS polling period (msec) */
25 #define PCH_VBUS_INTERVAL 10 /* VBUS polling interval (msec) */
27 /* Address offset of Registers */
28 #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
30 #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
31 #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
32 #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
33 #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
34 #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
35 #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
36 #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
38 #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
39 #define UDC_DEVCTL_ADDR 0x404 /* Device control */
40 #define UDC_DEVSTS_ADDR 0x408 /* Device status */
41 #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
42 #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
43 #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
44 #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
45 #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
46 #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
47 #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
48 #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
50 /* Endpoint control register */
52 #define UDC_EPCTL_MRXFLUSH (1 << 12)
53 #define UDC_EPCTL_RRDY (1 << 9)
54 #define UDC_EPCTL_CNAK (1 << 8)
55 #define UDC_EPCTL_SNAK (1 << 7)
56 #define UDC_EPCTL_NAK (1 << 6)
57 #define UDC_EPCTL_P (1 << 3)
58 #define UDC_EPCTL_F (1 << 1)
59 #define UDC_EPCTL_S (1 << 0)
60 #define UDC_EPCTL_ET_SHIFT 4
62 #define UDC_EPCTL_ET_MASK 0x00000030
63 /* Value for ET field */
64 #define UDC_EPCTL_ET_CONTROL 0
65 #define UDC_EPCTL_ET_ISO 1
66 #define UDC_EPCTL_ET_BULK 2
67 #define UDC_EPCTL_ET_INTERRUPT 3
69 /* Endpoint status register */
71 #define UDC_EPSTS_XFERDONE (1 << 27)
72 #define UDC_EPSTS_RSS (1 << 26)
73 #define UDC_EPSTS_RCS (1 << 25)
74 #define UDC_EPSTS_TXEMPTY (1 << 24)
75 #define UDC_EPSTS_TDC (1 << 10)
76 #define UDC_EPSTS_HE (1 << 9)
77 #define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
78 #define UDC_EPSTS_BNA (1 << 7)
79 #define UDC_EPSTS_IN (1 << 6)
80 #define UDC_EPSTS_OUT_SHIFT 4
82 #define UDC_EPSTS_OUT_MASK 0x00000030
83 #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
84 /* Value for OUT field */
85 #define UDC_EPSTS_OUT_SETUP 2
86 #define UDC_EPSTS_OUT_DATA 1
88 /* Device configuration register */
90 #define UDC_DEVCFG_CSR_PRG (1 << 17)
91 #define UDC_DEVCFG_SP (1 << 3)
93 #define UDC_DEVCFG_SPD_HS 0x0
94 #define UDC_DEVCFG_SPD_FS 0x1
95 #define UDC_DEVCFG_SPD_LS 0x2
97 /* Device control register */
99 #define UDC_DEVCTL_THLEN_SHIFT 24
100 #define UDC_DEVCTL_BRLEN_SHIFT 16
101 #define UDC_DEVCTL_CSR_DONE (1 << 13)
102 #define UDC_DEVCTL_SD (1 << 10)
103 #define UDC_DEVCTL_MODE (1 << 9)
104 #define UDC_DEVCTL_BREN (1 << 8)
105 #define UDC_DEVCTL_THE (1 << 7)
106 #define UDC_DEVCTL_DU (1 << 4)
107 #define UDC_DEVCTL_TDE (1 << 3)
108 #define UDC_DEVCTL_RDE (1 << 2)
109 #define UDC_DEVCTL_RES (1 << 0)
111 /* Device status register */
113 #define UDC_DEVSTS_TS_SHIFT 18
114 #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
115 #define UDC_DEVSTS_ALT_SHIFT 8
116 #define UDC_DEVSTS_INTF_SHIFT 4
117 #define UDC_DEVSTS_CFG_SHIFT 0
119 #define UDC_DEVSTS_TS_MASK 0xfffc0000
120 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
121 #define UDC_DEVSTS_ALT_MASK 0x00000f00
122 #define UDC_DEVSTS_INTF_MASK 0x000000f0
123 #define UDC_DEVSTS_CFG_MASK 0x0000000f
124 /* value for maximum speed for SPEED field */
125 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
126 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
127 #define UDC_DEVSTS_ENUM_SPEED_LOW 2
128 #define UDC_DEVSTS_ENUM_SPEED_FULLX 3
130 /* Device irq register */
132 #define UDC_DEVINT_RWKP (1 << 7)
133 #define UDC_DEVINT_ENUM (1 << 6)
134 #define UDC_DEVINT_SOF (1 << 5)
135 #define UDC_DEVINT_US (1 << 4)
136 #define UDC_DEVINT_UR (1 << 3)
137 #define UDC_DEVINT_ES (1 << 2)
138 #define UDC_DEVINT_SI (1 << 1)
139 #define UDC_DEVINT_SC (1 << 0)
141 #define UDC_DEVINT_MSK 0x7f
143 /* Endpoint irq register */
145 #define UDC_EPINT_IN_SHIFT 0
146 #define UDC_EPINT_OUT_SHIFT 16
147 #define UDC_EPINT_IN_EP0 (1 << 0)
148 #define UDC_EPINT_OUT_EP0 (1 << 16)
150 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
152 /* UDC_CSR_BUSY Status register */
154 #define UDC_CSR_BUSY (1 << 0)
156 /* SOFT RESET register */
158 #define UDC_PSRST (1 << 1)
159 #define UDC_SRST (1 << 0)
161 /* USB_DEVICE endpoint register */
163 #define UDC_CSR_NE_NUM_SHIFT 0
164 #define UDC_CSR_NE_DIR_SHIFT 4
165 #define UDC_CSR_NE_TYPE_SHIFT 5
166 #define UDC_CSR_NE_CFG_SHIFT 7
167 #define UDC_CSR_NE_INTF_SHIFT 11
168 #define UDC_CSR_NE_ALT_SHIFT 15
169 #define UDC_CSR_NE_MAX_PKT_SHIFT 19
171 #define UDC_CSR_NE_NUM_MASK 0x0000000f
172 #define UDC_CSR_NE_DIR_MASK 0x00000010
173 #define UDC_CSR_NE_TYPE_MASK 0x00000060
174 #define UDC_CSR_NE_CFG_MASK 0x00000780
175 #define UDC_CSR_NE_INTF_MASK 0x00007800
176 #define UDC_CSR_NE_ALT_MASK 0x00078000
177 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
179 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
180 #define PCH_UDC_EPINT(in, num)\
181 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
183 /* Index of endpoint */
184 #define UDC_EP0IN_IDX 0
185 #define UDC_EP0OUT_IDX 1
186 #define UDC_EPIN_IDX(ep) (ep * 2)
187 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
188 #define PCH_UDC_EP0 0
189 #define PCH_UDC_EP1 1
190 #define PCH_UDC_EP2 2
191 #define PCH_UDC_EP3 3
193 /* Number of endpoint */
194 #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
195 #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
197 #define PCH_UDC_BRLEN 0x0F /* Burst length */
198 #define PCH_UDC_THLEN 0x1F /* Threshold length */
199 /* Value of EP Buffer Size */
200 #define UDC_EP0IN_BUFF_SIZE 16
201 #define UDC_EPIN_BUFF_SIZE 256
202 #define UDC_EP0OUT_BUFF_SIZE 16
203 #define UDC_EPOUT_BUFF_SIZE 256
204 /* Value of EP maximum packet size */
205 #define UDC_EP0IN_MAX_PKT_SIZE 64
206 #define UDC_EP0OUT_MAX_PKT_SIZE 64
207 #define UDC_BULK_MAX_PKT_SIZE 512
210 #define DMA_DIR_RX 1 /* DMA for data receive */
211 #define DMA_DIR_TX 2 /* DMA for data transmit */
212 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
213 #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
216 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
218 * @status: Status quadlet
219 * @reserved: Reserved
220 * @dataptr: Buffer descriptor
221 * @next: Next descriptor
223 struct pch_udc_data_dma_desc {
231 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
234 * @reserved: Reserved
235 * @data12: First setup word
236 * @data34: Second setup word
238 struct pch_udc_stp_dma_desc {
241 struct usb_ctrlrequest request;
242 } __attribute((packed));
244 /* DMA status definitions */
246 #define PCH_UDC_BUFF_STS 0xC0000000
247 #define PCH_UDC_BS_HST_RDY 0x00000000
248 #define PCH_UDC_BS_DMA_BSY 0x40000000
249 #define PCH_UDC_BS_DMA_DONE 0x80000000
250 #define PCH_UDC_BS_HST_BSY 0xC0000000
252 #define PCH_UDC_RXTX_STS 0x30000000
253 #define PCH_UDC_RTS_SUCC 0x00000000
254 #define PCH_UDC_RTS_DESERR 0x10000000
255 #define PCH_UDC_RTS_BUFERR 0x30000000
256 /* Last Descriptor Indication */
257 #define PCH_UDC_DMA_LAST 0x08000000
258 /* Number of Rx/Tx Bytes Mask */
259 #define PCH_UDC_RXTX_BYTES 0x0000ffff
262 * struct pch_udc_cfg_data - Structure to hold current configuration
263 * and interface information
264 * @cur_cfg: current configuration in use
265 * @cur_intf: current interface in use
266 * @cur_alt: current alt interface in use
268 struct pch_udc_cfg_data {
275 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
276 * @ep: embedded ep request
277 * @td_stp_phys: for setup request
278 * @td_data_phys: for data request
279 * @td_stp: for setup request
280 * @td_data: for data request
281 * @dev: reference to device struct
282 * @offset_addr: offset address of ep register
284 * @queue: queue for requests
285 * @num: endpoint number
286 * @in: endpoint is IN
287 * @halted: endpoint halted?
288 * @epsts: Endpoint status
292 dma_addr_t td_stp_phys;
293 dma_addr_t td_data_phys;
294 struct pch_udc_stp_dma_desc *td_stp;
295 struct pch_udc_data_dma_desc *td_data;
296 struct pch_udc_dev *dev;
297 unsigned long offset_addr;
298 struct list_head queue;
306 * struct pch_vbus_gpio_data - Structure holding GPIO informaton
308 * @port: gpio port number
309 * @intr: gpio interrupt number
310 * @irq_work_fall Structure for WorkQueue
311 * @irq_work_rise Structure for WorkQueue
313 struct pch_vbus_gpio_data {
316 struct work_struct irq_work_fall;
317 struct work_struct irq_work_rise;
321 * struct pch_udc_dev - Structure holding complete information
322 * of the PCH USB device
323 * @gadget: gadget driver data
324 * @driver: reference to gadget driver bound
325 * @pdev: reference to the PCI device
326 * @ep: array of endpoints
327 * @lock: protects all state
328 * @active: enabled the PCI device
329 * @stall: stall requested
330 * @prot_stall: protcol stall requested
331 * @irq_registered: irq registered with system
332 * @mem_region: device memory mapped
333 * @registered: driver registered with system
334 * @suspended: driver in suspended state
335 * @connected: gadget driver associated
336 * @vbus_session: required vbus_session state
337 * @set_cfg_not_acked: pending acknowledgement 4 setup
338 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
339 * @data_requests: DMA pool for data requests
340 * @stp_requests: DMA pool for setup requests
341 * @dma_addr: DMA pool for received
342 * @ep0out_buf: Buffer for DMA
343 * @setup_data: Received setup data
344 * @phys_addr: of device memory
345 * @base_addr: for mapped device memory
346 * @bar: Indicates which PCI BAR for USB regs
347 * @irq: IRQ line for the device
348 * @cfg_data: current cfg, intf, and alt in use
349 * @vbus_gpio: GPIO informaton for detecting VBUS
352 struct usb_gadget gadget;
353 struct usb_gadget_driver *driver;
354 struct pci_dev *pdev;
355 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
356 spinlock_t lock; /* protects all state */
367 struct pci_pool *data_requests;
368 struct pci_pool *stp_requests;
371 struct usb_ctrlrequest setup_data;
372 unsigned long phys_addr;
373 void __iomem *base_addr;
376 struct pch_udc_cfg_data cfg_data;
377 struct pch_vbus_gpio_data vbus_gpio;
379 #define to_pch_udc(g) (container_of((g), struct pch_udc_dev, gadget))
381 #define PCH_UDC_PCI_BAR_QUARK_X1000 0
382 #define PCH_UDC_PCI_BAR 1
383 #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
384 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC 0x0939
385 #define PCI_VENDOR_ID_ROHM 0x10DB
386 #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
387 #define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
389 static const char ep0_string[] = "ep0in";
390 static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
391 static bool speed_fs;
392 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
393 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
396 * struct pch_udc_request - Structure holding a PCH USB device request packet
397 * @req: embedded ep request
398 * @td_data_phys: phys. address
399 * @td_data: first dma desc. of chain
400 * @td_data_last: last dma desc. of chain
401 * @queue: associated queue
402 * @dma_going: DMA in progress for request
403 * @dma_mapped: DMA memory mapped for request
404 * @dma_done: DMA completed for request
405 * @chain_len: chain length
406 * @buf: Buffer memory for align adjustment
407 * @dma: DMA memory for align adjustment
409 struct pch_udc_request {
410 struct usb_request req;
411 dma_addr_t td_data_phys;
412 struct pch_udc_data_dma_desc *td_data;
413 struct pch_udc_data_dma_desc *td_data_last;
414 struct list_head queue;
415 unsigned dma_going:1,
423 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
425 return ioread32(dev->base_addr + reg);
428 static inline void pch_udc_writel(struct pch_udc_dev *dev,
429 unsigned long val, unsigned long reg)
431 iowrite32(val, dev->base_addr + reg);
434 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
436 unsigned long bitmask)
438 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
441 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
443 unsigned long bitmask)
445 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
448 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
450 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
453 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
454 unsigned long val, unsigned long reg)
456 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
459 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
461 unsigned long bitmask)
463 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
466 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
468 unsigned long bitmask)
470 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
474 * pch_udc_csr_busy() - Wait till idle.
475 * @dev: Reference to pch_udc_dev structure
477 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
479 unsigned int count = 200;
482 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
486 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
490 * pch_udc_write_csr() - Write the command and status registers.
491 * @dev: Reference to pch_udc_dev structure
492 * @val: value to be written to CSR register
493 * @addr: address of CSR register
495 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
498 unsigned long reg = PCH_UDC_CSR(ep);
500 pch_udc_csr_busy(dev); /* Wait till idle */
501 pch_udc_writel(dev, val, reg);
502 pch_udc_csr_busy(dev); /* Wait till idle */
506 * pch_udc_read_csr() - Read the command and status registers.
507 * @dev: Reference to pch_udc_dev structure
508 * @addr: address of CSR register
510 * Return codes: content of CSR register
512 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
514 unsigned long reg = PCH_UDC_CSR(ep);
516 pch_udc_csr_busy(dev); /* Wait till idle */
517 pch_udc_readl(dev, reg); /* Dummy read */
518 pch_udc_csr_busy(dev); /* Wait till idle */
519 return pch_udc_readl(dev, reg);
523 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
524 * @dev: Reference to pch_udc_dev structure
526 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
528 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
530 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
534 * pch_udc_get_frame() - Get the current frame from device status register
535 * @dev: Reference to pch_udc_dev structure
536 * Retern current frame
538 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
540 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
541 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
545 * pch_udc_clear_selfpowered() - Clear the self power control
546 * @dev: Reference to pch_udc_regs structure
548 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
550 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
554 * pch_udc_set_selfpowered() - Set the self power control
555 * @dev: Reference to pch_udc_regs structure
557 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
559 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
563 * pch_udc_set_disconnect() - Set the disconnect status.
564 * @dev: Reference to pch_udc_regs structure
566 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
568 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
572 * pch_udc_clear_disconnect() - Clear the disconnect status.
573 * @dev: Reference to pch_udc_regs structure
575 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
577 /* Clear the disconnect */
578 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
579 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
581 /* Resume USB signalling */
582 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
586 * pch_udc_reconnect() - This API initializes usb device controller,
587 * and clear the disconnect status.
588 * @dev: Reference to pch_udc_regs structure
590 static void pch_udc_init(struct pch_udc_dev *dev);
591 static void pch_udc_reconnect(struct pch_udc_dev *dev)
595 /* enable device interrupts */
596 /* pch_udc_enable_interrupts() */
597 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
598 UDC_DEVINT_UR | UDC_DEVINT_ENUM);
600 /* Clear the disconnect */
601 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
602 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
604 /* Resume USB signalling */
605 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
609 * pch_udc_vbus_session() - set or clearr the disconnect status.
610 * @dev: Reference to pch_udc_regs structure
611 * @is_active: Parameter specifying the action
612 * 0: indicating VBUS power is ending
613 * !0: indicating VBUS power is starting
615 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
618 unsigned long iflags;
620 spin_lock_irqsave(&dev->lock, iflags);
622 pch_udc_reconnect(dev);
623 dev->vbus_session = 1;
625 if (dev->driver && dev->driver->disconnect) {
626 spin_unlock_irqrestore(&dev->lock, iflags);
627 dev->driver->disconnect(&dev->gadget);
628 spin_lock_irqsave(&dev->lock, iflags);
630 pch_udc_set_disconnect(dev);
631 dev->vbus_session = 0;
633 spin_unlock_irqrestore(&dev->lock, iflags);
637 * pch_udc_ep_set_stall() - Set the stall of endpoint
638 * @ep: Reference to structure of type pch_udc_ep_regs
640 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
643 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
644 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
646 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
651 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
652 * @ep: Reference to structure of type pch_udc_ep_regs
654 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
656 /* Clear the stall */
657 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
658 /* Clear NAK by writing CNAK */
659 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
663 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
664 * @ep: Reference to structure of type pch_udc_ep_regs
665 * @type: Type of endpoint
667 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
670 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
671 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
675 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
676 * @ep: Reference to structure of type pch_udc_ep_regs
677 * @buf_size: The buffer word size
679 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
680 u32 buf_size, u32 ep_in)
684 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
685 data = (data & 0xffff0000) | (buf_size & 0xffff);
686 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
688 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
689 data = (buf_size << 16) | (data & 0xffff);
690 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
695 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
696 * @ep: Reference to structure of type pch_udc_ep_regs
697 * @pkt_size: The packet byte size
699 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
701 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
702 data = (data & 0xffff0000) | (pkt_size & 0xffff);
703 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
707 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
708 * @ep: Reference to structure of type pch_udc_ep_regs
709 * @addr: Address of the register
711 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
713 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
717 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
718 * @ep: Reference to structure of type pch_udc_ep_regs
719 * @addr: Address of the register
721 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
723 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
727 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
728 * @ep: Reference to structure of type pch_udc_ep_regs
730 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
732 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
736 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
737 * @ep: Reference to structure of type pch_udc_ep_regs
739 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
741 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
745 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
746 * @ep: Reference to structure of type pch_udc_ep_regs
748 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
750 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
754 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
755 * register depending on the direction specified
756 * @dev: Reference to structure of type pch_udc_regs
757 * @dir: whether Tx or Rx
758 * DMA_DIR_RX: Receive
759 * DMA_DIR_TX: Transmit
761 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
763 if (dir == DMA_DIR_RX)
764 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
765 else if (dir == DMA_DIR_TX)
766 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
770 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
771 * register depending on the direction specified
772 * @dev: Reference to structure of type pch_udc_regs
773 * @dir: Whether Tx or Rx
774 * DMA_DIR_RX: Receive
775 * DMA_DIR_TX: Transmit
777 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
779 if (dir == DMA_DIR_RX)
780 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
781 else if (dir == DMA_DIR_TX)
782 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
786 * pch_udc_set_csr_done() - Set the device control register
787 * CSR done field (bit 13)
788 * @dev: reference to structure of type pch_udc_regs
790 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
792 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
796 * pch_udc_disable_interrupts() - Disables the specified interrupts
797 * @dev: Reference to structure of type pch_udc_regs
798 * @mask: Mask to disable interrupts
800 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
803 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
807 * pch_udc_enable_interrupts() - Enable the specified interrupts
808 * @dev: Reference to structure of type pch_udc_regs
809 * @mask: Mask to enable interrupts
811 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
814 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
818 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
819 * @dev: Reference to structure of type pch_udc_regs
820 * @mask: Mask to disable interrupts
822 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
825 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
829 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
830 * @dev: Reference to structure of type pch_udc_regs
831 * @mask: Mask to enable interrupts
833 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
836 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
840 * pch_udc_read_device_interrupts() - Read the device interrupts
841 * @dev: Reference to structure of type pch_udc_regs
842 * Retern The device interrupts
844 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
846 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
850 * pch_udc_write_device_interrupts() - Write device interrupts
851 * @dev: Reference to structure of type pch_udc_regs
852 * @val: The value to be written to interrupt register
854 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
857 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
861 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
862 * @dev: Reference to structure of type pch_udc_regs
863 * Retern The endpoint interrupt
865 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
867 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
871 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
872 * @dev: Reference to structure of type pch_udc_regs
873 * @val: The value to be written to interrupt register
875 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
878 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
882 * pch_udc_read_device_status() - Read the device status
883 * @dev: Reference to structure of type pch_udc_regs
884 * Retern The device status
886 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
888 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
892 * pch_udc_read_ep_control() - Read the endpoint control
893 * @ep: Reference to structure of type pch_udc_ep_regs
894 * Retern The endpoint control register value
896 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
898 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
902 * pch_udc_clear_ep_control() - Clear the endpoint control register
903 * @ep: Reference to structure of type pch_udc_ep_regs
904 * Retern The endpoint control register value
906 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
908 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
912 * pch_udc_read_ep_status() - Read the endpoint status
913 * @ep: Reference to structure of type pch_udc_ep_regs
914 * Retern The endpoint status
916 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
918 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
922 * pch_udc_clear_ep_status() - Clear the endpoint status
923 * @ep: Reference to structure of type pch_udc_ep_regs
924 * @stat: Endpoint status
926 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
929 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
933 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
934 * of the endpoint control register
935 * @ep: Reference to structure of type pch_udc_ep_regs
937 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
939 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
943 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
944 * of the endpoint control register
945 * @ep: reference to structure of type pch_udc_ep_regs
947 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
949 unsigned int loopcnt = 0;
950 struct pch_udc_dev *dev = ep->dev;
952 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
956 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
960 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
964 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
965 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
969 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
970 __func__, ep->num, (ep->in ? "in" : "out"));
974 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
975 * @ep: reference to structure of type pch_udc_ep_regs
976 * @dir: direction of endpoint
980 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
982 if (dir) { /* IN ep */
983 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
989 * pch_udc_ep_enable() - This api enables endpoint
990 * @regs: Reference to structure pch_udc_ep_regs
991 * @desc: endpoint descriptor
993 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
994 struct pch_udc_cfg_data *cfg,
995 const struct usb_endpoint_descriptor *desc)
1000 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
1002 buff_size = UDC_EPIN_BUFF_SIZE;
1004 buff_size = UDC_EPOUT_BUFF_SIZE;
1005 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
1006 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
1007 pch_udc_ep_set_nak(ep);
1008 pch_udc_ep_fifo_flush(ep, ep->in);
1009 /* Configure the endpoint */
1010 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
1011 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
1012 UDC_CSR_NE_TYPE_SHIFT) |
1013 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
1014 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
1015 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
1016 usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
1019 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1021 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1025 * pch_udc_ep_disable() - This api disables endpoint
1026 * @regs: Reference to structure pch_udc_ep_regs
1028 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1031 /* flush the fifo */
1032 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1034 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1035 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1038 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1040 /* reset desc pointer */
1041 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1045 * pch_udc_wait_ep_stall() - Wait EP stall.
1046 * @dev: Reference to pch_udc_dev structure
1048 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1050 unsigned int count = 10000;
1052 /* Wait till idle */
1053 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1056 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1060 * pch_udc_init() - This API initializes usb device controller
1061 * @dev: Rreference to pch_udc_regs structure
1063 static void pch_udc_init(struct pch_udc_dev *dev)
1066 pr_err("%s: Invalid address\n", __func__);
1069 /* Soft Reset and Reset PHY */
1070 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1071 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1073 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1074 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1076 /* mask and clear all device interrupts */
1077 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1078 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1080 /* mask and clear all ep interrupts */
1081 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1082 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1084 /* enable dynamic CSR programmingi, self powered and device speed */
1086 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1087 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1088 else /* defaul high speed */
1089 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1090 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1091 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1092 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1093 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1094 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1099 * pch_udc_exit() - This API exit usb device controller
1100 * @dev: Reference to pch_udc_regs structure
1102 static void pch_udc_exit(struct pch_udc_dev *dev)
1104 /* mask all device interrupts */
1105 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1106 /* mask all ep interrupts */
1107 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1108 /* put device in disconnected state */
1109 pch_udc_set_disconnect(dev);
1113 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1114 * @gadget: Reference to the gadget driver
1118 * -EINVAL: If the gadget passed is NULL
1120 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1122 struct pch_udc_dev *dev;
1126 dev = container_of(gadget, struct pch_udc_dev, gadget);
1127 return pch_udc_get_frame(dev);
1131 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1132 * @gadget: Reference to the gadget driver
1136 * -EINVAL: If the gadget passed is NULL
1138 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1140 struct pch_udc_dev *dev;
1141 unsigned long flags;
1145 dev = container_of(gadget, struct pch_udc_dev, gadget);
1146 spin_lock_irqsave(&dev->lock, flags);
1147 pch_udc_rmt_wakeup(dev);
1148 spin_unlock_irqrestore(&dev->lock, flags);
1153 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1154 * is self powered or not
1155 * @gadget: Reference to the gadget driver
1156 * @value: Specifies self powered or not
1160 * -EINVAL: If the gadget passed is NULL
1162 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1164 struct pch_udc_dev *dev;
1168 gadget->is_selfpowered = (value != 0);
1169 dev = container_of(gadget, struct pch_udc_dev, gadget);
1171 pch_udc_set_selfpowered(dev);
1173 pch_udc_clear_selfpowered(dev);
1178 * pch_udc_pcd_pullup() - This API is invoked to make the device
1179 * visible/invisible to the host
1180 * @gadget: Reference to the gadget driver
1181 * @is_on: Specifies whether the pull up is made active or inactive
1185 * -EINVAL: If the gadget passed is NULL
1187 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1189 struct pch_udc_dev *dev;
1190 unsigned long iflags;
1195 dev = container_of(gadget, struct pch_udc_dev, gadget);
1197 spin_lock_irqsave(&dev->lock, iflags);
1199 pch_udc_reconnect(dev);
1201 if (dev->driver && dev->driver->disconnect) {
1202 spin_unlock_irqrestore(&dev->lock, iflags);
1203 dev->driver->disconnect(&dev->gadget);
1204 spin_lock_irqsave(&dev->lock, iflags);
1206 pch_udc_set_disconnect(dev);
1208 spin_unlock_irqrestore(&dev->lock, iflags);
1214 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1215 * transceiver (or GPIO) that
1216 * detects a VBUS power session starting/ending
1217 * @gadget: Reference to the gadget driver
1218 * @is_active: specifies whether the session is starting or ending
1222 * -EINVAL: If the gadget passed is NULL
1224 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1226 struct pch_udc_dev *dev;
1230 dev = container_of(gadget, struct pch_udc_dev, gadget);
1231 pch_udc_vbus_session(dev, is_active);
1236 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1237 * SET_CONFIGURATION calls to
1238 * specify how much power the device can consume
1239 * @gadget: Reference to the gadget driver
1240 * @mA: specifies the current limit in 2mA unit
1243 * -EINVAL: If the gadget passed is NULL
1246 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1251 static int pch_udc_start(struct usb_gadget *g,
1252 struct usb_gadget_driver *driver);
1253 static int pch_udc_stop(struct usb_gadget *g);
1255 static const struct usb_gadget_ops pch_udc_ops = {
1256 .get_frame = pch_udc_pcd_get_frame,
1257 .wakeup = pch_udc_pcd_wakeup,
1258 .set_selfpowered = pch_udc_pcd_selfpowered,
1259 .pullup = pch_udc_pcd_pullup,
1260 .vbus_session = pch_udc_pcd_vbus_session,
1261 .vbus_draw = pch_udc_pcd_vbus_draw,
1262 .udc_start = pch_udc_start,
1263 .udc_stop = pch_udc_stop,
1267 * pch_vbus_gpio_get_value() - This API gets value of GPIO port as VBUS status.
1268 * @dev: Reference to the driver structure
1273 * -1: It is not enable to detect VBUS using GPIO
1275 static int pch_vbus_gpio_get_value(struct pch_udc_dev *dev)
1279 if (dev->vbus_gpio.port)
1280 vbus = gpio_get_value(dev->vbus_gpio.port) ? 1 : 0;
1288 * pch_vbus_gpio_work_fall() - This API keeps watch on VBUS becoming Low.
1289 * If VBUS is Low, disconnect is processed
1290 * @irq_work: Structure for WorkQueue
1293 static void pch_vbus_gpio_work_fall(struct work_struct *irq_work)
1295 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1296 struct pch_vbus_gpio_data, irq_work_fall);
1297 struct pch_udc_dev *dev =
1298 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1299 int vbus_saved = -1;
1303 if (!dev->vbus_gpio.port)
1306 for (count = 0; count < (PCH_VBUS_PERIOD / PCH_VBUS_INTERVAL);
1308 vbus = pch_vbus_gpio_get_value(dev);
1310 if ((vbus_saved == vbus) && (vbus == 0)) {
1311 dev_dbg(&dev->pdev->dev, "VBUS fell");
1313 && dev->driver->disconnect) {
1314 dev->driver->disconnect(
1317 if (dev->vbus_gpio.intr)
1320 pch_udc_reconnect(dev);
1324 mdelay(PCH_VBUS_INTERVAL);
1329 * pch_vbus_gpio_work_rise() - This API checks VBUS is High.
1330 * If VBUS is High, connect is processed
1331 * @irq_work: Structure for WorkQueue
1334 static void pch_vbus_gpio_work_rise(struct work_struct *irq_work)
1336 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1337 struct pch_vbus_gpio_data, irq_work_rise);
1338 struct pch_udc_dev *dev =
1339 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1342 if (!dev->vbus_gpio.port)
1345 mdelay(PCH_VBUS_INTERVAL);
1346 vbus = pch_vbus_gpio_get_value(dev);
1349 dev_dbg(&dev->pdev->dev, "VBUS rose");
1350 pch_udc_reconnect(dev);
1356 * pch_vbus_gpio_irq() - IRQ handler for GPIO intrerrupt for changing VBUS
1357 * @irq: Interrupt request number
1358 * @dev: Reference to the device structure
1362 * -EINVAL: GPIO port is invalid or can't be initialized.
1364 static irqreturn_t pch_vbus_gpio_irq(int irq, void *data)
1366 struct pch_udc_dev *dev = (struct pch_udc_dev *)data;
1368 if (!dev->vbus_gpio.port || !dev->vbus_gpio.intr)
1371 if (pch_vbus_gpio_get_value(dev))
1372 schedule_work(&dev->vbus_gpio.irq_work_rise);
1374 schedule_work(&dev->vbus_gpio.irq_work_fall);
1380 * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS.
1381 * @dev: Reference to the driver structure
1382 * @vbus_gpio Number of GPIO port to detect gpio
1386 * -EINVAL: GPIO port is invalid or can't be initialized.
1388 static int pch_vbus_gpio_init(struct pch_udc_dev *dev, int vbus_gpio_port)
1393 dev->vbus_gpio.port = 0;
1394 dev->vbus_gpio.intr = 0;
1396 if (vbus_gpio_port <= -1)
1399 err = gpio_is_valid(vbus_gpio_port);
1401 pr_err("%s: gpio port %d is invalid\n",
1402 __func__, vbus_gpio_port);
1406 err = gpio_request(vbus_gpio_port, "pch_vbus");
1408 pr_err("%s: can't request gpio port %d, err: %d\n",
1409 __func__, vbus_gpio_port, err);
1413 dev->vbus_gpio.port = vbus_gpio_port;
1414 gpio_direction_input(vbus_gpio_port);
1415 INIT_WORK(&dev->vbus_gpio.irq_work_fall, pch_vbus_gpio_work_fall);
1417 irq_num = gpio_to_irq(vbus_gpio_port);
1419 irq_set_irq_type(irq_num, IRQ_TYPE_EDGE_BOTH);
1420 err = request_irq(irq_num, pch_vbus_gpio_irq, 0,
1421 "vbus_detect", dev);
1423 dev->vbus_gpio.intr = irq_num;
1424 INIT_WORK(&dev->vbus_gpio.irq_work_rise,
1425 pch_vbus_gpio_work_rise);
1427 pr_err("%s: can't request irq %d, err: %d\n",
1428 __func__, irq_num, err);
1436 * pch_vbus_gpio_free() - This API frees resources of GPIO port
1437 * @dev: Reference to the driver structure
1439 static void pch_vbus_gpio_free(struct pch_udc_dev *dev)
1441 if (dev->vbus_gpio.intr)
1442 free_irq(dev->vbus_gpio.intr, dev);
1444 if (dev->vbus_gpio.port)
1445 gpio_free(dev->vbus_gpio.port);
1449 * complete_req() - This API is invoked from the driver when processing
1450 * of a request is complete
1451 * @ep: Reference to the endpoint structure
1452 * @req: Reference to the request structure
1453 * @status: Indicates the success/failure of completion
1455 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1457 __releases(&dev->lock)
1458 __acquires(&dev->lock)
1460 struct pch_udc_dev *dev;
1461 unsigned halted = ep->halted;
1463 list_del_init(&req->queue);
1465 /* set new status if pending */
1466 if (req->req.status == -EINPROGRESS)
1467 req->req.status = status;
1469 status = req->req.status;
1472 if (req->dma_mapped) {
1473 if (req->dma == DMA_ADDR_INVALID) {
1475 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1479 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1482 req->req.dma = DMA_ADDR_INVALID;
1485 dma_unmap_single(&dev->pdev->dev, req->dma,
1489 dma_unmap_single(&dev->pdev->dev, req->dma,
1492 memcpy(req->req.buf, req->buf, req->req.length);
1495 req->dma = DMA_ADDR_INVALID;
1497 req->dma_mapped = 0;
1500 spin_unlock(&dev->lock);
1502 pch_udc_ep_clear_rrdy(ep);
1503 usb_gadget_giveback_request(&ep->ep, &req->req);
1504 spin_lock(&dev->lock);
1505 ep->halted = halted;
1509 * empty_req_queue() - This API empties the request queue of an endpoint
1510 * @ep: Reference to the endpoint structure
1512 static void empty_req_queue(struct pch_udc_ep *ep)
1514 struct pch_udc_request *req;
1517 while (!list_empty(&ep->queue)) {
1518 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1519 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1524 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1526 * @dev Reference to the driver structure
1527 * @req Reference to the request to be freed
1532 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1533 struct pch_udc_request *req)
1535 struct pch_udc_data_dma_desc *td = req->td_data;
1536 unsigned i = req->chain_len;
1539 dma_addr_t addr = (dma_addr_t)td->next;
1541 for (; i > 1; --i) {
1542 /* do not free first desc., will be done by free for request */
1543 td = phys_to_virt(addr);
1544 addr2 = (dma_addr_t)td->next;
1545 pci_pool_free(dev->data_requests, td, addr);
1552 * pch_udc_create_dma_chain() - This function creates or reinitializes
1554 * @ep: Reference to the endpoint structure
1555 * @req: Reference to the request
1556 * @buf_len: The buffer length
1557 * @gfp_flags: Flags to be used while mapping the data buffer
1561 * -ENOMEM: pci_pool_alloc invocation fails
1563 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1564 struct pch_udc_request *req,
1565 unsigned long buf_len,
1568 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1569 unsigned long bytes = req->req.length, i = 0;
1570 dma_addr_t dma_addr;
1573 if (req->chain_len > 1)
1574 pch_udc_free_dma_chain(ep->dev, req);
1576 if (req->dma == DMA_ADDR_INVALID)
1577 td->dataptr = req->req.dma;
1579 td->dataptr = req->dma;
1581 td->status = PCH_UDC_BS_HST_BSY;
1582 for (; ; bytes -= buf_len, ++len) {
1583 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1584 if (bytes <= buf_len)
1587 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1592 td->dataptr = req->td_data->dataptr + i;
1593 last->next = dma_addr;
1596 req->td_data_last = td;
1597 td->status |= PCH_UDC_DMA_LAST;
1598 td->next = req->td_data_phys;
1599 req->chain_len = len;
1604 req->chain_len = len;
1605 pch_udc_free_dma_chain(ep->dev, req);
1612 * prepare_dma() - This function creates and initializes the DMA chain
1614 * @ep: Reference to the endpoint structure
1615 * @req: Reference to the request
1616 * @gfp: Flag to be used while mapping the data buffer
1620 * Other 0: linux error number on failure
1622 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1627 /* Allocate and create a DMA chain */
1628 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1630 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1634 req->td_data->status = (req->td_data->status &
1635 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1640 * process_zlp() - This function process zero length packets
1641 * from the gadget driver
1642 * @ep: Reference to the endpoint structure
1643 * @req: Reference to the request
1645 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1647 struct pch_udc_dev *dev = ep->dev;
1649 /* IN zlp's are handled by hardware */
1650 complete_req(ep, req, 0);
1652 /* if set_config or set_intf is waiting for ack by zlp
1655 if (dev->set_cfg_not_acked) {
1656 pch_udc_set_csr_done(dev);
1657 dev->set_cfg_not_acked = 0;
1659 /* setup command is ACK'ed now by zlp */
1660 if (!dev->stall && dev->waiting_zlp_ack) {
1661 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1662 dev->waiting_zlp_ack = 0;
1667 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1668 * @ep: Reference to the endpoint structure
1669 * @req: Reference to the request structure
1671 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1672 struct pch_udc_request *req)
1674 struct pch_udc_data_dma_desc *td_data;
1676 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1677 td_data = req->td_data;
1678 /* Set the status bits for all descriptors */
1680 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1682 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1684 td_data = phys_to_virt(td_data->next);
1686 /* Write the descriptor pointer */
1687 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1689 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1690 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1691 pch_udc_ep_clear_nak(ep);
1692 pch_udc_ep_set_rrdy(ep);
1696 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1697 * from gadget driver
1698 * @usbep: Reference to the USB endpoint structure
1699 * @desc: Reference to the USB endpoint descriptor structure
1706 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1707 const struct usb_endpoint_descriptor *desc)
1709 struct pch_udc_ep *ep;
1710 struct pch_udc_dev *dev;
1711 unsigned long iflags;
1713 if (!usbep || (usbep->name == ep0_string) || !desc ||
1714 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1717 ep = container_of(usbep, struct pch_udc_ep, ep);
1719 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1721 spin_lock_irqsave(&dev->lock, iflags);
1724 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1725 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1726 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1727 spin_unlock_irqrestore(&dev->lock, iflags);
1732 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1733 * from gadget driver
1734 * @usbep Reference to the USB endpoint structure
1740 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1742 struct pch_udc_ep *ep;
1743 unsigned long iflags;
1748 ep = container_of(usbep, struct pch_udc_ep, ep);
1749 if ((usbep->name == ep0_string) || !ep->ep.desc)
1752 spin_lock_irqsave(&ep->dev->lock, iflags);
1753 empty_req_queue(ep);
1755 pch_udc_ep_disable(ep);
1756 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1758 INIT_LIST_HEAD(&ep->queue);
1759 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1764 * pch_udc_alloc_request() - This function allocates request structure.
1765 * It is called by gadget driver
1766 * @usbep: Reference to the USB endpoint structure
1767 * @gfp: Flag to be used while allocating memory
1771 * Allocated address: Success
1773 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1776 struct pch_udc_request *req;
1777 struct pch_udc_ep *ep;
1778 struct pch_udc_data_dma_desc *dma_desc;
1782 ep = container_of(usbep, struct pch_udc_ep, ep);
1783 req = kzalloc(sizeof *req, gfp);
1786 req->req.dma = DMA_ADDR_INVALID;
1787 req->dma = DMA_ADDR_INVALID;
1788 INIT_LIST_HEAD(&req->queue);
1789 if (!ep->dev->dma_addr)
1791 /* ep0 in requests are allocated from data pool here */
1792 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1793 &req->td_data_phys);
1794 if (NULL == dma_desc) {
1798 /* prevent from using desc. - set HOST BUSY */
1799 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1800 dma_desc->dataptr = lower_32_bits(DMA_ADDR_INVALID);
1801 req->td_data = dma_desc;
1802 req->td_data_last = dma_desc;
1808 * pch_udc_free_request() - This function frees request structure.
1809 * It is called by gadget driver
1810 * @usbep: Reference to the USB endpoint structure
1811 * @usbreq: Reference to the USB request
1813 static void pch_udc_free_request(struct usb_ep *usbep,
1814 struct usb_request *usbreq)
1816 struct pch_udc_ep *ep;
1817 struct pch_udc_request *req;
1818 struct pch_udc_dev *dev;
1820 if (!usbep || !usbreq)
1822 ep = container_of(usbep, struct pch_udc_ep, ep);
1823 req = container_of(usbreq, struct pch_udc_request, req);
1825 if (!list_empty(&req->queue))
1826 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1827 __func__, usbep->name, req);
1828 if (req->td_data != NULL) {
1829 if (req->chain_len > 1)
1830 pch_udc_free_dma_chain(ep->dev, req);
1831 pci_pool_free(ep->dev->data_requests, req->td_data,
1838 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1840 * @usbep: Reference to the USB endpoint structure
1841 * @usbreq: Reference to the USB request
1842 * @gfp: Flag to be used while mapping the data buffer
1846 * linux error number: Failure
1848 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1852 struct pch_udc_ep *ep;
1853 struct pch_udc_dev *dev;
1854 struct pch_udc_request *req;
1855 unsigned long iflags;
1857 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1859 ep = container_of(usbep, struct pch_udc_ep, ep);
1861 if (!ep->ep.desc && ep->num)
1863 req = container_of(usbreq, struct pch_udc_request, req);
1864 if (!list_empty(&req->queue))
1866 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1868 spin_lock_irqsave(&dev->lock, iflags);
1869 /* map the buffer for dma */
1870 if (usbreq->length &&
1871 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1872 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1874 usbreq->dma = dma_map_single(&dev->pdev->dev,
1879 usbreq->dma = dma_map_single(&dev->pdev->dev,
1884 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1890 memcpy(req->buf, usbreq->buf, usbreq->length);
1891 req->dma = dma_map_single(&dev->pdev->dev,
1896 req->dma = dma_map_single(&dev->pdev->dev,
1901 req->dma_mapped = 1;
1903 if (usbreq->length > 0) {
1904 retval = prepare_dma(ep, req, GFP_ATOMIC);
1909 usbreq->status = -EINPROGRESS;
1911 if (list_empty(&ep->queue) && !ep->halted) {
1912 /* no pending transfer, so start this req */
1913 if (!usbreq->length) {
1914 process_zlp(ep, req);
1919 pch_udc_start_rxrequest(ep, req);
1922 * For IN trfr the descriptors will be programmed and
1923 * P bit will be set when
1924 * we get an IN token
1926 pch_udc_wait_ep_stall(ep);
1927 pch_udc_ep_clear_nak(ep);
1928 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1931 /* Now add this request to the ep's pending requests */
1933 list_add_tail(&req->queue, &ep->queue);
1936 spin_unlock_irqrestore(&dev->lock, iflags);
1941 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1942 * It is called by gadget driver
1943 * @usbep: Reference to the USB endpoint structure
1944 * @usbreq: Reference to the USB request
1948 * linux error number: Failure
1950 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1951 struct usb_request *usbreq)
1953 struct pch_udc_ep *ep;
1954 struct pch_udc_request *req;
1955 unsigned long flags;
1958 ep = container_of(usbep, struct pch_udc_ep, ep);
1959 if (!usbep || !usbreq || (!ep->ep.desc && ep->num))
1961 req = container_of(usbreq, struct pch_udc_request, req);
1962 spin_lock_irqsave(&ep->dev->lock, flags);
1963 /* make sure it's still queued on this endpoint */
1964 list_for_each_entry(req, &ep->queue, queue) {
1965 if (&req->req == usbreq) {
1966 pch_udc_ep_set_nak(ep);
1967 if (!list_empty(&req->queue))
1968 complete_req(ep, req, -ECONNRESET);
1973 spin_unlock_irqrestore(&ep->dev->lock, flags);
1978 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1980 * @usbep: Reference to the USB endpoint structure
1981 * @halt: Specifies whether to set or clear the feature
1985 * linux error number: Failure
1987 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1989 struct pch_udc_ep *ep;
1990 unsigned long iflags;
1995 ep = container_of(usbep, struct pch_udc_ep, ep);
1996 if (!ep->ep.desc && !ep->num)
1998 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2000 spin_lock_irqsave(&udc_stall_spinlock, iflags);
2001 if (list_empty(&ep->queue)) {
2003 if (ep->num == PCH_UDC_EP0)
2005 pch_udc_ep_set_stall(ep);
2006 pch_udc_enable_ep_interrupts(ep->dev,
2007 PCH_UDC_EPINT(ep->in,
2010 pch_udc_ep_clear_stall(ep);
2016 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2021 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
2023 * @usbep: Reference to the USB endpoint structure
2024 * @halt: Specifies whether to set or clear the feature
2028 * linux error number: Failure
2030 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
2032 struct pch_udc_ep *ep;
2033 unsigned long iflags;
2038 ep = container_of(usbep, struct pch_udc_ep, ep);
2039 if (!ep->ep.desc && !ep->num)
2041 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2043 spin_lock_irqsave(&udc_stall_spinlock, iflags);
2044 if (!list_empty(&ep->queue)) {
2047 if (ep->num == PCH_UDC_EP0)
2049 pch_udc_ep_set_stall(ep);
2050 pch_udc_enable_ep_interrupts(ep->dev,
2051 PCH_UDC_EPINT(ep->in, ep->num));
2052 ep->dev->prot_stall = 1;
2055 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2060 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
2061 * @usbep: Reference to the USB endpoint structure
2063 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
2065 struct pch_udc_ep *ep;
2070 ep = container_of(usbep, struct pch_udc_ep, ep);
2071 if (ep->ep.desc || !ep->num)
2072 pch_udc_ep_fifo_flush(ep, ep->in);
2075 static const struct usb_ep_ops pch_udc_ep_ops = {
2076 .enable = pch_udc_pcd_ep_enable,
2077 .disable = pch_udc_pcd_ep_disable,
2078 .alloc_request = pch_udc_alloc_request,
2079 .free_request = pch_udc_free_request,
2080 .queue = pch_udc_pcd_queue,
2081 .dequeue = pch_udc_pcd_dequeue,
2082 .set_halt = pch_udc_pcd_set_halt,
2083 .set_wedge = pch_udc_pcd_set_wedge,
2084 .fifo_status = NULL,
2085 .fifo_flush = pch_udc_pcd_fifo_flush,
2089 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
2090 * @td_stp: Reference to the SETP buffer structure
2092 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
2094 static u32 pky_marker;
2098 td_stp->reserved = ++pky_marker;
2099 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
2100 td_stp->status = PCH_UDC_BS_HST_RDY;
2104 * pch_udc_start_next_txrequest() - This function starts
2105 * the next transmission requirement
2106 * @ep: Reference to the endpoint structure
2108 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2110 struct pch_udc_request *req;
2111 struct pch_udc_data_dma_desc *td_data;
2113 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2116 if (list_empty(&ep->queue))
2120 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2125 pch_udc_wait_ep_stall(ep);
2127 pch_udc_ep_set_ddptr(ep, 0);
2128 td_data = req->td_data;
2130 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
2132 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
2134 td_data = phys_to_virt(td_data->next);
2136 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2137 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2138 pch_udc_ep_set_pd(ep);
2139 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2140 pch_udc_ep_clear_nak(ep);
2144 * pch_udc_complete_transfer() - This function completes a transfer
2145 * @ep: Reference to the endpoint structure
2147 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2149 struct pch_udc_request *req;
2150 struct pch_udc_dev *dev = ep->dev;
2152 if (list_empty(&ep->queue))
2154 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2155 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2156 PCH_UDC_BS_DMA_DONE)
2158 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
2160 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
2161 "epstatus=0x%08x\n",
2162 (req->td_data_last->status & PCH_UDC_RXTX_STS),
2167 req->req.actual = req->req.length;
2168 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2169 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2170 complete_req(ep, req, 0);
2172 if (!list_empty(&ep->queue)) {
2173 pch_udc_wait_ep_stall(ep);
2174 pch_udc_ep_clear_nak(ep);
2175 pch_udc_enable_ep_interrupts(ep->dev,
2176 PCH_UDC_EPINT(ep->in, ep->num));
2178 pch_udc_disable_ep_interrupts(ep->dev,
2179 PCH_UDC_EPINT(ep->in, ep->num));
2184 * pch_udc_complete_receiver() - This function completes a receiver
2185 * @ep: Reference to the endpoint structure
2187 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2189 struct pch_udc_request *req;
2190 struct pch_udc_dev *dev = ep->dev;
2192 struct pch_udc_data_dma_desc *td;
2195 if (list_empty(&ep->queue))
2198 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2199 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
2200 pch_udc_ep_set_ddptr(ep, 0);
2201 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
2202 PCH_UDC_BS_DMA_DONE)
2203 td = req->td_data_last;
2208 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
2209 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2210 "epstatus=0x%08x\n",
2211 (req->td_data->status & PCH_UDC_RXTX_STS),
2215 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2216 if (td->status & PCH_UDC_DMA_LAST) {
2217 count = td->status & PCH_UDC_RXTX_BYTES;
2220 if (td == req->td_data_last) {
2221 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2224 addr = (dma_addr_t)td->next;
2225 td = phys_to_virt(addr);
2227 /* on 64k packets the RXBYTES field is zero */
2228 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2229 count = UDC_DMA_MAXPACKET;
2230 req->td_data->status |= PCH_UDC_DMA_LAST;
2231 td->status |= PCH_UDC_BS_HST_BSY;
2234 req->req.actual = count;
2235 complete_req(ep, req, 0);
2236 /* If there is a new/failed requests try that now */
2237 if (!list_empty(&ep->queue)) {
2238 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2239 pch_udc_start_rxrequest(ep, req);
2244 * pch_udc_svc_data_in() - This function process endpoint interrupts
2246 * @dev: Reference to the device structure
2247 * @ep_num: Endpoint that generated the interrupt
2249 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2252 struct pch_udc_ep *ep;
2254 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2258 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2259 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2260 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2262 if ((epsts & UDC_EPSTS_BNA))
2264 if (epsts & UDC_EPSTS_HE)
2266 if (epsts & UDC_EPSTS_RSS) {
2267 pch_udc_ep_set_stall(ep);
2268 pch_udc_enable_ep_interrupts(ep->dev,
2269 PCH_UDC_EPINT(ep->in, ep->num));
2271 if (epsts & UDC_EPSTS_RCS) {
2272 if (!dev->prot_stall) {
2273 pch_udc_ep_clear_stall(ep);
2275 pch_udc_ep_set_stall(ep);
2276 pch_udc_enable_ep_interrupts(ep->dev,
2277 PCH_UDC_EPINT(ep->in, ep->num));
2280 if (epsts & UDC_EPSTS_TDC)
2281 pch_udc_complete_transfer(ep);
2282 /* On IN interrupt, provide data if we have any */
2283 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2284 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2285 pch_udc_start_next_txrequest(ep);
2289 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2290 * @dev: Reference to the device structure
2291 * @ep_num: Endpoint that generated the interrupt
2293 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2296 struct pch_udc_ep *ep;
2297 struct pch_udc_request *req = NULL;
2299 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2303 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2305 req = list_entry(ep->queue.next, struct pch_udc_request,
2307 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2308 PCH_UDC_BS_DMA_DONE) {
2309 if (!req->dma_going)
2310 pch_udc_start_rxrequest(ep, req);
2314 if (epsts & UDC_EPSTS_HE)
2316 if (epsts & UDC_EPSTS_RSS) {
2317 pch_udc_ep_set_stall(ep);
2318 pch_udc_enable_ep_interrupts(ep->dev,
2319 PCH_UDC_EPINT(ep->in, ep->num));
2321 if (epsts & UDC_EPSTS_RCS) {
2322 if (!dev->prot_stall) {
2323 pch_udc_ep_clear_stall(ep);
2325 pch_udc_ep_set_stall(ep);
2326 pch_udc_enable_ep_interrupts(ep->dev,
2327 PCH_UDC_EPINT(ep->in, ep->num));
2330 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2331 UDC_EPSTS_OUT_DATA) {
2332 if (ep->dev->prot_stall == 1) {
2333 pch_udc_ep_set_stall(ep);
2334 pch_udc_enable_ep_interrupts(ep->dev,
2335 PCH_UDC_EPINT(ep->in, ep->num));
2337 pch_udc_complete_receiver(ep);
2340 if (list_empty(&ep->queue))
2341 pch_udc_set_dma(dev, DMA_DIR_RX);
2344 static int pch_udc_gadget_setup(struct pch_udc_dev *dev)
2345 __must_hold(&dev->lock)
2349 /* In some cases we can get an interrupt before driver gets setup */
2353 spin_unlock(&dev->lock);
2354 rc = dev->driver->setup(&dev->gadget, &dev->setup_data);
2355 spin_lock(&dev->lock);
2360 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2361 * @dev: Reference to the device structure
2363 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2366 struct pch_udc_ep *ep;
2367 struct pch_udc_ep *ep_out;
2369 ep = &dev->ep[UDC_EP0IN_IDX];
2370 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2374 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2375 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2376 UDC_EPSTS_XFERDONE)))
2378 if ((epsts & UDC_EPSTS_BNA))
2380 if (epsts & UDC_EPSTS_HE)
2382 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2383 pch_udc_complete_transfer(ep);
2384 pch_udc_clear_dma(dev, DMA_DIR_RX);
2385 ep_out->td_data->status = (ep_out->td_data->status &
2386 ~PCH_UDC_BUFF_STS) |
2388 pch_udc_ep_clear_nak(ep_out);
2389 pch_udc_set_dma(dev, DMA_DIR_RX);
2390 pch_udc_ep_set_rrdy(ep_out);
2392 /* On IN interrupt, provide data if we have any */
2393 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2394 !(epsts & UDC_EPSTS_TXEMPTY))
2395 pch_udc_start_next_txrequest(ep);
2399 * pch_udc_svc_control_out() - Routine that handle Control
2400 * OUT endpoint interrupts
2401 * @dev: Reference to the device structure
2403 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2404 __releases(&dev->lock)
2405 __acquires(&dev->lock)
2408 int setup_supported;
2409 struct pch_udc_ep *ep;
2411 ep = &dev->ep[UDC_EP0OUT_IDX];
2416 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2417 UDC_EPSTS_OUT_SETUP) {
2419 dev->ep[UDC_EP0IN_IDX].halted = 0;
2420 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2421 dev->setup_data = ep->td_stp->request;
2422 pch_udc_init_setup_buff(ep->td_stp);
2423 pch_udc_clear_dma(dev, DMA_DIR_RX);
2424 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2425 dev->ep[UDC_EP0IN_IDX].in);
2426 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2427 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2429 dev->gadget.ep0 = &ep->ep;
2430 /* If Mass storage Reset */
2431 if ((dev->setup_data.bRequestType == 0x21) &&
2432 (dev->setup_data.bRequest == 0xFF))
2433 dev->prot_stall = 0;
2434 /* call gadget with setup data received */
2435 setup_supported = pch_udc_gadget_setup(dev);
2437 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2438 ep->td_data->status = (ep->td_data->status &
2439 ~PCH_UDC_BUFF_STS) |
2441 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2443 /* ep0 in returns data on IN phase */
2444 if (setup_supported >= 0 && setup_supported <
2445 UDC_EP0IN_MAX_PKT_SIZE) {
2446 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2447 /* Gadget would have queued a request when
2448 * we called the setup */
2449 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2450 pch_udc_set_dma(dev, DMA_DIR_RX);
2451 pch_udc_ep_clear_nak(ep);
2453 } else if (setup_supported < 0) {
2454 /* if unsupported request, then stall */
2455 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2456 pch_udc_enable_ep_interrupts(ep->dev,
2457 PCH_UDC_EPINT(ep->in, ep->num));
2459 pch_udc_set_dma(dev, DMA_DIR_RX);
2461 dev->waiting_zlp_ack = 1;
2463 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2464 UDC_EPSTS_OUT_DATA) && !dev->stall) {
2465 pch_udc_clear_dma(dev, DMA_DIR_RX);
2466 pch_udc_ep_set_ddptr(ep, 0);
2467 if (!list_empty(&ep->queue)) {
2469 pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2471 pch_udc_set_dma(dev, DMA_DIR_RX);
2473 pch_udc_ep_set_rrdy(ep);
2478 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2479 * and clears NAK status
2480 * @dev: Reference to the device structure
2481 * @ep_num: End point number
2483 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2485 struct pch_udc_ep *ep;
2486 struct pch_udc_request *req;
2488 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2489 if (!list_empty(&ep->queue)) {
2490 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2491 pch_udc_enable_ep_interrupts(ep->dev,
2492 PCH_UDC_EPINT(ep->in, ep->num));
2493 pch_udc_ep_clear_nak(ep);
2498 * pch_udc_read_all_epstatus() - This function read all endpoint status
2499 * @dev: Reference to the device structure
2500 * @ep_intr: Status of endpoint interrupt
2502 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2505 struct pch_udc_ep *ep;
2507 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2509 if (ep_intr & (0x1 << i)) {
2510 ep = &dev->ep[UDC_EPIN_IDX(i)];
2511 ep->epsts = pch_udc_read_ep_status(ep);
2512 pch_udc_clear_ep_status(ep, ep->epsts);
2515 if (ep_intr & (0x10000 << i)) {
2516 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2517 ep->epsts = pch_udc_read_ep_status(ep);
2518 pch_udc_clear_ep_status(ep, ep->epsts);
2524 * pch_udc_activate_control_ep() - This function enables the control endpoints
2525 * for traffic after a reset
2526 * @dev: Reference to the device structure
2528 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2530 struct pch_udc_ep *ep;
2533 /* Setup the IN endpoint */
2534 ep = &dev->ep[UDC_EP0IN_IDX];
2535 pch_udc_clear_ep_control(ep);
2536 pch_udc_ep_fifo_flush(ep, ep->in);
2537 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2538 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2539 /* Initialize the IN EP Descriptor */
2542 ep->td_data_phys = 0;
2543 ep->td_stp_phys = 0;
2545 /* Setup the OUT endpoint */
2546 ep = &dev->ep[UDC_EP0OUT_IDX];
2547 pch_udc_clear_ep_control(ep);
2548 pch_udc_ep_fifo_flush(ep, ep->in);
2549 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2550 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2551 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2552 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2554 /* Initialize the SETUP buffer */
2555 pch_udc_init_setup_buff(ep->td_stp);
2556 /* Write the pointer address of dma descriptor */
2557 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2558 /* Write the pointer address of Setup descriptor */
2559 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2561 /* Initialize the dma descriptor */
2562 ep->td_data->status = PCH_UDC_DMA_LAST;
2563 ep->td_data->dataptr = dev->dma_addr;
2564 ep->td_data->next = ep->td_data_phys;
2566 pch_udc_ep_clear_nak(ep);
2571 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2572 * @dev: Reference to driver structure
2574 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2576 struct pch_udc_ep *ep;
2579 pch_udc_clear_dma(dev, DMA_DIR_TX);
2580 pch_udc_clear_dma(dev, DMA_DIR_RX);
2581 /* Mask all endpoint interrupts */
2582 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2583 /* clear all endpoint interrupts */
2584 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2586 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2588 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2589 pch_udc_clear_ep_control(ep);
2590 pch_udc_ep_set_ddptr(ep, 0);
2591 pch_udc_write_csr(ep->dev, 0x00, i);
2594 dev->prot_stall = 0;
2595 dev->waiting_zlp_ack = 0;
2596 dev->set_cfg_not_acked = 0;
2598 /* disable ep to empty req queue. Skip the control EP's */
2599 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2601 pch_udc_ep_set_nak(ep);
2602 pch_udc_ep_fifo_flush(ep, ep->in);
2603 /* Complete request queue */
2604 empty_req_queue(ep);
2607 spin_unlock(&dev->lock);
2608 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2609 spin_lock(&dev->lock);
2614 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2616 * @dev: Reference to driver structure
2618 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2620 u32 dev_stat, dev_speed;
2621 u32 speed = USB_SPEED_FULL;
2623 dev_stat = pch_udc_read_device_status(dev);
2624 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2625 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2626 switch (dev_speed) {
2627 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2628 speed = USB_SPEED_HIGH;
2630 case UDC_DEVSTS_ENUM_SPEED_FULL:
2631 speed = USB_SPEED_FULL;
2633 case UDC_DEVSTS_ENUM_SPEED_LOW:
2634 speed = USB_SPEED_LOW;
2639 dev->gadget.speed = speed;
2640 pch_udc_activate_control_ep(dev);
2641 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2642 pch_udc_set_dma(dev, DMA_DIR_TX);
2643 pch_udc_set_dma(dev, DMA_DIR_RX);
2644 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2646 /* enable device interrupts */
2647 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2648 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2649 UDC_DEVINT_SI | UDC_DEVINT_SC);
2653 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2655 * @dev: Reference to driver structure
2657 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2659 u32 reg, dev_stat = 0;
2662 dev_stat = pch_udc_read_device_status(dev);
2663 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2664 UDC_DEVSTS_INTF_SHIFT;
2665 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2666 UDC_DEVSTS_ALT_SHIFT;
2667 dev->set_cfg_not_acked = 1;
2668 /* Construct the usb request for gadget driver and inform it */
2669 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2670 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2671 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2672 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2673 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2674 /* programm the Endpoint Cfg registers */
2675 /* Only one end point cfg register */
2676 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2677 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2678 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2679 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2680 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2681 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2682 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2683 /* clear stall bits */
2684 pch_udc_ep_clear_stall(&(dev->ep[i]));
2685 dev->ep[i].halted = 0;
2688 pch_udc_gadget_setup(dev);
2692 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2694 * @dev: Reference to driver structure
2696 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2699 u32 reg, dev_stat = 0;
2701 dev_stat = pch_udc_read_device_status(dev);
2702 dev->set_cfg_not_acked = 1;
2703 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2704 UDC_DEVSTS_CFG_SHIFT;
2705 /* make usb request for gadget driver */
2706 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2707 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2708 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2709 /* program the NE registers */
2710 /* Only one end point cfg register */
2711 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2712 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2713 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2714 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2715 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2716 /* clear stall bits */
2717 pch_udc_ep_clear_stall(&(dev->ep[i]));
2718 dev->ep[i].halted = 0;
2722 /* call gadget zero with setup data received */
2723 pch_udc_gadget_setup(dev);
2727 * pch_udc_dev_isr() - This function services device interrupts
2728 * by invoking appropriate routines.
2729 * @dev: Reference to the device structure
2730 * @dev_intr: The Device interrupt status.
2732 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2736 /* USB Reset Interrupt */
2737 if (dev_intr & UDC_DEVINT_UR) {
2738 pch_udc_svc_ur_interrupt(dev);
2739 dev_dbg(&dev->pdev->dev, "USB_RESET\n");
2741 /* Enumeration Done Interrupt */
2742 if (dev_intr & UDC_DEVINT_ENUM) {
2743 pch_udc_svc_enum_interrupt(dev);
2744 dev_dbg(&dev->pdev->dev, "USB_ENUM\n");
2746 /* Set Interface Interrupt */
2747 if (dev_intr & UDC_DEVINT_SI)
2748 pch_udc_svc_intf_interrupt(dev);
2749 /* Set Config Interrupt */
2750 if (dev_intr & UDC_DEVINT_SC)
2751 pch_udc_svc_cfg_interrupt(dev);
2752 /* USB Suspend interrupt */
2753 if (dev_intr & UDC_DEVINT_US) {
2755 && dev->driver->suspend) {
2756 spin_unlock(&dev->lock);
2757 dev->driver->suspend(&dev->gadget);
2758 spin_lock(&dev->lock);
2761 vbus = pch_vbus_gpio_get_value(dev);
2762 if ((dev->vbus_session == 0)
2764 if (dev->driver && dev->driver->disconnect) {
2765 spin_unlock(&dev->lock);
2766 dev->driver->disconnect(&dev->gadget);
2767 spin_lock(&dev->lock);
2769 pch_udc_reconnect(dev);
2770 } else if ((dev->vbus_session == 0)
2772 && !dev->vbus_gpio.intr)
2773 schedule_work(&dev->vbus_gpio.irq_work_fall);
2775 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2777 /* Clear the SOF interrupt, if enabled */
2778 if (dev_intr & UDC_DEVINT_SOF)
2779 dev_dbg(&dev->pdev->dev, "SOF\n");
2780 /* ES interrupt, IDLE > 3ms on the USB */
2781 if (dev_intr & UDC_DEVINT_ES)
2782 dev_dbg(&dev->pdev->dev, "ES\n");
2783 /* RWKP interrupt */
2784 if (dev_intr & UDC_DEVINT_RWKP)
2785 dev_dbg(&dev->pdev->dev, "RWKP\n");
2789 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2790 * @irq: Interrupt request number
2791 * @dev: Reference to the device structure
2793 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2795 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2796 u32 dev_intr, ep_intr;
2799 dev_intr = pch_udc_read_device_interrupts(dev);
2800 ep_intr = pch_udc_read_ep_interrupts(dev);
2802 /* For a hot plug, this find that the controller is hung up. */
2803 if (dev_intr == ep_intr)
2804 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2805 dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2806 /* The controller is reset */
2807 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2811 /* Clear device interrupts */
2812 pch_udc_write_device_interrupts(dev, dev_intr);
2814 /* Clear ep interrupts */
2815 pch_udc_write_ep_interrupts(dev, ep_intr);
2816 if (!dev_intr && !ep_intr)
2818 spin_lock(&dev->lock);
2820 pch_udc_dev_isr(dev, dev_intr);
2822 pch_udc_read_all_epstatus(dev, ep_intr);
2823 /* Process Control In interrupts, if present */
2824 if (ep_intr & UDC_EPINT_IN_EP0) {
2825 pch_udc_svc_control_in(dev);
2826 pch_udc_postsvc_epinters(dev, 0);
2828 /* Process Control Out interrupts, if present */
2829 if (ep_intr & UDC_EPINT_OUT_EP0)
2830 pch_udc_svc_control_out(dev);
2831 /* Process data in end point interrupts */
2832 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2833 if (ep_intr & (1 << i)) {
2834 pch_udc_svc_data_in(dev, i);
2835 pch_udc_postsvc_epinters(dev, i);
2838 /* Process data out end point interrupts */
2839 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2840 PCH_UDC_USED_EP_NUM); i++)
2841 if (ep_intr & (1 << i))
2842 pch_udc_svc_data_out(dev, i -
2843 UDC_EPINT_OUT_SHIFT);
2845 spin_unlock(&dev->lock);
2850 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2851 * @dev: Reference to the device structure
2853 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2855 /* enable ep0 interrupts */
2856 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2858 /* enable device interrupts */
2859 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2860 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2861 UDC_DEVINT_SI | UDC_DEVINT_SC);
2865 * gadget_release() - Free the gadget driver private data
2866 * @pdev reference to struct pci_dev
2868 static void gadget_release(struct device *pdev)
2870 struct pch_udc_dev *dev = dev_get_drvdata(pdev);
2876 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2877 * @dev: Reference to the driver structure
2879 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2881 const char *const ep_string[] = {
2882 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2883 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2884 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2885 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2886 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2887 "ep15in", "ep15out",
2891 dev->gadget.speed = USB_SPEED_UNKNOWN;
2892 INIT_LIST_HEAD(&dev->gadget.ep_list);
2894 /* Initialize the endpoints structures */
2895 memset(dev->ep, 0, sizeof dev->ep);
2896 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2897 struct pch_udc_ep *ep = &dev->ep[i];
2902 ep->ep.name = ep_string[i];
2903 ep->ep.ops = &pch_udc_ep_ops;
2905 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2906 ep->ep.caps.dir_in = true;
2908 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2910 ep->ep.caps.dir_out = true;
2912 if (i == UDC_EP0IN_IDX || i == UDC_EP0OUT_IDX) {
2913 ep->ep.caps.type_control = true;
2915 ep->ep.caps.type_iso = true;
2916 ep->ep.caps.type_bulk = true;
2917 ep->ep.caps.type_int = true;
2919 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2920 usb_ep_set_maxpacket_limit(&ep->ep, UDC_BULK_MAX_PKT_SIZE);
2921 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2922 INIT_LIST_HEAD(&ep->queue);
2924 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IDX].ep, UDC_EP0IN_MAX_PKT_SIZE);
2925 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IDX].ep, UDC_EP0OUT_MAX_PKT_SIZE);
2927 /* remove ep0 in and out from the list. They have own pointer */
2928 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2929 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2931 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2932 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2936 * pch_udc_pcd_init() - This API initializes the driver structure
2937 * @dev: Reference to the driver structure
2942 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2945 pch_udc_pcd_reinit(dev);
2946 pch_vbus_gpio_init(dev, vbus_gpio_port);
2951 * init_dma_pools() - create dma pools during initialization
2952 * @pdev: reference to struct pci_dev
2954 static int init_dma_pools(struct pch_udc_dev *dev)
2956 struct pch_udc_stp_dma_desc *td_stp;
2957 struct pch_udc_data_dma_desc *td_data;
2960 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2961 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2962 if (!dev->data_requests) {
2963 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2968 /* dma desc for setup data */
2969 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2970 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2971 if (!dev->stp_requests) {
2972 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2977 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2978 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2980 dev_err(&dev->pdev->dev,
2981 "%s: can't allocate setup dma descriptor\n", __func__);
2984 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2986 /* data: 0 packets !? */
2987 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2988 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2990 dev_err(&dev->pdev->dev,
2991 "%s: can't allocate data dma descriptor\n", __func__);
2994 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2995 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2996 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2997 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2998 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
3000 dev->ep0out_buf = kzalloc(UDC_EP0OUT_BUFF_SIZE * 4, GFP_KERNEL);
3001 if (!dev->ep0out_buf)
3003 dev->dma_addr = dma_map_single(&dev->pdev->dev, dev->ep0out_buf,
3004 UDC_EP0OUT_BUFF_SIZE * 4,
3006 return dma_mapping_error(&dev->pdev->dev, dev->dma_addr);
3009 static int pch_udc_start(struct usb_gadget *g,
3010 struct usb_gadget_driver *driver)
3012 struct pch_udc_dev *dev = to_pch_udc(g);
3014 driver->driver.bus = NULL;
3015 dev->driver = driver;
3017 /* get ready for ep0 traffic */
3018 pch_udc_setup_ep0(dev);
3021 if ((pch_vbus_gpio_get_value(dev) != 0) || !dev->vbus_gpio.intr)
3022 pch_udc_clear_disconnect(dev);
3028 static int pch_udc_stop(struct usb_gadget *g)
3030 struct pch_udc_dev *dev = to_pch_udc(g);
3032 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3034 /* Assures that there are no pending requests with this driver */
3039 pch_udc_set_disconnect(dev);
3044 static void pch_udc_shutdown(struct pci_dev *pdev)
3046 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3048 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3049 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3051 /* disable the pullup so the host will think we're gone */
3052 pch_udc_set_disconnect(dev);
3055 static void pch_udc_remove(struct pci_dev *pdev)
3057 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3059 usb_del_gadget_udc(&dev->gadget);
3061 /* gadget driver must not be registered */
3064 "%s: gadget driver still bound!!!\n", __func__);
3065 /* dma pool cleanup */
3066 if (dev->data_requests)
3067 pci_pool_destroy(dev->data_requests);
3069 if (dev->stp_requests) {
3070 /* cleanup DMA desc's for ep0in */
3071 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
3072 pci_pool_free(dev->stp_requests,
3073 dev->ep[UDC_EP0OUT_IDX].td_stp,
3074 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3076 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3077 pci_pool_free(dev->stp_requests,
3078 dev->ep[UDC_EP0OUT_IDX].td_data,
3079 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
3081 pci_pool_destroy(dev->stp_requests);
3085 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
3086 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
3087 kfree(dev->ep0out_buf);
3089 pch_vbus_gpio_free(dev);
3093 if (dev->irq_registered)
3094 free_irq(pdev->irq, dev);
3096 iounmap(dev->base_addr);
3097 if (dev->mem_region)
3098 release_mem_region(dev->phys_addr,
3099 pci_resource_len(pdev, dev->bar));
3101 pci_disable_device(pdev);
3106 static int pch_udc_suspend(struct pci_dev *pdev, pm_message_t state)
3108 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3110 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3111 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3113 pci_disable_device(pdev);
3114 pci_enable_wake(pdev, PCI_D3hot, 0);
3116 if (pci_save_state(pdev)) {
3118 "%s: could not save PCI config state\n", __func__);
3121 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3125 static int pch_udc_resume(struct pci_dev *pdev)
3129 pci_set_power_state(pdev, PCI_D0);
3130 pci_restore_state(pdev);
3131 ret = pci_enable_device(pdev);
3133 dev_err(&pdev->dev, "%s: pci_enable_device failed\n", __func__);
3136 pci_enable_wake(pdev, PCI_D3hot, 0);
3140 #define pch_udc_suspend NULL
3141 #define pch_udc_resume NULL
3142 #endif /* CONFIG_PM */
3144 static int pch_udc_probe(struct pci_dev *pdev,
3145 const struct pci_device_id *id)
3147 unsigned long resource;
3150 struct pch_udc_dev *dev;
3153 dev = kzalloc(sizeof *dev, GFP_KERNEL);
3155 pr_err("%s: no memory for device structure\n", __func__);
3159 if (pci_enable_device(pdev) < 0) {
3161 pr_err("%s: pci_enable_device failed\n", __func__);
3165 pci_set_drvdata(pdev, dev);
3167 /* Determine BAR based on PCI ID */
3168 if (id->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC)
3169 dev->bar = PCH_UDC_PCI_BAR_QUARK_X1000;
3171 dev->bar = PCH_UDC_PCI_BAR;
3173 /* PCI resource allocation */
3174 resource = pci_resource_start(pdev, dev->bar);
3175 len = pci_resource_len(pdev, dev->bar);
3177 if (!request_mem_region(resource, len, KBUILD_MODNAME)) {
3178 dev_err(&pdev->dev, "%s: pci device used already\n", __func__);
3182 dev->phys_addr = resource;
3183 dev->mem_region = 1;
3185 dev->base_addr = ioremap_nocache(resource, len);
3186 if (!dev->base_addr) {
3187 pr_err("%s: device memory cannot be mapped\n", __func__);
3192 dev_err(&pdev->dev, "%s: irq not set\n", __func__);
3196 /* initialize the hardware */
3197 if (pch_udc_pcd_init(dev)) {
3201 if (request_irq(pdev->irq, pch_udc_isr, IRQF_SHARED, KBUILD_MODNAME,
3203 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
3208 dev->irq = pdev->irq;
3209 dev->irq_registered = 1;
3211 pci_set_master(pdev);
3212 pci_try_set_mwi(pdev);
3214 /* device struct setup */
3215 spin_lock_init(&dev->lock);
3217 dev->gadget.ops = &pch_udc_ops;
3219 retval = init_dma_pools(dev);
3223 dev->gadget.name = KBUILD_MODNAME;
3224 dev->gadget.max_speed = USB_SPEED_HIGH;
3226 /* Put the device in disconnected state till a driver is bound */
3227 pch_udc_set_disconnect(dev);
3228 retval = usb_add_gadget_udc_release(&pdev->dev, &dev->gadget,
3235 pch_udc_remove(pdev);
3239 static const struct pci_device_id pch_udc_pcidev_id[] = {
3241 PCI_DEVICE(PCI_VENDOR_ID_INTEL,
3242 PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC),
3243 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3244 .class_mask = 0xffffffff,
3247 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3248 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3249 .class_mask = 0xffffffff,
3252 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3253 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3254 .class_mask = 0xffffffff,
3257 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3258 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3259 .class_mask = 0xffffffff,
3264 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3266 static struct pci_driver pch_udc_driver = {
3267 .name = KBUILD_MODNAME,
3268 .id_table = pch_udc_pcidev_id,
3269 .probe = pch_udc_probe,
3270 .remove = pch_udc_remove,
3271 .suspend = pch_udc_suspend,
3272 .resume = pch_udc_resume,
3273 .shutdown = pch_udc_shutdown,
3276 module_pci_driver(pch_udc_driver);
3278 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3279 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3280 MODULE_LICENSE("GPL");