drivers/usb/gadget/udc/pch_udc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   6 #include <linux/kernel.h>
   7 #include <linux/module.h>
   8 #include <linux/pci.h>
   9 #include <linux/delay.h>
  10 #include <linux/errno.h>
  11 #include <linux/list.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/usb/ch9.h>
  14 #include <linux/usb/gadget.h>
  15 #include <linux/gpio.h>
  16 #include <linux/irq.h>
  17
  18 /* GPIO port for VBUS detecting */
  19 static int vbus_gpio_port = -1;         /* GPIO port number (-1:Not used) */
  20
  21 #define PCH_VBUS_PERIOD         3000    /* VBUS polling period (msec) */
  22 #define PCH_VBUS_INTERVAL       10      /* VBUS polling interval (msec) */
  23
  24 /* Address offset of Registers */
  25 #define UDC_EP_REG_SHIFT        0x20    /* Offset to next EP */
  26
  27 #define UDC_EPCTL_ADDR          0x00    /* Endpoint control */
  28 #define UDC_EPSTS_ADDR          0x04    /* Endpoint status */
  29 #define UDC_BUFIN_FRAMENUM_ADDR 0x08    /* buffer size in / frame number out */
  30 #define UDC_BUFOUT_MAXPKT_ADDR  0x0C    /* buffer size out / maxpkt in */
  31 #define UDC_SUBPTR_ADDR         0x10    /* setup buffer pointer */
  32 #define UDC_DESPTR_ADDR         0x14    /* Data descriptor pointer */
  33 #define UDC_CONFIRM_ADDR        0x18    /* Write/Read confirmation */
  34
  35 #define UDC_DEVCFG_ADDR         0x400   /* Device configuration */
  36 #define UDC_DEVCTL_ADDR         0x404   /* Device control */
  37 #define UDC_DEVSTS_ADDR         0x408   /* Device status */
  38 #define UDC_DEVIRQSTS_ADDR      0x40C   /* Device irq status */
  39 #define UDC_DEVIRQMSK_ADDR      0x410   /* Device irq mask */
  40 #define UDC_EPIRQSTS_ADDR       0x414   /* Endpoint irq status */
  41 #define UDC_EPIRQMSK_ADDR       0x418   /* Endpoint irq mask */
  42 #define UDC_DEVLPM_ADDR         0x41C   /* LPM control / status */
  43 #define UDC_CSR_BUSY_ADDR       0x4f0   /* UDC_CSR_BUSY Status register */
  44 #define UDC_SRST_ADDR           0x4fc   /* SOFT RESET register */
  45 #define UDC_CSR_ADDR            0x500   /* USB_DEVICE endpoint register */
  46
  47 /* Endpoint control register */
  48 /* Bit position */
  49 #define UDC_EPCTL_MRXFLUSH              (1 << 12)
  50 #define UDC_EPCTL_RRDY                  (1 << 9)
  51 #define UDC_EPCTL_CNAK                  (1 << 8)
  52 #define UDC_EPCTL_SNAK                  (1 << 7)
  53 #define UDC_EPCTL_NAK                   (1 << 6)
  54 #define UDC_EPCTL_P                     (1 << 3)
  55 #define UDC_EPCTL_F                     (1 << 1)
  56 #define UDC_EPCTL_S                     (1 << 0)
  57 #define UDC_EPCTL_ET_SHIFT              4
  58 /* Mask patern */
  59 #define UDC_EPCTL_ET_MASK               0x00000030
  60 /* Value for ET field */
  61 #define UDC_EPCTL_ET_CONTROL            0
  62 #define UDC_EPCTL_ET_ISO                1
  63 #define UDC_EPCTL_ET_BULK               2
  64 #define UDC_EPCTL_ET_INTERRUPT          3
  65
  66 /* Endpoint status register */
  67 /* Bit position */
  68 #define UDC_EPSTS_XFERDONE              (1 << 27)
  69 #define UDC_EPSTS_RSS                   (1 << 26)
  70 #define UDC_EPSTS_RCS                   (1 << 25)
  71 #define UDC_EPSTS_TXEMPTY               (1 << 24)
  72 #define UDC_EPSTS_TDC                   (1 << 10)
  73 #define UDC_EPSTS_HE                    (1 << 9)
  74 #define UDC_EPSTS_MRXFIFO_EMP           (1 << 8)
  75 #define UDC_EPSTS_BNA                   (1 << 7)
  76 #define UDC_EPSTS_IN                    (1 << 6)
  77 #define UDC_EPSTS_OUT_SHIFT             4
  78 /* Mask patern */
  79 #define UDC_EPSTS_OUT_MASK              0x00000030
  80 #define UDC_EPSTS_ALL_CLR_MASK          0x1F0006F0
  81 /* Value for OUT field */
  82 #define UDC_EPSTS_OUT_SETUP             2
  83 #define UDC_EPSTS_OUT_DATA              1
  84
  85 /* Device configuration register */
  86 /* Bit position */
  87 #define UDC_DEVCFG_CSR_PRG              (1 << 17)
  88 #define UDC_DEVCFG_SP                   (1 << 3)
  89 /* SPD Valee */
  90 #define UDC_DEVCFG_SPD_HS               0x0
  91 #define UDC_DEVCFG_SPD_FS               0x1
  92 #define UDC_DEVCFG_SPD_LS               0x2
  93
  94 /* Device control register */
  95 /* Bit position */
  96 #define UDC_DEVCTL_THLEN_SHIFT          24
  97 #define UDC_DEVCTL_BRLEN_SHIFT          16
  98 #define UDC_DEVCTL_CSR_DONE             (1 << 13)
  99 #define UDC_DEVCTL_SD                   (1 << 10)
 100 #define UDC_DEVCTL_MODE                 (1 << 9)
 101 #define UDC_DEVCTL_BREN                 (1 << 8)
 102 #define UDC_DEVCTL_THE                  (1 << 7)
 103 #define UDC_DEVCTL_DU                   (1 << 4)
 104 #define UDC_DEVCTL_TDE                  (1 << 3)
 105 #define UDC_DEVCTL_RDE                  (1 << 2)
 106 #define UDC_DEVCTL_RES                  (1 << 0)
 107
 108 /* Device status register */
 109 /* Bit position */
 110 #define UDC_DEVSTS_TS_SHIFT             18
 111 #define UDC_DEVSTS_ENUM_SPEED_SHIFT     13
 112 #define UDC_DEVSTS_ALT_SHIFT            8
 113 #define UDC_DEVSTS_INTF_SHIFT           4
 114 #define UDC_DEVSTS_CFG_SHIFT            0
 115 /* Mask patern */
 116 #define UDC_DEVSTS_TS_MASK              0xfffc0000
 117 #define UDC_DEVSTS_ENUM_SPEED_MASK      0x00006000
 118 #define UDC_DEVSTS_ALT_MASK             0x00000f00
 119 #define UDC_DEVSTS_INTF_MASK            0x000000f0
 120 #define UDC_DEVSTS_CFG_MASK             0x0000000f
 121 /* value for maximum speed for SPEED field */
 122 #define UDC_DEVSTS_ENUM_SPEED_FULL      1
 123 #define UDC_DEVSTS_ENUM_SPEED_HIGH      0
 124 #define UDC_DEVSTS_ENUM_SPEED_LOW       2
 125 #define UDC_DEVSTS_ENUM_SPEED_FULLX     3
 126
 127 /* Device irq register */
 128 /* Bit position */
 129 #define UDC_DEVINT_RWKP                 (1 << 7)
 130 #define UDC_DEVINT_ENUM                 (1 << 6)
 131 #define UDC_DEVINT_SOF                  (1 << 5)
 132 #define UDC_DEVINT_US                   (1 << 4)
 133 #define UDC_DEVINT_UR                   (1 << 3)
 134 #define UDC_DEVINT_ES                   (1 << 2)
 135 #define UDC_DEVINT_SI                   (1 << 1)
 136 #define UDC_DEVINT_SC                   (1 << 0)
 137 /* Mask patern */
 138 #define UDC_DEVINT_MSK                  0x7f
 139
 140 /* Endpoint irq register */
 141 /* Bit position */
 142 #define UDC_EPINT_IN_SHIFT              0
 143 #define UDC_EPINT_OUT_SHIFT             16
 144 #define UDC_EPINT_IN_EP0                (1 << 0)
 145 #define UDC_EPINT_OUT_EP0               (1 << 16)
 146 /* Mask patern */
 147 #define UDC_EPINT_MSK_DISABLE_ALL       0xffffffff
 148
 149 /* UDC_CSR_BUSY Status register */
 150 /* Bit position */
 151 #define UDC_CSR_BUSY                    (1 << 0)
 152
 153 /* SOFT RESET register */
 154 /* Bit position */
 155 #define UDC_PSRST                       (1 << 1)
 156 #define UDC_SRST                        (1 << 0)
 157
 158 /* USB_DEVICE endpoint register */
 159 /* Bit position */
 160 #define UDC_CSR_NE_NUM_SHIFT            0
 161 #define UDC_CSR_NE_DIR_SHIFT            4
 162 #define UDC_CSR_NE_TYPE_SHIFT           5
 163 #define UDC_CSR_NE_CFG_SHIFT            7
 164 #define UDC_CSR_NE_INTF_SHIFT           11
 165 #define UDC_CSR_NE_ALT_SHIFT            15
 166 #define UDC_CSR_NE_MAX_PKT_SHIFT        19
 167 /* Mask patern */
 168 #define UDC_CSR_NE_NUM_MASK             0x0000000f
 169 #define UDC_CSR_NE_DIR_MASK             0x00000010
 170 #define UDC_CSR_NE_TYPE_MASK            0x00000060
 171 #define UDC_CSR_NE_CFG_MASK             0x00000780
 172 #define UDC_CSR_NE_INTF_MASK            0x00007800
 173 #define UDC_CSR_NE_ALT_MASK             0x00078000
 174 #define UDC_CSR_NE_MAX_PKT_MASK         0x3ff80000
 175
 176 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
 177 #define PCH_UDC_EPINT(in, num)\
 178                 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
 179
 180 /* Index of endpoint */
 181 #define UDC_EP0IN_IDX           0
 182 #define UDC_EP0OUT_IDX          1
 183 #define UDC_EPIN_IDX(ep)        (ep * 2)
 184 #define UDC_EPOUT_IDX(ep)       (ep * 2 + 1)
 185 #define PCH_UDC_EP0             0
 186 #define PCH_UDC_EP1             1
 187 #define PCH_UDC_EP2             2
 188 #define PCH_UDC_EP3             3
 189
 190 /* Number of endpoint */
 191 #define PCH_UDC_EP_NUM          32      /* Total number of EPs (16 IN,16 OUT) */
 192 #define PCH_UDC_USED_EP_NUM     4       /* EP number of EP's really used */
 193 /* Length Value */
 194 #define PCH_UDC_BRLEN           0x0F    /* Burst length */
 195 #define PCH_UDC_THLEN           0x1F    /* Threshold length */
 196 /* Value of EP Buffer Size */
 197 #define UDC_EP0IN_BUFF_SIZE     16
 198 #define UDC_EPIN_BUFF_SIZE      256
 199 #define UDC_EP0OUT_BUFF_SIZE    16
 200 #define UDC_EPOUT_BUFF_SIZE     256
 201 /* Value of EP maximum packet size */
 202 #define UDC_EP0IN_MAX_PKT_SIZE  64
 203 #define UDC_EP0OUT_MAX_PKT_SIZE 64
 204 #define UDC_BULK_MAX_PKT_SIZE   512
 205
 206 /* DMA */
 207 #define DMA_DIR_RX              1       /* DMA for data receive */
 208 #define DMA_DIR_TX              2       /* DMA for data transmit */
 209 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
 210 #define UDC_DMA_MAXPACKET       65536   /* maximum packet size for DMA */
 211
 212 /**
 213  * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
 214  *                                for data
 215  * @status:             Status quadlet
 216  * @reserved:           Reserved
 217  * @dataptr:            Buffer descriptor
 218  * @next:               Next descriptor
 219  */
 220 struct pch_udc_data_dma_desc {
 221         u32 status;
 222         u32 reserved;
 223         u32 dataptr;
 224         u32 next;
 225 };
 226
 227 /**
 228  * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
 229  *                               for control data
 230  * @status:     Status
 231  * @reserved:   Reserved
 232  * @data12:     First setup word
 233  * @data34:     Second setup word
 234  */
 235 struct pch_udc_stp_dma_desc {
 236         u32 status;
 237         u32 reserved;
 238         struct usb_ctrlrequest request;
 239 } __attribute((packed));
 240
 241 /* DMA status definitions */
 242 /* Buffer status */
 243 #define PCH_UDC_BUFF_STS        0xC0000000
 244 #define PCH_UDC_BS_HST_RDY      0x00000000
 245 #define PCH_UDC_BS_DMA_BSY      0x40000000
 246 #define PCH_UDC_BS_DMA_DONE     0x80000000
 247 #define PCH_UDC_BS_HST_BSY      0xC0000000
 248 /*  Rx/Tx Status */
 249 #define PCH_UDC_RXTX_STS        0x30000000
 250 #define PCH_UDC_RTS_SUCC        0x00000000
 251 #define PCH_UDC_RTS_DESERR      0x10000000
 252 #define PCH_UDC_RTS_BUFERR      0x30000000
 253 /* Last Descriptor Indication */
 254 #define PCH_UDC_DMA_LAST        0x08000000
 255 /* Number of Rx/Tx Bytes Mask */
 256 #define PCH_UDC_RXTX_BYTES      0x0000ffff
 257
 258 /**
 259  * struct pch_udc_cfg_data - Structure to hold current configuration
 260  *                           and interface information
 261  * @cur_cfg:    current configuration in use
 262  * @cur_intf:   current interface in use
 263  * @cur_alt:    current alt interface in use
 264  */
 265 struct pch_udc_cfg_data {
 266         u16 cur_cfg;
 267         u16 cur_intf;
 268         u16 cur_alt;
 269 };
 270
 271 /**
 272  * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
 273  * @ep:                 embedded ep request
 274  * @td_stp_phys:        for setup request
 275  * @td_data_phys:       for data request
 276  * @td_stp:             for setup request
 277  * @td_data:            for data request
 278  * @dev:                reference to device struct
 279  * @offset_addr:        offset address of ep register
 280  * @desc:               for this ep
 281  * @queue:              queue for requests
 282  * @num:                endpoint number
 283  * @in:                 endpoint is IN
 284  * @halted:             endpoint halted?
 285  * @epsts:              Endpoint status
 286  */
 287 struct pch_udc_ep {
 288         struct usb_ep                   ep;
 289         dma_addr_t                      td_stp_phys;
 290         dma_addr_t                      td_data_phys;
 291         struct pch_udc_stp_dma_desc     *td_stp;
 292         struct pch_udc_data_dma_desc    *td_data;
 293         struct pch_udc_dev              *dev;
 294         unsigned long                   offset_addr;
 295         struct list_head                queue;
 296         unsigned                        num:5,
 297                                         in:1,
 298                                         halted:1;
 299         unsigned long                   epsts;
 300 };
 301
 302 /**
 303  * struct pch_vbus_gpio_data - Structure holding GPIO informaton
 304  *                                      for detecting VBUS
 305  * @port:               gpio port number
 306  * @intr:               gpio interrupt number
 307  * @irq_work_fall       Structure for WorkQueue
 308  * @irq_work_rise       Structure for WorkQueue
 309  */
 310 struct pch_vbus_gpio_data {
 311         int                     port;
 312         int                     intr;
 313         struct work_struct      irq_work_fall;
 314         struct work_struct      irq_work_rise;
 315 };
 316
 317 /**
 318  * struct pch_udc_dev - Structure holding complete information
 319  *                      of the PCH USB device
 320  * @gadget:             gadget driver data
 321  * @driver:             reference to gadget driver bound
 322  * @pdev:               reference to the PCI device
 323  * @ep:                 array of endpoints
 324  * @lock:               protects all state
 325  * @stall:              stall requested
 326  * @prot_stall:         protcol stall requested
 327  * @registered:         driver registered with system
 328  * @suspended:          driver in suspended state
 329  * @connected:          gadget driver associated
 330  * @vbus_session:       required vbus_session state
 331  * @set_cfg_not_acked:  pending acknowledgement 4 setup
 332  * @waiting_zlp_ack:    pending acknowledgement 4 ZLP
 333  * @data_requests:      DMA pool for data requests
 334  * @stp_requests:       DMA pool for setup requests
 335  * @dma_addr:           DMA pool for received
 336  * @setup_data:         Received setup data
 337  * @base_addr:          for mapped device memory
 338  * @cfg_data:           current cfg, intf, and alt in use
 339  * @vbus_gpio:          GPIO informaton for detecting VBUS
 340  */
 341 struct pch_udc_dev {
 342         struct usb_gadget               gadget;
 343         struct usb_gadget_driver        *driver;
 344         struct pci_dev                  *pdev;
 345         struct pch_udc_ep               ep[PCH_UDC_EP_NUM];
 346         spinlock_t                      lock; /* protects all state */
 347         unsigned
 348                         stall:1,
 349                         prot_stall:1,
 350                         suspended:1,
 351                         connected:1,
 352                         vbus_session:1,
 353                         set_cfg_not_acked:1,
 354                         waiting_zlp_ack:1;
 355         struct dma_pool         *data_requests;
 356         struct dma_pool         *stp_requests;
 357         dma_addr_t                      dma_addr;
 358         struct usb_ctrlrequest          setup_data;
 359         void __iomem                    *base_addr;
 360         struct pch_udc_cfg_data         cfg_data;
 361         struct pch_vbus_gpio_data       vbus_gpio;
 362 };
 363 #define to_pch_udc(g)   (container_of((g), struct pch_udc_dev, gadget))
 364
 365 #define PCH_UDC_PCI_BAR_QUARK_X1000     0
 366 #define PCH_UDC_PCI_BAR                 1
 367
 368 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC     0x0939
 369 #define PCI_DEVICE_ID_INTEL_EG20T_UDC           0x8808
 370
 371 #define PCI_DEVICE_ID_ML7213_IOH_UDC    0x801D
 372 #define PCI_DEVICE_ID_ML7831_IOH_UDC    0x8808
 373
 374 static const char       ep0_string[] = "ep0in";
 375 static DEFINE_SPINLOCK(udc_stall_spinlock);     /* stall spin lock */
 376 static bool speed_fs;
 377 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
 378 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
 379
 380 /**
 381  * struct pch_udc_request - Structure holding a PCH USB device request packet
 382  * @req:                embedded ep request
 383  * @td_data_phys:       phys. address
 384  * @td_data:            first dma desc. of chain
 385  * @td_data_last:       last dma desc. of chain
 386  * @queue:              associated queue
 387  * @dma_going:          DMA in progress for request
 388  * @dma_mapped:         DMA memory mapped for request
 389  * @dma_done:           DMA completed for request
 390  * @chain_len:          chain length
 391  * @buf:                Buffer memory for align adjustment
 392  * @dma:                DMA memory for align adjustment
 393  */
 394 struct pch_udc_request {
 395         struct usb_request              req;
 396         dma_addr_t                      td_data_phys;
 397         struct pch_udc_data_dma_desc    *td_data;
 398         struct pch_udc_data_dma_desc    *td_data_last;
 399         struct list_head                queue;
 400         unsigned                        dma_going:1,
 401                                         dma_mapped:1,
 402                                         dma_done:1;
 403         unsigned                        chain_len;
 404         void                            *buf;
 405         dma_addr_t                      dma;
 406 };
 407
 408 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
 409 {
 410         return ioread32(dev->base_addr + reg);
 411 }
 412
 413 static inline void pch_udc_writel(struct pch_udc_dev *dev,
 414                                     unsigned long val, unsigned long reg)
 415 {
 416         iowrite32(val, dev->base_addr + reg);
 417 }
 418
 419 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
 420                                      unsigned long reg,
 421                                      unsigned long bitmask)
 422 {
 423         pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
 424 }
 425
 426 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
 427                                      unsigned long reg,
 428                                      unsigned long bitmask)
 429 {
 430         pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
 431 }
 432
 433 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
 434 {
 435         return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
 436 }
 437
 438 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
 439                                     unsigned long val, unsigned long reg)
 440 {
 441         iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
 442 }
 443
 444 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
 445                                      unsigned long reg,
 446                                      unsigned long bitmask)
 447 {
 448         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
 449 }
 450
 451 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
 452                                      unsigned long reg,
 453                                      unsigned long bitmask)
 454 {
 455         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
 456 }
 457
 458 /**
 459  * pch_udc_csr_busy() - Wait till idle.
 460  * @dev:        Reference to pch_udc_dev structure
 461  */
 462 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
 463 {
 464         unsigned int count = 200;
 465
 466         /* Wait till idle */
 467         while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
 468                 && --count)
 469                 cpu_relax();
 470         if (!count)
 471                 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
 472 }
 473
 474 /**
 475  * pch_udc_write_csr() - Write the command and status registers.
 476  * @dev:        Reference to pch_udc_dev structure
 477  * @val:        value to be written to CSR register
 478  * @addr:       address of CSR register
 479  */
 480 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
 481                                unsigned int ep)
 482 {
 483         unsigned long reg = PCH_UDC_CSR(ep);
 484
 485         pch_udc_csr_busy(dev);          /* Wait till idle */
 486         pch_udc_writel(dev, val, reg);
 487         pch_udc_csr_busy(dev);          /* Wait till idle */
 488 }
 489
 490 /**
 491  * pch_udc_read_csr() - Read the command and status registers.
 492  * @dev:        Reference to pch_udc_dev structure
 493  * @addr:       address of CSR register
 494  *
 495  * Return codes:        content of CSR register
 496  */
 497 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
 498 {
 499         unsigned long reg = PCH_UDC_CSR(ep);
 500
 501         pch_udc_csr_busy(dev);          /* Wait till idle */
 502         pch_udc_readl(dev, reg);        /* Dummy read */
 503         pch_udc_csr_busy(dev);          /* Wait till idle */
 504         return pch_udc_readl(dev, reg);
 505 }
 506
 507 /**
 508  * pch_udc_rmt_wakeup() - Initiate for remote wakeup
 509  * @dev:        Reference to pch_udc_dev structure
 510  */
 511 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
 512 {
 513         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 514         mdelay(1);
 515         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 516 }
 517
 518 /**
 519  * pch_udc_get_frame() - Get the current frame from device status register
 520  * @dev:        Reference to pch_udc_dev structure
 521  * Retern       current frame
 522  */
 523 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
 524 {
 525         u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 526         return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
 527 }
 528
 529 /**
 530  * pch_udc_clear_selfpowered() - Clear the self power control
 531  * @dev:        Reference to pch_udc_regs structure
 532  */
 533 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
 534 {
 535         pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 536 }
 537
 538 /**
 539  * pch_udc_set_selfpowered() - Set the self power control
 540  * @dev:        Reference to pch_udc_regs structure
 541  */
 542 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
 543 {
 544         pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 545 }
 546
 547 /**
 548  * pch_udc_set_disconnect() - Set the disconnect status.
 549  * @dev:        Reference to pch_udc_regs structure
 550  */
 551 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
 552 {
 553         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 554 }
 555
 556 /**
 557  * pch_udc_clear_disconnect() - Clear the disconnect status.
 558  * @dev:        Reference to pch_udc_regs structure
 559  */
 560 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
 561 {
 562         /* Clear the disconnect */
 563         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 564         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 565         mdelay(1);
 566         /* Resume USB signalling */
 567         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 568 }
 569
 570 /**
 571  * pch_udc_reconnect() - This API initializes usb device controller,
 572  *                                              and clear the disconnect status.
 573  * @dev:                Reference to pch_udc_regs structure
 574  */
 575 static void pch_udc_init(struct pch_udc_dev *dev);
 576 static void pch_udc_reconnect(struct pch_udc_dev *dev)
 577 {
 578         pch_udc_init(dev);
 579
 580         /* enable device interrupts */
 581         /* pch_udc_enable_interrupts() */
 582         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
 583                         UDC_DEVINT_UR | UDC_DEVINT_ENUM);
 584
 585         /* Clear the disconnect */
 586         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 587         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 588         mdelay(1);
 589         /* Resume USB signalling */
 590         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 591 }
 592
 593 /**
 594  * pch_udc_vbus_session() - set or clearr the disconnect status.
 595  * @dev:        Reference to pch_udc_regs structure
 596  * @is_active:  Parameter specifying the action
 597  *                0:   indicating VBUS power is ending
 598  *                !0:  indicating VBUS power is starting
 599  */
 600 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
 601                                           int is_active)
 602 {
 603         unsigned long           iflags;
 604
 605         spin_lock_irqsave(&dev->lock, iflags);
 606         if (is_active) {
 607                 pch_udc_reconnect(dev);
 608                 dev->vbus_session = 1;
 609         } else {
 610                 if (dev->driver && dev->driver->disconnect) {
 611                         spin_unlock_irqrestore(&dev->lock, iflags);
 612                         dev->driver->disconnect(&dev->gadget);
 613                         spin_lock_irqsave(&dev->lock, iflags);
 614                 }
 615                 pch_udc_set_disconnect(dev);
 616                 dev->vbus_session = 0;
 617         }
 618         spin_unlock_irqrestore(&dev->lock, iflags);
 619 }
 620
 621 /**
 622  * pch_udc_ep_set_stall() - Set the stall of endpoint
 623  * @ep:         Reference to structure of type pch_udc_ep_regs
 624  */
 625 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
 626 {
 627         if (ep->in) {
 628                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 629                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 630         } else {
 631                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 632         }
 633 }
 634
 635 /**
 636  * pch_udc_ep_clear_stall() - Clear the stall of endpoint
 637  * @ep:         Reference to structure of type pch_udc_ep_regs
 638  */
 639 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
 640 {
 641         /* Clear the stall */
 642         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 643         /* Clear NAK by writing CNAK */
 644         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 645 }
 646
 647 /**
 648  * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
 649  * @ep:         Reference to structure of type pch_udc_ep_regs
 650  * @type:       Type of endpoint
 651  */
 652 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
 653                                         u8 type)
 654 {
 655         pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
 656                                 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
 657 }
 658
 659 /**
 660  * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
 661  * @ep:         Reference to structure of type pch_udc_ep_regs
 662  * @buf_size:   The buffer word size
 663  */
 664 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
 665                                                  u32 buf_size, u32 ep_in)
 666 {
 667         u32 data;
 668         if (ep_in) {
 669                 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
 670                 data = (data & 0xffff0000) | (buf_size & 0xffff);
 671                 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
 672         } else {
 673                 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 674                 data = (buf_size << 16) | (data & 0xffff);
 675                 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 676         }
 677 }
 678
 679 /**
 680  * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
 681  * @ep:         Reference to structure of type pch_udc_ep_regs
 682  * @pkt_size:   The packet byte size
 683  */
 684 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
 685 {
 686         u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 687         data = (data & 0xffff0000) | (pkt_size & 0xffff);
 688         pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 689 }
 690
 691 /**
 692  * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
 693  * @ep:         Reference to structure of type pch_udc_ep_regs
 694  * @addr:       Address of the register
 695  */
 696 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
 697 {
 698         pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
 699 }
 700
 701 /**
 702  * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
 703  * @ep:         Reference to structure of type pch_udc_ep_regs
 704  * @addr:       Address of the register
 705  */
 706 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
 707 {
 708         pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
 709 }
 710
 711 /**
 712  * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
 713  * @ep:         Reference to structure of type pch_udc_ep_regs
 714  */
 715 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
 716 {
 717         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
 718 }
 719
 720 /**
 721  * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
 722  * @ep:         Reference to structure of type pch_udc_ep_regs
 723  */
 724 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
 725 {
 726         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 727 }
 728
 729 /**
 730  * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
 731  * @ep:         Reference to structure of type pch_udc_ep_regs
 732  */
 733 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
 734 {
 735         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 736 }
 737
 738 /**
 739  * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
 740  *                      register depending on the direction specified
 741  * @dev:        Reference to structure of type pch_udc_regs
 742  * @dir:        whether Tx or Rx
 743  *                DMA_DIR_RX: Receive
 744  *                DMA_DIR_TX: Transmit
 745  */
 746 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
 747 {
 748         if (dir == DMA_DIR_RX)
 749                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 750         else if (dir == DMA_DIR_TX)
 751                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 752 }
 753
 754 /**
 755  * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
 756  *                               register depending on the direction specified
 757  * @dev:        Reference to structure of type pch_udc_regs
 758  * @dir:        Whether Tx or Rx
 759  *                DMA_DIR_RX: Receive
 760  *                DMA_DIR_TX: Transmit
 761  */
 762 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
 763 {
 764         if (dir == DMA_DIR_RX)
 765                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 766         else if (dir == DMA_DIR_TX)
 767                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 768 }
 769
 770 /**
 771  * pch_udc_set_csr_done() - Set the device control register
 772  *                              CSR done field (bit 13)
 773  * @dev:        reference to structure of type pch_udc_regs
 774  */
 775 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
 776 {
 777         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
 778 }
 779
 780 /**
 781  * pch_udc_disable_interrupts() - Disables the specified interrupts
 782  * @dev:        Reference to structure of type pch_udc_regs
 783  * @mask:       Mask to disable interrupts
 784  */
 785 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
 786                                             u32 mask)
 787 {
 788         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
 789 }
 790
 791 /**
 792  * pch_udc_enable_interrupts() - Enable the specified interrupts
 793  * @dev:        Reference to structure of type pch_udc_regs
 794  * @mask:       Mask to enable interrupts
 795  */
 796 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
 797                                            u32 mask)
 798 {
 799         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
 800 }
 801
 802 /**
 803  * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
 804  * @dev:        Reference to structure of type pch_udc_regs
 805  * @mask:       Mask to disable interrupts
 806  */
 807 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
 808                                                 u32 mask)
 809 {
 810         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
 811 }
 812
 813 /**
 814  * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
 815  * @dev:        Reference to structure of type pch_udc_regs
 816  * @mask:       Mask to enable interrupts
 817  */
 818 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
 819                                               u32 mask)
 820 {
 821         pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
 822 }
 823
 824 /**
 825  * pch_udc_read_device_interrupts() - Read the device interrupts
 826  * @dev:        Reference to structure of type pch_udc_regs
 827  * Retern       The device interrupts
 828  */
 829 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
 830 {
 831         return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
 832 }
 833
 834 /**
 835  * pch_udc_write_device_interrupts() - Write device interrupts
 836  * @dev:        Reference to structure of type pch_udc_regs
 837  * @val:        The value to be written to interrupt register
 838  */
 839 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
 840                                                      u32 val)
 841 {
 842         pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
 843 }
 844
 845 /**
 846  * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
 847  * @dev:        Reference to structure of type pch_udc_regs
 848  * Retern       The endpoint interrupt
 849  */
 850 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
 851 {
 852         return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
 853 }
 854
 855 /**
 856  * pch_udc_write_ep_interrupts() - Clear endpoint interupts
 857  * @dev:        Reference to structure of type pch_udc_regs
 858  * @val:        The value to be written to interrupt register
 859  */
 860 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
 861                                              u32 val)
 862 {
 863         pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
 864 }
 865
 866 /**
 867  * pch_udc_read_device_status() - Read the device status
 868  * @dev:        Reference to structure of type pch_udc_regs
 869  * Retern       The device status
 870  */
 871 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
 872 {
 873         return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 874 }
 875
 876 /**
 877  * pch_udc_read_ep_control() - Read the endpoint control
 878  * @ep:         Reference to structure of type pch_udc_ep_regs
 879  * Retern       The endpoint control register value
 880  */
 881 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
 882 {
 883         return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
 884 }
 885
 886 /**
 887  * pch_udc_clear_ep_control() - Clear the endpoint control register
 888  * @ep:         Reference to structure of type pch_udc_ep_regs
 889  * Retern       The endpoint control register value
 890  */
 891 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
 892 {
 893         return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
 894 }
 895
 896 /**
 897  * pch_udc_read_ep_status() - Read the endpoint status
 898  * @ep:         Reference to structure of type pch_udc_ep_regs
 899  * Retern       The endpoint status
 900  */
 901 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
 902 {
 903         return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
 904 }
 905
 906 /**
 907  * pch_udc_clear_ep_status() - Clear the endpoint status
 908  * @ep:         Reference to structure of type pch_udc_ep_regs
 909  * @stat:       Endpoint status
 910  */
 911 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
 912                                          u32 stat)
 913 {
 914         return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
 915 }
 916
 917 /**
 918  * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
 919  *                              of the endpoint control register
 920  * @ep:         Reference to structure of type pch_udc_ep_regs
 921  */
 922 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
 923 {
 924         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
 925 }
 926
 927 /**
 928  * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
 929  *                              of the endpoint control register
 930  * @ep:         reference to structure of type pch_udc_ep_regs
 931  */
 932 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
 933 {
 934         unsigned int loopcnt = 0;
 935         struct pch_udc_dev *dev = ep->dev;
 936
 937         if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
 938                 return;
 939         if (!ep->in) {
 940                 loopcnt = 10000;
 941                 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
 942                         --loopcnt)
 943                         udelay(5);
 944                 if (!loopcnt)
 945                         dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
 946                                 __func__);
 947         }
 948         loopcnt = 10000;
 949         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
 950                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 951                 udelay(5);
 952         }
 953         if (!loopcnt)
 954                 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
 955                         __func__, ep->num, (ep->in ? "in" : "out"));
 956 }
 957
 958 /**
 959  * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
 960  * @ep: reference to structure of type pch_udc_ep_regs
 961  * @dir:        direction of endpoint
 962  *                0:  endpoint is OUT
 963  *                !0: endpoint is IN
 964  */
 965 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
 966 {
 967         if (dir) {      /* IN ep */
 968                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 969                 return;
 970         }
 971 }
 972
 973 /**
 974  * pch_udc_ep_enable() - This api enables endpoint
 975  * @regs:       Reference to structure pch_udc_ep_regs
 976  * @desc:       endpoint descriptor
 977  */
 978 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
 979                                struct pch_udc_cfg_data *cfg,
 980                                const struct usb_endpoint_descriptor *desc)
 981 {
 982         u32 val = 0;
 983         u32 buff_size = 0;
 984
 985         pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
 986         if (ep->in)
 987                 buff_size = UDC_EPIN_BUFF_SIZE;
 988         else
 989                 buff_size = UDC_EPOUT_BUFF_SIZE;
 990         pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
 991         pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
 992         pch_udc_ep_set_nak(ep);
 993         pch_udc_ep_fifo_flush(ep, ep->in);
 994         /* Configure the endpoint */
 995         val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
 996               ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
 997                 UDC_CSR_NE_TYPE_SHIFT) |
 998               (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
 999               (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
1000               (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
1001               usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
1002
1003         if (ep->in)
1004                 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1005         else
1006                 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1007 }
1008
1009 /**
1010  * pch_udc_ep_disable() - This api disables endpoint
1011  * @regs:       Reference to structure pch_udc_ep_regs
1012  */
1013 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1014 {
1015         if (ep->in) {
1016                 /* flush the fifo */
1017                 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1018                 /* set NAK */
1019                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1020                 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1021         } else {
1022                 /* set NAK */
1023                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1024         }
1025         /* reset desc pointer */
1026         pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1027 }
1028
1029 /**
1030  * pch_udc_wait_ep_stall() - Wait EP stall.
1031  * @dev:        Reference to pch_udc_dev structure
1032  */
1033 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1034 {
1035         unsigned int count = 10000;
1036
1037         /* Wait till idle */
1038         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1039                 udelay(5);
1040         if (!count)
1041                 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1042 }
1043
1044 /**
1045  * pch_udc_init() - This API initializes usb device controller
1046  * @dev:        Rreference to pch_udc_regs structure
1047  */
1048 static void pch_udc_init(struct pch_udc_dev *dev)
1049 {
1050         if (NULL == dev) {
1051                 pr_err("%s: Invalid address\n", __func__);
1052                 return;
1053         }
1054         /* Soft Reset and Reset PHY */
1055         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1056         pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1057         mdelay(1);
1058         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1059         pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1060         mdelay(1);
1061         /* mask and clear all device interrupts */
1062         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1063         pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1064
1065         /* mask and clear all ep interrupts */
1066         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1067         pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1068
1069         /* enable dynamic CSR programmingi, self powered and device speed */
1070         if (speed_fs)
1071                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1072                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1073         else /* defaul high speed */
1074                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1075                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1076         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1077                         (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1078                         (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1079                         UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1080                         UDC_DEVCTL_THE);
1081 }
1082
1083 /**
1084  * pch_udc_exit() - This API exit usb device controller
1085  * @dev:        Reference to pch_udc_regs structure
1086  */
1087 static void pch_udc_exit(struct pch_udc_dev *dev)
1088 {
1089         /* mask all device interrupts */
1090         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1091         /* mask all ep interrupts */
1092         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1093         /* put device in disconnected state */
1094         pch_udc_set_disconnect(dev);
1095 }
1096
1097 /**
1098  * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1099  * @gadget:     Reference to the gadget driver
1100  *
1101  * Return codes:
1102  *      0:              Success
1103  *      -EINVAL:        If the gadget passed is NULL
1104  */
1105 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1106 {
1107         struct pch_udc_dev      *dev;
1108
1109         if (!gadget)
1110                 return -EINVAL;
1111         dev = container_of(gadget, struct pch_udc_dev, gadget);
1112         return pch_udc_get_frame(dev);
1113 }
1114
1115 /**
1116  * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1117  * @gadget:     Reference to the gadget driver
1118  *
1119  * Return codes:
1120  *      0:              Success
1121  *      -EINVAL:        If the gadget passed is NULL
1122  */
1123 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1124 {
1125         struct pch_udc_dev      *dev;
1126         unsigned long           flags;
1127
1128         if (!gadget)
1129                 return -EINVAL;
1130         dev = container_of(gadget, struct pch_udc_dev, gadget);
1131         spin_lock_irqsave(&dev->lock, flags);
1132         pch_udc_rmt_wakeup(dev);
1133         spin_unlock_irqrestore(&dev->lock, flags);
1134         return 0;
1135 }
1136
1137 /**
1138  * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1139  *                              is self powered or not
1140  * @gadget:     Reference to the gadget driver
1141  * @value:      Specifies self powered or not
1142  *
1143  * Return codes:
1144  *      0:              Success
1145  *      -EINVAL:        If the gadget passed is NULL
1146  */
1147 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1148 {
1149         struct pch_udc_dev      *dev;
1150
1151         if (!gadget)
1152                 return -EINVAL;
1153         gadget->is_selfpowered = (value != 0);
1154         dev = container_of(gadget, struct pch_udc_dev, gadget);
1155         if (value)
1156                 pch_udc_set_selfpowered(dev);
1157         else
1158                 pch_udc_clear_selfpowered(dev);
1159         return 0;
1160 }
1161
1162 /**
1163  * pch_udc_pcd_pullup() - This API is invoked to make the device
1164  *                              visible/invisible to the host
1165  * @gadget:     Reference to the gadget driver
1166  * @is_on:      Specifies whether the pull up is made active or inactive
1167  *
1168  * Return codes:
1169  *      0:              Success
1170  *      -EINVAL:        If the gadget passed is NULL
1171  */
1172 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1173 {
1174         struct pch_udc_dev      *dev;
1175         unsigned long           iflags;
1176
1177         if (!gadget)
1178                 return -EINVAL;
1179
1180         dev = container_of(gadget, struct pch_udc_dev, gadget);
1181
1182         spin_lock_irqsave(&dev->lock, iflags);
1183         if (is_on) {
1184                 pch_udc_reconnect(dev);
1185         } else {
1186                 if (dev->driver && dev->driver->disconnect) {
1187                         spin_unlock_irqrestore(&dev->lock, iflags);
1188                         dev->driver->disconnect(&dev->gadget);
1189                         spin_lock_irqsave(&dev->lock, iflags);
1190                 }
1191                 pch_udc_set_disconnect(dev);
1192         }
1193         spin_unlock_irqrestore(&dev->lock, iflags);
1194
1195         return 0;
1196 }
1197
1198 /**
1199  * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1200  *                              transceiver (or GPIO) that
1201  *                              detects a VBUS power session starting/ending
1202  * @gadget:     Reference to the gadget driver
1203  * @is_active:  specifies whether the session is starting or ending
1204  *
1205  * Return codes:
1206  *      0:              Success
1207  *      -EINVAL:        If the gadget passed is NULL
1208  */
1209 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1210 {
1211         struct pch_udc_dev      *dev;
1212
1213         if (!gadget)
1214                 return -EINVAL;
1215         dev = container_of(gadget, struct pch_udc_dev, gadget);
1216         pch_udc_vbus_session(dev, is_active);
1217         return 0;
1218 }
1219
1220 /**
1221  * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1222  *                              SET_CONFIGURATION calls to
1223  *                              specify how much power the device can consume
1224  * @gadget:     Reference to the gadget driver
1225  * @mA:         specifies the current limit in 2mA unit
1226  *
1227  * Return codes:
1228  *      -EINVAL:        If the gadget passed is NULL
1229  *      -EOPNOTSUPP:
1230  */
1231 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1232 {
1233         return -EOPNOTSUPP;
1234 }
1235
1236 static int pch_udc_start(struct usb_gadget *g,
1237                 struct usb_gadget_driver *driver);
1238 static int pch_udc_stop(struct usb_gadget *g);
1239
1240 static const struct usb_gadget_ops pch_udc_ops = {
1241         .get_frame = pch_udc_pcd_get_frame,
1242         .wakeup = pch_udc_pcd_wakeup,
1243         .set_selfpowered = pch_udc_pcd_selfpowered,
1244         .pullup = pch_udc_pcd_pullup,
1245         .vbus_session = pch_udc_pcd_vbus_session,
1246         .vbus_draw = pch_udc_pcd_vbus_draw,
1247         .udc_start = pch_udc_start,
1248         .udc_stop = pch_udc_stop,
1249 };
1250
1251 /**
1252  * pch_vbus_gpio_get_value() - This API gets value of GPIO port as VBUS status.
1253  * @dev:        Reference to the driver structure
1254  *
1255  * Return value:
1256  *      1: VBUS is high
1257  *      0: VBUS is low
1258  *     -1: It is not enable to detect VBUS using GPIO
1259  */
1260 static int pch_vbus_gpio_get_value(struct pch_udc_dev *dev)
1261 {
1262         int vbus = 0;
1263
1264         if (dev->vbus_gpio.port)
1265                 vbus = gpio_get_value(dev->vbus_gpio.port) ? 1 : 0;
1266         else
1267                 vbus = -1;
1268
1269         return vbus;
1270 }
1271
1272 /**
1273  * pch_vbus_gpio_work_fall() - This API keeps watch on VBUS becoming Low.
1274  *                             If VBUS is Low, disconnect is processed
1275  * @irq_work:   Structure for WorkQueue
1276  *
1277  */
1278 static void pch_vbus_gpio_work_fall(struct work_struct *irq_work)
1279 {
1280         struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1281                 struct pch_vbus_gpio_data, irq_work_fall);
1282         struct pch_udc_dev *dev =
1283                 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1284         int vbus_saved = -1;
1285         int vbus;
1286         int count;
1287
1288         if (!dev->vbus_gpio.port)
1289                 return;
1290
1291         for (count = 0; count < (PCH_VBUS_PERIOD / PCH_VBUS_INTERVAL);
1292                 count++) {
1293                 vbus = pch_vbus_gpio_get_value(dev);
1294
1295                 if ((vbus_saved == vbus) && (vbus == 0)) {
1296                         dev_dbg(&dev->pdev->dev, "VBUS fell");
1297                         if (dev->driver
1298                                 && dev->driver->disconnect) {
1299                                 dev->driver->disconnect(
1300                                         &dev->gadget);
1301                         }
1302                         if (dev->vbus_gpio.intr)
1303                                 pch_udc_init(dev);
1304                         else
1305                                 pch_udc_reconnect(dev);
1306                         return;
1307                 }
1308                 vbus_saved = vbus;
1309                 mdelay(PCH_VBUS_INTERVAL);
1310         }
1311 }
1312
1313 /**
1314  * pch_vbus_gpio_work_rise() - This API checks VBUS is High.
1315  *                             If VBUS is High, connect is processed
1316  * @irq_work:   Structure for WorkQueue
1317  *
1318  */
1319 static void pch_vbus_gpio_work_rise(struct work_struct *irq_work)
1320 {
1321         struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1322                 struct pch_vbus_gpio_data, irq_work_rise);
1323         struct pch_udc_dev *dev =
1324                 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1325         int vbus;
1326
1327         if (!dev->vbus_gpio.port)
1328                 return;
1329
1330         mdelay(PCH_VBUS_INTERVAL);
1331         vbus = pch_vbus_gpio_get_value(dev);
1332
1333         if (vbus == 1) {
1334                 dev_dbg(&dev->pdev->dev, "VBUS rose");
1335                 pch_udc_reconnect(dev);
1336                 return;
1337         }
1338 }
1339
1340 /**
1341  * pch_vbus_gpio_irq() - IRQ handler for GPIO intrerrupt for changing VBUS
1342  * @irq:        Interrupt request number
1343  * @dev:        Reference to the device structure
1344  *
1345  * Return codes:
1346  *      0: Success
1347  *      -EINVAL: GPIO port is invalid or can't be initialized.
1348  */
1349 static irqreturn_t pch_vbus_gpio_irq(int irq, void *data)
1350 {
1351         struct pch_udc_dev *dev = (struct pch_udc_dev *)data;
1352
1353         if (!dev->vbus_gpio.port || !dev->vbus_gpio.intr)
1354                 return IRQ_NONE;
1355
1356         if (pch_vbus_gpio_get_value(dev))
1357                 schedule_work(&dev->vbus_gpio.irq_work_rise);
1358         else
1359                 schedule_work(&dev->vbus_gpio.irq_work_fall);
1360
1361         return IRQ_HANDLED;
1362 }
1363
1364 /**
1365  * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS.
1366  * @dev:        Reference to the driver structure
1367  * @vbus_gpio   Number of GPIO port to detect gpio
1368  *
1369  * Return codes:
1370  *      0: Success
1371  *      -EINVAL: GPIO port is invalid or can't be initialized.
1372  */
1373 static int pch_vbus_gpio_init(struct pch_udc_dev *dev, int vbus_gpio_port)
1374 {
1375         int err;
1376         int irq_num = 0;
1377
1378         dev->vbus_gpio.port = 0;
1379         dev->vbus_gpio.intr = 0;
1380
1381         if (vbus_gpio_port <= -1)
1382                 return -EINVAL;
1383
1384         err = gpio_is_valid(vbus_gpio_port);
1385         if (!err) {
1386                 pr_err("%s: gpio port %d is invalid\n",
1387                         __func__, vbus_gpio_port);
1388                 return -EINVAL;
1389         }
1390
1391         err = gpio_request(vbus_gpio_port, "pch_vbus");
1392         if (err) {
1393                 pr_err("%s: can't request gpio port %d, err: %d\n",
1394                         __func__, vbus_gpio_port, err);
1395                 return -EINVAL;
1396         }
1397
1398         dev->vbus_gpio.port = vbus_gpio_port;
1399         gpio_direction_input(vbus_gpio_port);
1400         INIT_WORK(&dev->vbus_gpio.irq_work_fall, pch_vbus_gpio_work_fall);
1401
1402         irq_num = gpio_to_irq(vbus_gpio_port);
1403         if (irq_num > 0) {
1404                 irq_set_irq_type(irq_num, IRQ_TYPE_EDGE_BOTH);
1405                 err = request_irq(irq_num, pch_vbus_gpio_irq, 0,
1406                         "vbus_detect", dev);
1407                 if (!err) {
1408                         dev->vbus_gpio.intr = irq_num;
1409                         INIT_WORK(&dev->vbus_gpio.irq_work_rise,
1410                                 pch_vbus_gpio_work_rise);
1411                 } else {
1412                         pr_err("%s: can't request irq %d, err: %d\n",
1413                                 __func__, irq_num, err);
1414                 }
1415         }
1416
1417         return 0;
1418 }
1419
1420 /**
1421  * pch_vbus_gpio_free() - This API frees resources of GPIO port
1422  * @dev:        Reference to the driver structure
1423  */
1424 static void pch_vbus_gpio_free(struct pch_udc_dev *dev)
1425 {
1426         if (dev->vbus_gpio.intr)
1427                 free_irq(dev->vbus_gpio.intr, dev);
1428
1429         if (dev->vbus_gpio.port)
1430                 gpio_free(dev->vbus_gpio.port);
1431 }
1432
1433 /**
1434  * complete_req() - This API is invoked from the driver when processing
1435  *                      of a request is complete
1436  * @ep:         Reference to the endpoint structure
1437  * @req:        Reference to the request structure
1438  * @status:     Indicates the success/failure of completion
1439  */
1440 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1441                                                                  int status)
1442         __releases(&dev->lock)
1443         __acquires(&dev->lock)
1444 {
1445         struct pch_udc_dev      *dev;
1446         unsigned halted = ep->halted;
1447
1448         list_del_init(&req->queue);
1449
1450         /* set new status if pending */
1451         if (req->req.status == -EINPROGRESS)
1452                 req->req.status = status;
1453         else
1454                 status = req->req.status;
1455
1456         dev = ep->dev;
1457         if (req->dma_mapped) {
1458                 if (req->dma == DMA_ADDR_INVALID) {
1459                         if (ep->in)
1460                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1461                                                  req->req.length,
1462                                                  DMA_TO_DEVICE);
1463                         else
1464                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1465                                                  req->req.length,
1466                                                  DMA_FROM_DEVICE);
1467                         req->req.dma = DMA_ADDR_INVALID;
1468                 } else {
1469                         if (ep->in)
1470                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1471                                                  req->req.length,
1472                                                  DMA_TO_DEVICE);
1473                         else {
1474                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1475                                                  req->req.length,
1476                                                  DMA_FROM_DEVICE);
1477                                 memcpy(req->req.buf, req->buf, req->req.length);
1478                         }
1479                         kfree(req->buf);
1480                         req->dma = DMA_ADDR_INVALID;
1481                 }
1482                 req->dma_mapped = 0;
1483         }
1484         ep->halted = 1;
1485         spin_unlock(&dev->lock);
1486         if (!ep->in)
1487                 pch_udc_ep_clear_rrdy(ep);
1488         usb_gadget_giveback_request(&ep->ep, &req->req);
1489         spin_lock(&dev->lock);
1490         ep->halted = halted;
1491 }
1492
1493 /**
1494  * empty_req_queue() - This API empties the request queue of an endpoint
1495  * @ep:         Reference to the endpoint structure
1496  */
1497 static void empty_req_queue(struct pch_udc_ep *ep)
1498 {
1499         struct pch_udc_request  *req;
1500
1501         ep->halted = 1;
1502         while (!list_empty(&ep->queue)) {
1503                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1504                 complete_req(ep, req, -ESHUTDOWN);      /* Remove from list */
1505         }
1506 }
1507
1508 /**
1509  * pch_udc_free_dma_chain() - This function frees the DMA chain created
1510  *                              for the request
1511  * @dev         Reference to the driver structure
1512  * @req         Reference to the request to be freed
1513  *
1514  * Return codes:
1515  *      0: Success
1516  */
1517 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1518                                    struct pch_udc_request *req)
1519 {
1520         struct pch_udc_data_dma_desc *td = req->td_data;
1521         unsigned i = req->chain_len;
1522
1523         dma_addr_t addr2;
1524         dma_addr_t addr = (dma_addr_t)td->next;
1525         td->next = 0x00;
1526         for (; i > 1; --i) {
1527                 /* do not free first desc., will be done by free for request */
1528                 td = phys_to_virt(addr);
1529                 addr2 = (dma_addr_t)td->next;
1530                 dma_pool_free(dev->data_requests, td, addr);
1531                 addr = addr2;
1532         }
1533         req->chain_len = 1;
1534 }
1535
1536 /**
1537  * pch_udc_create_dma_chain() - This function creates or reinitializes
1538  *                              a DMA chain
1539  * @ep:         Reference to the endpoint structure
1540  * @req:        Reference to the request
1541  * @buf_len:    The buffer length
1542  * @gfp_flags:  Flags to be used while mapping the data buffer
1543  *
1544  * Return codes:
1545  *      0:              success,
1546  *      -ENOMEM:        dma_pool_alloc invocation fails
1547  */
1548 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1549                                     struct pch_udc_request *req,
1550                                     unsigned long buf_len,
1551                                     gfp_t gfp_flags)
1552 {
1553         struct pch_udc_data_dma_desc *td = req->td_data, *last;
1554         unsigned long bytes = req->req.length, i = 0;
1555         dma_addr_t dma_addr;
1556         unsigned len = 1;
1557
1558         if (req->chain_len > 1)
1559                 pch_udc_free_dma_chain(ep->dev, req);
1560
1561         if (req->dma == DMA_ADDR_INVALID)
1562                 td->dataptr = req->req.dma;
1563         else
1564                 td->dataptr = req->dma;
1565
1566         td->status = PCH_UDC_BS_HST_BSY;
1567         for (; ; bytes -= buf_len, ++len) {
1568                 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1569                 if (bytes <= buf_len)
1570                         break;
1571                 last = td;
1572                 td = dma_pool_alloc(ep->dev->data_requests, gfp_flags,
1573                                     &dma_addr);
1574                 if (!td)
1575                         goto nomem;
1576                 i += buf_len;
1577                 td->dataptr = req->td_data->dataptr + i;
1578                 last->next = dma_addr;
1579         }
1580
1581         req->td_data_last = td;
1582         td->status |= PCH_UDC_DMA_LAST;
1583         td->next = req->td_data_phys;
1584         req->chain_len = len;
1585         return 0;
1586
1587 nomem:
1588         if (len > 1) {
1589                 req->chain_len = len;
1590                 pch_udc_free_dma_chain(ep->dev, req);
1591         }
1592         req->chain_len = 1;
1593         return -ENOMEM;
1594 }
1595
1596 /**
1597  * prepare_dma() - This function creates and initializes the DMA chain
1598  *                      for the request
1599  * @ep:         Reference to the endpoint structure
1600  * @req:        Reference to the request
1601  * @gfp:        Flag to be used while mapping the data buffer
1602  *
1603  * Return codes:
1604  *      0:              Success
1605  *      Other 0:        linux error number on failure
1606  */
1607 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1608                           gfp_t gfp)
1609 {
1610         int     retval;
1611
1612         /* Allocate and create a DMA chain */
1613         retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1614         if (retval) {
1615                 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1616                 return retval;
1617         }
1618         if (ep->in)
1619                 req->td_data->status = (req->td_data->status &
1620                                 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1621         return 0;
1622 }
1623
1624 /**
1625  * process_zlp() - This function process zero length packets
1626  *                      from the gadget driver
1627  * @ep:         Reference to the endpoint structure
1628  * @req:        Reference to the request
1629  */
1630 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1631 {
1632         struct pch_udc_dev      *dev = ep->dev;
1633
1634         /* IN zlp's are handled by hardware */
1635         complete_req(ep, req, 0);
1636
1637         /* if set_config or set_intf is waiting for ack by zlp
1638          * then set CSR_DONE
1639          */
1640         if (dev->set_cfg_not_acked) {
1641                 pch_udc_set_csr_done(dev);
1642                 dev->set_cfg_not_acked = 0;
1643         }
1644         /* setup command is ACK'ed now by zlp */
1645         if (!dev->stall && dev->waiting_zlp_ack) {
1646                 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1647                 dev->waiting_zlp_ack = 0;
1648         }
1649 }
1650
1651 /**
1652  * pch_udc_start_rxrequest() - This function starts the receive requirement.
1653  * @ep:         Reference to the endpoint structure
1654  * @req:        Reference to the request structure
1655  */
1656 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1657                                          struct pch_udc_request *req)
1658 {
1659         struct pch_udc_data_dma_desc *td_data;
1660
1661         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1662         td_data = req->td_data;
1663         /* Set the status bits for all descriptors */
1664         while (1) {
1665                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1666                                     PCH_UDC_BS_HST_RDY;
1667                 if ((td_data->status & PCH_UDC_DMA_LAST) ==  PCH_UDC_DMA_LAST)
1668                         break;
1669                 td_data = phys_to_virt(td_data->next);
1670         }
1671         /* Write the descriptor pointer */
1672         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1673         req->dma_going = 1;
1674         pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1675         pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1676         pch_udc_ep_clear_nak(ep);
1677         pch_udc_ep_set_rrdy(ep);
1678 }
1679
1680 /**
1681  * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1682  *                              from gadget driver
1683  * @usbep:      Reference to the USB endpoint structure
1684  * @desc:       Reference to the USB endpoint descriptor structure
1685  *
1686  * Return codes:
1687  *      0:              Success
1688  *      -EINVAL:
1689  *      -ESHUTDOWN:
1690  */
1691 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1692                                     const struct usb_endpoint_descriptor *desc)
1693 {
1694         struct pch_udc_ep       *ep;
1695         struct pch_udc_dev      *dev;
1696         unsigned long           iflags;
1697
1698         if (!usbep || (usbep->name == ep0_string) || !desc ||
1699             (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1700                 return -EINVAL;
1701
1702         ep = container_of(usbep, struct pch_udc_ep, ep);
1703         dev = ep->dev;
1704         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1705                 return -ESHUTDOWN;
1706         spin_lock_irqsave(&dev->lock, iflags);
1707         ep->ep.desc = desc;
1708         ep->halted = 0;
1709         pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1710         ep->ep.maxpacket = usb_endpoint_maxp(desc);
1711         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1712         spin_unlock_irqrestore(&dev->lock, iflags);
1713         return 0;
1714 }
1715
1716 /**
1717  * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1718  *                              from gadget driver
1719  * @usbep       Reference to the USB endpoint structure
1720  *
1721  * Return codes:
1722  *      0:              Success
1723  *      -EINVAL:
1724  */
1725 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1726 {
1727         struct pch_udc_ep       *ep;
1728         unsigned long   iflags;
1729
1730         if (!usbep)
1731                 return -EINVAL;
1732
1733         ep = container_of(usbep, struct pch_udc_ep, ep);
1734         if ((usbep->name == ep0_string) || !ep->ep.desc)
1735                 return -EINVAL;
1736
1737         spin_lock_irqsave(&ep->dev->lock, iflags);
1738         empty_req_queue(ep);
1739         ep->halted = 1;
1740         pch_udc_ep_disable(ep);
1741         pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1742         ep->ep.desc = NULL;
1743         INIT_LIST_HEAD(&ep->queue);
1744         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1745         return 0;
1746 }
1747
1748 /**
1749  * pch_udc_alloc_request() - This function allocates request structure.
1750  *                              It is called by gadget driver
1751  * @usbep:      Reference to the USB endpoint structure
1752  * @gfp:        Flag to be used while allocating memory
1753  *
1754  * Return codes:
1755  *      NULL:                   Failure
1756  *      Allocated address:      Success
1757  */
1758 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1759                                                   gfp_t gfp)
1760 {
1761         struct pch_udc_request          *req;
1762         struct pch_udc_ep               *ep;
1763         struct pch_udc_data_dma_desc    *dma_desc;
1764
1765         if (!usbep)
1766                 return NULL;
1767         ep = container_of(usbep, struct pch_udc_ep, ep);
1768         req = kzalloc(sizeof *req, gfp);
1769         if (!req)
1770                 return NULL;
1771         req->req.dma = DMA_ADDR_INVALID;
1772         req->dma = DMA_ADDR_INVALID;
1773         INIT_LIST_HEAD(&req->queue);
1774         if (!ep->dev->dma_addr)
1775                 return &req->req;
1776         /* ep0 in requests are allocated from data pool here */
1777         dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
1778                                   &req->td_data_phys);
1779         if (NULL == dma_desc) {
1780                 kfree(req);
1781                 return NULL;
1782         }
1783         /* prevent from using desc. - set HOST BUSY */
1784         dma_desc->status |= PCH_UDC_BS_HST_BSY;
1785         dma_desc->dataptr = lower_32_bits(DMA_ADDR_INVALID);
1786         req->td_data = dma_desc;
1787         req->td_data_last = dma_desc;
1788         req->chain_len = 1;
1789         return &req->req;
1790 }
1791
1792 /**
1793  * pch_udc_free_request() - This function frees request structure.
1794  *                              It is called by gadget driver
1795  * @usbep:      Reference to the USB endpoint structure
1796  * @usbreq:     Reference to the USB request
1797  */
1798 static void pch_udc_free_request(struct usb_ep *usbep,
1799                                   struct usb_request *usbreq)
1800 {
1801         struct pch_udc_ep       *ep;
1802         struct pch_udc_request  *req;
1803         struct pch_udc_dev      *dev;
1804
1805         if (!usbep || !usbreq)
1806                 return;
1807         ep = container_of(usbep, struct pch_udc_ep, ep);
1808         req = container_of(usbreq, struct pch_udc_request, req);
1809         dev = ep->dev;
1810         if (!list_empty(&req->queue))
1811                 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1812                         __func__, usbep->name, req);
1813         if (req->td_data != NULL) {
1814                 if (req->chain_len > 1)
1815                         pch_udc_free_dma_chain(ep->dev, req);
1816                 dma_pool_free(ep->dev->data_requests, req->td_data,
1817                               req->td_data_phys);
1818         }
1819         kfree(req);
1820 }
1821
1822 /**
1823  * pch_udc_pcd_queue() - This function queues a request packet. It is called
1824  *                      by gadget driver
1825  * @usbep:      Reference to the USB endpoint structure
1826  * @usbreq:     Reference to the USB request
1827  * @gfp:        Flag to be used while mapping the data buffer
1828  *
1829  * Return codes:
1830  *      0:                      Success
1831  *      linux error number:     Failure
1832  */
1833 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1834                                                                  gfp_t gfp)
1835 {
1836         int retval = 0;
1837         struct pch_udc_ep       *ep;
1838         struct pch_udc_dev      *dev;
1839         struct pch_udc_request  *req;
1840         unsigned long   iflags;
1841
1842         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1843                 return -EINVAL;
1844         ep = container_of(usbep, struct pch_udc_ep, ep);
1845         dev = ep->dev;
1846         if (!ep->ep.desc && ep->num)
1847                 return -EINVAL;
1848         req = container_of(usbreq, struct pch_udc_request, req);
1849         if (!list_empty(&req->queue))
1850                 return -EINVAL;
1851         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1852                 return -ESHUTDOWN;
1853         spin_lock_irqsave(&dev->lock, iflags);
1854         /* map the buffer for dma */
1855         if (usbreq->length &&
1856             ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1857                 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1858                         if (ep->in)
1859                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1860                                                              usbreq->buf,
1861                                                              usbreq->length,
1862                                                              DMA_TO_DEVICE);
1863                         else
1864                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1865                                                              usbreq->buf,
1866                                                              usbreq->length,
1867                                                              DMA_FROM_DEVICE);
1868                 } else {
1869                         req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1870                         if (!req->buf) {
1871                                 retval = -ENOMEM;
1872                                 goto probe_end;
1873                         }
1874                         if (ep->in) {
1875                                 memcpy(req->buf, usbreq->buf, usbreq->length);
1876                                 req->dma = dma_map_single(&dev->pdev->dev,
1877                                                           req->buf,
1878                                                           usbreq->length,
1879                                                           DMA_TO_DEVICE);
1880                         } else
1881                                 req->dma = dma_map_single(&dev->pdev->dev,
1882                                                           req->buf,
1883                                                           usbreq->length,
1884                                                           DMA_FROM_DEVICE);
1885                 }
1886                 req->dma_mapped = 1;
1887         }
1888         if (usbreq->length > 0) {
1889                 retval = prepare_dma(ep, req, GFP_ATOMIC);
1890                 if (retval)
1891                         goto probe_end;
1892         }
1893         usbreq->actual = 0;
1894         usbreq->status = -EINPROGRESS;
1895         req->dma_done = 0;
1896         if (list_empty(&ep->queue) && !ep->halted) {
1897                 /* no pending transfer, so start this req */
1898                 if (!usbreq->length) {
1899                         process_zlp(ep, req);
1900                         retval = 0;
1901                         goto probe_end;
1902                 }
1903                 if (!ep->in) {
1904                         pch_udc_start_rxrequest(ep, req);
1905                 } else {
1906                         /*
1907                         * For IN trfr the descriptors will be programmed and
1908                         * P bit will be set when
1909                         * we get an IN token
1910                         */
1911                         pch_udc_wait_ep_stall(ep);
1912                         pch_udc_ep_clear_nak(ep);
1913                         pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1914                 }
1915         }
1916         /* Now add this request to the ep's pending requests */
1917         if (req != NULL)
1918                 list_add_tail(&req->queue, &ep->queue);
1919
1920 probe_end:
1921         spin_unlock_irqrestore(&dev->lock, iflags);
1922         return retval;
1923 }
1924
1925 /**
1926  * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1927  *                              It is called by gadget driver
1928  * @usbep:      Reference to the USB endpoint structure
1929  * @usbreq:     Reference to the USB request
1930  *
1931  * Return codes:
1932  *      0:                      Success
1933  *      linux error number:     Failure
1934  */
1935 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1936                                 struct usb_request *usbreq)
1937 {
1938         struct pch_udc_ep       *ep;
1939         struct pch_udc_request  *req;
1940         unsigned long           flags;
1941         int ret = -EINVAL;
1942
1943         ep = container_of(usbep, struct pch_udc_ep, ep);
1944         if (!usbep || !usbreq || (!ep->ep.desc && ep->num))
1945                 return ret;
1946         req = container_of(usbreq, struct pch_udc_request, req);
1947         spin_lock_irqsave(&ep->dev->lock, flags);
1948         /* make sure it's still queued on this endpoint */
1949         list_for_each_entry(req, &ep->queue, queue) {
1950                 if (&req->req == usbreq) {
1951                         pch_udc_ep_set_nak(ep);
1952                         if (!list_empty(&req->queue))
1953                                 complete_req(ep, req, -ECONNRESET);
1954                         ret = 0;
1955                         break;
1956                 }
1957         }
1958         spin_unlock_irqrestore(&ep->dev->lock, flags);
1959         return ret;
1960 }
1961
1962 /**
1963  * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1964  *                          feature
1965  * @usbep:      Reference to the USB endpoint structure
1966  * @halt:       Specifies whether to set or clear the feature
1967  *
1968  * Return codes:
1969  *      0:                      Success
1970  *      linux error number:     Failure
1971  */
1972 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1973 {
1974         struct pch_udc_ep       *ep;
1975         unsigned long iflags;
1976         int ret;
1977
1978         if (!usbep)
1979                 return -EINVAL;
1980         ep = container_of(usbep, struct pch_udc_ep, ep);
1981         if (!ep->ep.desc && !ep->num)
1982                 return -EINVAL;
1983         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1984                 return -ESHUTDOWN;
1985         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1986         if (list_empty(&ep->queue)) {
1987                 if (halt) {
1988                         if (ep->num == PCH_UDC_EP0)
1989                                 ep->dev->stall = 1;
1990                         pch_udc_ep_set_stall(ep);
1991                         pch_udc_enable_ep_interrupts(
1992                                 ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1993                 } else {
1994                         pch_udc_ep_clear_stall(ep);
1995                 }
1996                 ret = 0;
1997         } else {
1998                 ret = -EAGAIN;
1999         }
2000         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2001         return ret;
2002 }
2003
2004 /**
2005  * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
2006  *                              halt feature
2007  * @usbep:      Reference to the USB endpoint structure
2008  * @halt:       Specifies whether to set or clear the feature
2009  *
2010  * Return codes:
2011  *      0:                      Success
2012  *      linux error number:     Failure
2013  */
2014 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
2015 {
2016         struct pch_udc_ep       *ep;
2017         unsigned long iflags;
2018         int ret;
2019
2020         if (!usbep)
2021                 return -EINVAL;
2022         ep = container_of(usbep, struct pch_udc_ep, ep);
2023         if (!ep->ep.desc && !ep->num)
2024                 return -EINVAL;
2025         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2026                 return -ESHUTDOWN;
2027         spin_lock_irqsave(&udc_stall_spinlock, iflags);
2028         if (!list_empty(&ep->queue)) {
2029                 ret = -EAGAIN;
2030         } else {
2031                 if (ep->num == PCH_UDC_EP0)
2032                         ep->dev->stall = 1;
2033                 pch_udc_ep_set_stall(ep);
2034                 pch_udc_enable_ep_interrupts(ep->dev,
2035                                              PCH_UDC_EPINT(ep->in, ep->num));
2036                 ep->dev->prot_stall = 1;
2037                 ret = 0;
2038         }
2039         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2040         return ret;
2041 }
2042
2043 /**
2044  * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
2045  * @usbep:      Reference to the USB endpoint structure
2046  */
2047 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
2048 {
2049         struct pch_udc_ep  *ep;
2050
2051         if (!usbep)
2052                 return;
2053
2054         ep = container_of(usbep, struct pch_udc_ep, ep);
2055         if (ep->ep.desc || !ep->num)
2056                 pch_udc_ep_fifo_flush(ep, ep->in);
2057 }
2058
2059 static const struct usb_ep_ops pch_udc_ep_ops = {
2060         .enable         = pch_udc_pcd_ep_enable,
2061         .disable        = pch_udc_pcd_ep_disable,
2062         .alloc_request  = pch_udc_alloc_request,
2063         .free_request   = pch_udc_free_request,
2064         .queue          = pch_udc_pcd_queue,
2065         .dequeue        = pch_udc_pcd_dequeue,
2066         .set_halt       = pch_udc_pcd_set_halt,
2067         .set_wedge      = pch_udc_pcd_set_wedge,
2068         .fifo_status    = NULL,
2069         .fifo_flush     = pch_udc_pcd_fifo_flush,
2070 };
2071
2072 /**
2073  * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
2074  * @td_stp:     Reference to the SETP buffer structure
2075  */
2076 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
2077 {
2078         static u32      pky_marker;
2079
2080         if (!td_stp)
2081                 return;
2082         td_stp->reserved = ++pky_marker;
2083         memset(&td_stp->request, 0xFF, sizeof td_stp->request);
2084         td_stp->status = PCH_UDC_BS_HST_RDY;
2085 }
2086
2087 /**
2088  * pch_udc_start_next_txrequest() - This function starts
2089  *                                      the next transmission requirement
2090  * @ep: Reference to the endpoint structure
2091  */
2092 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2093 {
2094         struct pch_udc_request *req;
2095         struct pch_udc_data_dma_desc *td_data;
2096
2097         if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2098                 return;
2099
2100         if (list_empty(&ep->queue))
2101                 return;
2102
2103         /* next request */
2104         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2105         if (req->dma_going)
2106                 return;
2107         if (!req->td_data)
2108                 return;
2109         pch_udc_wait_ep_stall(ep);
2110         req->dma_going = 1;
2111         pch_udc_ep_set_ddptr(ep, 0);
2112         td_data = req->td_data;
2113         while (1) {
2114                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
2115                                    PCH_UDC_BS_HST_RDY;
2116                 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
2117                         break;
2118                 td_data = phys_to_virt(td_data->next);
2119         }
2120         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2121         pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2122         pch_udc_ep_set_pd(ep);
2123         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2124         pch_udc_ep_clear_nak(ep);
2125 }
2126
2127 /**
2128  * pch_udc_complete_transfer() - This function completes a transfer
2129  * @ep:         Reference to the endpoint structure
2130  */
2131 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2132 {
2133         struct pch_udc_request *req;
2134         struct pch_udc_dev *dev = ep->dev;
2135
2136         if (list_empty(&ep->queue))
2137                 return;
2138         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2139         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2140             PCH_UDC_BS_DMA_DONE)
2141                 return;
2142         if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
2143              PCH_UDC_RTS_SUCC) {
2144                 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
2145                         "epstatus=0x%08x\n",
2146                        (req->td_data_last->status & PCH_UDC_RXTX_STS),
2147                        (int)(ep->epsts));
2148                 return;
2149         }
2150
2151         req->req.actual = req->req.length;
2152         req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2153         req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2154         complete_req(ep, req, 0);
2155         req->dma_going = 0;
2156         if (!list_empty(&ep->queue)) {
2157                 pch_udc_wait_ep_stall(ep);
2158                 pch_udc_ep_clear_nak(ep);
2159                 pch_udc_enable_ep_interrupts(ep->dev,
2160                                              PCH_UDC_EPINT(ep->in, ep->num));
2161         } else {
2162                 pch_udc_disable_ep_interrupts(ep->dev,
2163                                               PCH_UDC_EPINT(ep->in, ep->num));
2164         }
2165 }
2166
2167 /**
2168  * pch_udc_complete_receiver() - This function completes a receiver
2169  * @ep:         Reference to the endpoint structure
2170  */
2171 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2172 {
2173         struct pch_udc_request *req;
2174         struct pch_udc_dev *dev = ep->dev;
2175         unsigned int count;
2176         struct pch_udc_data_dma_desc *td;
2177         dma_addr_t addr;
2178
2179         if (list_empty(&ep->queue))
2180                 return;
2181         /* next request */
2182         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2183         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
2184         pch_udc_ep_set_ddptr(ep, 0);
2185         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
2186             PCH_UDC_BS_DMA_DONE)
2187                 td = req->td_data_last;
2188         else
2189                 td = req->td_data;
2190
2191         while (1) {
2192                 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
2193                         dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2194                                 "epstatus=0x%08x\n",
2195                                 (req->td_data->status & PCH_UDC_RXTX_STS),
2196                                 (int)(ep->epsts));
2197                         return;
2198                 }
2199                 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2200                         if (td->status & PCH_UDC_DMA_LAST) {
2201                                 count = td->status & PCH_UDC_RXTX_BYTES;
2202                                 break;
2203                         }
2204                 if (td == req->td_data_last) {
2205                         dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2206                         return;
2207                 }
2208                 addr = (dma_addr_t)td->next;
2209                 td = phys_to_virt(addr);
2210         }
2211         /* on 64k packets the RXBYTES field is zero */
2212         if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2213                 count = UDC_DMA_MAXPACKET;
2214         req->td_data->status |= PCH_UDC_DMA_LAST;
2215         td->status |= PCH_UDC_BS_HST_BSY;
2216
2217         req->dma_going = 0;
2218         req->req.actual = count;
2219         complete_req(ep, req, 0);
2220         /* If there is a new/failed requests try that now */
2221         if (!list_empty(&ep->queue)) {
2222                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2223                 pch_udc_start_rxrequest(ep, req);
2224         }
2225 }
2226
2227 /**
2228  * pch_udc_svc_data_in() - This function process endpoint interrupts
2229  *                              for IN endpoints
2230  * @dev:        Reference to the device structure
2231  * @ep_num:     Endpoint that generated the interrupt
2232  */
2233 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2234 {
2235         u32     epsts;
2236         struct pch_udc_ep       *ep;
2237
2238         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2239         epsts = ep->epsts;
2240         ep->epsts = 0;
2241
2242         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA  | UDC_EPSTS_HE |
2243                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2244                        UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2245                 return;
2246         if ((epsts & UDC_EPSTS_BNA))
2247                 return;
2248         if (epsts & UDC_EPSTS_HE)
2249                 return;
2250         if (epsts & UDC_EPSTS_RSS) {
2251                 pch_udc_ep_set_stall(ep);
2252                 pch_udc_enable_ep_interrupts(ep->dev,
2253                                              PCH_UDC_EPINT(ep->in, ep->num));
2254         }
2255         if (epsts & UDC_EPSTS_RCS) {
2256                 if (!dev->prot_stall) {
2257                         pch_udc_ep_clear_stall(ep);
2258                 } else {
2259                         pch_udc_ep_set_stall(ep);
2260                         pch_udc_enable_ep_interrupts(ep->dev,
2261                                                 PCH_UDC_EPINT(ep->in, ep->num));
2262                 }
2263         }
2264         if (epsts & UDC_EPSTS_TDC)
2265                 pch_udc_complete_transfer(ep);
2266         /* On IN interrupt, provide data if we have any */
2267         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2268             !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2269                 pch_udc_start_next_txrequest(ep);
2270 }
2271
2272 /**
2273  * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2274  * @dev:        Reference to the device structure
2275  * @ep_num:     Endpoint that generated the interrupt
2276  */
2277 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2278 {
2279         u32                     epsts;
2280         struct pch_udc_ep               *ep;
2281         struct pch_udc_request          *req = NULL;
2282
2283         ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2284         epsts = ep->epsts;
2285         ep->epsts = 0;
2286
2287         if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2288                 /* next request */
2289                 req = list_entry(ep->queue.next, struct pch_udc_request,
2290                                  queue);
2291                 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2292                      PCH_UDC_BS_DMA_DONE) {
2293                         if (!req->dma_going)
2294                                 pch_udc_start_rxrequest(ep, req);
2295                         return;
2296                 }
2297         }
2298         if (epsts & UDC_EPSTS_HE)
2299                 return;
2300         if (epsts & UDC_EPSTS_RSS) {
2301                 pch_udc_ep_set_stall(ep);
2302                 pch_udc_enable_ep_interrupts(ep->dev,
2303                                              PCH_UDC_EPINT(ep->in, ep->num));
2304         }
2305         if (epsts & UDC_EPSTS_RCS) {
2306                 if (!dev->prot_stall) {
2307                         pch_udc_ep_clear_stall(ep);
2308                 } else {
2309                         pch_udc_ep_set_stall(ep);
2310                         pch_udc_enable_ep_interrupts(ep->dev,
2311                                                 PCH_UDC_EPINT(ep->in, ep->num));
2312                 }
2313         }
2314         if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2315             UDC_EPSTS_OUT_DATA) {
2316                 if (ep->dev->prot_stall == 1) {
2317                         pch_udc_ep_set_stall(ep);
2318                         pch_udc_enable_ep_interrupts(ep->dev,
2319                                                 PCH_UDC_EPINT(ep->in, ep->num));
2320                 } else {
2321                         pch_udc_complete_receiver(ep);
2322                 }
2323         }
2324         if (list_empty(&ep->queue))
2325                 pch_udc_set_dma(dev, DMA_DIR_RX);
2326 }
2327
2328 static int pch_udc_gadget_setup(struct pch_udc_dev *dev)
2329         __must_hold(&dev->lock)
2330 {
2331         int rc;
2332
2333         /* In some cases we can get an interrupt before driver gets setup */
2334         if (!dev->driver)
2335                 return -ESHUTDOWN;
2336
2337         spin_unlock(&dev->lock);
2338         rc = dev->driver->setup(&dev->gadget, &dev->setup_data);
2339         spin_lock(&dev->lock);
2340         return rc;
2341 }
2342
2343 /**
2344  * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2345  * @dev:        Reference to the device structure
2346  */
2347 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2348 {
2349         u32     epsts;
2350         struct pch_udc_ep       *ep;
2351         struct pch_udc_ep       *ep_out;
2352
2353         ep = &dev->ep[UDC_EP0IN_IDX];
2354         ep_out = &dev->ep[UDC_EP0OUT_IDX];
2355         epsts = ep->epsts;
2356         ep->epsts = 0;
2357
2358         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2359                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2360                        UDC_EPSTS_XFERDONE)))
2361                 return;
2362         if ((epsts & UDC_EPSTS_BNA))
2363                 return;
2364         if (epsts & UDC_EPSTS_HE)
2365                 return;
2366         if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2367                 pch_udc_complete_transfer(ep);
2368                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2369                 ep_out->td_data->status = (ep_out->td_data->status &
2370                                         ~PCH_UDC_BUFF_STS) |
2371                                         PCH_UDC_BS_HST_RDY;
2372                 pch_udc_ep_clear_nak(ep_out);
2373                 pch_udc_set_dma(dev, DMA_DIR_RX);
2374                 pch_udc_ep_set_rrdy(ep_out);
2375         }
2376         /* On IN interrupt, provide data if we have any */
2377         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2378              !(epsts & UDC_EPSTS_TXEMPTY))
2379                 pch_udc_start_next_txrequest(ep);
2380 }
2381
2382 /**
2383  * pch_udc_svc_control_out() - Routine that handle Control
2384  *                                      OUT endpoint interrupts
2385  * @dev:        Reference to the device structure
2386  */
2387 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2388         __releases(&dev->lock)
2389         __acquires(&dev->lock)
2390 {
2391         u32     stat;
2392         int setup_supported;
2393         struct pch_udc_ep       *ep;
2394
2395         ep = &dev->ep[UDC_EP0OUT_IDX];
2396         stat = ep->epsts;
2397         ep->epsts = 0;
2398
2399         /* If setup data */
2400         if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2401             UDC_EPSTS_OUT_SETUP) {
2402                 dev->stall = 0;
2403                 dev->ep[UDC_EP0IN_IDX].halted = 0;
2404                 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2405                 dev->setup_data = ep->td_stp->request;
2406                 pch_udc_init_setup_buff(ep->td_stp);
2407                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2408                 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2409                                       dev->ep[UDC_EP0IN_IDX].in);
2410                 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2411                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2412                 else /* OUT */
2413                         dev->gadget.ep0 = &ep->ep;
2414                 /* If Mass storage Reset */
2415                 if ((dev->setup_data.bRequestType == 0x21) &&
2416                     (dev->setup_data.bRequest == 0xFF))
2417                         dev->prot_stall = 0;
2418                 /* call gadget with setup data received */
2419                 setup_supported = pch_udc_gadget_setup(dev);
2420
2421                 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2422                         ep->td_data->status = (ep->td_data->status &
2423                                                 ~PCH_UDC_BUFF_STS) |
2424                                                 PCH_UDC_BS_HST_RDY;
2425                         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2426                 }
2427                 /* ep0 in returns data on IN phase */
2428                 if (setup_supported >= 0 && setup_supported <
2429                                             UDC_EP0IN_MAX_PKT_SIZE) {
2430                         pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2431                         /* Gadget would have queued a request when
2432                          * we called the setup */
2433                         if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2434                                 pch_udc_set_dma(dev, DMA_DIR_RX);
2435                                 pch_udc_ep_clear_nak(ep);
2436                         }
2437                 } else if (setup_supported < 0) {
2438                         /* if unsupported request, then stall */
2439                         pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2440                         pch_udc_enable_ep_interrupts(ep->dev,
2441                                                 PCH_UDC_EPINT(ep->in, ep->num));
2442                         dev->stall = 0;
2443                         pch_udc_set_dma(dev, DMA_DIR_RX);
2444                 } else {
2445                         dev->waiting_zlp_ack = 1;
2446                 }
2447         } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2448                      UDC_EPSTS_OUT_DATA) && !dev->stall) {
2449                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2450                 pch_udc_ep_set_ddptr(ep, 0);
2451                 if (!list_empty(&ep->queue)) {
2452                         ep->epsts = stat;
2453                         pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2454                 }
2455                 pch_udc_set_dma(dev, DMA_DIR_RX);
2456         }
2457         pch_udc_ep_set_rrdy(ep);
2458 }
2459
2460
2461 /**
2462  * pch_udc_postsvc_epinters() - This function enables end point interrupts
2463  *                              and clears NAK status
2464  * @dev:        Reference to the device structure
2465  * @ep_num:     End point number
2466  */
2467 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2468 {
2469         struct pch_udc_ep       *ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2470         if (list_empty(&ep->queue))
2471                 return;
2472         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2473         pch_udc_ep_clear_nak(ep);
2474 }
2475
2476 /**
2477  * pch_udc_read_all_epstatus() - This function read all endpoint status
2478  * @dev:        Reference to the device structure
2479  * @ep_intr:    Status of endpoint interrupt
2480  */
2481 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2482 {
2483         int i;
2484         struct pch_udc_ep       *ep;
2485
2486         for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2487                 /* IN */
2488                 if (ep_intr & (0x1 << i)) {
2489                         ep = &dev->ep[UDC_EPIN_IDX(i)];
2490                         ep->epsts = pch_udc_read_ep_status(ep);
2491                         pch_udc_clear_ep_status(ep, ep->epsts);
2492                 }
2493                 /* OUT */
2494                 if (ep_intr & (0x10000 << i)) {
2495                         ep = &dev->ep[UDC_EPOUT_IDX(i)];
2496                         ep->epsts = pch_udc_read_ep_status(ep);
2497                         pch_udc_clear_ep_status(ep, ep->epsts);
2498                 }
2499         }
2500 }
2501
2502 /**
2503  * pch_udc_activate_control_ep() - This function enables the control endpoints
2504  *                                      for traffic after a reset
2505  * @dev:        Reference to the device structure
2506  */
2507 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2508 {
2509         struct pch_udc_ep       *ep;
2510         u32 val;
2511
2512         /* Setup the IN endpoint */
2513         ep = &dev->ep[UDC_EP0IN_IDX];
2514         pch_udc_clear_ep_control(ep);
2515         pch_udc_ep_fifo_flush(ep, ep->in);
2516         pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2517         pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2518         /* Initialize the IN EP Descriptor */
2519         ep->td_data      = NULL;
2520         ep->td_stp       = NULL;
2521         ep->td_data_phys = 0;
2522         ep->td_stp_phys  = 0;
2523
2524         /* Setup the OUT endpoint */
2525         ep = &dev->ep[UDC_EP0OUT_IDX];
2526         pch_udc_clear_ep_control(ep);
2527         pch_udc_ep_fifo_flush(ep, ep->in);
2528         pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2529         pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2530         val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2531         pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2532
2533         /* Initialize the SETUP buffer */
2534         pch_udc_init_setup_buff(ep->td_stp);
2535         /* Write the pointer address of dma descriptor */
2536         pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2537         /* Write the pointer address of Setup descriptor */
2538         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2539
2540         /* Initialize the dma descriptor */
2541         ep->td_data->status  = PCH_UDC_DMA_LAST;
2542         ep->td_data->dataptr = dev->dma_addr;
2543         ep->td_data->next    = ep->td_data_phys;
2544
2545         pch_udc_ep_clear_nak(ep);
2546 }
2547
2548
2549 /**
2550  * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2551  * @dev:        Reference to driver structure
2552  */
2553 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2554 {
2555         struct pch_udc_ep       *ep;
2556         int i;
2557
2558         pch_udc_clear_dma(dev, DMA_DIR_TX);
2559         pch_udc_clear_dma(dev, DMA_DIR_RX);
2560         /* Mask all endpoint interrupts */
2561         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2562         /* clear all endpoint interrupts */
2563         pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2564
2565         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2566                 ep = &dev->ep[i];
2567                 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2568                 pch_udc_clear_ep_control(ep);
2569                 pch_udc_ep_set_ddptr(ep, 0);
2570                 pch_udc_write_csr(ep->dev, 0x00, i);
2571         }
2572         dev->stall = 0;
2573         dev->prot_stall = 0;
2574         dev->waiting_zlp_ack = 0;
2575         dev->set_cfg_not_acked = 0;
2576
2577         /* disable ep to empty req queue. Skip the control EP's */
2578         for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2579                 ep = &dev->ep[i];
2580                 pch_udc_ep_set_nak(ep);
2581                 pch_udc_ep_fifo_flush(ep, ep->in);
2582                 /* Complete request queue */
2583                 empty_req_queue(ep);
2584         }
2585         if (dev->driver) {
2586                 spin_unlock(&dev->lock);
2587                 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2588                 spin_lock(&dev->lock);
2589         }
2590 }
2591
2592 /**
2593  * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2594  *                              done interrupt
2595  * @dev:        Reference to driver structure
2596  */
2597 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2598 {
2599         u32 dev_stat, dev_speed;
2600         u32 speed = USB_SPEED_FULL;
2601
2602         dev_stat = pch_udc_read_device_status(dev);
2603         dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2604                                                  UDC_DEVSTS_ENUM_SPEED_SHIFT;
2605         switch (dev_speed) {
2606         case UDC_DEVSTS_ENUM_SPEED_HIGH:
2607                 speed = USB_SPEED_HIGH;
2608                 break;
2609         case  UDC_DEVSTS_ENUM_SPEED_FULL:
2610                 speed = USB_SPEED_FULL;
2611                 break;
2612         case  UDC_DEVSTS_ENUM_SPEED_LOW:
2613                 speed = USB_SPEED_LOW;
2614                 break;
2615         default:
2616                 BUG();
2617         }
2618         dev->gadget.speed = speed;
2619         pch_udc_activate_control_ep(dev);
2620         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2621         pch_udc_set_dma(dev, DMA_DIR_TX);
2622         pch_udc_set_dma(dev, DMA_DIR_RX);
2623         pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2624
2625         /* enable device interrupts */
2626         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2627                                         UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2628                                         UDC_DEVINT_SI | UDC_DEVINT_SC);
2629 }
2630
2631 /**
2632  * pch_udc_svc_intf_interrupt() - This function handles a set interface
2633  *                                interrupt
2634  * @dev:        Reference to driver structure
2635  */
2636 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2637 {
2638         u32 reg, dev_stat = 0;
2639         int i;
2640
2641         dev_stat = pch_udc_read_device_status(dev);
2642         dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2643                                                          UDC_DEVSTS_INTF_SHIFT;
2644         dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2645                                                          UDC_DEVSTS_ALT_SHIFT;
2646         dev->set_cfg_not_acked = 1;
2647         /* Construct the usb request for gadget driver and inform it */
2648         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2649         dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2650         dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2651         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2652         dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2653         /* programm the Endpoint Cfg registers */
2654         /* Only one end point cfg register */
2655         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2656         reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2657               (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2658         reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2659               (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2660         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2661         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2662                 /* clear stall bits */
2663                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2664                 dev->ep[i].halted = 0;
2665         }
2666         dev->stall = 0;
2667         pch_udc_gadget_setup(dev);
2668 }
2669
2670 /**
2671  * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2672  *                              interrupt
2673  * @dev:        Reference to driver structure
2674  */
2675 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2676 {
2677         int i;
2678         u32 reg, dev_stat = 0;
2679
2680         dev_stat = pch_udc_read_device_status(dev);
2681         dev->set_cfg_not_acked = 1;
2682         dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2683                                 UDC_DEVSTS_CFG_SHIFT;
2684         /* make usb request for gadget driver */
2685         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2686         dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2687         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2688         /* program the NE registers */
2689         /* Only one end point cfg register */
2690         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2691         reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2692               (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2693         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2694         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2695                 /* clear stall bits */
2696                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2697                 dev->ep[i].halted = 0;
2698         }
2699         dev->stall = 0;
2700
2701         /* call gadget zero with setup data received */
2702         pch_udc_gadget_setup(dev);
2703 }
2704
2705 /**
2706  * pch_udc_dev_isr() - This function services device interrupts
2707  *                      by invoking appropriate routines.
2708  * @dev:        Reference to the device structure
2709  * @dev_intr:   The Device interrupt status.
2710  */
2711 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2712 {
2713         int vbus;
2714
2715         /* USB Reset Interrupt */
2716         if (dev_intr & UDC_DEVINT_UR) {
2717                 pch_udc_svc_ur_interrupt(dev);
2718                 dev_dbg(&dev->pdev->dev, "USB_RESET\n");
2719         }
2720         /* Enumeration Done Interrupt */
2721         if (dev_intr & UDC_DEVINT_ENUM) {
2722                 pch_udc_svc_enum_interrupt(dev);
2723                 dev_dbg(&dev->pdev->dev, "USB_ENUM\n");
2724         }
2725         /* Set Interface Interrupt */
2726         if (dev_intr & UDC_DEVINT_SI)
2727                 pch_udc_svc_intf_interrupt(dev);
2728         /* Set Config Interrupt */
2729         if (dev_intr & UDC_DEVINT_SC)
2730                 pch_udc_svc_cfg_interrupt(dev);
2731         /* USB Suspend interrupt */
2732         if (dev_intr & UDC_DEVINT_US) {
2733                 if (dev->driver
2734                         && dev->driver->suspend) {
2735                         spin_unlock(&dev->lock);
2736                         dev->driver->suspend(&dev->gadget);
2737                         spin_lock(&dev->lock);
2738                 }
2739
2740                 vbus = pch_vbus_gpio_get_value(dev);
2741                 if ((dev->vbus_session == 0)
2742                         && (vbus != 1)) {
2743                         if (dev->driver && dev->driver->disconnect) {
2744                                 spin_unlock(&dev->lock);
2745                                 dev->driver->disconnect(&dev->gadget);
2746                                 spin_lock(&dev->lock);
2747                         }
2748                         pch_udc_reconnect(dev);
2749                 } else if ((dev->vbus_session == 0)
2750                         && (vbus == 1)
2751                         && !dev->vbus_gpio.intr)
2752                         schedule_work(&dev->vbus_gpio.irq_work_fall);
2753
2754                 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2755         }
2756         /* Clear the SOF interrupt, if enabled */
2757         if (dev_intr & UDC_DEVINT_SOF)
2758                 dev_dbg(&dev->pdev->dev, "SOF\n");
2759         /* ES interrupt, IDLE > 3ms on the USB */
2760         if (dev_intr & UDC_DEVINT_ES)
2761                 dev_dbg(&dev->pdev->dev, "ES\n");
2762         /* RWKP interrupt */
2763         if (dev_intr & UDC_DEVINT_RWKP)
2764                 dev_dbg(&dev->pdev->dev, "RWKP\n");
2765 }
2766
2767 /**
2768  * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2769  * @irq:        Interrupt request number
2770  * @dev:        Reference to the device structure
2771  */
2772 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2773 {
2774         struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2775         u32 dev_intr, ep_intr;
2776         int i;
2777
2778         dev_intr = pch_udc_read_device_interrupts(dev);
2779         ep_intr = pch_udc_read_ep_interrupts(dev);
2780
2781         /* For a hot plug, this find that the controller is hung up. */
2782         if (dev_intr == ep_intr)
2783                 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2784                         dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2785                         /* The controller is reset */
2786                         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2787                         return IRQ_HANDLED;
2788                 }
2789         if (dev_intr)
2790                 /* Clear device interrupts */
2791                 pch_udc_write_device_interrupts(dev, dev_intr);
2792         if (ep_intr)
2793                 /* Clear ep interrupts */
2794                 pch_udc_write_ep_interrupts(dev, ep_intr);
2795         if (!dev_intr && !ep_intr)
2796                 return IRQ_NONE;
2797         spin_lock(&dev->lock);
2798         if (dev_intr)
2799                 pch_udc_dev_isr(dev, dev_intr);
2800         if (ep_intr) {
2801                 pch_udc_read_all_epstatus(dev, ep_intr);
2802                 /* Process Control In interrupts, if present */
2803                 if (ep_intr & UDC_EPINT_IN_EP0) {
2804                         pch_udc_svc_control_in(dev);
2805                         pch_udc_postsvc_epinters(dev, 0);
2806                 }
2807                 /* Process Control Out interrupts, if present */
2808                 if (ep_intr & UDC_EPINT_OUT_EP0)
2809                         pch_udc_svc_control_out(dev);
2810                 /* Process data in end point interrupts */
2811                 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2812                         if (ep_intr & (1 <<  i)) {
2813                                 pch_udc_svc_data_in(dev, i);
2814                                 pch_udc_postsvc_epinters(dev, i);
2815                         }
2816                 }
2817                 /* Process data out end point interrupts */
2818                 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2819                                                  PCH_UDC_USED_EP_NUM); i++)
2820                         if (ep_intr & (1 <<  i))
2821                                 pch_udc_svc_data_out(dev, i -
2822                                                          UDC_EPINT_OUT_SHIFT);
2823         }
2824         spin_unlock(&dev->lock);
2825         return IRQ_HANDLED;
2826 }
2827
2828 /**
2829  * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2830  * @dev:        Reference to the device structure
2831  */
2832 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2833 {
2834         /* enable ep0 interrupts */
2835         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2836                                                 UDC_EPINT_OUT_EP0);
2837         /* enable device interrupts */
2838         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2839                                        UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2840                                        UDC_DEVINT_SI | UDC_DEVINT_SC);
2841 }
2842
2843 /**
2844  * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2845  * @dev:        Reference to the driver structure
2846  */
2847 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2848 {
2849         const char *const ep_string[] = {
2850                 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2851                 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2852                 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2853                 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2854                 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2855                 "ep15in", "ep15out",
2856         };
2857         int i;
2858
2859         dev->gadget.speed = USB_SPEED_UNKNOWN;
2860         INIT_LIST_HEAD(&dev->gadget.ep_list);
2861
2862         /* Initialize the endpoints structures */
2863         memset(dev->ep, 0, sizeof dev->ep);
2864         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2865                 struct pch_udc_ep *ep = &dev->ep[i];
2866                 ep->dev = dev;
2867                 ep->halted = 1;
2868                 ep->num = i / 2;
2869                 ep->in = ~i & 1;
2870                 ep->ep.name = ep_string[i];
2871                 ep->ep.ops = &pch_udc_ep_ops;
2872                 if (ep->in) {
2873                         ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2874                         ep->ep.caps.dir_in = true;
2875                 } else {
2876                         ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2877                                           UDC_EP_REG_SHIFT;
2878                         ep->ep.caps.dir_out = true;
2879                 }
2880                 if (i == UDC_EP0IN_IDX || i == UDC_EP0OUT_IDX) {
2881                         ep->ep.caps.type_control = true;
2882                 } else {
2883                         ep->ep.caps.type_iso = true;
2884                         ep->ep.caps.type_bulk = true;
2885                         ep->ep.caps.type_int = true;
2886                 }
2887                 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2888                 usb_ep_set_maxpacket_limit(&ep->ep, UDC_BULK_MAX_PKT_SIZE);
2889                 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2890                 INIT_LIST_HEAD(&ep->queue);
2891         }
2892         usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IDX].ep, UDC_EP0IN_MAX_PKT_SIZE);
2893         usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IDX].ep, UDC_EP0OUT_MAX_PKT_SIZE);
2894
2895         /* remove ep0 in and out from the list.  They have own pointer */
2896         list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2897         list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2898
2899         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2900         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2901 }
2902
2903 /**
2904  * pch_udc_pcd_init() - This API initializes the driver structure
2905  * @dev:        Reference to the driver structure
2906  *
2907  * Return codes:
2908  *      0: Success
2909  */
2910 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2911 {
2912         pch_udc_init(dev);
2913         pch_udc_pcd_reinit(dev);
2914         pch_vbus_gpio_init(dev, vbus_gpio_port);
2915         return 0;
2916 }
2917
2918 /**
2919  * init_dma_pools() - create dma pools during initialization
2920  * @pdev:       reference to struct pci_dev
2921  */
2922 static int init_dma_pools(struct pch_udc_dev *dev)
2923 {
2924         struct pch_udc_stp_dma_desc     *td_stp;
2925         struct pch_udc_data_dma_desc    *td_data;
2926         void                            *ep0out_buf;
2927
2928         /* DMA setup */
2929         dev->data_requests = dma_pool_create("data_requests", &dev->pdev->dev,
2930                 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2931         if (!dev->data_requests) {
2932                 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2933                         __func__);
2934                 return -ENOMEM;
2935         }
2936
2937         /* dma desc for setup data */
2938         dev->stp_requests = dma_pool_create("setup requests", &dev->pdev->dev,
2939                 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2940         if (!dev->stp_requests) {
2941                 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2942                         __func__);
2943                 return -ENOMEM;
2944         }
2945         /* setup */
2946         td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
2947                                 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2948         if (!td_stp) {
2949                 dev_err(&dev->pdev->dev,
2950                         "%s: can't allocate setup dma descriptor\n", __func__);
2951                 return -ENOMEM;
2952         }
2953         dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2954
2955         /* data: 0 packets !? */
2956         td_data = dma_pool_alloc(dev->data_requests, GFP_KERNEL,
2957                                 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2958         if (!td_data) {
2959                 dev_err(&dev->pdev->dev,
2960                         "%s: can't allocate data dma descriptor\n", __func__);
2961                 return -ENOMEM;
2962         }
2963         dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2964         dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2965         dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2966         dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2967         dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2968
2969         ep0out_buf = devm_kzalloc(&dev->pdev->dev, UDC_EP0OUT_BUFF_SIZE * 4,
2970                                   GFP_KERNEL);
2971         if (!ep0out_buf)
2972                 return -ENOMEM;
2973         dev->dma_addr = dma_map_single(&dev->pdev->dev, ep0out_buf,
2974                                        UDC_EP0OUT_BUFF_SIZE * 4,
2975                                        DMA_FROM_DEVICE);
2976         return dma_mapping_error(&dev->pdev->dev, dev->dma_addr);
2977 }
2978
2979 static int pch_udc_start(struct usb_gadget *g,
2980                 struct usb_gadget_driver *driver)
2981 {
2982         struct pch_udc_dev      *dev = to_pch_udc(g);
2983
2984         driver->driver.bus = NULL;
2985         dev->driver = driver;
2986
2987         /* get ready for ep0 traffic */
2988         pch_udc_setup_ep0(dev);
2989
2990         /* clear SD */
2991         if ((pch_vbus_gpio_get_value(dev) != 0) || !dev->vbus_gpio.intr)
2992                 pch_udc_clear_disconnect(dev);
2993
2994         dev->connected = 1;
2995         return 0;
2996 }
2997
2998 static int pch_udc_stop(struct usb_gadget *g)
2999 {
3000         struct pch_udc_dev      *dev = to_pch_udc(g);
3001
3002         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3003
3004         /* Assures that there are no pending requests with this driver */
3005         dev->driver = NULL;
3006         dev->connected = 0;
3007
3008         /* set SD */
3009         pch_udc_set_disconnect(dev);
3010
3011         return 0;
3012 }
3013
3014 static void pch_udc_shutdown(struct pci_dev *pdev)
3015 {
3016         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3017
3018         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3019         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3020
3021         /* disable the pullup so the host will think we're gone */
3022         pch_udc_set_disconnect(dev);
3023 }
3024
3025 static void pch_udc_remove(struct pci_dev *pdev)
3026 {
3027         struct pch_udc_dev      *dev = pci_get_drvdata(pdev);
3028
3029         usb_del_gadget_udc(&dev->gadget);
3030
3031         /* gadget driver must not be registered */
3032         if (dev->driver)
3033                 dev_err(&pdev->dev,
3034                         "%s: gadget driver still bound!!!\n", __func__);
3035         /* dma pool cleanup */
3036         dma_pool_destroy(dev->data_requests);
3037
3038         if (dev->stp_requests) {
3039                 /* cleanup DMA desc's for ep0in */
3040                 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
3041                         dma_pool_free(dev->stp_requests,
3042                                 dev->ep[UDC_EP0OUT_IDX].td_stp,
3043                                 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3044                 }
3045                 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3046                         dma_pool_free(dev->stp_requests,
3047                                 dev->ep[UDC_EP0OUT_IDX].td_data,
3048                                 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
3049                 }
3050                 dma_pool_destroy(dev->stp_requests);
3051         }
3052
3053         if (dev->dma_addr)
3054                 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
3055                                  UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
3056
3057         pch_vbus_gpio_free(dev);
3058
3059         pch_udc_exit(dev);
3060 }
3061
3062 #ifdef CONFIG_PM_SLEEP
3063 static int pch_udc_suspend(struct device *d)
3064 {
3065         struct pci_dev *pdev = to_pci_dev(d);
3066         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3067
3068         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3069         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3070
3071         return 0;
3072 }
3073
3074 static int pch_udc_resume(struct device *d)
3075 {
3076         return 0;
3077 }
3078
3079 static SIMPLE_DEV_PM_OPS(pch_udc_pm, pch_udc_suspend, pch_udc_resume);
3080 #define PCH_UDC_PM_OPS          (&pch_udc_pm)
3081 #else
3082 #define PCH_UDC_PM_OPS          NULL
3083 #endif /* CONFIG_PM_SLEEP */
3084
3085 static int pch_udc_probe(struct pci_dev *pdev,
3086                           const struct pci_device_id *id)
3087 {
3088         int                     bar;
3089         int                     retval;
3090         struct pch_udc_dev      *dev;
3091
3092         /* init */
3093         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3094         if (!dev)
3095                 return -ENOMEM;
3096
3097         /* pci setup */
3098         retval = pcim_enable_device(pdev);
3099         if (retval)
3100                 return retval;
3101
3102         pci_set_drvdata(pdev, dev);
3103
3104         /* Determine BAR based on PCI ID */
3105         if (id->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC)
3106                 bar = PCH_UDC_PCI_BAR_QUARK_X1000;
3107         else
3108                 bar = PCH_UDC_PCI_BAR;
3109
3110         /* PCI resource allocation */
3111         retval = pcim_iomap_regions(pdev, 1 << bar, pci_name(pdev));
3112         if (retval)
3113                 return retval;
3114
3115         dev->base_addr = pcim_iomap_table(pdev)[bar];
3116
3117         /* initialize the hardware */
3118         if (pch_udc_pcd_init(dev))
3119                 return -ENODEV;
3120
3121         pci_enable_msi(pdev);
3122
3123         retval = devm_request_irq(&pdev->dev, pdev->irq, pch_udc_isr,
3124                                   IRQF_SHARED, KBUILD_MODNAME, dev);
3125         if (retval) {
3126                 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
3127                         pdev->irq);
3128                 goto finished;
3129         }
3130
3131         pci_set_master(pdev);
3132         pci_try_set_mwi(pdev);
3133
3134         /* device struct setup */
3135         spin_lock_init(&dev->lock);
3136         dev->pdev = pdev;
3137         dev->gadget.ops = &pch_udc_ops;
3138
3139         retval = init_dma_pools(dev);
3140         if (retval)
3141                 goto finished;
3142
3143         dev->gadget.name = KBUILD_MODNAME;
3144         dev->gadget.max_speed = USB_SPEED_HIGH;
3145
3146         /* Put the device in disconnected state till a driver is bound */
3147         pch_udc_set_disconnect(dev);
3148         retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3149         if (retval)
3150                 goto finished;
3151         return 0;
3152
3153 finished:
3154         pch_udc_remove(pdev);
3155         return retval;
3156 }
3157
3158 static const struct pci_device_id pch_udc_pcidev_id[] = {
3159         {
3160                 PCI_DEVICE(PCI_VENDOR_ID_INTEL,
3161                            PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC),
3162                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3163                 .class_mask = 0xffffffff,
3164         },
3165         {
3166                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3167                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3168                 .class_mask = 0xffffffff,
3169         },
3170         {
3171                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3172                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3173                 .class_mask = 0xffffffff,
3174         },
3175         {
3176                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3177                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3178                 .class_mask = 0xffffffff,
3179         },
3180         { 0 },
3181 };
3182
3183 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3184
3185 static struct pci_driver pch_udc_driver = {
3186         .name = KBUILD_MODNAME,
3187         .id_table =     pch_udc_pcidev_id,
3188         .probe =        pch_udc_probe,
3189         .remove =       pch_udc_remove,
3190         .shutdown =     pch_udc_shutdown,
3191         .driver = {
3192                 .pm = PCH_UDC_PM_OPS,
3193         },
3194 };
3195
3196 module_pci_driver(pch_udc_driver);
3197
3198 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3199 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3200 MODULE_LICENSE("GPL");