1 // SPDX-License-Identifier: GPL-2.0+
3 * PLX NET2272 high/full speed USB device controller
5 * Copyright (C) 2005-2006 PLX Technology, Inc.
6 * Copyright (C) 2006-2011 Analog Devices, Inc.
13 #define REGADDRPTR 0x00
16 #define ENDPOINT_0_INTERRUPT 0
17 #define ENDPOINT_A_INTERRUPT 1
18 #define ENDPOINT_B_INTERRUPT 2
19 #define ENDPOINT_C_INTERRUPT 3
20 #define VIRTUALIZED_ENDPOINT_INTERRUPT 4
21 #define SETUP_PACKET_INTERRUPT 5
22 #define DMA_DONE_INTERRUPT 6
23 #define SOF_INTERRUPT 7
25 #define CONTROL_STATUS_INTERRUPT 1
26 #define VBUS_INTERRUPT 2
27 #define SUSPEND_REQUEST_INTERRUPT 3
28 #define SUSPEND_REQUEST_CHANGE_INTERRUPT 4
29 #define RESUME_INTERRUPT 5
30 #define ROOT_PORT_RESET_INTERRUPT 6
31 #define RESET_STATUS 7
34 #define DMA_ENDPOINT_SELECT 0
35 #define DREQ_POLARITY 1
36 #define DACK_POLARITY 2
37 #define EOT_POLARITY 3
38 #define DMA_CONTROL_DACK 4
39 #define DMA_REQUEST_ENABLE 5
41 #define DMA_BUFFER_VALID 7
44 #define ENDPOINT_0_INTERRUPT_ENABLE 0
45 #define ENDPOINT_A_INTERRUPT_ENABLE 1
46 #define ENDPOINT_B_INTERRUPT_ENABLE 2
47 #define ENDPOINT_C_INTERRUPT_ENABLE 3
48 #define VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE 4
49 #define SETUP_PACKET_INTERRUPT_ENABLE 5
50 #define DMA_DONE_INTERRUPT_ENABLE 6
51 #define SOF_INTERRUPT_ENABLE 7
53 #define VBUS_INTERRUPT_ENABLE 2
54 #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
55 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 4
56 #define RESUME_INTERRUPT_ENABLE 5
57 #define ROOT_PORT_RESET_INTERRUPT_ENABLE 6
60 #define LOCAL_CLOCK_OUTPUT 1
61 #define LOCAL_CLOCK_OUTPUT_OFF 0
62 #define LOCAL_CLOCK_OUTPUT_3_75MHZ 1
63 #define LOCAL_CLOCK_OUTPUT_7_5MHZ 2
64 #define LOCAL_CLOCK_OUTPUT_15MHZ 3
65 #define LOCAL_CLOCK_OUTPUT_30MHZ 4
66 #define LOCAL_CLOCK_OUTPUT_60MHZ 5
67 #define DMA_SPLIT_BUS_MODE 4
69 #define BUFFER_CONFIGURATION 6
70 #define BUFFER_CONFIGURATION_EPA512_EPB512 0
71 #define BUFFER_CONFIGURATION_EPA1024_EPB512 1
72 #define BUFFER_CONFIGURATION_EPA1024_EPB1024 2
73 #define BUFFER_CONFIGURATION_EPA1024DB 3
74 #define CHIPREV_LEGACY 0x23
75 #define NET2270_LEGACY_REV 0x40
81 #define DMA_DACK_ENABLE 2
82 #define CHIPREV_2272 0x25
83 #define CHIPREV_NET2272_R1 0x10
84 #define CHIPREV_NET2272_R1A 0x11
87 #define IO_WAKEUP_ENABLE 1
88 #define USB_DETECT_ENABLE 3
89 #define USB_ROOT_PORT_WAKEUP_ENABLE 5
92 #define USB_FULL_SPEED 1
93 #define USB_HIGH_SPEED 2
94 #define GENERATE_RESUME 3
95 #define VIRTUAL_ENDPOINT_ENABLE 4
99 #define FORCE_IMMEDIATE 7
101 #define FORCE_TRANSMIT_CRC_ERROR 0
102 #define PREVENT_TRANSMIT_BIT_STUFF 1
103 #define FORCE_RECEIVE_ERROR 2
106 #define TEST_MODE_SELECT 0
107 #define NORMAL_OPERATION 0
108 #define XCVRDIAG 0x33
109 #define FORCE_FULL_SPEED 2
110 #define FORCE_HIGH_SPEED 3
112 #define NORMAL_OPERATION 0
113 #define NON_DRIVING 1
114 #define DISABLE_BITSTUFF_AND_NRZI_ENCODE 2
120 #define VIRTOUT0 0x34
121 #define VIRTOUT1 0x35
132 /* Endpoint Registers (Paged via PAGESEL) */
134 #define EP_STAT0 0x06
135 #define DATA_IN_TOKEN_INTERRUPT 0
136 #define DATA_OUT_TOKEN_INTERRUPT 1
137 #define DATA_PACKET_TRANSMITTED_INTERRUPT 2
138 #define DATA_PACKET_RECEIVED_INTERRUPT 3
139 #define SHORT_PACKET_TRANSFERRED_INTERRUPT 4
140 #define NAK_OUT_PACKETS 5
141 #define BUFFER_EMPTY 6
142 #define BUFFER_FULL 7
143 #define EP_STAT1 0x07
145 #define USB_OUT_ACK_SENT 1
146 #define USB_OUT_NAK_SENT 2
147 #define USB_IN_ACK_RCVD 3
148 #define USB_IN_NAK_SENT 4
149 #define USB_STALL_SENT 5
150 #define LOCAL_OUT_ZLP 6
151 #define BUFFER_FLUSH 7
152 #define EP_TRANSFER0 0x08
153 #define EP_TRANSFER1 0x09
154 #define EP_TRANSFER2 0x0a
155 #define EP_IRQENB 0x0b
156 #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0
157 #define DATA_OUT_TOKEN_INTERRUPT_ENABLE 1
158 #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2
159 #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3
160 #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 4
161 #define EP_AVAIL0 0x0c
162 #define EP_AVAIL1 0x0d
163 #define EP_RSPCLR 0x0e
164 #define EP_RSPSET 0x0f
165 #define ENDPOINT_HALT 0
166 #define ENDPOINT_TOGGLE 1
167 #define NAK_OUT_PACKETS_MODE 2
168 #define CONTROL_STATUS_PHASE_HANDSHAKE 3
169 #define INTERRUPT_MODE 4
170 #define AUTOVALIDATE 5
171 #define HIDE_STATUS_PHASE 6
172 #define ALT_NAK_OUT_PACKETS 7
173 #define EP_MAXPKT0 0x28
174 #define EP_MAXPKT1 0x29
175 #define ADDITIONAL_TRANSACTION_OPPORTUNITIES 3
176 #define NONE_ADDITIONAL_TRANSACTION 0
177 #define ONE_ADDITIONAL_TRANSACTION 1
178 #define TWO_ADDITIONAL_TRANSACTION 2
180 #define ENDPOINT_NUMBER 0
181 #define ENDPOINT_DIRECTION 4
182 #define ENDPOINT_TYPE 5
183 #define ENDPOINT_ENABLE 7
185 #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 0
190 #define EP_BUFF_STATES 0x2c
191 #define BUFFER_A_STATE 0
192 #define BUFFER_B_STATE 2
198 /*---------------------------------------------------------------------------*/
200 #define PCI_DEVICE_ID_RDK1 0x9054
202 /* PCI-RDK EPLD Registers */
203 #define RDK_EPLD_IO_REGISTER1 0x00000000
204 #define RDK_EPLD_USB_RESET 0
205 #define RDK_EPLD_USB_POWERDOWN 1
206 #define RDK_EPLD_USB_WAKEUP 2
207 #define RDK_EPLD_USB_EOT 3
208 #define RDK_EPLD_DPPULL 4
209 #define RDK_EPLD_IO_REGISTER2 0x00000004
210 #define RDK_EPLD_BUSWIDTH 0
211 #define RDK_EPLD_USER 2
212 #define RDK_EPLD_RESET_INTERRUPT_ENABLE 3
213 #define RDK_EPLD_DMA_TIMEOUT_ENABLE 4
214 #define RDK_EPLD_STATUS_REGISTER 0x00000008
215 #define RDK_EPLD_USB_LRESET 0
216 #define RDK_EPLD_REVISION_REGISTER 0x0000000c
218 /* PCI-RDK PLX 9054 Registers */
220 #define PCI_INTERRUPT_ENABLE 8
221 #define LOCAL_INTERRUPT_INPUT_ENABLE 11
222 #define LOCAL_INPUT_INTERRUPT_ACTIVE 15
223 #define LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE 18
224 #define LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE 19
225 #define DMA_CHANNEL_0_INTERRUPT_ACTIVE 21
226 #define DMA_CHANNEL_1_INTERRUPT_ACTIVE 22
228 #define RELOAD_CONFIGURATION_REGISTERS 29
229 #define PCI_ADAPTER_SOFTWARE_RESET 30
230 #define DMAMODE0 0x80
231 #define LOCAL_BUS_WIDTH 0
232 #define INTERNAL_WAIT_STATES 2
233 #define TA_READY_INPUT_ENABLE 6
234 #define LOCAL_BURST_ENABLE 8
235 #define SCATTER_GATHER_MODE 9
236 #define DONE_INTERRUPT_ENABLE 10
237 #define LOCAL_ADDRESSING_MODE 11
238 #define DEMAND_MODE 12
239 #define DMA_EOT_ENABLE 14
240 #define FAST_SLOW_TERMINATE_MODE_SELECT 15
241 #define DMA_CHANNEL_INTERRUPT_SELECT 17
242 #define DMAPADR0 0x84
243 #define DMALADR0 0x88
246 #define DESCRIPTOR_LOCATION 0
247 #define END_OF_CHAIN 1
248 #define INTERRUPT_AFTER_TERMINAL_COUNT 2
249 #define DIRECTION_OF_TRANSFER 3
251 #define CHANNEL_ENABLE 0
252 #define CHANNEL_START 1
253 #define CHANNEL_ABORT 2
254 #define CHANNEL_CLEAR_INTERRUPT 3
255 #define CHANNEL_DONE 4
258 #define MEMORY_SPACE_LOCAL_BUS_WIDTH 0
262 /* Special OR'ing of INTCSR bits */
263 #define LOCAL_INTERRUPT_TEST \
264 ((1 << LOCAL_INPUT_INTERRUPT_ACTIVE) | \
265 (1 << LOCAL_INTERRUPT_INPUT_ENABLE))
267 #define DMA_CHANNEL_0_TEST \
268 ((1 << DMA_CHANNEL_0_INTERRUPT_ACTIVE) | \
269 (1 << LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE))
271 #define DMA_CHANNEL_1_TEST \
272 ((1 << DMA_CHANNEL_1_INTERRUPT_ACTIVE) | \
273 (1 << LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE))
276 #define RDK_EPLD_IO_REGISTER1 0x00000000
277 #define RDK_EPLD_USB_RESET 0
278 #define RDK_EPLD_USB_POWERDOWN 1
279 #define RDK_EPLD_USB_WAKEUP 2
280 #define RDK_EPLD_USB_EOT 3
281 #define RDK_EPLD_DPPULL 4
282 #define RDK_EPLD_IO_REGISTER2 0x00000004
283 #define RDK_EPLD_BUSWIDTH 0
284 #define RDK_EPLD_USER 2
285 #define RDK_EPLD_RESET_INTERRUPT_ENABLE 3
286 #define RDK_EPLD_DMA_TIMEOUT_ENABLE 4
287 #define RDK_EPLD_STATUS_REGISTER 0x00000008
288 #define RDK_EPLD_USB_LRESET 0
289 #define RDK_EPLD_REVISION_REGISTER 0x0000000c
291 #define EPLD_IO_CONTROL_REGISTER 0x400
292 #define NET2272_RESET 0
296 #define DMA_TIMEOUT_ENABLE 5
297 #define DMA_CTL_DACK 6
298 #define EPLD_DMA_ENABLE 7
299 #define EPLD_DMA_CONTROL_REGISTER 0x800
300 #define SPLIT_DMA_MODE 0
301 #define SPLIT_DMA_DIRECTION 1
302 #define SPLIT_DMA_ENABLE 2
303 #define SPLIT_DMA_INTERRUPT_ENABLE 3
304 #define SPLIT_DMA_INTERRUPT 4
305 #define EPLD_DMA_MODE 5
306 #define EPLD_DMA_CONTROLLER_ENABLE 7
307 #define SPLIT_DMA_ADDRESS_LOW 0xc00
308 #define SPLIT_DMA_ADDRESS_HIGH 0x1000
309 #define SPLIT_DMA_BYTE_COUNT_LOW 0x1400
310 #define SPLIT_DMA_BYTE_COUNT_HIGH 0x1800
311 #define EPLD_REVISION_REGISTER 0x1c00
312 #define SPLIT_DMA_RAM 0x4000
313 #define DMA_RAM_SIZE 0x1000
315 /*---------------------------------------------------------------------------*/
317 #define PCI_DEVICE_ID_RDK2 0x3272
319 /* PCI-RDK version 2 registers */
321 /* Main Control Registers */
323 #define RDK2_IRQENB 0x00
324 #define RDK2_IRQSTAT 0x04
337 #define DMA_RETRY_ABORT 6
338 #define DMA_PAUSE_DONE 5
339 #define DMA_ABORT_DONE 4
340 #define DMA_OUT_FIFO_TRANSFER_DONE 3
341 #define DMA_LOCAL_DONE 2
342 #define DMA_PCI_DONE 1
343 #define NET2272_PCI_IRQ 0
345 #define RDK2_LOCCTLRDK 0x08
348 #define MULTIPLEX_MODE 1
351 #define RDK2_GPIOCTL 0x10
352 #define GP3_OUT_ENABLE 7
353 #define GP2_OUT_ENABLE 6
354 #define GP1_OUT_ENABLE 5
355 #define GP0_OUT_ENABLE 4
361 #define RDK2_LEDSW 0x14
369 #define RDK2_DIAG 0x18
370 #define RDK2_FAST_TIMES 2
371 #define FORCE_PCI_SERR 1
372 #define FORCE_PCI_INT 0
373 #define RDK2_FPGAREV 0x1C
375 /* Dma Control registers */
376 #define RDK2_DMACTL 0x80
378 #define RETRY_COUNT 16 /* 23:16 */
379 #define FIFO_THRESHOLD 11 /* 15:11 */
380 #define MEM_WRITE_INVALIDATE 10
381 #define READ_MULTIPLE 9
383 #define RDK2_DMA_MODE 6 /* 7:6 */
384 #define CONTROL_DACK 5
386 #define EOT_POLARITY 3
387 #define DACK_POLARITY 2
388 #define DREQ_POLARITY 1
391 #define RDK2_DMASTAT 0x84
392 #define GATHER_COUNT 12 /* 14:12 */
393 #define FIFO_COUNT 6 /* 11:6 */
395 #define FIFO_TRANSFER 4
401 #define RDK2_DMAPCICOUNT 0x88
402 #define DMA_DIRECTION 31
403 #define DMA_PCI_BYTE_COUNT 0 /* 0:23 */
405 #define RDK2_DMALOCCOUNT 0x8C /* 0:23 dma local byte count */
407 #define RDK2_DMAADDR 0x90 /* 2:31 PCI bus starting address */
409 /*---------------------------------------------------------------------------*/
411 #define REG_INDEXED_THRESHOLD (1 << 5)
413 /* DRIVER DATA STRUCTURES and UTILITIES */
419 /* analogous to a host-side qh */
420 struct list_head queue;
421 const struct usb_endpoint_descriptor *desc;
433 /* each device provides one gadget, several endpoints */
434 struct usb_gadget gadget;
436 unsigned short dev_id;
439 struct net2272_ep ep[4];
440 struct usb_gadget_driver *driver;
441 unsigned protocol_stall:1,
454 unsigned short fifo_mode;
456 unsigned int base_shift;
457 u16 __iomem *base_addr;
459 #ifdef CONFIG_USB_PCI
461 void __iomem *plx9054_base_addr;
462 void __iomem *epld_base_addr;
465 /* Bar0, Bar1 is base_addr both mem-mapped */
466 void __iomem *fpga_base_addr;
472 static void __iomem *
473 net2272_reg_addr(struct net2272 *dev, unsigned int reg)
475 return dev->base_addr + (reg << dev->base_shift);
479 net2272_write(struct net2272 *dev, unsigned int reg, u8 value)
481 if (reg >= REG_INDEXED_THRESHOLD) {
483 * Indexed register; use REGADDRPTR/REGDATA
484 * - Save and restore REGADDRPTR. This prevents REGADDRPTR from
485 * changes between other code sections, but it is time consuming.
486 * - Performance tips: either do not save and restore REGADDRPTR (if it
487 * is safe) or do save/restore operations only in critical sections.
488 u8 tmp = readb(dev->base_addr + REGADDRPTR);
490 writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
491 writeb(value, net2272_reg_addr(dev, REGDATA));
492 /* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */
494 writeb(value, net2272_reg_addr(dev, reg));
498 net2272_read(struct net2272 *dev, unsigned int reg)
502 if (reg >= REG_INDEXED_THRESHOLD) {
504 * Indexed register; use REGADDRPTR/REGDATA
505 * - Save and restore REGADDRPTR. This prevents REGADDRPTR from
506 * changes between other code sections, but it is time consuming.
507 * - Performance tips: either do not save and restore REGADDRPTR (if it
508 * is safe) or do save/restore operations only in critical sections.
509 u8 tmp = readb(dev->base_addr + REGADDRPTR);
511 writeb((u8)reg, net2272_reg_addr(dev, REGADDRPTR));
512 ret = readb(net2272_reg_addr(dev, REGDATA));
513 /* writeb(tmp, net2272_reg_addr(dev, REGADDRPTR)); */
515 ret = readb(net2272_reg_addr(dev, reg));
521 net2272_ep_write(struct net2272_ep *ep, unsigned int reg, u8 value)
523 struct net2272 *dev = ep->dev;
525 if (dev->pagesel != ep->num) {
526 net2272_write(dev, PAGESEL, ep->num);
527 dev->pagesel = ep->num;
529 net2272_write(dev, reg, value);
533 net2272_ep_read(struct net2272_ep *ep, unsigned int reg)
535 struct net2272 *dev = ep->dev;
537 if (dev->pagesel != ep->num) {
538 net2272_write(dev, PAGESEL, ep->num);
539 dev->pagesel = ep->num;
541 return net2272_read(dev, reg);
544 static void allow_status(struct net2272_ep *ep)
547 net2272_ep_write(ep, EP_RSPCLR,
548 (1 << CONTROL_STATUS_PHASE_HANDSHAKE) |
549 (1 << ALT_NAK_OUT_PACKETS) |
550 (1 << NAK_OUT_PACKETS_MODE));
554 static void set_halt(struct net2272_ep *ep)
556 /* ep0 and bulk/intr endpoints */
557 net2272_ep_write(ep, EP_RSPCLR, 1 << CONTROL_STATUS_PHASE_HANDSHAKE);
558 net2272_ep_write(ep, EP_RSPSET, 1 << ENDPOINT_HALT);
561 static void clear_halt(struct net2272_ep *ep)
563 /* ep0 and bulk/intr endpoints */
564 net2272_ep_write(ep, EP_RSPCLR,
565 (1 << ENDPOINT_HALT) | (1 << ENDPOINT_TOGGLE));
568 /* count (<= 4) bytes in the next fifo write will be valid */
569 static void set_fifo_bytecount(struct net2272_ep *ep, unsigned count)
571 /* net2272_ep_write will truncate to u8 for us */
572 net2272_ep_write(ep, EP_TRANSFER2, count >> 16);
573 net2272_ep_write(ep, EP_TRANSFER1, count >> 8);
574 net2272_ep_write(ep, EP_TRANSFER0, count);
577 struct net2272_request {
578 struct usb_request req;
579 struct list_head queue;