1 // SPDX-License-Identifier: GPL-2.0+
3 * USB Gadget driver for LPC32xx
6 * Kevin Wells <kevin.wells@nxp.com>
8 * Roland Stigge <stigge@antcom.de>
10 * Copyright (C) 2006 Philips Semiconductors
11 * Copyright (C) 2009 NXP Semiconductors
12 * Copyright (C) 2012 Roland Stigge
14 * Note: This driver is based on original work done by Mike James for
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/dmapool.h>
22 #include <linux/i2c.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
26 #include <linux/platform_device.h>
27 #include <linux/prefetch.h>
28 #include <linux/proc_fs.h>
29 #include <linux/slab.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/isp1301.h>
34 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
40 * USB device configuration structure
42 typedef void (*usc_chg_event)(int);
43 struct lpc32xx_usbd_cfg {
44 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
45 usc_chg_event conn_chgb; /* Connection change event (optional) */
46 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
47 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
51 * controller driver data structures
54 /* 16 endpoints (not to be confused with 32 hardware endpoints) */
55 #define NUM_ENDPOINTS 16
58 * IRQ indices make reading the code a little easier
62 #define IRQ_USB_DEVDMA 2
65 #define EP_OUT 0 /* RX (from host) */
66 #define EP_IN 1 /* TX (to host) */
68 /* Returns the interrupt mask for the selected hardware endpoint */
69 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
77 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
78 #define DATA_IN 1 /* Expect dev->host transfer */
79 #define DATA_OUT 2 /* Expect host->dev transfer */
81 /* DD (DMA Descriptor) structure, requires word alignment, this is already
82 * defined in the LPC32XX USB device header file, but this version is slightly
83 * modified to tag some work data with each DMA descriptor. */
84 struct lpc32xx_usbd_dd_gad {
89 u32 dd_iso_ps_mem_addr;
91 u32 iso_status[6]; /* 5 spare */
96 * Logical endpoint structure
100 struct list_head queue;
101 struct lpc32xx_udc *udc;
103 u32 hwep_num_base; /* Physical hardware EP */
104 u32 hwep_num; /* Maps to hardware endpoint */
123 * Common UDC structure
126 struct usb_gadget gadget;
127 struct usb_gadget_driver *driver;
128 struct platform_device *pdev;
131 struct i2c_client *isp1301_i2c_client;
133 /* Board and device specific */
134 struct lpc32xx_usbd_cfg *board;
135 void __iomem *udp_baseaddr;
137 struct clk *usb_slv_clk;
142 struct dma_pool *dd_cache;
144 /* Common EP and control data */
146 u32 enabled_hwepints;
150 /* VBUS detection, pullup, and power flags */
157 /* Work queues related to I2C support */
158 struct work_struct pullup_job;
159 struct work_struct power_job;
161 /* USB device peripheral - various */
162 struct lpc32xx_ep ep[NUM_ENDPOINTS];
167 atomic_t enabled_ep_cnt;
168 wait_queue_head_t ep_disable_wait_queue;
174 struct lpc32xx_request {
175 struct usb_request req;
176 struct list_head queue;
177 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
182 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
184 return container_of(g, struct lpc32xx_udc, gadget);
187 #define ep_dbg(epp, fmt, arg...) \
188 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
189 #define ep_err(epp, fmt, arg...) \
190 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
191 #define ep_info(epp, fmt, arg...) \
192 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
193 #define ep_warn(epp, fmt, arg...) \
194 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
196 #define UDCA_BUFF_SIZE (128)
198 /**********************************************************************
199 * USB device controller register offsets
200 **********************************************************************/
202 #define USBD_DEVINTST(x) ((x) + 0x200)
203 #define USBD_DEVINTEN(x) ((x) + 0x204)
204 #define USBD_DEVINTCLR(x) ((x) + 0x208)
205 #define USBD_DEVINTSET(x) ((x) + 0x20C)
206 #define USBD_CMDCODE(x) ((x) + 0x210)
207 #define USBD_CMDDATA(x) ((x) + 0x214)
208 #define USBD_RXDATA(x) ((x) + 0x218)
209 #define USBD_TXDATA(x) ((x) + 0x21C)
210 #define USBD_RXPLEN(x) ((x) + 0x220)
211 #define USBD_TXPLEN(x) ((x) + 0x224)
212 #define USBD_CTRL(x) ((x) + 0x228)
213 #define USBD_DEVINTPRI(x) ((x) + 0x22C)
214 #define USBD_EPINTST(x) ((x) + 0x230)
215 #define USBD_EPINTEN(x) ((x) + 0x234)
216 #define USBD_EPINTCLR(x) ((x) + 0x238)
217 #define USBD_EPINTSET(x) ((x) + 0x23C)
218 #define USBD_EPINTPRI(x) ((x) + 0x240)
219 #define USBD_REEP(x) ((x) + 0x244)
220 #define USBD_EPIND(x) ((x) + 0x248)
221 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
222 /* DMA support registers only below */
223 /* Set, clear, or get enabled state of the DMA request status. If
224 * enabled, an IN or OUT token will start a DMA transfer for the EP */
225 #define USBD_DMARST(x) ((x) + 0x250)
226 #define USBD_DMARCLR(x) ((x) + 0x254)
227 #define USBD_DMARSET(x) ((x) + 0x258)
228 /* DMA UDCA head pointer */
229 #define USBD_UDCAH(x) ((x) + 0x280)
230 /* EP DMA status, enable, and disable. This is used to specifically
231 * enabled or disable DMA for a specific EP */
232 #define USBD_EPDMAST(x) ((x) + 0x284)
233 #define USBD_EPDMAEN(x) ((x) + 0x288)
234 #define USBD_EPDMADIS(x) ((x) + 0x28C)
235 /* DMA master interrupts enable and pending interrupts */
236 #define USBD_DMAINTST(x) ((x) + 0x290)
237 #define USBD_DMAINTEN(x) ((x) + 0x294)
238 /* DMA end of transfer interrupt enable, disable, status */
239 #define USBD_EOTINTST(x) ((x) + 0x2A0)
240 #define USBD_EOTINTCLR(x) ((x) + 0x2A4)
241 #define USBD_EOTINTSET(x) ((x) + 0x2A8)
242 /* New DD request interrupt enable, disable, status */
243 #define USBD_NDDRTINTST(x) ((x) + 0x2AC)
244 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
245 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
246 /* DMA error interrupt enable, disable, status */
247 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
248 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
249 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
251 /**********************************************************************
252 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
253 * USBD_DEVINTPRI register definitions
254 **********************************************************************/
255 #define USBD_ERR_INT (1 << 9)
256 #define USBD_EP_RLZED (1 << 8)
257 #define USBD_TXENDPKT (1 << 7)
258 #define USBD_RXENDPKT (1 << 6)
259 #define USBD_CDFULL (1 << 5)
260 #define USBD_CCEMPTY (1 << 4)
261 #define USBD_DEV_STAT (1 << 3)
262 #define USBD_EP_SLOW (1 << 2)
263 #define USBD_EP_FAST (1 << 1)
264 #define USBD_FRAME (1 << 0)
266 /**********************************************************************
267 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
268 * USBD_EPINTPRI register definitions
269 **********************************************************************/
270 /* End point selection macro (RX) */
271 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
273 /* End point selection macro (TX) */
274 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
276 /**********************************************************************
277 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
278 * USBD_EPDMAEN/USBD_EPDMADIS/
279 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
280 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
281 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
282 * register definitions
283 **********************************************************************/
284 /* Endpoint selection macro */
285 #define USBD_EP_SEL(e) (1 << (e))
287 /**********************************************************************
288 * SBD_DMAINTST/USBD_DMAINTEN
289 **********************************************************************/
290 #define USBD_SYS_ERR_INT (1 << 2)
291 #define USBD_NEW_DD_INT (1 << 1)
292 #define USBD_EOT_INT (1 << 0)
294 /**********************************************************************
295 * USBD_RXPLEN register definitions
296 **********************************************************************/
297 #define USBD_PKT_RDY (1 << 11)
298 #define USBD_DV (1 << 10)
299 #define USBD_PK_LEN_MASK 0x3FF
301 /**********************************************************************
302 * USBD_CTRL register definitions
303 **********************************************************************/
304 #define USBD_LOG_ENDPOINT(e) ((e) << 2)
305 #define USBD_WR_EN (1 << 1)
306 #define USBD_RD_EN (1 << 0)
308 /**********************************************************************
309 * USBD_CMDCODE register definitions
310 **********************************************************************/
311 #define USBD_CMD_CODE(c) ((c) << 16)
312 #define USBD_CMD_PHASE(p) ((p) << 8)
314 /**********************************************************************
315 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
316 **********************************************************************/
317 #define USBD_DMAEP(e) (1 << (e))
319 /* DD (DMA Descriptor) structure, requires word alignment */
320 struct lpc32xx_usbd_dd {
325 u32 dd_iso_ps_mem_addr;
328 /* dd_setup bit defines */
329 #define DD_SETUP_ATLE_DMA_MODE 0x01
330 #define DD_SETUP_NEXT_DD_VALID 0x04
331 #define DD_SETUP_ISO_EP 0x10
332 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
333 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
335 /* dd_status bit defines */
336 #define DD_STATUS_DD_RETIRED 0x01
337 #define DD_STATUS_STS_MASK 0x1E
338 #define DD_STATUS_STS_NS 0x00 /* Not serviced */
339 #define DD_STATUS_STS_BS 0x02 /* Being serviced */
340 #define DD_STATUS_STS_NC 0x04 /* Normal completion */
341 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
342 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */
343 #define DD_STATUS_STS_SE 0x12 /* System error */
344 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
345 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
346 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
347 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
348 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
352 * Protocol engine bits below
355 /* Device Interrupt Bit Definitions */
356 #define FRAME_INT 0x00000001
357 #define EP_FAST_INT 0x00000002
358 #define EP_SLOW_INT 0x00000004
359 #define DEV_STAT_INT 0x00000008
360 #define CCEMTY_INT 0x00000010
361 #define CDFULL_INT 0x00000020
362 #define RxENDPKT_INT 0x00000040
363 #define TxENDPKT_INT 0x00000080
364 #define EP_RLZED_INT 0x00000100
365 #define ERR_INT 0x00000200
367 /* Rx & Tx Packet Length Definitions */
368 #define PKT_LNGTH_MASK 0x000003FF
369 #define PKT_DV 0x00000400
370 #define PKT_RDY 0x00000800
372 /* USB Control Definitions */
373 #define CTRL_RD_EN 0x00000001
374 #define CTRL_WR_EN 0x00000002
377 #define CMD_SET_ADDR 0x00D00500
378 #define CMD_CFG_DEV 0x00D80500
379 #define CMD_SET_MODE 0x00F30500
380 #define CMD_RD_FRAME 0x00F50500
381 #define DAT_RD_FRAME 0x00F50200
382 #define CMD_RD_TEST 0x00FD0500
383 #define DAT_RD_TEST 0x00FD0200
384 #define CMD_SET_DEV_STAT 0x00FE0500
385 #define CMD_GET_DEV_STAT 0x00FE0500
386 #define DAT_GET_DEV_STAT 0x00FE0200
387 #define CMD_GET_ERR_CODE 0x00FF0500
388 #define DAT_GET_ERR_CODE 0x00FF0200
389 #define CMD_RD_ERR_STAT 0x00FB0500
390 #define DAT_RD_ERR_STAT 0x00FB0200
391 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
392 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
393 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
394 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
395 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
396 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
397 #define CMD_CLR_BUF 0x00F20500
398 #define DAT_CLR_BUF 0x00F20200
399 #define CMD_VALID_BUF 0x00FA0500
401 /* Device Address Register Definitions */
402 #define DEV_ADDR_MASK 0x7F
405 /* Device Configure Register Definitions */
406 #define CONF_DVICE 0x01
408 /* Device Mode Register Definitions */
417 /* Device Status Register Definitions */
419 #define DEV_CON_CH 0x02
421 #define DEV_SUS_CH 0x08
424 /* Error Code Register Definitions */
425 #define ERR_EC_MASK 0x0F
428 /* Error Status Register Definitions */
430 #define ERR_UEPKT 0x02
431 #define ERR_DCRC 0x04
432 #define ERR_TIMOUT 0x08
434 #define ERR_B_OVRN 0x20
435 #define ERR_BTSTF 0x40
438 /* Endpoint Select Register Definitions */
439 #define EP_SEL_F 0x01
440 #define EP_SEL_ST 0x02
441 #define EP_SEL_STP 0x04
442 #define EP_SEL_PO 0x08
443 #define EP_SEL_EPN 0x10
444 #define EP_SEL_B_1_FULL 0x20
445 #define EP_SEL_B_2_FULL 0x40
447 /* Endpoint Status Register Definitions */
448 #define EP_STAT_ST 0x01
449 #define EP_STAT_DA 0x20
450 #define EP_STAT_RF_MO 0x40
451 #define EP_STAT_CND_ST 0x80
453 /* Clear Buffer Register Definitions */
454 #define CLR_BUF_PO 0x01
456 /* DMA Interrupt Bit Definitions */
458 #define NDD_REQ_INT 0x02
459 #define SYS_ERR_INT 0x04
461 #define DRIVER_VERSION "1.03"
462 static const char driver_name[] = "lpc32xx_udc";
466 * proc interface support
469 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
470 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
471 static const char debug_filename[] = "driver/udc";
473 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
475 struct lpc32xx_request *req;
478 seq_printf(s, "%12s, maxpacket %4d %3s",
479 ep->ep.name, ep->ep.maxpacket,
480 ep->is_in ? "in" : "out");
481 seq_printf(s, " type %4s", epnames[ep->eptype]);
482 seq_printf(s, " ints: %12d", ep->totalints);
484 if (list_empty(&ep->queue))
485 seq_printf(s, "\t(queue empty)\n");
487 list_for_each_entry(req, &ep->queue, queue) {
488 u32 length = req->req.actual;
490 seq_printf(s, "\treq %p len %d/%d buf %p\n",
492 req->req.length, req->req.buf);
497 static int udc_show(struct seq_file *s, void *unused)
499 struct lpc32xx_udc *udc = s->private;
500 struct lpc32xx_ep *ep;
503 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
505 spin_lock_irqsave(&udc->lock, flags);
507 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
508 udc->vbus ? "present" : "off",
509 udc->enabled ? (udc->vbus ? "active" : "enabled") :
511 udc->gadget.is_selfpowered ? "self" : "VBUS",
512 udc->suspended ? ", suspended" : "",
513 udc->driver ? udc->driver->driver.name : "(none)");
515 if (udc->enabled && udc->vbus) {
516 proc_ep_show(s, &udc->ep[0]);
517 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
521 spin_unlock_irqrestore(&udc->lock, flags);
526 DEFINE_SHOW_ATTRIBUTE(udc);
528 static void create_debug_file(struct lpc32xx_udc *udc)
530 debugfs_create_file(debug_filename, 0, NULL, udc, &udc_fops);
533 static void remove_debug_file(struct lpc32xx_udc *udc)
535 debugfs_remove(debugfs_lookup(debug_filename, NULL));
539 static inline void create_debug_file(struct lpc32xx_udc *udc) {}
540 static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
543 /* Primary initialization sequence for the ISP1301 transceiver */
544 static void isp1301_udc_configure(struct lpc32xx_udc *udc)
549 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
550 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
552 if (vendor == 0x0483 && product == 0xa0c4)
555 /* LPC32XX only supports DAT_SE0 USB mode */
556 /* This sequence is important */
558 /* Disable transparent UART mode first */
559 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
560 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
563 /* Set full speed and SE0 mode */
564 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
565 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
566 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
567 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
570 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
572 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
573 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
576 if (udc->atx != STOTG04)
577 value |= MC2_SPD_SUSP_CTRL;
578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
579 ISP1301_I2C_MODE_CONTROL_2, value);
581 /* Driver VBUS_DRV high or low depending on board setup */
582 if (udc->board->vbus_drv_pol != 0)
583 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
584 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
586 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
587 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
590 /* Bi-directional mode with suspend control
591 * Enable both pulldowns for now - the pullup will be enable when VBUS
593 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
594 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
595 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
596 ISP1301_I2C_OTG_CONTROL_1,
597 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
599 /* Discharge VBUS (just in case) */
600 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
601 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
603 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
604 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
610 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
611 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
613 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
615 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
616 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
617 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
618 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
622 /* Enables or disables the USB device pullup via the ISP1301 transceiver */
623 static void isp1301_pullup_set(struct lpc32xx_udc *udc)
626 /* Enable pullup for bus signalling */
627 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
628 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
630 /* Enable pullup for bus signalling */
631 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
632 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
636 static void pullup_work(struct work_struct *work)
638 struct lpc32xx_udc *udc =
639 container_of(work, struct lpc32xx_udc, pullup_job);
641 isp1301_pullup_set(udc);
644 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
647 if (en_pullup == udc->pullup)
650 udc->pullup = en_pullup;
652 isp1301_pullup_set(udc);
654 /* defer slow i2c pull up setting */
655 schedule_work(&udc->pullup_job);
659 /* Powers up or down the ISP1301 transceiver */
660 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
662 /* There is no "global power down" register for stotg04 */
663 if (udc->atx == STOTG04)
667 /* Power up ISP1301 - this ISP1301 will automatically wakeup
668 when VBUS is detected */
669 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
670 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
673 /* Power down ISP1301 */
674 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
675 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
678 static void power_work(struct work_struct *work)
680 struct lpc32xx_udc *udc =
681 container_of(work, struct lpc32xx_udc, power_job);
683 isp1301_set_powerstate(udc, udc->poweron);
689 * USB protocol engine command/data read/write helper functions
692 /* Issues a single command to the USB device state machine */
693 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
698 /* EP may lock on CLRI if this read isn't done */
699 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
703 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
705 /* Write command code */
706 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
708 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
709 USBD_CCEMPTY) == 0) && (to > 0)) {
720 /* Issues 2 commands (or command and data) to the USB device state machine */
721 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
724 udc_protocol_cmd_w(udc, cmd);
725 udc_protocol_cmd_w(udc, data);
728 /* Issues a single command to the USB device state machine and reads
730 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
734 /* Write a command and read data from the protocol engine */
735 writel((USBD_CDFULL | USBD_CCEMPTY),
736 USBD_DEVINTCLR(udc->udp_baseaddr));
738 /* Write command code */
739 udc_protocol_cmd_w(udc, cmd);
741 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
746 "Protocol engine didn't receive response (CDFULL)\n");
748 return readl(USBD_CMDDATA(udc->udp_baseaddr));
753 * USB device interrupt mask support functions
756 /* Enable one or more USB device interrupts */
757 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
759 udc->enabled_devints |= devmask;
760 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
763 /* Disable one or more USB device interrupts */
764 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
766 udc->enabled_devints &= ~mask;
767 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
770 /* Clear one or more USB device interrupts */
771 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
773 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
778 * Endpoint interrupt disable/enable functions
781 /* Enable one or more USB endpoint interrupts */
782 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
784 udc->enabled_hwepints |= (1 << hwep);
785 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
788 /* Disable one or more USB endpoint interrupts */
789 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
791 udc->enabled_hwepints &= ~(1 << hwep);
792 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
795 /* Clear one or more USB endpoint interrupts */
796 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
798 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
801 /* Enable DMA for the HW channel */
802 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
804 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
807 /* Disable DMA for the HW channel */
808 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
810 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
815 * Endpoint realize/unrealize functions
818 /* Before an endpoint can be used, it needs to be realized
819 * in the USB protocol engine - this realizes the endpoint.
820 * The interrupt (FIFO or DMA) is not enabled with this function */
821 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
826 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
827 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
828 udc->realized_eps |= (1 << hwep);
829 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
830 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
832 /* Wait until endpoint is realized in hardware */
833 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
834 USBD_EP_RLZED)) && (to > 0))
837 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
839 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
842 /* Unrealize an EP */
843 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
845 udc->realized_eps &= ~(1 << hwep);
846 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
851 * Endpoint support functions
854 /* Select and clear endpoint interrupt */
855 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
857 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
858 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
861 /* Disables the endpoint in the USB protocol engine */
862 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
864 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
865 DAT_WR_BYTE(EP_STAT_DA));
868 /* Stalls the endpoint - endpoint will return STALL */
869 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
871 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
872 DAT_WR_BYTE(EP_STAT_ST));
875 /* Clear stall or reset endpoint */
876 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
882 /* Select an endpoint for endpoint status, clear, validate */
883 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
885 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
890 * Endpoint buffer management functions
893 /* Clear the current endpoint's buffer */
894 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
896 udc_select_hwep(udc, hwep);
897 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
900 /* Validate the current endpoint's buffer */
901 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
903 udc_select_hwep(udc, hwep);
904 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
907 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
909 /* Clear EP interrupt */
910 uda_clear_hwepint(udc, hwep);
911 return udc_selep_clrint(udc, hwep);
919 /* Allocate a DMA Descriptor */
920 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
923 struct lpc32xx_usbd_dd_gad *dd;
925 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
932 /* Free a DMA Descriptor */
933 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
935 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
940 * USB setup and shutdown functions
943 /* Enables or disables most of the USB system clocks when low power mode is
944 * needed. Clocks are typically started on a connection event, and disabled
945 * when a cable is disconnected */
946 static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
953 clk_prepare_enable(udc->usb_slv_clk);
959 clk_disable_unprepare(udc->usb_slv_clk);
963 /* Set/reset USB device address */
964 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
966 /* Address will be latched at the end of the status phase, or
967 latched immediately if function is called twice */
968 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
969 DAT_WR_BYTE(DEV_EN | addr));
972 /* Setup up a IN request for DMA transfer - this consists of determining the
973 * list of DMA addresses for the transfer, allocating DMA Descriptors,
974 * installing the DD into the UDCA, and then enabling the DMA for that EP */
975 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
977 struct lpc32xx_request *req;
978 u32 hwep = ep->hwep_num;
982 /* There will always be a request waiting here */
983 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
985 /* Place the DD Descriptor into the UDCA */
986 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
988 /* Enable DMA and interrupt for the HW EP */
989 udc_ep_dma_enable(udc, hwep);
991 /* Clear ZLP if last packet is not of MAXP size */
992 if (req->req.length % ep->ep.maxpacket)
998 /* Setup up a OUT request for DMA transfer - this consists of determining the
999 * list of DMA addresses for the transfer, allocating DMA Descriptors,
1000 * installing the DD into the UDCA, and then enabling the DMA for that EP */
1001 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1003 struct lpc32xx_request *req;
1004 u32 hwep = ep->hwep_num;
1006 ep->req_pending = 1;
1008 /* There will always be a request waiting here */
1009 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1011 /* Place the DD Descriptor into the UDCA */
1012 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1014 /* Enable DMA and interrupt for the HW EP */
1015 udc_ep_dma_enable(udc, hwep);
1019 static void udc_disable(struct lpc32xx_udc *udc)
1023 /* Disable device */
1024 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1025 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1027 /* Disable all device interrupts (including EP0) */
1028 uda_disable_devint(udc, 0x3FF);
1030 /* Disable and reset all endpoint interrupts */
1031 for (i = 0; i < 32; i++) {
1032 uda_disable_hwepint(udc, i);
1033 uda_clear_hwepint(udc, i);
1034 udc_disable_hwep(udc, i);
1035 udc_unrealize_hwep(udc, i);
1036 udc->udca_v_base[i] = 0;
1038 /* Disable and clear all interrupts and DMA */
1039 udc_ep_dma_disable(udc, i);
1040 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1041 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1042 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1043 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1046 /* Disable DMA interrupts */
1047 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1049 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1052 static void udc_enable(struct lpc32xx_udc *udc)
1055 struct lpc32xx_ep *ep = &udc->ep[0];
1057 /* Start with known state */
1061 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1063 /* EP interrupts on high priority, FRAME interrupt on low priority */
1064 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1065 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1067 /* Clear any pending device interrupts */
1068 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1070 /* Setup UDCA - not yet used (DMA) */
1071 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1073 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1074 for (i = 0; i <= 1; i++) {
1075 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1076 uda_enable_hwepint(udc, i);
1077 udc_select_hwep(udc, i);
1078 udc_clrstall_hwep(udc, i);
1079 udc_clr_buffer_hwep(udc, i);
1082 /* Device interrupt setup */
1083 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1085 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1088 /* Set device address to 0 - called twice to force a latch in the USB
1089 engine without the need of a setup packet status closure */
1090 udc_set_address(udc, 0);
1091 udc_set_address(udc, 0);
1093 /* Enable master DMA interrupts */
1094 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1095 USBD_DMAINTEN(udc->udp_baseaddr));
1097 udc->dev_status = 0;
1102 * USB device board specific events handled via callbacks
1105 /* Connection change event - notify board function of change */
1106 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1108 /* Just notify of a connection change event (optional) */
1109 if (udc->board->conn_chgb != NULL)
1110 udc->board->conn_chgb(conn);
1113 /* Suspend/resume event - notify board function of change */
1114 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1116 /* Just notify of a Suspend/resume change event (optional) */
1117 if (udc->board->susp_chgb != NULL)
1118 udc->board->susp_chgb(conn);
1126 /* Remote wakeup enable/disable - notify board function of change */
1127 static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1129 if (udc->board->rmwk_chgb != NULL)
1130 udc->board->rmwk_chgb(udc->dev_status &
1131 (1 << USB_DEVICE_REMOTE_WAKEUP));
1134 /* Reads data from FIFO, adjusts for alignment and data size */
1135 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1139 u32 *p32, tmp, cbytes;
1141 /* Use optimal data transfer method based on source address and size */
1142 switch (((uintptr_t) data) & 0x3) {
1143 case 0: /* 32-bit aligned */
1145 cbytes = (bytes & ~0x3);
1147 /* Copy 32-bit aligned data first */
1148 for (n = 0; n < cbytes; n += 4)
1149 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1151 /* Handle any remaining bytes */
1152 bl = bytes - cbytes;
1154 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1155 for (n = 0; n < bl; n++)
1156 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1161 case 1: /* 8-bit aligned */
1163 /* Each byte has to be handled independently */
1164 for (n = 0; n < bytes; n += 4) {
1165 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1171 for (i = 0; i < bl; i++)
1172 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1176 case 2: /* 16-bit aligned */
1178 cbytes = (bytes & ~0x3);
1180 /* Copy 32-bit sized objects first with 16-bit alignment */
1181 for (n = 0; n < cbytes; n += 4) {
1182 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1183 *p16++ = (u16)(tmp & 0xFFFF);
1184 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1187 /* Handle any remaining bytes */
1188 bl = bytes - cbytes;
1190 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1191 for (n = 0; n < bl; n++)
1192 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1198 /* Read data from the FIFO for an endpoint. This function is for endpoints (such
1199 * as EP0) that don't use DMA. This function should only be called if a packet
1200 * is known to be ready to read for the endpoint. Note that the endpoint must
1201 * be selected in the protocol engine prior to this call. */
1202 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1207 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1209 /* Setup read of endpoint */
1210 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1212 /* Wait until packet is ready */
1213 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1214 PKT_RDY) == 0) && (to > 0))
1217 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1219 /* Mask out count */
1220 tmp = tmpv & PKT_LNGTH_MASK;
1224 if ((tmp > 0) && (data != NULL))
1225 udc_pop_fifo(udc, (u8 *) data, tmp);
1227 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1229 /* Clear the buffer */
1230 udc_clr_buffer_hwep(udc, hwep);
1235 /* Stuffs data into the FIFO, adjusts for alignment and data size */
1236 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1240 u32 *p32, tmp, cbytes;
1242 /* Use optimal data transfer method based on source address and size */
1243 switch (((uintptr_t) data) & 0x3) {
1244 case 0: /* 32-bit aligned */
1246 cbytes = (bytes & ~0x3);
1248 /* Copy 32-bit aligned data first */
1249 for (n = 0; n < cbytes; n += 4)
1250 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1252 /* Handle any remaining bytes */
1253 bl = bytes - cbytes;
1256 for (n = 0; n < bl; n++)
1257 tmp |= data[cbytes + n] << (n * 8);
1259 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1263 case 1: /* 8-bit aligned */
1265 /* Each byte has to be handled independently */
1266 for (n = 0; n < bytes; n += 4) {
1272 for (i = 0; i < bl; i++)
1273 tmp |= data[n + i] << (i * 8);
1275 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1279 case 2: /* 16-bit aligned */
1281 cbytes = (bytes & ~0x3);
1283 /* Copy 32-bit aligned data first */
1284 for (n = 0; n < cbytes; n += 4) {
1285 tmp = *p16++ & 0xFFFF;
1286 tmp |= (*p16++ & 0xFFFF) << 16;
1287 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1290 /* Handle any remaining bytes */
1291 bl = bytes - cbytes;
1294 for (n = 0; n < bl; n++)
1295 tmp |= data[cbytes + n] << (n * 8);
1297 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1303 /* Write data to the FIFO for an endpoint. This function is for endpoints (such
1304 * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1305 * protocol engine prior to this call. */
1306 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1309 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1311 if ((bytes > 0) && (data == NULL))
1314 /* Setup write of endpoint */
1315 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1317 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1319 /* Need at least 1 byte to trigger TX */
1321 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1323 udc_stuff_fifo(udc, (u8 *) data, bytes);
1325 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1327 udc_val_buffer_hwep(udc, hwep);
1330 /* USB device reset - resets USB to a default state with just EP0
1332 static void uda_usb_reset(struct lpc32xx_udc *udc)
1335 /* Re-init device controller and EP0 */
1337 udc->gadget.speed = USB_SPEED_FULL;
1339 for (i = 1; i < NUM_ENDPOINTS; i++) {
1340 struct lpc32xx_ep *ep = &udc->ep[i];
1341 ep->req_pending = 0;
1345 /* Send a ZLP on EP0 */
1346 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1348 udc_write_hwep(udc, EP_IN, NULL, 0);
1351 /* Get current frame number */
1352 static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1356 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1357 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1358 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1360 return (fhi << 8) | flo;
1363 /* Set the device as configured - enables all endpoints */
1364 static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1366 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1369 /* Set the device as unconfigured - disables all endpoints */
1370 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1372 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1375 /* reinit == restore initial software state */
1376 static void udc_reinit(struct lpc32xx_udc *udc)
1380 INIT_LIST_HEAD(&udc->gadget.ep_list);
1381 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1383 for (i = 0; i < NUM_ENDPOINTS; i++) {
1384 struct lpc32xx_ep *ep = &udc->ep[i];
1387 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1388 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1389 INIT_LIST_HEAD(&ep->queue);
1390 ep->req_pending = 0;
1393 udc->ep0state = WAIT_FOR_SETUP;
1396 /* Must be called with lock */
1397 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1399 struct lpc32xx_udc *udc = ep->udc;
1401 list_del_init(&req->queue);
1402 if (req->req.status == -EINPROGRESS)
1403 req->req.status = status;
1405 status = req->req.status;
1408 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1411 udc_dd_free(udc, req->dd_desc_ptr);
1414 if (status && status != -ESHUTDOWN)
1415 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1417 ep->req_pending = 0;
1418 spin_unlock(&udc->lock);
1419 usb_gadget_giveback_request(&ep->ep, &req->req);
1420 spin_lock(&udc->lock);
1423 /* Must be called with lock */
1424 static void nuke(struct lpc32xx_ep *ep, int status)
1426 struct lpc32xx_request *req;
1428 while (!list_empty(&ep->queue)) {
1429 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1430 done(ep, req, status);
1433 if (status == -ESHUTDOWN) {
1434 uda_disable_hwepint(ep->udc, ep->hwep_num);
1435 udc_disable_hwep(ep->udc, ep->hwep_num);
1439 /* IN endpoint 0 transfer */
1440 static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1442 struct lpc32xx_request *req;
1443 struct lpc32xx_ep *ep0 = &udc->ep[0];
1446 if (list_empty(&ep0->queue))
1447 /* Nothing to send */
1450 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1453 tsend = ts = req->req.length - req->req.actual;
1456 udc_ep0_send_zlp(udc);
1459 } else if (ts > ep0->ep.maxpacket)
1460 ts = ep0->ep.maxpacket; /* Just send what we can */
1462 /* Write data to the EP0 FIFO and start transfer */
1463 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1465 /* Increment data pointer */
1466 req->req.actual += ts;
1468 if (tsend >= ep0->ep.maxpacket)
1469 return 0; /* Stay in data transfer state */
1471 /* Transfer request is complete */
1472 udc->ep0state = WAIT_FOR_SETUP;
1477 /* OUT endpoint 0 transfer */
1478 static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1480 struct lpc32xx_request *req;
1481 struct lpc32xx_ep *ep0 = &udc->ep[0];
1482 u32 tr, bufferspace;
1484 if (list_empty(&ep0->queue))
1487 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1491 if (req->req.length == 0) {
1492 /* Just dequeue request */
1494 udc->ep0state = WAIT_FOR_SETUP;
1498 /* Get data from FIFO */
1499 bufferspace = req->req.length - req->req.actual;
1500 if (bufferspace > ep0->ep.maxpacket)
1501 bufferspace = ep0->ep.maxpacket;
1503 /* Copy data to buffer */
1504 prefetchw(req->req.buf + req->req.actual);
1505 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1507 req->req.actual += bufferspace;
1509 if (tr < ep0->ep.maxpacket) {
1510 /* This is the last packet */
1512 udc->ep0state = WAIT_FOR_SETUP;
1520 /* Must be called with lock */
1521 static void stop_activity(struct lpc32xx_udc *udc)
1523 struct usb_gadget_driver *driver = udc->driver;
1526 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1529 udc->gadget.speed = USB_SPEED_UNKNOWN;
1532 for (i = 0; i < NUM_ENDPOINTS; i++) {
1533 struct lpc32xx_ep *ep = &udc->ep[i];
1534 nuke(ep, -ESHUTDOWN);
1537 spin_unlock(&udc->lock);
1538 driver->disconnect(&udc->gadget);
1539 spin_lock(&udc->lock);
1542 isp1301_pullup_enable(udc, 0, 0);
1548 * Activate or kill host pullup
1549 * Can be called with or without lock
1551 static void pullup(struct lpc32xx_udc *udc, int is_on)
1556 if (!udc->enabled || !udc->vbus)
1559 if (is_on != udc->pullup)
1560 isp1301_pullup_enable(udc, is_on, 0);
1563 /* Must be called without lock */
1564 static int lpc32xx_ep_disable(struct usb_ep *_ep)
1566 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1567 struct lpc32xx_udc *udc = ep->udc;
1568 unsigned long flags;
1570 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1572 spin_lock_irqsave(&udc->lock, flags);
1574 nuke(ep, -ESHUTDOWN);
1576 /* Clear all DMA statuses for this EP */
1577 udc_ep_dma_disable(udc, ep->hwep_num);
1578 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1579 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1580 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1581 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1583 /* Remove the DD pointer in the UDCA */
1584 udc->udca_v_base[ep->hwep_num] = 0;
1586 /* Disable and reset endpoint and interrupt */
1587 uda_clear_hwepint(udc, ep->hwep_num);
1588 udc_unrealize_hwep(udc, ep->hwep_num);
1592 spin_unlock_irqrestore(&udc->lock, flags);
1594 atomic_dec(&udc->enabled_ep_cnt);
1595 wake_up(&udc->ep_disable_wait_queue);
1600 /* Must be called without lock */
1601 static int lpc32xx_ep_enable(struct usb_ep *_ep,
1602 const struct usb_endpoint_descriptor *desc)
1604 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1605 struct lpc32xx_udc *udc;
1608 unsigned long flags;
1610 /* Verify EP data */
1611 if ((!_ep) || (!ep) || (!desc) ||
1612 (desc->bDescriptorType != USB_DT_ENDPOINT))
1616 maxpacket = usb_endpoint_maxp(desc);
1617 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1618 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1622 /* Don't touch EP0 */
1623 if (ep->hwep_num_base == 0) {
1624 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1628 /* Is driver ready? */
1629 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1630 dev_dbg(udc->dev, "bogus device state\n");
1634 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1636 case USB_ENDPOINT_XFER_CONTROL:
1639 case USB_ENDPOINT_XFER_INT:
1640 if (maxpacket > ep->maxpacket) {
1642 "Bad INT endpoint maxpacket %d\n", maxpacket);
1647 case USB_ENDPOINT_XFER_BULK:
1648 switch (maxpacket) {
1657 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1662 case USB_ENDPOINT_XFER_ISOC:
1665 spin_lock_irqsave(&udc->lock, flags);
1667 /* Initialize endpoint to match the selected descriptor */
1668 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1669 ep->ep.maxpacket = maxpacket;
1671 /* Map hardware endpoint from base and direction */
1673 /* IN endpoints are offset 1 from the OUT endpoint */
1674 ep->hwep_num = ep->hwep_num_base + EP_IN;
1676 ep->hwep_num = ep->hwep_num_base;
1678 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1679 ep->hwep_num, maxpacket, (ep->is_in == 1));
1681 /* Realize the endpoint, interrupt is enabled later when
1682 * buffers are queued, IN EPs will NAK until buffers are ready */
1683 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1684 udc_clr_buffer_hwep(udc, ep->hwep_num);
1685 uda_disable_hwepint(udc, ep->hwep_num);
1686 udc_clrstall_hwep(udc, ep->hwep_num);
1688 /* Clear all DMA statuses for this EP */
1689 udc_ep_dma_disable(udc, ep->hwep_num);
1690 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1691 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1692 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1693 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1695 spin_unlock_irqrestore(&udc->lock, flags);
1697 atomic_inc(&udc->enabled_ep_cnt);
1702 * Allocate a USB request list
1703 * Can be called with or without lock
1705 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1708 struct lpc32xx_request *req;
1710 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1714 INIT_LIST_HEAD(&req->queue);
1719 * De-allocate a USB request list
1720 * Can be called with or without lock
1722 static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1723 struct usb_request *_req)
1725 struct lpc32xx_request *req;
1727 req = container_of(_req, struct lpc32xx_request, req);
1728 BUG_ON(!list_empty(&req->queue));
1732 /* Must be called without lock */
1733 static int lpc32xx_ep_queue(struct usb_ep *_ep,
1734 struct usb_request *_req, gfp_t gfp_flags)
1736 struct lpc32xx_request *req;
1737 struct lpc32xx_ep *ep;
1738 struct lpc32xx_udc *udc;
1739 unsigned long flags;
1742 req = container_of(_req, struct lpc32xx_request, req);
1743 ep = container_of(_ep, struct lpc32xx_ep, ep);
1745 if (!_ep || !_req || !_req->complete || !_req->buf ||
1746 !list_empty(&req->queue))
1751 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1755 struct lpc32xx_usbd_dd_gad *dd;
1757 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1761 /* For the request, build a list of DDs */
1762 dd = udc_dd_alloc(udc);
1764 /* Error allocating DD */
1767 req->dd_desc_ptr = dd;
1769 /* Setup the DMA descriptor */
1770 dd->dd_next_phy = dd->dd_next_v = 0;
1771 dd->dd_buffer_addr = req->req.dma;
1774 /* Special handling for ISO EPs */
1775 if (ep->eptype == EP_ISO_TYPE) {
1776 dd->dd_setup = DD_SETUP_ISO_EP |
1777 DD_SETUP_PACKETLEN(0) |
1778 DD_SETUP_DMALENBYTES(1);
1779 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1781 dd->iso_status[0] = req->req.length;
1783 dd->iso_status[0] = 0;
1785 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1786 DD_SETUP_DMALENBYTES(req->req.length);
1789 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1790 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1792 spin_lock_irqsave(&udc->lock, flags);
1794 _req->status = -EINPROGRESS;
1796 req->send_zlp = _req->zero;
1798 /* Kickstart empty queues */
1799 if (list_empty(&ep->queue)) {
1800 list_add_tail(&req->queue, &ep->queue);
1802 if (ep->hwep_num_base == 0) {
1803 /* Handle expected data direction */
1805 /* IN packet to host */
1806 udc->ep0state = DATA_IN;
1807 status = udc_ep0_in_req(udc);
1809 /* OUT packet from host */
1810 udc->ep0state = DATA_OUT;
1811 status = udc_ep0_out_req(udc);
1813 } else if (ep->is_in) {
1814 /* IN packet to host and kick off transfer */
1815 if (!ep->req_pending)
1816 udc_ep_in_req_dma(udc, ep);
1818 /* OUT packet from host and kick off list */
1819 if (!ep->req_pending)
1820 udc_ep_out_req_dma(udc, ep);
1822 list_add_tail(&req->queue, &ep->queue);
1824 spin_unlock_irqrestore(&udc->lock, flags);
1826 return (status < 0) ? status : 0;
1829 /* Must be called without lock */
1830 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1832 struct lpc32xx_ep *ep;
1833 struct lpc32xx_request *req;
1834 unsigned long flags;
1836 ep = container_of(_ep, struct lpc32xx_ep, ep);
1837 if (!_ep || ep->hwep_num_base == 0)
1840 spin_lock_irqsave(&ep->udc->lock, flags);
1842 /* make sure it's actually queued on this endpoint */
1843 list_for_each_entry(req, &ep->queue, queue) {
1844 if (&req->req == _req)
1847 if (&req->req != _req) {
1848 spin_unlock_irqrestore(&ep->udc->lock, flags);
1852 done(ep, req, -ECONNRESET);
1854 spin_unlock_irqrestore(&ep->udc->lock, flags);
1859 /* Must be called without lock */
1860 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1862 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1863 struct lpc32xx_udc *udc;
1864 unsigned long flags;
1866 if ((!ep) || (ep->hwep_num <= 1))
1869 /* Don't halt an IN EP */
1874 spin_lock_irqsave(&udc->lock, flags);
1878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1879 DAT_WR_BYTE(EP_STAT_ST));
1883 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1887 spin_unlock_irqrestore(&udc->lock, flags);
1892 /* set the halt feature and ignores clear requests */
1893 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1895 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1897 if (!_ep || !ep->udc)
1902 return usb_ep_set_halt(_ep);
1905 static const struct usb_ep_ops lpc32xx_ep_ops = {
1906 .enable = lpc32xx_ep_enable,
1907 .disable = lpc32xx_ep_disable,
1908 .alloc_request = lpc32xx_ep_alloc_request,
1909 .free_request = lpc32xx_ep_free_request,
1910 .queue = lpc32xx_ep_queue,
1911 .dequeue = lpc32xx_ep_dequeue,
1912 .set_halt = lpc32xx_ep_set_halt,
1913 .set_wedge = lpc32xx_ep_set_wedge,
1916 /* Send a ZLP on a non-0 IN EP */
1917 static void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1919 /* Clear EP status */
1920 udc_clearep_getsts(udc, ep->hwep_num);
1922 /* Send ZLP via FIFO mechanism */
1923 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1927 * Handle EP completion for ZLP
1928 * This function will only be called when a delayed ZLP needs to be sent out
1929 * after a DMA transfer has filled both buffers.
1931 static void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1934 struct lpc32xx_request *req;
1936 if (ep->hwep_num <= 0)
1939 uda_clear_hwepint(udc, ep->hwep_num);
1941 /* If this interrupt isn't enabled, return now */
1942 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1945 /* Get endpoint status */
1946 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1949 * This should never happen, but protect against writing to the
1952 if (epstatus & EP_SEL_F)
1956 udc_send_in_zlp(udc, ep);
1957 uda_disable_hwepint(udc, ep->hwep_num);
1961 /* If there isn't a request waiting, something went wrong */
1962 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1966 /* Start another request if ready */
1967 if (!list_empty(&ep->queue)) {
1969 udc_ep_in_req_dma(udc, ep);
1971 udc_ep_out_req_dma(udc, ep);
1973 ep->req_pending = 0;
1978 /* DMA end of transfer completion */
1979 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1982 struct lpc32xx_request *req;
1983 struct lpc32xx_usbd_dd_gad *dd;
1985 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1989 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1991 ep_err(ep, "DMA interrupt on no req!\n");
1994 dd = req->dd_desc_ptr;
1996 /* DMA descriptor should always be retired for this call */
1997 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
1998 ep_warn(ep, "DMA descriptor did not retire\n");
2001 udc_ep_dma_disable(udc, ep->hwep_num);
2002 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2003 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2006 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2007 (1 << ep->hwep_num)) {
2008 writel((1 << ep->hwep_num),
2009 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2010 ep_err(ep, "AHB critical error!\n");
2011 ep->req_pending = 0;
2013 /* The error could have occurred on a packet of a multipacket
2014 * transfer, so recovering the transfer is not possible. Close
2015 * the request with an error */
2016 done(ep, req, -ECONNABORTED);
2020 /* Handle the current DD's status */
2021 status = dd->dd_status;
2022 switch (status & DD_STATUS_STS_MASK) {
2023 case DD_STATUS_STS_NS:
2024 /* DD not serviced? This shouldn't happen! */
2025 ep->req_pending = 0;
2026 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2029 done(ep, req, -ECONNABORTED);
2032 case DD_STATUS_STS_BS:
2033 /* Interrupt only fires on EOT - This shouldn't happen! */
2034 ep->req_pending = 0;
2035 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2037 done(ep, req, -ECONNABORTED);
2040 case DD_STATUS_STS_NC:
2041 case DD_STATUS_STS_DUR:
2042 /* Really just a short packet, not an underrun */
2043 /* This is a good status and what we expect */
2047 /* Data overrun, system error, or unknown */
2048 ep->req_pending = 0;
2049 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2051 done(ep, req, -ECONNABORTED);
2055 /* ISO endpoints are handled differently */
2056 if (ep->eptype == EP_ISO_TYPE) {
2058 req->req.actual = req->req.length;
2060 req->req.actual = dd->iso_status[0] & 0xFFFF;
2062 req->req.actual += DD_STATUS_CURDMACNT(status);
2064 /* Send a ZLP if necessary. This will be done for non-int
2065 * packets which have a size that is a divisor of MAXP */
2066 if (req->send_zlp) {
2068 * If at least 1 buffer is available, send the ZLP now.
2069 * Otherwise, the ZLP send needs to be deferred until a
2070 * buffer is available.
2072 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2073 udc_clearep_getsts(udc, ep->hwep_num);
2074 uda_enable_hwepint(udc, ep->hwep_num);
2075 udc_clearep_getsts(udc, ep->hwep_num);
2077 /* Let the EP interrupt handle the ZLP */
2080 udc_send_in_zlp(udc, ep);
2083 /* Transfer request is complete */
2086 /* Start another request if ready */
2087 udc_clearep_getsts(udc, ep->hwep_num);
2088 if (!list_empty((&ep->queue))) {
2090 udc_ep_in_req_dma(udc, ep);
2092 udc_ep_out_req_dma(udc, ep);
2094 ep->req_pending = 0;
2100 * Endpoint 0 functions
2103 static void udc_handle_dev(struct lpc32xx_udc *udc)
2107 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2108 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2112 else if (tmp & DEV_CON_CH)
2113 uda_power_event(udc, (tmp & DEV_CON));
2114 else if (tmp & DEV_SUS_CH) {
2115 if (tmp & DEV_SUS) {
2118 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2120 /* Power down transceiver */
2122 schedule_work(&udc->pullup_job);
2123 uda_resm_susp_event(udc, 1);
2125 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2126 udc->driver && udc->vbus) {
2127 uda_resm_susp_event(udc, 0);
2128 /* Power up transceiver */
2130 schedule_work(&udc->pullup_job);
2135 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2137 struct lpc32xx_ep *ep;
2138 u32 ep0buff = 0, tmp;
2140 switch (reqtype & USB_RECIP_MASK) {
2141 case USB_RECIP_INTERFACE:
2142 break; /* Not supported */
2144 case USB_RECIP_DEVICE:
2145 ep0buff = udc->gadget.is_selfpowered;
2146 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2147 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2150 case USB_RECIP_ENDPOINT:
2151 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2153 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2156 if (wIndex & USB_DIR_IN) {
2158 return -EOPNOTSUPP; /* Something's wrong */
2159 } else if (ep->is_in)
2160 return -EOPNOTSUPP; /* Not an IN endpoint */
2162 /* Get status of the endpoint */
2163 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2164 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2166 if (tmp & EP_SEL_ST)
2167 ep0buff = (1 << USB_ENDPOINT_HALT);
2177 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2182 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2184 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2185 struct usb_ctrlrequest ctrlpkt;
2187 u16 wIndex, wValue, reqtype, req, tmp;
2189 /* Nuke previous transfers */
2192 /* Get setup packet */
2193 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2195 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2200 /* Native endianness */
2201 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2202 wValue = le16_to_cpu(ctrlpkt.wValue);
2203 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2205 /* Set direction of EP0 */
2206 if (likely(reqtype & USB_DIR_IN))
2211 /* Handle SETUP packet */
2212 req = le16_to_cpu(ctrlpkt.bRequest);
2214 case USB_REQ_CLEAR_FEATURE:
2215 case USB_REQ_SET_FEATURE:
2217 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2218 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2219 goto stall; /* Nothing else handled */
2221 /* Tell board about event */
2222 if (req == USB_REQ_CLEAR_FEATURE)
2224 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2227 (1 << USB_DEVICE_REMOTE_WAKEUP);
2228 uda_remwkp_cgh(udc);
2231 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2232 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2233 if ((wValue != USB_ENDPOINT_HALT) ||
2234 (tmp >= NUM_ENDPOINTS))
2237 /* Find hardware endpoint from logical endpoint */
2243 if (req == USB_REQ_SET_FEATURE)
2244 udc_stall_hwep(udc, tmp);
2245 else if (!ep->wedge)
2246 udc_clrstall_hwep(udc, tmp);
2255 case USB_REQ_SET_ADDRESS:
2256 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2257 udc_set_address(udc, wValue);
2262 case USB_REQ_GET_STATUS:
2263 udc_get_status(udc, reqtype, wIndex);
2267 break; /* Let GadgetFS handle the descriptor instead */
2270 if (likely(udc->driver)) {
2271 /* device-2-host (IN) or no data setup command, process
2273 spin_unlock(&udc->lock);
2274 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2276 spin_lock(&udc->lock);
2277 if (req == USB_REQ_SET_CONFIGURATION) {
2278 /* Configuration is set after endpoints are realized */
2280 /* Set configuration */
2281 udc_set_device_configured(udc);
2283 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2284 DAT_WR_BYTE(AP_CLK |
2285 INAK_BI | INAK_II));
2287 /* Clear configuration */
2288 udc_set_device_unconfigured(udc);
2290 /* Disable NAK interrupts */
2291 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2292 DAT_WR_BYTE(AP_CLK));
2297 /* setup processing failed, force stall */
2299 "req %02x.%02x protocol STALL; stat %d\n",
2301 udc->ep0state = WAIT_FOR_SETUP;
2307 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2312 udc_stall_hwep(udc, EP_IN);
2316 udc_ep0_send_zlp(udc);
2320 /* IN endpoint 0 transfer */
2321 static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2323 struct lpc32xx_ep *ep0 = &udc->ep[0];
2326 /* Clear EP interrupt */
2327 epstatus = udc_clearep_getsts(udc, EP_IN);
2329 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2333 /* Stalled? Clear stall and reset buffers */
2334 if (epstatus & EP_SEL_ST) {
2335 udc_clrstall_hwep(udc, EP_IN);
2336 nuke(ep0, -ECONNABORTED);
2337 udc->ep0state = WAIT_FOR_SETUP;
2341 /* Is a buffer available? */
2342 if (!(epstatus & EP_SEL_F)) {
2343 /* Handle based on current state */
2344 if (udc->ep0state == DATA_IN)
2345 udc_ep0_in_req(udc);
2347 /* Unknown state for EP0 oe end of DATA IN phase */
2348 nuke(ep0, -ECONNABORTED);
2349 udc->ep0state = WAIT_FOR_SETUP;
2354 /* OUT endpoint 0 transfer */
2355 static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2357 struct lpc32xx_ep *ep0 = &udc->ep[0];
2360 /* Clear EP interrupt */
2361 epstatus = udc_clearep_getsts(udc, EP_OUT);
2364 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2369 if (epstatus & EP_SEL_ST) {
2370 udc_clrstall_hwep(udc, EP_OUT);
2371 nuke(ep0, -ECONNABORTED);
2372 udc->ep0state = WAIT_FOR_SETUP;
2376 /* A NAK may occur if a packet couldn't be received yet */
2377 if (epstatus & EP_SEL_EPN)
2379 /* Setup packet incoming? */
2380 if (epstatus & EP_SEL_STP) {
2382 udc->ep0state = WAIT_FOR_SETUP;
2385 /* Data available? */
2386 if (epstatus & EP_SEL_F)
2387 /* Handle based on current state */
2388 switch (udc->ep0state) {
2389 case WAIT_FOR_SETUP:
2390 udc_handle_ep0_setup(udc);
2394 udc_ep0_out_req(udc);
2398 /* Unknown state for EP0 */
2399 nuke(ep0, -ECONNABORTED);
2400 udc->ep0state = WAIT_FOR_SETUP;
2404 /* Must be called without lock */
2405 static int lpc32xx_get_frame(struct usb_gadget *gadget)
2408 unsigned long flags;
2409 struct lpc32xx_udc *udc = to_udc(gadget);
2414 spin_lock_irqsave(&udc->lock, flags);
2416 frame = (int) udc_get_current_frame(udc);
2418 spin_unlock_irqrestore(&udc->lock, flags);
2423 static int lpc32xx_wakeup(struct usb_gadget *gadget)
2428 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2430 gadget->is_selfpowered = (is_on != 0);
2436 * vbus is here! turn everything on that's ready
2437 * Must be called without lock
2439 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2441 unsigned long flags;
2442 struct lpc32xx_udc *udc = to_udc(gadget);
2444 spin_lock_irqsave(&udc->lock, flags);
2446 /* Doesn't need lock */
2448 udc_clk_set(udc, 1);
2450 pullup(udc, is_active);
2455 spin_unlock_irqrestore(&udc->lock, flags);
2457 * Wait for all the endpoints to disable,
2458 * before disabling clocks. Don't wait if
2459 * endpoints are not enabled.
2461 if (atomic_read(&udc->enabled_ep_cnt))
2462 wait_event_interruptible(udc->ep_disable_wait_queue,
2463 (atomic_read(&udc->enabled_ep_cnt) == 0));
2465 spin_lock_irqsave(&udc->lock, flags);
2467 udc_clk_set(udc, 0);
2470 spin_unlock_irqrestore(&udc->lock, flags);
2475 /* Can be called with or without lock */
2476 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2478 struct lpc32xx_udc *udc = to_udc(gadget);
2480 /* Doesn't need lock */
2486 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2487 static int lpc32xx_stop(struct usb_gadget *);
2489 static const struct usb_gadget_ops lpc32xx_udc_ops = {
2490 .get_frame = lpc32xx_get_frame,
2491 .wakeup = lpc32xx_wakeup,
2492 .set_selfpowered = lpc32xx_set_selfpowered,
2493 .vbus_session = lpc32xx_vbus_session,
2494 .pullup = lpc32xx_pullup,
2495 .udc_start = lpc32xx_start,
2496 .udc_stop = lpc32xx_stop,
2499 static void nop_release(struct device *dev)
2501 /* nothing to free */
2504 static const struct lpc32xx_udc controller_template = {
2506 .ops = &lpc32xx_udc_ops,
2507 .name = driver_name,
2509 .init_name = "gadget",
2510 .release = nop_release,
2516 .ops = &lpc32xx_ep_ops,
2517 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2518 USB_EP_CAPS_DIR_ALL),
2522 .hwep_num = 0, /* Can be 0 or 1, has special handling */
2524 .eptype = EP_CTL_TYPE,
2529 .ops = &lpc32xx_ep_ops,
2530 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2531 USB_EP_CAPS_DIR_ALL),
2535 .hwep_num = 0, /* 2 or 3, will be set later */
2537 .eptype = EP_INT_TYPE,
2542 .ops = &lpc32xx_ep_ops,
2543 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2544 USB_EP_CAPS_DIR_ALL),
2548 .hwep_num = 0, /* 4 or 5, will be set later */
2550 .eptype = EP_BLK_TYPE,
2555 .ops = &lpc32xx_ep_ops,
2556 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2557 USB_EP_CAPS_DIR_ALL),
2561 .hwep_num = 0, /* 6 or 7, will be set later */
2563 .eptype = EP_ISO_TYPE,
2568 .ops = &lpc32xx_ep_ops,
2569 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2570 USB_EP_CAPS_DIR_ALL),
2574 .hwep_num = 0, /* 8 or 9, will be set later */
2576 .eptype = EP_INT_TYPE,
2581 .ops = &lpc32xx_ep_ops,
2582 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2583 USB_EP_CAPS_DIR_ALL),
2586 .hwep_num_base = 10,
2587 .hwep_num = 0, /* 10 or 11, will be set later */
2589 .eptype = EP_BLK_TYPE,
2594 .ops = &lpc32xx_ep_ops,
2595 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2596 USB_EP_CAPS_DIR_ALL),
2599 .hwep_num_base = 12,
2600 .hwep_num = 0, /* 12 or 13, will be set later */
2602 .eptype = EP_ISO_TYPE,
2607 .ops = &lpc32xx_ep_ops,
2608 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2609 USB_EP_CAPS_DIR_ALL),
2612 .hwep_num_base = 14,
2615 .eptype = EP_INT_TYPE,
2620 .ops = &lpc32xx_ep_ops,
2621 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2622 USB_EP_CAPS_DIR_ALL),
2625 .hwep_num_base = 16,
2628 .eptype = EP_BLK_TYPE,
2633 .ops = &lpc32xx_ep_ops,
2634 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2635 USB_EP_CAPS_DIR_ALL),
2638 .hwep_num_base = 18,
2641 .eptype = EP_ISO_TYPE,
2646 .ops = &lpc32xx_ep_ops,
2647 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2648 USB_EP_CAPS_DIR_ALL),
2651 .hwep_num_base = 20,
2654 .eptype = EP_INT_TYPE,
2658 .name = "ep11-bulk",
2659 .ops = &lpc32xx_ep_ops,
2660 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2661 USB_EP_CAPS_DIR_ALL),
2664 .hwep_num_base = 22,
2667 .eptype = EP_BLK_TYPE,
2672 .ops = &lpc32xx_ep_ops,
2673 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2674 USB_EP_CAPS_DIR_ALL),
2677 .hwep_num_base = 24,
2680 .eptype = EP_ISO_TYPE,
2685 .ops = &lpc32xx_ep_ops,
2686 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2687 USB_EP_CAPS_DIR_ALL),
2690 .hwep_num_base = 26,
2693 .eptype = EP_INT_TYPE,
2697 .name = "ep14-bulk",
2698 .ops = &lpc32xx_ep_ops,
2699 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2700 USB_EP_CAPS_DIR_ALL),
2703 .hwep_num_base = 28,
2706 .eptype = EP_BLK_TYPE,
2710 .name = "ep15-bulk",
2711 .ops = &lpc32xx_ep_ops,
2712 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2713 USB_EP_CAPS_DIR_ALL),
2716 .hwep_num_base = 30,
2719 .eptype = EP_BLK_TYPE,
2723 /* ISO and status interrupts */
2724 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2727 struct lpc32xx_udc *udc = _udc;
2729 spin_lock(&udc->lock);
2731 /* Read the device status register */
2732 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2734 devstat &= ~USBD_EP_FAST;
2735 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2736 devstat = devstat & udc->enabled_devints;
2738 /* Device specific handling needed? */
2739 if (devstat & USBD_DEV_STAT)
2740 udc_handle_dev(udc);
2742 /* Start of frame? (devstat & FRAME_INT):
2743 * The frame interrupt isn't really needed for ISO support,
2744 * as the driver will queue the necessary packets */
2747 if (devstat & ERR_INT) {
2748 /* All types of errors, from cable removal during transfer to
2749 * misc protocol and bit errors. These are mostly for just info,
2750 * as the USB hardware will work around these. If these errors
2751 * happen alot, something is wrong. */
2752 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2753 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2754 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2757 spin_unlock(&udc->lock);
2763 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2766 struct lpc32xx_udc *udc = _udc;
2768 spin_lock(&udc->lock);
2770 /* Read the device status register */
2771 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2774 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2776 /* Special handling for EP0 */
2777 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2779 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2780 udc_handle_ep0_in(udc);
2782 /* Handle EP0 OUT */
2783 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2784 udc_handle_ep0_out(udc);
2788 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2791 /* Handle other EP interrupts */
2792 for (i = 1; i < NUM_ENDPOINTS; i++) {
2793 if (tmp & (1 << udc->ep[i].hwep_num))
2794 udc_handle_eps(udc, &udc->ep[i]);
2798 spin_unlock(&udc->lock);
2803 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2805 struct lpc32xx_udc *udc = _udc;
2810 spin_lock(&udc->lock);
2812 /* Handle EP DMA EOT interrupts */
2813 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2814 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2815 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2816 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2817 for (i = 1; i < NUM_ENDPOINTS; i++) {
2818 if (tmp & (1 << udc->ep[i].hwep_num))
2819 udc_handle_dma_ep(udc, &udc->ep[i]);
2822 spin_unlock(&udc->lock);
2829 * VBUS detection, pullup handler, and Gadget cable state notification
2832 static void vbus_work(struct lpc32xx_udc *udc)
2836 if (udc->enabled != 0) {
2837 /* Discharge VBUS real quick */
2838 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2839 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2841 /* Give VBUS some time (100mS) to discharge */
2844 /* Disable VBUS discharge resistor */
2845 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2846 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2849 /* Clear interrupt */
2850 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2851 ISP1301_I2C_INTERRUPT_LATCH |
2852 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2854 /* Get the VBUS status from the transceiver */
2855 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2856 ISP1301_I2C_INTERRUPT_SOURCE);
2858 /* VBUS on or off? */
2859 if (value & INT_SESS_VLD)
2865 if (udc->last_vbus != udc->vbus) {
2866 udc->last_vbus = udc->vbus;
2867 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2872 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2874 struct lpc32xx_udc *udc = _udc;
2881 static int lpc32xx_start(struct usb_gadget *gadget,
2882 struct usb_gadget_driver *driver)
2884 struct lpc32xx_udc *udc = to_udc(gadget);
2886 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2887 dev_err(udc->dev, "bad parameter.\n");
2892 dev_err(udc->dev, "UDC already has a gadget driver\n");
2896 udc->driver = driver;
2897 udc->gadget.dev.of_node = udc->dev->of_node;
2899 udc->gadget.is_selfpowered = 1;
2902 /* Force VBUS process once to check for cable insertion */
2903 udc->last_vbus = udc->vbus = 0;
2906 /* enable interrupts */
2907 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2908 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2909 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2910 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2915 static int lpc32xx_stop(struct usb_gadget *gadget)
2917 struct lpc32xx_udc *udc = to_udc(gadget);
2919 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2920 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2921 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2922 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2925 spin_lock(&udc->lock);
2927 spin_unlock(&udc->lock);
2930 * Wait for all the endpoints to disable,
2931 * before disabling clocks. Don't wait if
2932 * endpoints are not enabled.
2934 if (atomic_read(&udc->enabled_ep_cnt))
2935 wait_event_interruptible(udc->ep_disable_wait_queue,
2936 (atomic_read(&udc->enabled_ep_cnt) == 0));
2938 spin_lock(&udc->lock);
2939 udc_clk_set(udc, 0);
2940 spin_unlock(&udc->lock);
2949 static void lpc32xx_udc_shutdown(struct platform_device *dev)
2951 /* Force disconnect on reboot */
2952 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
2958 * Callbacks to be overridden by options passed via OF (TODO)
2961 static void lpc32xx_usbd_conn_chg(int conn)
2963 /* Do nothing, it might be nice to enable an LED
2964 * based on conn state being !0 */
2967 static void lpc32xx_usbd_susp_chg(int susp)
2969 /* Device suspend if susp != 0 */
2972 static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2974 /* Enable or disable USB remote wakeup */
2977 static struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2979 .conn_chgb = &lpc32xx_usbd_conn_chg,
2980 .susp_chgb = &lpc32xx_usbd_susp_chg,
2981 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2985 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2987 static int lpc32xx_udc_probe(struct platform_device *pdev)
2989 struct device *dev = &pdev->dev;
2990 struct lpc32xx_udc *udc;
2992 dma_addr_t dma_handle;
2993 struct device_node *isp1301_node;
2995 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
2999 for (i = 0; i <= 15; i++)
3000 udc->ep[i].udc = udc;
3001 udc->gadget.ep0 = &udc->ep[0].ep;
3003 /* init software state */
3004 udc->gadget.dev.parent = dev;
3006 udc->dev = &pdev->dev;
3009 if (pdev->dev.of_node) {
3010 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3013 isp1301_node = NULL;
3016 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3017 if (!udc->isp1301_i2c_client) {
3018 return -EPROBE_DEFER;
3021 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3022 udc->isp1301_i2c_client->addr);
3024 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3025 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3029 udc->board = &lpc32xx_usbddata;
3032 * Resources are mapped as follows:
3033 * IORESOURCE_MEM, base address and size of USB space
3034 * IORESOURCE_IRQ, USB device low priority interrupt number
3035 * IORESOURCE_IRQ, USB device high priority interrupt number
3036 * IORESOURCE_IRQ, USB device interrupt number
3037 * IORESOURCE_IRQ, USB transceiver interrupt number
3040 spin_lock_init(&udc->lock);
3043 for (i = 0; i < 4; i++) {
3044 udc->udp_irq[i] = platform_get_irq(pdev, i);
3045 if (udc->udp_irq[i] < 0)
3046 return udc->udp_irq[i];
3049 udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, 0);
3050 if (IS_ERR(udc->udp_baseaddr)) {
3051 dev_err(udc->dev, "IO map failure\n");
3052 return PTR_ERR(udc->udp_baseaddr);
3055 /* Get USB device clock */
3056 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
3057 if (IS_ERR(udc->usb_slv_clk)) {
3058 dev_err(udc->dev, "failed to acquire USB device clock\n");
3059 return PTR_ERR(udc->usb_slv_clk);
3062 /* Enable USB device clock */
3063 retval = clk_prepare_enable(udc->usb_slv_clk);
3065 dev_err(udc->dev, "failed to start USB device clock\n");
3069 /* Setup deferred workqueue data */
3070 udc->poweron = udc->pullup = 0;
3071 INIT_WORK(&udc->pullup_job, pullup_work);
3073 INIT_WORK(&udc->power_job, power_work);
3076 /* All clocks are now on */
3079 isp1301_udc_configure(udc);
3080 /* Allocate memory for the UDCA */
3081 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3083 (GFP_KERNEL | GFP_DMA));
3084 if (!udc->udca_v_base) {
3085 dev_err(udc->dev, "error getting UDCA region\n");
3089 udc->udca_p_base = dma_handle;
3090 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3091 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3093 /* Setup the DD DMA memory pool */
3094 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3095 sizeof(struct lpc32xx_usbd_dd_gad),
3097 if (!udc->dd_cache) {
3098 dev_err(udc->dev, "error getting DD DMA region\n");
3100 goto dma_alloc_fail;
3103 /* Clear USB peripheral and initialize gadget endpoints */
3107 /* Request IRQs - low and high priority USB device IRQs are routed to
3108 * the same handler, while the DMA interrupt is routed elsewhere */
3109 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3110 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
3112 dev_err(udc->dev, "LP request irq %d failed\n",
3113 udc->udp_irq[IRQ_USB_LP]);
3116 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3117 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
3119 dev_err(udc->dev, "HP request irq %d failed\n",
3120 udc->udp_irq[IRQ_USB_HP]);
3124 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3125 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3127 dev_err(udc->dev, "DEV request irq %d failed\n",
3128 udc->udp_irq[IRQ_USB_DEVDMA]);
3132 /* The transceiver interrupt is used for VBUS detection and will
3133 kick off the VBUS handler function */
3134 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3135 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3138 dev_err(udc->dev, "VBUS request irq %d failed\n",
3139 udc->udp_irq[IRQ_USB_ATX]);
3143 /* Initialize wait queue */
3144 init_waitqueue_head(&udc->ep_disable_wait_queue);
3145 atomic_set(&udc->enabled_ep_cnt, 0);
3147 retval = usb_add_gadget_udc(dev, &udc->gadget);
3149 goto add_gadget_fail;
3151 dev_set_drvdata(dev, udc);
3152 device_init_wakeup(dev, 1);
3153 create_debug_file(udc);
3155 /* Disable clocks for now */
3156 udc_clk_set(udc, 0);
3158 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3163 dma_pool_destroy(udc->dd_cache);
3165 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3166 udc->udca_v_base, udc->udca_p_base);
3168 clk_disable_unprepare(udc->usb_slv_clk);
3169 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3174 static int lpc32xx_udc_remove(struct platform_device *pdev)
3176 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3178 usb_del_gadget_udc(&udc->gadget);
3182 udc_clk_set(udc, 1);
3186 device_init_wakeup(&pdev->dev, 0);
3187 remove_debug_file(udc);
3189 dma_pool_destroy(udc->dd_cache);
3190 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3191 udc->udca_v_base, udc->udca_p_base);
3193 clk_disable_unprepare(udc->usb_slv_clk);
3199 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3201 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3204 /* Power down ISP */
3206 isp1301_set_powerstate(udc, 0);
3208 /* Disable clocking */
3209 udc_clk_set(udc, 0);
3211 /* Keep clock flag on, so we know to re-enable clocks
3215 /* Kill global USB clock */
3216 clk_disable_unprepare(udc->usb_slv_clk);
3222 static int lpc32xx_udc_resume(struct platform_device *pdev)
3224 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3227 /* Enable global USB clock */
3228 clk_prepare_enable(udc->usb_slv_clk);
3230 /* Enable clocking */
3231 udc_clk_set(udc, 1);
3233 /* ISP back to normal power mode */
3235 isp1301_set_powerstate(udc, 1);
3241 #define lpc32xx_udc_suspend NULL
3242 #define lpc32xx_udc_resume NULL
3246 static const struct of_device_id lpc32xx_udc_of_match[] = {
3247 { .compatible = "nxp,lpc3220-udc", },
3250 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3253 static struct platform_driver lpc32xx_udc_driver = {
3254 .remove = lpc32xx_udc_remove,
3255 .shutdown = lpc32xx_udc_shutdown,
3256 .suspend = lpc32xx_udc_suspend,
3257 .resume = lpc32xx_udc_resume,
3259 .name = driver_name,
3260 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3264 module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
3266 MODULE_DESCRIPTION("LPC32XX udc driver");
3267 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3268 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3269 MODULE_LICENSE("GPL");
3270 MODULE_ALIAS("platform:lpc32xx_udc");