drivers/usb/gadget/udc/fsl_udc_core.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
   4  * All rights reserved.
   5  *
   6  * Author: Li Yang <leoli@freescale.com>
   7  *         Jiang Bo <tanya.jiang@freescale.com>
   8  *
   9  * Description:
  10  * Freescale high-speed USB SOC DR module device controller driver.
  11  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  12  * The driver is previously named as mpc_udc.  Based on bare board
  13  * code from Dave Liu and Shlomi Gridish.
  14  */
  15
  16 #undef VERBOSE
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/ioport.h>
  21 #include <linux/types.h>
  22 #include <linux/errno.h>
  23 #include <linux/err.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/mm.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/device.h>
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/fsl_devices.h>
  38 #include <linux/dmapool.h>
  39 #include <linux/of_device.h>
  40
  41 #include <asm/byteorder.h>
  42 #include <asm/io.h>
  43 #include <asm/unaligned.h>
  44 #include <asm/dma.h>
  45
  46 #include "fsl_usb2_udc.h"
  47
  48 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  49 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  50 #define DRIVER_VERSION  "Apr 20, 2007"
  51
  52 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  53
  54 static const char driver_name[] = "fsl-usb2-udc";
  55
  56 static struct usb_dr_device __iomem *dr_regs;
  57
  58 static struct usb_sys_interface __iomem *usb_sys_regs;
  59
  60 /* it is initialized in probe()  */
  61 static struct fsl_udc *udc_controller = NULL;
  62
  63 static const struct usb_endpoint_descriptor
  64 fsl_ep0_desc = {
  65         .bLength =              USB_DT_ENDPOINT_SIZE,
  66         .bDescriptorType =      USB_DT_ENDPOINT,
  67         .bEndpointAddress =     0,
  68         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  69         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  70 };
  71
  72 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  73
  74 #ifdef CONFIG_PPC32
  75 /*
  76  * On some SoCs, the USB controller registers can be big or little endian,
  77  * depending on the version of the chip. In order to be able to run the
  78  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  79  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  80  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  81  * call through those pointers. Platform code for SoCs that have BE USB
  82  * registers should set pdata->big_endian_mmio flag.
  83  *
  84  * This also applies to controller-to-cpu accessors for the USB descriptors,
  85  * since their endianness is also SoC dependant. Platform code for SoCs that
  86  * have BE USB descriptors should set pdata->big_endian_desc flag.
  87  */
  88 static u32 _fsl_readl_be(const unsigned __iomem *p)
  89 {
  90         return in_be32(p);
  91 }
  92
  93 static u32 _fsl_readl_le(const unsigned __iomem *p)
  94 {
  95         return in_le32(p);
  96 }
  97
  98 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
  99 {
 100         out_be32(p, v);
 101 }
 102
 103 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 104 {
 105         out_le32(p, v);
 106 }
 107
 108 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 109 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 110
 111 #define fsl_readl(p)            (*_fsl_readl)((p))
 112 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 113
 114 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 115 {
 116         if (pdata->big_endian_mmio) {
 117                 _fsl_readl = _fsl_readl_be;
 118                 _fsl_writel = _fsl_writel_be;
 119         } else {
 120                 _fsl_readl = _fsl_readl_le;
 121                 _fsl_writel = _fsl_writel_le;
 122         }
 123 }
 124
 125 static inline u32 cpu_to_hc32(const u32 x)
 126 {
 127         return udc_controller->pdata->big_endian_desc
 128                 ? (__force u32)cpu_to_be32(x)
 129                 : (__force u32)cpu_to_le32(x);
 130 }
 131
 132 static inline u32 hc32_to_cpu(const u32 x)
 133 {
 134         return udc_controller->pdata->big_endian_desc
 135                 ? be32_to_cpu((__force __be32)x)
 136                 : le32_to_cpu((__force __le32)x);
 137 }
 138 #else /* !CONFIG_PPC32 */
 139 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 140
 141 #define fsl_readl(addr)         readl(addr)
 142 #define fsl_writel(val32, addr) writel(val32, addr)
 143 #define cpu_to_hc32(x)          cpu_to_le32(x)
 144 #define hc32_to_cpu(x)          le32_to_cpu(x)
 145 #endif /* CONFIG_PPC32 */
 146
 147 /********************************************************************
 148  *      Internal Used Function
 149 ********************************************************************/
 150 /*-----------------------------------------------------------------
 151  * done() - retire a request; caller blocked irqs
 152  * @status : request status to be set, only works when
 153  *      request is still in progress.
 154  *--------------------------------------------------------------*/
 155 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 156 __releases(ep->udc->lock)
 157 __acquires(ep->udc->lock)
 158 {
 159         struct fsl_udc *udc = NULL;
 160         unsigned char stopped = ep->stopped;
 161         struct ep_td_struct *curr_td, *next_td;
 162         int j;
 163
 164         udc = (struct fsl_udc *)ep->udc;
 165         /* Removed the req from fsl_ep->queue */
 166         list_del_init(&req->queue);
 167
 168         /* req.status should be set as -EINPROGRESS in ep_queue() */
 169         if (req->req.status == -EINPROGRESS)
 170                 req->req.status = status;
 171         else
 172                 status = req->req.status;
 173
 174         /* Free dtd for the request */
 175         next_td = req->head;
 176         for (j = 0; j < req->dtd_count; j++) {
 177                 curr_td = next_td;
 178                 if (j != req->dtd_count - 1) {
 179                         next_td = curr_td->next_td_virt;
 180                 }
 181                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 182         }
 183
 184         usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 185
 186         if (status && (status != -ESHUTDOWN))
 187                 VDBG("complete %s req %p stat %d len %u/%u",
 188                         ep->ep.name, &req->req, status,
 189                         req->req.actual, req->req.length);
 190
 191         ep->stopped = 1;
 192
 193         spin_unlock(&ep->udc->lock);
 194
 195         usb_gadget_giveback_request(&ep->ep, &req->req);
 196
 197         spin_lock(&ep->udc->lock);
 198         ep->stopped = stopped;
 199 }
 200
 201 /*-----------------------------------------------------------------
 202  * nuke(): delete all requests related to this ep
 203  * called with spinlock held
 204  *--------------------------------------------------------------*/
 205 static void nuke(struct fsl_ep *ep, int status)
 206 {
 207         ep->stopped = 1;
 208
 209         /* Flush fifo */
 210         fsl_ep_fifo_flush(&ep->ep);
 211
 212         /* Whether this eq has request linked */
 213         while (!list_empty(&ep->queue)) {
 214                 struct fsl_req *req = NULL;
 215
 216                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 217                 done(ep, req, status);
 218         }
 219 }
 220
 221 /*------------------------------------------------------------------
 222         Internal Hardware related function
 223  ------------------------------------------------------------------*/
 224
 225 static int dr_controller_setup(struct fsl_udc *udc)
 226 {
 227         unsigned int tmp, portctrl, ep_num;
 228         unsigned int max_no_of_ep;
 229         unsigned int ctrl;
 230         unsigned long timeout;
 231
 232 #define FSL_UDC_RESET_TIMEOUT 1000
 233
 234         /* Config PHY interface */
 235         portctrl = fsl_readl(&dr_regs->portsc1);
 236         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 237         switch (udc->phy_mode) {
 238         case FSL_USB2_PHY_ULPI:
 239                 if (udc->pdata->have_sysif_regs) {
 240                         if (udc->pdata->controller_ver) {
 241                                 /* controller version 1.6 or above */
 242                                 ctrl = __raw_readl(&usb_sys_regs->control);
 243                                 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
 244                                 ctrl |= USB_CTRL_USB_EN;
 245                                 __raw_writel(ctrl, &usb_sys_regs->control);
 246                         }
 247                 }
 248                 portctrl |= PORTSCX_PTS_ULPI;
 249                 break;
 250         case FSL_USB2_PHY_UTMI_WIDE:
 251                 portctrl |= PORTSCX_PTW_16BIT;
 252                 fallthrough;
 253         case FSL_USB2_PHY_UTMI:
 254         case FSL_USB2_PHY_UTMI_DUAL:
 255                 if (udc->pdata->have_sysif_regs) {
 256                         if (udc->pdata->controller_ver) {
 257                                 /* controller version 1.6 or above */
 258                                 ctrl = __raw_readl(&usb_sys_regs->control);
 259                                 ctrl |= (USB_CTRL_UTMI_PHY_EN |
 260                                         USB_CTRL_USB_EN);
 261                                 __raw_writel(ctrl, &usb_sys_regs->control);
 262                                 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
 263                                         PHY CLK to become stable - 10ms*/
 264                         }
 265                 }
 266                 portctrl |= PORTSCX_PTS_UTMI;
 267                 break;
 268         case FSL_USB2_PHY_SERIAL:
 269                 portctrl |= PORTSCX_PTS_FSLS;
 270                 break;
 271         default:
 272                 return -EINVAL;
 273         }
 274         fsl_writel(portctrl, &dr_regs->portsc1);
 275
 276         /* Stop and reset the usb controller */
 277         tmp = fsl_readl(&dr_regs->usbcmd);
 278         tmp &= ~USB_CMD_RUN_STOP;
 279         fsl_writel(tmp, &dr_regs->usbcmd);
 280
 281         tmp = fsl_readl(&dr_regs->usbcmd);
 282         tmp |= USB_CMD_CTRL_RESET;
 283         fsl_writel(tmp, &dr_regs->usbcmd);
 284
 285         /* Wait for reset to complete */
 286         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 287         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 288                 if (time_after(jiffies, timeout)) {
 289                         ERR("udc reset timeout!\n");
 290                         return -ETIMEDOUT;
 291                 }
 292                 cpu_relax();
 293         }
 294
 295         /* Set the controller as device mode */
 296         tmp = fsl_readl(&dr_regs->usbmode);
 297         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 298         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 299         /* Disable Setup Lockout */
 300         tmp |= USB_MODE_SETUP_LOCK_OFF;
 301         if (udc->pdata->es)
 302                 tmp |= USB_MODE_ES;
 303         fsl_writel(tmp, &dr_regs->usbmode);
 304
 305         /* Clear the setup status */
 306         fsl_writel(0, &dr_regs->usbsts);
 307
 308         tmp = udc->ep_qh_dma;
 309         tmp &= USB_EP_LIST_ADDRESS_MASK;
 310         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 311
 312         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 313                 udc->ep_qh, (int)tmp,
 314                 fsl_readl(&dr_regs->endpointlistaddr));
 315
 316         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 317         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 318                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 319                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 320                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 321                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 322                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 323         }
 324         /* Config control enable i/o output, cpu endian register */
 325         if (udc->pdata->have_sysif_regs) {
 326                 ctrl = __raw_readl(&usb_sys_regs->control);
 327                 ctrl |= USB_CTRL_IOENB;
 328                 __raw_writel(ctrl, &usb_sys_regs->control);
 329         }
 330
 331 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 332         /* Turn on cache snooping hardware, since some PowerPC platforms
 333          * wholly rely on hardware to deal with cache coherent. */
 334
 335         if (udc->pdata->have_sysif_regs) {
 336                 /* Setup Snooping for all the 4GB space */
 337                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 338                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 339                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 340                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 341         }
 342 #endif
 343
 344         return 0;
 345 }
 346
 347 /* Enable DR irq and set controller to run state */
 348 static void dr_controller_run(struct fsl_udc *udc)
 349 {
 350         u32 temp;
 351
 352         /* Enable DR irq reg */
 353         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 354                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 355                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 356
 357         fsl_writel(temp, &dr_regs->usbintr);
 358
 359         /* Clear stopped bit */
 360         udc->stopped = 0;
 361
 362         /* Set the controller as device mode */
 363         temp = fsl_readl(&dr_regs->usbmode);
 364         temp |= USB_MODE_CTRL_MODE_DEVICE;
 365         fsl_writel(temp, &dr_regs->usbmode);
 366
 367         /* Set controller to Run */
 368         temp = fsl_readl(&dr_regs->usbcmd);
 369         temp |= USB_CMD_RUN_STOP;
 370         fsl_writel(temp, &dr_regs->usbcmd);
 371 }
 372
 373 static void dr_controller_stop(struct fsl_udc *udc)
 374 {
 375         unsigned int tmp;
 376
 377         pr_debug("%s\n", __func__);
 378
 379         /* if we're in OTG mode, and the Host is currently using the port,
 380          * stop now and don't rip the controller out from under the
 381          * ehci driver
 382          */
 383         if (udc->gadget.is_otg) {
 384                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 385                         pr_debug("udc: Leaving early\n");
 386                         return;
 387                 }
 388         }
 389
 390         /* disable all INTR */
 391         fsl_writel(0, &dr_regs->usbintr);
 392
 393         /* Set stopped bit for isr */
 394         udc->stopped = 1;
 395
 396         /* disable IO output */
 397 /*      usb_sys_regs->control = 0; */
 398
 399         /* set controller to Stop */
 400         tmp = fsl_readl(&dr_regs->usbcmd);
 401         tmp &= ~USB_CMD_RUN_STOP;
 402         fsl_writel(tmp, &dr_regs->usbcmd);
 403 }
 404
 405 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 406                         unsigned char ep_type)
 407 {
 408         unsigned int tmp_epctrl = 0;
 409
 410         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 411         if (dir) {
 412                 if (ep_num)
 413                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 414                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 415                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 416                 tmp_epctrl |= ((unsigned int)(ep_type)
 417                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 418         } else {
 419                 if (ep_num)
 420                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 421                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 422                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 423                 tmp_epctrl |= ((unsigned int)(ep_type)
 424                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 425         }
 426
 427         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 428 }
 429
 430 static void
 431 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 432 {
 433         u32 tmp_epctrl = 0;
 434
 435         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 436
 437         if (value) {
 438                 /* set the stall bit */
 439                 if (dir)
 440                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 441                 else
 442                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 443         } else {
 444                 /* clear the stall bit and reset data toggle */
 445                 if (dir) {
 446                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 447                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 448                 } else {
 449                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 450                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 451                 }
 452         }
 453         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 454 }
 455
 456 /* Get stall status of a specific ep
 457    Return: 0: not stalled; 1:stalled */
 458 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 459 {
 460         u32 epctrl;
 461
 462         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 463         if (dir)
 464                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 465         else
 466                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 467 }
 468
 469 /********************************************************************
 470         Internal Structure Build up functions
 471 ********************************************************************/
 472
 473 /*------------------------------------------------------------------
 474 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 475  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 476  * @mult: Mult field
 477  ------------------------------------------------------------------*/
 478 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 479                 unsigned char dir, unsigned char ep_type,
 480                 unsigned int max_pkt_len,
 481                 unsigned int zlt, unsigned char mult)
 482 {
 483         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 484         unsigned int tmp = 0;
 485
 486         /* set the Endpoint Capabilites in QH */
 487         switch (ep_type) {
 488         case USB_ENDPOINT_XFER_CONTROL:
 489                 /* Interrupt On Setup (IOS). for control ep  */
 490                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 491                         | EP_QUEUE_HEAD_IOS;
 492                 break;
 493         case USB_ENDPOINT_XFER_ISOC:
 494                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 495                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 496                 break;
 497         case USB_ENDPOINT_XFER_BULK:
 498         case USB_ENDPOINT_XFER_INT:
 499                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 500                 break;
 501         default:
 502                 VDBG("error ep type is %d", ep_type);
 503                 return;
 504         }
 505         if (zlt)
 506                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 507
 508         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 509         p_QH->next_dtd_ptr = 1;
 510         p_QH->size_ioc_int_sts = 0;
 511 }
 512
 513 /* Setup qh structure and ep register for ep0. */
 514 static void ep0_setup(struct fsl_udc *udc)
 515 {
 516         /* the initialization of an ep includes: fields in QH, Regs,
 517          * fsl_ep struct */
 518         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 519                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 520         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 521                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 522         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 523         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 524
 525         return;
 526
 527 }
 528
 529 /***********************************************************************
 530                 Endpoint Management Functions
 531 ***********************************************************************/
 532
 533 /*-------------------------------------------------------------------------
 534  * when configurations are set, or when interface settings change
 535  * for example the do_set_interface() in gadget layer,
 536  * the driver will enable or disable the relevant endpoints
 537  * ep0 doesn't use this routine. It is always enabled.
 538 -------------------------------------------------------------------------*/
 539 static int fsl_ep_enable(struct usb_ep *_ep,
 540                 const struct usb_endpoint_descriptor *desc)
 541 {
 542         struct fsl_udc *udc = NULL;
 543         struct fsl_ep *ep = NULL;
 544         unsigned short max = 0;
 545         unsigned char mult = 0, zlt;
 546         int retval = -EINVAL;
 547         unsigned long flags;
 548
 549         ep = container_of(_ep, struct fsl_ep, ep);
 550
 551         /* catch various bogus parameters */
 552         if (!_ep || !desc
 553                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 554                 return -EINVAL;
 555
 556         udc = ep->udc;
 557
 558         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 559                 return -ESHUTDOWN;
 560
 561         max = usb_endpoint_maxp(desc);
 562
 563         /* Disable automatic zlp generation.  Driver is responsible to indicate
 564          * explicitly through req->req.zero.  This is needed to enable multi-td
 565          * request. */
 566         zlt = 1;
 567
 568         /* Assume the max packet size from gadget is always correct */
 569         switch (desc->bmAttributes & 0x03) {
 570         case USB_ENDPOINT_XFER_CONTROL:
 571         case USB_ENDPOINT_XFER_BULK:
 572         case USB_ENDPOINT_XFER_INT:
 573                 /* mult = 0.  Execute N Transactions as demonstrated by
 574                  * the USB variable length packet protocol where N is
 575                  * computed using the Maximum Packet Length (dQH) and
 576                  * the Total Bytes field (dTD) */
 577                 mult = 0;
 578                 break;
 579         case USB_ENDPOINT_XFER_ISOC:
 580                 /* Calculate transactions needed for high bandwidth iso */
 581                 mult = usb_endpoint_maxp_mult(desc);
 582                 /* 3 transactions at most */
 583                 if (mult > 3)
 584                         goto en_done;
 585                 break;
 586         default:
 587                 goto en_done;
 588         }
 589
 590         spin_lock_irqsave(&udc->lock, flags);
 591         ep->ep.maxpacket = max;
 592         ep->ep.desc = desc;
 593         ep->stopped = 0;
 594
 595         /* Controller related setup */
 596         /* Init EPx Queue Head (Ep Capabilites field in QH
 597          * according to max, zlt, mult) */
 598         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 599                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 600                                         ?  USB_SEND : USB_RECV),
 601                         (unsigned char) (desc->bmAttributes
 602                                         & USB_ENDPOINT_XFERTYPE_MASK),
 603                         max, zlt, mult);
 604
 605         /* Init endpoint ctrl register */
 606         dr_ep_setup((unsigned char) ep_index(ep),
 607                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 608                                         ? USB_SEND : USB_RECV),
 609                         (unsigned char) (desc->bmAttributes
 610                                         & USB_ENDPOINT_XFERTYPE_MASK));
 611
 612         spin_unlock_irqrestore(&udc->lock, flags);
 613         retval = 0;
 614
 615         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 616                         ep->ep.desc->bEndpointAddress & 0x0f,
 617                         (desc->bEndpointAddress & USB_DIR_IN)
 618                                 ? "in" : "out", max);
 619 en_done:
 620         return retval;
 621 }
 622
 623 /*---------------------------------------------------------------------
 624  * @ep : the ep being unconfigured. May not be ep0
 625  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 626 *---------------------------------------------------------------------*/
 627 static int fsl_ep_disable(struct usb_ep *_ep)
 628 {
 629         struct fsl_udc *udc = NULL;
 630         struct fsl_ep *ep = NULL;
 631         unsigned long flags;
 632         u32 epctrl;
 633         int ep_num;
 634
 635         ep = container_of(_ep, struct fsl_ep, ep);
 636         if (!_ep || !ep->ep.desc) {
 637                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 638                 return -EINVAL;
 639         }
 640
 641         /* disable ep on controller */
 642         ep_num = ep_index(ep);
 643         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 644         if (ep_is_in(ep)) {
 645                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 646                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 647         } else {
 648                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 649                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 650         }
 651         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 652
 653         udc = (struct fsl_udc *)ep->udc;
 654         spin_lock_irqsave(&udc->lock, flags);
 655
 656         /* nuke all pending requests (does flush) */
 657         nuke(ep, -ESHUTDOWN);
 658
 659         ep->ep.desc = NULL;
 660         ep->stopped = 1;
 661         spin_unlock_irqrestore(&udc->lock, flags);
 662
 663         VDBG("disabled %s OK", _ep->name);
 664         return 0;
 665 }
 666
 667 /*---------------------------------------------------------------------
 668  * allocate a request object used by this endpoint
 669  * the main operation is to insert the req->queue to the eq->queue
 670  * Returns the request, or null if one could not be allocated
 671 *---------------------------------------------------------------------*/
 672 static struct usb_request *
 673 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 674 {
 675         struct fsl_req *req = NULL;
 676
 677         req = kzalloc(sizeof *req, gfp_flags);
 678         if (!req)
 679                 return NULL;
 680
 681         req->req.dma = DMA_ADDR_INVALID;
 682         INIT_LIST_HEAD(&req->queue);
 683
 684         return &req->req;
 685 }
 686
 687 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 688 {
 689         struct fsl_req *req = NULL;
 690
 691         req = container_of(_req, struct fsl_req, req);
 692
 693         if (_req)
 694                 kfree(req);
 695 }
 696
 697 /* Actually add a dTD chain to an empty dQH and let go */
 698 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 699 {
 700         struct ep_queue_head *qh = get_qh_by_ep(ep);
 701
 702         /* Write dQH next pointer and terminate bit to 0 */
 703         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 704                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 705
 706         /* Clear active and halt bit */
 707         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 708                                         | EP_QUEUE_HEAD_STATUS_HALT));
 709
 710         /* Ensure that updates to the QH will occur before priming. */
 711         wmb();
 712
 713         /* Prime endpoint by writing correct bit to ENDPTPRIME */
 714         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 715                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 716 }
 717
 718 /* Add dTD chain to the dQH of an EP */
 719 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 720 {
 721         u32 temp, bitmask, tmp_stat;
 722
 723         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 724         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 725
 726         bitmask = ep_is_in(ep)
 727                 ? (1 << (ep_index(ep) + 16))
 728                 : (1 << (ep_index(ep)));
 729
 730         /* check if the pipe is empty */
 731         if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
 732                 /* Add td to the end */
 733                 struct fsl_req *lastreq;
 734                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 735                 lastreq->tail->next_td_ptr =
 736                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 737                 /* Ensure dTD's next dtd pointer to be updated */
 738                 wmb();
 739                 /* Read prime bit, if 1 goto done */
 740                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 741                         return;
 742
 743                 do {
 744                         /* Set ATDTW bit in USBCMD */
 745                         temp = fsl_readl(&dr_regs->usbcmd);
 746                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 747
 748                         /* Read correct status bit */
 749                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 750
 751                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 752
 753                 /* Write ATDTW bit to 0 */
 754                 temp = fsl_readl(&dr_regs->usbcmd);
 755                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 756
 757                 if (tmp_stat)
 758                         return;
 759         }
 760
 761         fsl_prime_ep(ep, req->head);
 762 }
 763
 764 /* Fill in the dTD structure
 765  * @req: request that the transfer belongs to
 766  * @length: return actually data length of the dTD
 767  * @dma: return dma address of the dTD
 768  * @is_last: return flag if it is the last dTD of the request
 769  * return: pointer to the built dTD */
 770 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 771                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 772 {
 773         u32 swap_temp;
 774         struct ep_td_struct *dtd;
 775
 776         /* how big will this transfer be? */
 777         *length = min(req->req.length - req->req.actual,
 778                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 779
 780         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
 781         if (dtd == NULL)
 782                 return dtd;
 783
 784         dtd->td_dma = *dma;
 785         /* Clear reserved field */
 786         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 787         swap_temp &= ~DTD_RESERVED_FIELDS;
 788         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 789
 790         /* Init all of buffer page pointers */
 791         swap_temp = (u32) (req->req.dma + req->req.actual);
 792         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 793         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 794         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 795         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 796         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 797
 798         req->req.actual += *length;
 799
 800         /* zlp is needed if req->req.zero is set */
 801         if (req->req.zero) {
 802                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 803                         *is_last = 1;
 804                 else
 805                         *is_last = 0;
 806         } else if (req->req.length == req->req.actual)
 807                 *is_last = 1;
 808         else
 809                 *is_last = 0;
 810
 811         if ((*is_last) == 0)
 812                 VDBG("multi-dtd request!");
 813         /* Fill in the transfer size; set active bit */
 814         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 815
 816         /* Enable interrupt for the last dtd of a request */
 817         if (*is_last && !req->req.no_interrupt)
 818                 swap_temp |= DTD_IOC;
 819
 820         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 821
 822         mb();
 823
 824         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 825
 826         return dtd;
 827 }
 828
 829 /* Generate dtd chain for a request */
 830 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
 831 {
 832         unsigned        count;
 833         int             is_last;
 834         int             is_first =1;
 835         struct ep_td_struct     *last_dtd = NULL, *dtd;
 836         dma_addr_t dma;
 837
 838         do {
 839                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 840                 if (dtd == NULL)
 841                         return -ENOMEM;
 842
 843                 if (is_first) {
 844                         is_first = 0;
 845                         req->head = dtd;
 846                 } else {
 847                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 848                         last_dtd->next_td_virt = dtd;
 849                 }
 850                 last_dtd = dtd;
 851
 852                 req->dtd_count++;
 853         } while (!is_last);
 854
 855         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 856
 857         req->tail = dtd;
 858
 859         return 0;
 860 }
 861
 862 /* queues (submits) an I/O request to an endpoint */
 863 static int
 864 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 865 {
 866         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 867         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 868         struct fsl_udc *udc;
 869         unsigned long flags;
 870         int ret;
 871
 872         /* catch various bogus parameters */
 873         if (!_req || !req->req.complete || !req->req.buf
 874                         || !list_empty(&req->queue)) {
 875                 VDBG("%s, bad params", __func__);
 876                 return -EINVAL;
 877         }
 878         if (unlikely(!_ep || !ep->ep.desc)) {
 879                 VDBG("%s, bad ep", __func__);
 880                 return -EINVAL;
 881         }
 882         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
 883                 if (req->req.length > ep->ep.maxpacket)
 884                         return -EMSGSIZE;
 885         }
 886
 887         udc = ep->udc;
 888         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 889                 return -ESHUTDOWN;
 890
 891         req->ep = ep;
 892
 893         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 894         if (ret)
 895                 return ret;
 896
 897         req->req.status = -EINPROGRESS;
 898         req->req.actual = 0;
 899         req->dtd_count = 0;
 900
 901         /* build dtds and push them to device queue */
 902         if (!fsl_req_to_dtd(req, gfp_flags)) {
 903                 spin_lock_irqsave(&udc->lock, flags);
 904                 fsl_queue_td(ep, req);
 905         } else {
 906                 return -ENOMEM;
 907         }
 908
 909         /* irq handler advances the queue */
 910         if (req != NULL)
 911                 list_add_tail(&req->queue, &ep->queue);
 912         spin_unlock_irqrestore(&udc->lock, flags);
 913
 914         return 0;
 915 }
 916
 917 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 918 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 919 {
 920         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 921         struct fsl_req *req = NULL;
 922         struct fsl_req *iter;
 923         unsigned long flags;
 924         int ep_num, stopped, ret = 0;
 925         u32 epctrl;
 926
 927         if (!_ep || !_req)
 928                 return -EINVAL;
 929
 930         spin_lock_irqsave(&ep->udc->lock, flags);
 931         stopped = ep->stopped;
 932
 933         /* Stop the ep before we deal with the queue */
 934         ep->stopped = 1;
 935         ep_num = ep_index(ep);
 936         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 937         if (ep_is_in(ep))
 938                 epctrl &= ~EPCTRL_TX_ENABLE;
 939         else
 940                 epctrl &= ~EPCTRL_RX_ENABLE;
 941         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 942
 943         /* make sure it's actually queued on this endpoint */
 944         list_for_each_entry(iter, &ep->queue, queue) {
 945                 if (&iter->req != _req)
 946                         continue;
 947                 req = iter;
 948                 break;
 949         }
 950         if (!req) {
 951                 ret = -EINVAL;
 952                 goto out;
 953         }
 954
 955         /* The request is in progress, or completed but not dequeued */
 956         if (ep->queue.next == &req->queue) {
 957                 _req->status = -ECONNRESET;
 958                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 959
 960                 /* The request isn't the last request in this ep queue */
 961                 if (req->queue.next != &ep->queue) {
 962                         struct fsl_req *next_req;
 963
 964                         next_req = list_entry(req->queue.next, struct fsl_req,
 965                                         queue);
 966
 967                         /* prime with dTD of next request */
 968                         fsl_prime_ep(ep, next_req->head);
 969                 }
 970         /* The request hasn't been processed, patch up the TD chain */
 971         } else {
 972                 struct fsl_req *prev_req;
 973
 974                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 975                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
 976         }
 977
 978         done(ep, req, -ECONNRESET);
 979
 980         /* Enable EP */
 981 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 982         if (ep_is_in(ep))
 983                 epctrl |= EPCTRL_TX_ENABLE;
 984         else
 985                 epctrl |= EPCTRL_RX_ENABLE;
 986         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 987         ep->stopped = stopped;
 988
 989         spin_unlock_irqrestore(&ep->udc->lock, flags);
 990         return ret;
 991 }
 992
 993 /*-------------------------------------------------------------------------*/
 994
 995 /*-----------------------------------------------------------------
 996  * modify the endpoint halt feature
 997  * @ep: the non-isochronous endpoint being stalled
 998  * @value: 1--set halt  0--clear halt
 999  * Returns zero, or a negative error code.
1000 *----------------------------------------------------------------*/
1001 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1002 {
1003         struct fsl_ep *ep = NULL;
1004         unsigned long flags;
1005         int status = -EOPNOTSUPP;       /* operation not supported */
1006         unsigned char ep_dir = 0, ep_num = 0;
1007         struct fsl_udc *udc = NULL;
1008
1009         ep = container_of(_ep, struct fsl_ep, ep);
1010         udc = ep->udc;
1011         if (!_ep || !ep->ep.desc) {
1012                 status = -EINVAL;
1013                 goto out;
1014         }
1015
1016         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1017                 status = -EOPNOTSUPP;
1018                 goto out;
1019         }
1020
1021         /* Attempt to halt IN ep will fail if any transfer requests
1022          * are still queue */
1023         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1024                 status = -EAGAIN;
1025                 goto out;
1026         }
1027
1028         status = 0;
1029         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1030         ep_num = (unsigned char)(ep_index(ep));
1031         spin_lock_irqsave(&ep->udc->lock, flags);
1032         dr_ep_change_stall(ep_num, ep_dir, value);
1033         spin_unlock_irqrestore(&ep->udc->lock, flags);
1034
1035         if (ep_index(ep) == 0) {
1036                 udc->ep0_state = WAIT_FOR_SETUP;
1037                 udc->ep0_dir = 0;
1038         }
1039 out:
1040         VDBG(" %s %s halt stat %d", ep->ep.name,
1041                         value ?  "set" : "clear", status);
1042
1043         return status;
1044 }
1045
1046 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1047 {
1048         struct fsl_ep *ep;
1049         struct fsl_udc *udc;
1050         int size = 0;
1051         u32 bitmask;
1052         struct ep_queue_head *qh;
1053
1054         if (!_ep || !_ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1055                 return -ENODEV;
1056
1057         ep = container_of(_ep, struct fsl_ep, ep);
1058
1059         udc = (struct fsl_udc *)ep->udc;
1060
1061         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1062                 return -ESHUTDOWN;
1063
1064         qh = get_qh_by_ep(ep);
1065
1066         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1067             (1 << (ep_index(ep)));
1068
1069         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1070                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1071                     >> DTD_LENGTH_BIT_POS;
1072
1073         pr_debug("%s %u\n", __func__, size);
1074         return size;
1075 }
1076
1077 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1078 {
1079         struct fsl_ep *ep;
1080         int ep_num, ep_dir;
1081         u32 bits;
1082         unsigned long timeout;
1083 #define FSL_UDC_FLUSH_TIMEOUT 1000
1084
1085         if (!_ep) {
1086                 return;
1087         } else {
1088                 ep = container_of(_ep, struct fsl_ep, ep);
1089                 if (!ep->ep.desc)
1090                         return;
1091         }
1092         ep_num = ep_index(ep);
1093         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1094
1095         if (ep_num == 0)
1096                 bits = (1 << 16) | 1;
1097         else if (ep_dir == USB_SEND)
1098                 bits = 1 << (16 + ep_num);
1099         else
1100                 bits = 1 << ep_num;
1101
1102         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1103         do {
1104                 fsl_writel(bits, &dr_regs->endptflush);
1105
1106                 /* Wait until flush complete */
1107                 while (fsl_readl(&dr_regs->endptflush)) {
1108                         if (time_after(jiffies, timeout)) {
1109                                 ERR("ep flush timeout\n");
1110                                 return;
1111                         }
1112                         cpu_relax();
1113                 }
1114                 /* See if we need to flush again */
1115         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1116 }
1117
1118 static const struct usb_ep_ops fsl_ep_ops = {
1119         .enable = fsl_ep_enable,
1120         .disable = fsl_ep_disable,
1121
1122         .alloc_request = fsl_alloc_request,
1123         .free_request = fsl_free_request,
1124
1125         .queue = fsl_ep_queue,
1126         .dequeue = fsl_ep_dequeue,
1127
1128         .set_halt = fsl_ep_set_halt,
1129         .fifo_status = fsl_ep_fifo_status,
1130         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1131 };
1132
1133 /*-------------------------------------------------------------------------
1134                 Gadget Driver Layer Operations
1135 -------------------------------------------------------------------------*/
1136
1137 /*----------------------------------------------------------------------
1138  * Get the current frame number (from DR frame_index Reg )
1139  *----------------------------------------------------------------------*/
1140 static int fsl_get_frame(struct usb_gadget *gadget)
1141 {
1142         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1143 }
1144
1145 /*-----------------------------------------------------------------------
1146  * Tries to wake up the host connected to this gadget
1147  -----------------------------------------------------------------------*/
1148 static int fsl_wakeup(struct usb_gadget *gadget)
1149 {
1150         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1151         u32 portsc;
1152
1153         /* Remote wakeup feature not enabled by host */
1154         if (!udc->remote_wakeup)
1155                 return -ENOTSUPP;
1156
1157         portsc = fsl_readl(&dr_regs->portsc1);
1158         /* not suspended? */
1159         if (!(portsc & PORTSCX_PORT_SUSPEND))
1160                 return 0;
1161         /* trigger force resume */
1162         portsc |= PORTSCX_PORT_FORCE_RESUME;
1163         fsl_writel(portsc, &dr_regs->portsc1);
1164         return 0;
1165 }
1166
1167 static int can_pullup(struct fsl_udc *udc)
1168 {
1169         return udc->driver && udc->softconnect && udc->vbus_active;
1170 }
1171
1172 /* Notify controller that VBUS is powered, Called by whatever
1173    detects VBUS sessions */
1174 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1175 {
1176         struct fsl_udc  *udc;
1177         unsigned long   flags;
1178
1179         udc = container_of(gadget, struct fsl_udc, gadget);
1180         spin_lock_irqsave(&udc->lock, flags);
1181         VDBG("VBUS %s", is_active ? "on" : "off");
1182         udc->vbus_active = (is_active != 0);
1183         if (can_pullup(udc))
1184                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1185                                 &dr_regs->usbcmd);
1186         else
1187                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1188                                 &dr_regs->usbcmd);
1189         spin_unlock_irqrestore(&udc->lock, flags);
1190         return 0;
1191 }
1192
1193 /* constrain controller's VBUS power usage
1194  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1195  * reporting how much power the device may consume.  For example, this
1196  * could affect how quickly batteries are recharged.
1197  *
1198  * Returns zero on success, else negative errno.
1199  */
1200 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1201 {
1202         struct fsl_udc *udc;
1203
1204         udc = container_of(gadget, struct fsl_udc, gadget);
1205         if (!IS_ERR_OR_NULL(udc->transceiver))
1206                 return usb_phy_set_power(udc->transceiver, mA);
1207         return -ENOTSUPP;
1208 }
1209
1210 /* Change Data+ pullup status
1211  * this func is used by usb_gadget_connect/disconnect
1212  */
1213 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1214 {
1215         struct fsl_udc *udc;
1216
1217         udc = container_of(gadget, struct fsl_udc, gadget);
1218
1219         if (!udc->vbus_active)
1220                 return -EOPNOTSUPP;
1221
1222         udc->softconnect = (is_on != 0);
1223         if (can_pullup(udc))
1224                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1225                                 &dr_regs->usbcmd);
1226         else
1227                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1228                                 &dr_regs->usbcmd);
1229
1230         return 0;
1231 }
1232
1233 static int fsl_udc_start(struct usb_gadget *g,
1234                 struct usb_gadget_driver *driver);
1235 static int fsl_udc_stop(struct usb_gadget *g);
1236
1237 static const struct usb_gadget_ops fsl_gadget_ops = {
1238         .get_frame = fsl_get_frame,
1239         .wakeup = fsl_wakeup,
1240 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1241         .vbus_session = fsl_vbus_session,
1242         .vbus_draw = fsl_vbus_draw,
1243         .pullup = fsl_pullup,
1244         .udc_start = fsl_udc_start,
1245         .udc_stop = fsl_udc_stop,
1246 };
1247
1248 /*
1249  * Empty complete function used by this driver to fill in the req->complete
1250  * field when creating a request since the complete field is mandatory.
1251  */
1252 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1253
1254 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1255    on new transaction */
1256 static void ep0stall(struct fsl_udc *udc)
1257 {
1258         u32 tmp;
1259
1260         /* must set tx and rx to stall at the same time */
1261         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1262         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1263         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1264         udc->ep0_state = WAIT_FOR_SETUP;
1265         udc->ep0_dir = 0;
1266 }
1267
1268 /* Prime a status phase for ep0 */
1269 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1270 {
1271         struct fsl_req *req = udc->status_req;
1272         struct fsl_ep *ep;
1273         int ret;
1274
1275         if (direction == EP_DIR_IN)
1276                 udc->ep0_dir = USB_DIR_IN;
1277         else
1278                 udc->ep0_dir = USB_DIR_OUT;
1279
1280         ep = &udc->eps[0];
1281         if (udc->ep0_state != DATA_STATE_XMIT)
1282                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1283
1284         req->ep = ep;
1285         req->req.length = 0;
1286         req->req.status = -EINPROGRESS;
1287         req->req.actual = 0;
1288         req->req.complete = fsl_noop_complete;
1289         req->dtd_count = 0;
1290
1291         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1292         if (ret)
1293                 return ret;
1294
1295         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1296                 fsl_queue_td(ep, req);
1297         else
1298                 return -ENOMEM;
1299
1300         list_add_tail(&req->queue, &ep->queue);
1301
1302         return 0;
1303 }
1304
1305 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1306 {
1307         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1308
1309         if (ep->ep.name)
1310                 nuke(ep, -ESHUTDOWN);
1311 }
1312
1313 /*
1314  * ch9 Set address
1315  */
1316 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1317 {
1318         /* Save the new address to device struct */
1319         udc->device_address = (u8) value;
1320         /* Update usb state */
1321         udc->usb_state = USB_STATE_ADDRESS;
1322         /* Status phase */
1323         if (ep0_prime_status(udc, EP_DIR_IN))
1324                 ep0stall(udc);
1325 }
1326
1327 /*
1328  * ch9 Get status
1329  */
1330 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1331                 u16 index, u16 length)
1332 {
1333         u16 tmp = 0;            /* Status, cpu endian */
1334         struct fsl_req *req;
1335         struct fsl_ep *ep;
1336         int ret;
1337
1338         ep = &udc->eps[0];
1339
1340         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1341                 /* Get device status */
1342                 tmp = udc->gadget.is_selfpowered;
1343                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1344         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1345                 /* Get interface status */
1346                 /* We don't have interface information in udc driver */
1347                 tmp = 0;
1348         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1349                 /* Get endpoint status */
1350                 struct fsl_ep *target_ep;
1351
1352                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1353
1354                 /* stall if endpoint doesn't exist */
1355                 if (!target_ep->ep.desc)
1356                         goto stall;
1357                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1358                                 << USB_ENDPOINT_HALT;
1359         }
1360
1361         udc->ep0_dir = USB_DIR_IN;
1362         /* Borrow the per device status_req */
1363         req = udc->status_req;
1364         /* Fill in the reqest structure */
1365         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1366
1367         req->ep = ep;
1368         req->req.length = 2;
1369         req->req.status = -EINPROGRESS;
1370         req->req.actual = 0;
1371         req->req.complete = fsl_noop_complete;
1372         req->dtd_count = 0;
1373
1374         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1375         if (ret)
1376                 goto stall;
1377
1378         /* prime the data phase */
1379         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1380                 fsl_queue_td(ep, req);
1381         else                    /* no mem */
1382                 goto stall;
1383
1384         list_add_tail(&req->queue, &ep->queue);
1385         udc->ep0_state = DATA_STATE_XMIT;
1386         if (ep0_prime_status(udc, EP_DIR_OUT))
1387                 ep0stall(udc);
1388
1389         return;
1390 stall:
1391         ep0stall(udc);
1392 }
1393
1394 static void setup_received_irq(struct fsl_udc *udc,
1395                 struct usb_ctrlrequest *setup)
1396 __releases(udc->lock)
1397 __acquires(udc->lock)
1398 {
1399         u16 wValue = le16_to_cpu(setup->wValue);
1400         u16 wIndex = le16_to_cpu(setup->wIndex);
1401         u16 wLength = le16_to_cpu(setup->wLength);
1402
1403         udc_reset_ep_queue(udc, 0);
1404
1405         /* We process some stardard setup requests here */
1406         switch (setup->bRequest) {
1407         case USB_REQ_GET_STATUS:
1408                 /* Data+Status phase from udc */
1409                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1410                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1411                         break;
1412                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1413                 return;
1414
1415         case USB_REQ_SET_ADDRESS:
1416                 /* Status phase from udc */
1417                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1418                                                 | USB_RECIP_DEVICE))
1419                         break;
1420                 ch9setaddress(udc, wValue, wIndex, wLength);
1421                 return;
1422
1423         case USB_REQ_CLEAR_FEATURE:
1424         case USB_REQ_SET_FEATURE:
1425                 /* Status phase from udc */
1426         {
1427                 int rc = -EOPNOTSUPP;
1428                 u16 ptc = 0;
1429
1430                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1431                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1432                         int pipe = get_pipe_by_windex(wIndex);
1433                         struct fsl_ep *ep;
1434
1435                         if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1436                                 break;
1437                         ep = get_ep_by_pipe(udc, pipe);
1438
1439                         spin_unlock(&udc->lock);
1440                         rc = fsl_ep_set_halt(&ep->ep,
1441                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1442                                                 ? 1 : 0);
1443                         spin_lock(&udc->lock);
1444
1445                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1446                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1447                                 | USB_TYPE_STANDARD)) {
1448                         /* Note: The driver has not include OTG support yet.
1449                          * This will be set when OTG support is added */
1450                         if (wValue == USB_DEVICE_TEST_MODE)
1451                                 ptc = wIndex >> 8;
1452                         else if (gadget_is_otg(&udc->gadget)) {
1453                                 if (setup->bRequest ==
1454                                     USB_DEVICE_B_HNP_ENABLE)
1455                                         udc->gadget.b_hnp_enable = 1;
1456                                 else if (setup->bRequest ==
1457                                          USB_DEVICE_A_HNP_SUPPORT)
1458                                         udc->gadget.a_hnp_support = 1;
1459                                 else if (setup->bRequest ==
1460                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1461                                         udc->gadget.a_alt_hnp_support = 1;
1462                         }
1463                         rc = 0;
1464                 } else
1465                         break;
1466
1467                 if (rc == 0) {
1468                         if (ep0_prime_status(udc, EP_DIR_IN))
1469                                 ep0stall(udc);
1470                 }
1471                 if (ptc) {
1472                         u32 tmp;
1473
1474                         mdelay(10);
1475                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1476                         fsl_writel(tmp, &dr_regs->portsc1);
1477                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1478                 }
1479
1480                 return;
1481         }
1482
1483         default:
1484                 break;
1485         }
1486
1487         /* Requests handled by gadget */
1488         if (wLength) {
1489                 /* Data phase from gadget, status phase from udc */
1490                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1491                                 ?  USB_DIR_IN : USB_DIR_OUT;
1492                 spin_unlock(&udc->lock);
1493                 if (udc->driver->setup(&udc->gadget,
1494                                 &udc->local_setup_buff) < 0)
1495                         ep0stall(udc);
1496                 spin_lock(&udc->lock);
1497                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1498                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1499                 /*
1500                  * If the data stage is IN, send status prime immediately.
1501                  * See 2.0 Spec chapter 8.5.3.3 for detail.
1502                  */
1503                 if (udc->ep0_state == DATA_STATE_XMIT)
1504                         if (ep0_prime_status(udc, EP_DIR_OUT))
1505                                 ep0stall(udc);
1506
1507         } else {
1508                 /* No data phase, IN status from gadget */
1509                 udc->ep0_dir = USB_DIR_IN;
1510                 spin_unlock(&udc->lock);
1511                 if (udc->driver->setup(&udc->gadget,
1512                                 &udc->local_setup_buff) < 0)
1513                         ep0stall(udc);
1514                 spin_lock(&udc->lock);
1515                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1516         }
1517 }
1518
1519 /* Process request for Data or Status phase of ep0
1520  * prime status phase if needed */
1521 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1522                 struct fsl_req *req)
1523 {
1524         if (udc->usb_state == USB_STATE_ADDRESS) {
1525                 /* Set the new address */
1526                 u32 new_address = (u32) udc->device_address;
1527                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1528                                 &dr_regs->deviceaddr);
1529         }
1530
1531         done(ep0, req, 0);
1532
1533         switch (udc->ep0_state) {
1534         case DATA_STATE_XMIT:
1535                 /* already primed at setup_received_irq */
1536                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1537                 break;
1538         case DATA_STATE_RECV:
1539                 /* send status phase */
1540                 if (ep0_prime_status(udc, EP_DIR_IN))
1541                         ep0stall(udc);
1542                 break;
1543         case WAIT_FOR_OUT_STATUS:
1544                 udc->ep0_state = WAIT_FOR_SETUP;
1545                 break;
1546         case WAIT_FOR_SETUP:
1547                 ERR("Unexpected ep0 packets\n");
1548                 break;
1549         default:
1550                 ep0stall(udc);
1551                 break;
1552         }
1553 }
1554
1555 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1556  * being corrupted by another incoming setup packet */
1557 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1558 {
1559         u32 temp;
1560         struct ep_queue_head *qh;
1561         struct fsl_usb2_platform_data *pdata = udc->pdata;
1562
1563         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1564
1565         /* Clear bit in ENDPTSETUPSTAT */
1566         temp = fsl_readl(&dr_regs->endptsetupstat);
1567         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1568
1569         /* while a hazard exists when setup package arrives */
1570         do {
1571                 /* Set Setup Tripwire */
1572                 temp = fsl_readl(&dr_regs->usbcmd);
1573                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1574
1575                 /* Copy the setup packet to local buffer */
1576                 if (pdata->le_setup_buf) {
1577                         u32 *p = (u32 *)buffer_ptr;
1578                         u32 *s = (u32 *)qh->setup_buffer;
1579
1580                         /* Convert little endian setup buffer to CPU endian */
1581                         *p++ = le32_to_cpu(*s++);
1582                         *p = le32_to_cpu(*s);
1583                 } else {
1584                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1585                 }
1586         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1587
1588         /* Clear Setup Tripwire */
1589         temp = fsl_readl(&dr_regs->usbcmd);
1590         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1591 }
1592
1593 /* process-ep_req(): free the completed Tds for this req */
1594 static int process_ep_req(struct fsl_udc *udc, int pipe,
1595                 struct fsl_req *curr_req)
1596 {
1597         struct ep_td_struct *curr_td;
1598         int     actual, remaining_length, j, tmp;
1599         int     status = 0;
1600         int     errors = 0;
1601         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1602         int direction = pipe % 2;
1603
1604         curr_td = curr_req->head;
1605         actual = curr_req->req.length;
1606
1607         for (j = 0; j < curr_req->dtd_count; j++) {
1608                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1609                                         & DTD_PACKET_SIZE)
1610                                 >> DTD_LENGTH_BIT_POS;
1611                 actual -= remaining_length;
1612
1613                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1614                 if (errors & DTD_ERROR_MASK) {
1615                         if (errors & DTD_STATUS_HALTED) {
1616                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1617                                 /* Clear the errors and Halt condition */
1618                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1619                                 tmp &= ~errors;
1620                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1621                                 status = -EPIPE;
1622                                 /* FIXME: continue with next queued TD? */
1623
1624                                 break;
1625                         }
1626                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1627                                 VDBG("Transfer overflow");
1628                                 status = -EPROTO;
1629                                 break;
1630                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1631                                 VDBG("ISO error");
1632                                 status = -EILSEQ;
1633                                 break;
1634                         } else
1635                                 ERR("Unknown error has occurred (0x%x)!\n",
1636                                         errors);
1637
1638                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1639                                 & DTD_STATUS_ACTIVE) {
1640                         VDBG("Request not complete");
1641                         status = REQ_UNCOMPLETE;
1642                         return status;
1643                 } else if (remaining_length) {
1644                         if (direction) {
1645                                 VDBG("Transmit dTD remaining length not zero");
1646                                 status = -EPROTO;
1647                                 break;
1648                         } else {
1649                                 break;
1650                         }
1651                 } else {
1652                         VDBG("dTD transmitted successful");
1653                 }
1654
1655                 if (j != curr_req->dtd_count - 1)
1656                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1657         }
1658
1659         if (status)
1660                 return status;
1661
1662         curr_req->req.actual = actual;
1663
1664         return 0;
1665 }
1666
1667 /* Process a DTD completion interrupt */
1668 static void dtd_complete_irq(struct fsl_udc *udc)
1669 {
1670         u32 bit_pos;
1671         int i, ep_num, direction, bit_mask, status;
1672         struct fsl_ep *curr_ep;
1673         struct fsl_req *curr_req, *temp_req;
1674
1675         /* Clear the bits in the register */
1676         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1677         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1678
1679         if (!bit_pos)
1680                 return;
1681
1682         for (i = 0; i < udc->max_ep; i++) {
1683                 ep_num = i >> 1;
1684                 direction = i % 2;
1685
1686                 bit_mask = 1 << (ep_num + 16 * direction);
1687
1688                 if (!(bit_pos & bit_mask))
1689                         continue;
1690
1691                 curr_ep = get_ep_by_pipe(udc, i);
1692
1693                 /* If the ep is configured */
1694                 if (!curr_ep->ep.name) {
1695                         WARNING("Invalid EP?");
1696                         continue;
1697                 }
1698
1699                 /* process the req queue until an uncomplete request */
1700                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1701                                 queue) {
1702                         status = process_ep_req(udc, i, curr_req);
1703
1704                         VDBG("status of process_ep_req= %d, ep = %d",
1705                                         status, ep_num);
1706                         if (status == REQ_UNCOMPLETE)
1707                                 break;
1708                         /* write back status to req */
1709                         curr_req->req.status = status;
1710
1711                         if (ep_num == 0) {
1712                                 ep0_req_complete(udc, curr_ep, curr_req);
1713                                 break;
1714                         } else
1715                                 done(curr_ep, curr_req, status);
1716                 }
1717         }
1718 }
1719
1720 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1721 {
1722         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1723         case PORTSCX_PORT_SPEED_HIGH:
1724                 return USB_SPEED_HIGH;
1725         case PORTSCX_PORT_SPEED_FULL:
1726                 return USB_SPEED_FULL;
1727         case PORTSCX_PORT_SPEED_LOW:
1728                 return USB_SPEED_LOW;
1729         default:
1730                 return USB_SPEED_UNKNOWN;
1731         }
1732 }
1733
1734 /* Process a port change interrupt */
1735 static void port_change_irq(struct fsl_udc *udc)
1736 {
1737         if (udc->bus_reset)
1738                 udc->bus_reset = 0;
1739
1740         /* Bus resetting is finished */
1741         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1742                 /* Get the speed */
1743                 udc->gadget.speed =
1744                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1745
1746         /* Update USB state */
1747         if (!udc->resume_state)
1748                 udc->usb_state = USB_STATE_DEFAULT;
1749 }
1750
1751 /* Process suspend interrupt */
1752 static void suspend_irq(struct fsl_udc *udc)
1753 {
1754         udc->resume_state = udc->usb_state;
1755         udc->usb_state = USB_STATE_SUSPENDED;
1756
1757         /* report suspend to the driver, serial.c does not support this */
1758         if (udc->driver->suspend)
1759                 udc->driver->suspend(&udc->gadget);
1760 }
1761
1762 static void bus_resume(struct fsl_udc *udc)
1763 {
1764         udc->usb_state = udc->resume_state;
1765         udc->resume_state = 0;
1766
1767         /* report resume to the driver, serial.c does not support this */
1768         if (udc->driver->resume)
1769                 udc->driver->resume(&udc->gadget);
1770 }
1771
1772 /* Clear up all ep queues */
1773 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1774 {
1775         u8 pipe;
1776
1777         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1778                 udc_reset_ep_queue(udc, pipe);
1779
1780         /* report disconnect; the driver is already quiesced */
1781         spin_unlock(&udc->lock);
1782         if (bus_reset)
1783                 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1784         else
1785                 udc->driver->disconnect(&udc->gadget);
1786         spin_lock(&udc->lock);
1787
1788         return 0;
1789 }
1790
1791 /* Process reset interrupt */
1792 static void reset_irq(struct fsl_udc *udc)
1793 {
1794         u32 temp;
1795         unsigned long timeout;
1796
1797         /* Clear the device address */
1798         temp = fsl_readl(&dr_regs->deviceaddr);
1799         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1800
1801         udc->device_address = 0;
1802
1803         /* Clear usb state */
1804         udc->resume_state = 0;
1805         udc->ep0_dir = 0;
1806         udc->ep0_state = WAIT_FOR_SETUP;
1807         udc->remote_wakeup = 0; /* default to 0 on reset */
1808         udc->gadget.b_hnp_enable = 0;
1809         udc->gadget.a_hnp_support = 0;
1810         udc->gadget.a_alt_hnp_support = 0;
1811
1812         /* Clear all the setup token semaphores */
1813         temp = fsl_readl(&dr_regs->endptsetupstat);
1814         fsl_writel(temp, &dr_regs->endptsetupstat);
1815
1816         /* Clear all the endpoint complete status bits */
1817         temp = fsl_readl(&dr_regs->endptcomplete);
1818         fsl_writel(temp, &dr_regs->endptcomplete);
1819
1820         timeout = jiffies + 100;
1821         while (fsl_readl(&dr_regs->endpointprime)) {
1822                 /* Wait until all endptprime bits cleared */
1823                 if (time_after(jiffies, timeout)) {
1824                         ERR("Timeout for reset\n");
1825                         break;
1826                 }
1827                 cpu_relax();
1828         }
1829
1830         /* Write 1s to the flush register */
1831         fsl_writel(0xffffffff, &dr_regs->endptflush);
1832
1833         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1834                 VDBG("Bus reset");
1835                 /* Bus is reseting */
1836                 udc->bus_reset = 1;
1837                 /* Reset all the queues, include XD, dTD, EP queue
1838                  * head and TR Queue */
1839                 reset_queues(udc, true);
1840                 udc->usb_state = USB_STATE_DEFAULT;
1841         } else {
1842                 VDBG("Controller reset");
1843                 /* initialize usb hw reg except for regs for EP, not
1844                  * touch usbintr reg */
1845                 dr_controller_setup(udc);
1846
1847                 /* Reset all internal used Queues */
1848                 reset_queues(udc, false);
1849
1850                 ep0_setup(udc);
1851
1852                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1853                 dr_controller_run(udc);
1854                 udc->usb_state = USB_STATE_ATTACHED;
1855         }
1856 }
1857
1858 /*
1859  * USB device controller interrupt handler
1860  */
1861 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1862 {
1863         struct fsl_udc *udc = _udc;
1864         u32 irq_src;
1865         irqreturn_t status = IRQ_NONE;
1866         unsigned long flags;
1867
1868         /* Disable ISR for OTG host mode */
1869         if (udc->stopped)
1870                 return IRQ_NONE;
1871         spin_lock_irqsave(&udc->lock, flags);
1872         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1873         /* Clear notification bits */
1874         fsl_writel(irq_src, &dr_regs->usbsts);
1875
1876         /* VDBG("irq_src [0x%8x]", irq_src); */
1877
1878         /* Need to resume? */
1879         if (udc->usb_state == USB_STATE_SUSPENDED)
1880                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1881                         bus_resume(udc);
1882
1883         /* USB Interrupt */
1884         if (irq_src & USB_STS_INT) {
1885                 VDBG("Packet int");
1886                 /* Setup package, we only support ep0 as control ep */
1887                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1888                         tripwire_handler(udc, 0,
1889                                         (u8 *) (&udc->local_setup_buff));
1890                         setup_received_irq(udc, &udc->local_setup_buff);
1891                         status = IRQ_HANDLED;
1892                 }
1893
1894                 /* completion of dtd */
1895                 if (fsl_readl(&dr_regs->endptcomplete)) {
1896                         dtd_complete_irq(udc);
1897                         status = IRQ_HANDLED;
1898                 }
1899         }
1900
1901         /* SOF (for ISO transfer) */
1902         if (irq_src & USB_STS_SOF) {
1903                 status = IRQ_HANDLED;
1904         }
1905
1906         /* Port Change */
1907         if (irq_src & USB_STS_PORT_CHANGE) {
1908                 port_change_irq(udc);
1909                 status = IRQ_HANDLED;
1910         }
1911
1912         /* Reset Received */
1913         if (irq_src & USB_STS_RESET) {
1914                 VDBG("reset int");
1915                 reset_irq(udc);
1916                 status = IRQ_HANDLED;
1917         }
1918
1919         /* Sleep Enable (Suspend) */
1920         if (irq_src & USB_STS_SUSPEND) {
1921                 suspend_irq(udc);
1922                 status = IRQ_HANDLED;
1923         }
1924
1925         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1926                 VDBG("Error IRQ %x", irq_src);
1927         }
1928
1929         spin_unlock_irqrestore(&udc->lock, flags);
1930         return status;
1931 }
1932
1933 /*----------------------------------------------------------------*
1934  * Hook to gadget drivers
1935  * Called by initialization code of gadget drivers
1936 *----------------------------------------------------------------*/
1937 static int fsl_udc_start(struct usb_gadget *g,
1938                 struct usb_gadget_driver *driver)
1939 {
1940         int retval = 0;
1941         unsigned long flags;
1942
1943         /* lock is needed but whether should use this lock or another */
1944         spin_lock_irqsave(&udc_controller->lock, flags);
1945
1946         driver->driver.bus = NULL;
1947         /* hook up the driver */
1948         udc_controller->driver = driver;
1949         spin_unlock_irqrestore(&udc_controller->lock, flags);
1950         g->is_selfpowered = 1;
1951
1952         if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1953                 /* Suspend the controller until OTG enable it */
1954                 udc_controller->stopped = 1;
1955                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1956
1957                 /* connect to bus through transceiver */
1958                 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1959                         retval = otg_set_peripheral(
1960                                         udc_controller->transceiver->otg,
1961                                                     &udc_controller->gadget);
1962                         if (retval < 0) {
1963                                 ERR("can't bind to transceiver\n");
1964                                 udc_controller->driver = NULL;
1965                                 return retval;
1966                         }
1967                 }
1968         } else {
1969                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1970                 dr_controller_run(udc_controller);
1971                 udc_controller->usb_state = USB_STATE_ATTACHED;
1972                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1973                 udc_controller->ep0_dir = 0;
1974         }
1975
1976         return retval;
1977 }
1978
1979 /* Disconnect from gadget driver */
1980 static int fsl_udc_stop(struct usb_gadget *g)
1981 {
1982         struct fsl_ep *loop_ep;
1983         unsigned long flags;
1984
1985         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1986                 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1987
1988         /* stop DR, disable intr */
1989         dr_controller_stop(udc_controller);
1990
1991         /* in fact, no needed */
1992         udc_controller->usb_state = USB_STATE_ATTACHED;
1993         udc_controller->ep0_state = WAIT_FOR_SETUP;
1994         udc_controller->ep0_dir = 0;
1995
1996         /* stand operation */
1997         spin_lock_irqsave(&udc_controller->lock, flags);
1998         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1999         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2000         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2001                         ep.ep_list)
2002                 nuke(loop_ep, -ESHUTDOWN);
2003         spin_unlock_irqrestore(&udc_controller->lock, flags);
2004
2005         udc_controller->driver = NULL;
2006
2007         return 0;
2008 }
2009
2010 /*-------------------------------------------------------------------------
2011                 PROC File System Support
2012 -------------------------------------------------------------------------*/
2013 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2014
2015 #include <linux/seq_file.h>
2016
2017 static const char proc_filename[] = "driver/fsl_usb2_udc";
2018
2019 static int fsl_proc_read(struct seq_file *m, void *v)
2020 {
2021         unsigned long flags;
2022         int i;
2023         u32 tmp_reg;
2024         struct fsl_ep *ep = NULL;
2025         struct fsl_req *req;
2026
2027         struct fsl_udc *udc = udc_controller;
2028
2029         spin_lock_irqsave(&udc->lock, flags);
2030
2031         /* ------basic driver information ---- */
2032         seq_printf(m,
2033                         DRIVER_DESC "\n"
2034                         "%s version: %s\n"
2035                         "Gadget driver: %s\n\n",
2036                         driver_name, DRIVER_VERSION,
2037                         udc->driver ? udc->driver->driver.name : "(none)");
2038
2039         /* ------ DR Registers ----- */
2040         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2041         seq_printf(m,
2042                         "USBCMD reg:\n"
2043                         "SetupTW: %d\n"
2044                         "Run/Stop: %s\n\n",
2045                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2046                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2047
2048         tmp_reg = fsl_readl(&dr_regs->usbsts);
2049         seq_printf(m,
2050                         "USB Status Reg:\n"
2051                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2052                         "USB Error Interrupt: %s\n\n",
2053                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2054                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2055                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2056                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2057
2058         tmp_reg = fsl_readl(&dr_regs->usbintr);
2059         seq_printf(m,
2060                         "USB Interrupt Enable Reg:\n"
2061                         "Sleep Enable: %d SOF Received Enable: %d "
2062                         "Reset Enable: %d\n"
2063                         "System Error Enable: %d "
2064                         "Port Change Detected Enable: %d\n"
2065                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2066                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2067                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2068                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2069                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2070                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2071                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2072                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2073
2074         tmp_reg = fsl_readl(&dr_regs->frindex);
2075         seq_printf(m,
2076                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2077                         (tmp_reg & USB_FRINDEX_MASKS));
2078
2079         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2080         seq_printf(m,
2081                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2082                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2083
2084         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2085         seq_printf(m,
2086                         "USB Endpoint List Address Reg: "
2087                         "Device Addr is 0x%x\n\n",
2088                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2089
2090         tmp_reg = fsl_readl(&dr_regs->portsc1);
2091         seq_printf(m,
2092                 "USB Port Status&Control Reg:\n"
2093                 "Port Transceiver Type : %s Port Speed: %s\n"
2094                 "PHY Low Power Suspend: %s Port Reset: %s "
2095                 "Port Suspend Mode: %s\n"
2096                 "Over-current Change: %s "
2097                 "Port Enable/Disable Change: %s\n"
2098                 "Port Enabled/Disabled: %s "
2099                 "Current Connect Status: %s\n\n", ( {
2100                         const char *s;
2101                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2102                         case PORTSCX_PTS_UTMI:
2103                                 s = "UTMI"; break;
2104                         case PORTSCX_PTS_ULPI:
2105                                 s = "ULPI "; break;
2106                         case PORTSCX_PTS_FSLS:
2107                                 s = "FS/LS Serial"; break;
2108                         default:
2109                                 s = "None"; break;
2110                         }
2111                         s;} ),
2112                 usb_speed_string(portscx_device_speed(tmp_reg)),
2113                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2114                 "Normal PHY mode" : "Low power mode",
2115                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2116                 "Not in Reset",
2117                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2118                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2119                 "No",
2120                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2121                 "Not change",
2122                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2123                 "Not correct",
2124                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2125                 "Attached" : "Not-Att");
2126
2127         tmp_reg = fsl_readl(&dr_regs->usbmode);
2128         seq_printf(m,
2129                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2130                                 const char *s;
2131                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2132                                 case USB_MODE_CTRL_MODE_IDLE:
2133                                         s = "Idle"; break;
2134                                 case USB_MODE_CTRL_MODE_DEVICE:
2135                                         s = "Device Controller"; break;
2136                                 case USB_MODE_CTRL_MODE_HOST:
2137                                         s = "Host Controller"; break;
2138                                 default:
2139                                         s = "None"; break;
2140                                 }
2141                                 s;
2142                         } ));
2143
2144         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2145         seq_printf(m,
2146                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2147                         (tmp_reg & EP_SETUP_STATUS_MASK));
2148
2149         for (i = 0; i < udc->max_ep / 2; i++) {
2150                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2151                 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2152         }
2153         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2154         seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2155
2156         if (udc->pdata->have_sysif_regs) {
2157                 tmp_reg = usb_sys_regs->snoop1;
2158                 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2159
2160                 tmp_reg = usb_sys_regs->control;
2161                 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2162         }
2163
2164         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2165         ep = &udc->eps[0];
2166         seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2167                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2168
2169         if (list_empty(&ep->queue)) {
2170                 seq_puts(m, "its req queue is empty\n\n");
2171         } else {
2172                 list_for_each_entry(req, &ep->queue, queue) {
2173                         seq_printf(m,
2174                                 "req %p actual 0x%x length 0x%x buf %p\n",
2175                                 &req->req, req->req.actual,
2176                                 req->req.length, req->req.buf);
2177                 }
2178         }
2179         /* other gadget->eplist ep */
2180         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2181                 if (ep->ep.desc) {
2182                         seq_printf(m,
2183                                         "\nFor %s Maxpkt is 0x%x "
2184                                         "index is 0x%x\n",
2185                                         ep->ep.name, ep_maxpacket(ep),
2186                                         ep_index(ep));
2187
2188                         if (list_empty(&ep->queue)) {
2189                                 seq_puts(m, "its req queue is empty\n\n");
2190                         } else {
2191                                 list_for_each_entry(req, &ep->queue, queue) {
2192                                         seq_printf(m,
2193                                                 "req %p actual 0x%x length "
2194                                                 "0x%x  buf %p\n",
2195                                                 &req->req, req->req.actual,
2196                                                 req->req.length, req->req.buf);
2197                                 }       /* end for each_entry of ep req */
2198                         }       /* end for else */
2199                 }       /* end for if(ep->queue) */
2200         }       /* end (ep->desc) */
2201
2202         spin_unlock_irqrestore(&udc->lock, flags);
2203         return 0;
2204 }
2205
2206 #define create_proc_file() \
2207         proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2208 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2209
2210 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2211
2212 #define create_proc_file()      do {} while (0)
2213 #define remove_proc_file()      do {} while (0)
2214
2215 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2216
2217 /*-------------------------------------------------------------------------*/
2218
2219 /* Release udc structures */
2220 static void fsl_udc_release(struct device *dev)
2221 {
2222         complete(udc_controller->done);
2223         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2224                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2225         kfree(udc_controller);
2226 }
2227
2228 /******************************************************************
2229         Internal structure setup functions
2230 *******************************************************************/
2231 /*------------------------------------------------------------------
2232  * init resource for global controller called by fsl_udc_probe()
2233  * On success the udc handle is initialized, on failure it is
2234  * unchanged (reset).
2235  * Return 0 on success and -1 on allocation failure
2236  ------------------------------------------------------------------*/
2237 static int struct_udc_setup(struct fsl_udc *udc,
2238                 struct platform_device *pdev)
2239 {
2240         struct fsl_usb2_platform_data *pdata;
2241         size_t size;
2242
2243         pdata = dev_get_platdata(&pdev->dev);
2244         udc->phy_mode = pdata->phy_mode;
2245
2246         udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2247         if (!udc->eps) {
2248                 ERR("kmalloc udc endpoint status failed\n");
2249                 goto eps_alloc_failed;
2250         }
2251
2252         /* initialized QHs, take care of alignment */
2253         size = udc->max_ep * sizeof(struct ep_queue_head);
2254         if (size < QH_ALIGNMENT)
2255                 size = QH_ALIGNMENT;
2256         else if ((size % QH_ALIGNMENT) != 0) {
2257                 size += QH_ALIGNMENT + 1;
2258                 size &= ~(QH_ALIGNMENT - 1);
2259         }
2260         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2261                                         &udc->ep_qh_dma, GFP_KERNEL);
2262         if (!udc->ep_qh) {
2263                 ERR("malloc QHs for udc failed\n");
2264                 goto ep_queue_alloc_failed;
2265         }
2266
2267         udc->ep_qh_size = size;
2268
2269         /* Initialize ep0 status request structure */
2270         /* FIXME: fsl_alloc_request() ignores ep argument */
2271         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2272                         struct fsl_req, req);
2273         if (!udc->status_req) {
2274                 ERR("kzalloc for udc status request failed\n");
2275                 goto udc_status_alloc_failed;
2276         }
2277
2278         /* allocate a small amount of memory to get valid address */
2279         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2280         if (!udc->status_req->req.buf) {
2281                 ERR("kzalloc for udc request buffer failed\n");
2282                 goto udc_req_buf_alloc_failed;
2283         }
2284
2285         udc->resume_state = USB_STATE_NOTATTACHED;
2286         udc->usb_state = USB_STATE_POWERED;
2287         udc->ep0_dir = 0;
2288         udc->remote_wakeup = 0; /* default to 0 on reset */
2289
2290         return 0;
2291
2292 udc_req_buf_alloc_failed:
2293         kfree(udc->status_req);
2294 udc_status_alloc_failed:
2295         kfree(udc->ep_qh);
2296         udc->ep_qh_size = 0;
2297 ep_queue_alloc_failed:
2298         kfree(udc->eps);
2299 eps_alloc_failed:
2300         udc->phy_mode = 0;
2301         return -1;
2302
2303 }
2304
2305 /*----------------------------------------------------------------
2306  * Setup the fsl_ep struct for eps
2307  * Link fsl_ep->ep to gadget->ep_list
2308  * ep0out is not used so do nothing here
2309  * ep0in should be taken care
2310  *--------------------------------------------------------------*/
2311 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2312                 char *name, int link)
2313 {
2314         struct fsl_ep *ep = &udc->eps[index];
2315
2316         ep->udc = udc;
2317         strcpy(ep->name, name);
2318         ep->ep.name = ep->name;
2319
2320         ep->ep.ops = &fsl_ep_ops;
2321         ep->stopped = 0;
2322
2323         if (index == 0) {
2324                 ep->ep.caps.type_control = true;
2325         } else {
2326                 ep->ep.caps.type_iso = true;
2327                 ep->ep.caps.type_bulk = true;
2328                 ep->ep.caps.type_int = true;
2329         }
2330
2331         if (index & 1)
2332                 ep->ep.caps.dir_in = true;
2333         else
2334                 ep->ep.caps.dir_out = true;
2335
2336         /* for ep0: maxP defined in desc
2337          * for other eps, maxP is set by epautoconfig() called by gadget layer
2338          */
2339         usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2340
2341         /* the queue lists any req for this ep */
2342         INIT_LIST_HEAD(&ep->queue);
2343
2344         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2345         if (link)
2346                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2347         ep->gadget = &udc->gadget;
2348         ep->qh = &udc->ep_qh[index];
2349
2350         return 0;
2351 }
2352
2353 /* Driver probe function
2354  * all initialization operations implemented here except enabling usb_intr reg
2355  * board setup should have been done in the platform code
2356  */
2357 static int fsl_udc_probe(struct platform_device *pdev)
2358 {
2359         struct fsl_usb2_platform_data *pdata;
2360         struct resource *res;
2361         int ret = -ENODEV;
2362         unsigned int i;
2363         u32 dccparams;
2364
2365         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2366         if (udc_controller == NULL)
2367                 return -ENOMEM;
2368
2369         pdata = dev_get_platdata(&pdev->dev);
2370         udc_controller->pdata = pdata;
2371         spin_lock_init(&udc_controller->lock);
2372         udc_controller->stopped = 1;
2373
2374 #ifdef CONFIG_USB_OTG
2375         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2376                 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2377                 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2378                         ERR("Can't find OTG driver!\n");
2379                         ret = -ENODEV;
2380                         goto err_kfree;
2381                 }
2382         }
2383 #endif
2384
2385         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2386         if (!res) {
2387                 ret = -ENXIO;
2388                 goto err_kfree;
2389         }
2390
2391         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2392                 if (!request_mem_region(res->start, resource_size(res),
2393                                         driver_name)) {
2394                         ERR("request mem region for %s failed\n", pdev->name);
2395                         ret = -EBUSY;
2396                         goto err_kfree;
2397                 }
2398         }
2399
2400         dr_regs = ioremap(res->start, resource_size(res));
2401         if (!dr_regs) {
2402                 ret = -ENOMEM;
2403                 goto err_release_mem_region;
2404         }
2405
2406         pdata->regs = (void __iomem *)dr_regs;
2407
2408         /*
2409          * do platform specific init: check the clock, grab/config pins, etc.
2410          */
2411         if (pdata->init && pdata->init(pdev)) {
2412                 ret = -ENODEV;
2413                 goto err_iounmap;
2414         }
2415
2416         /* Set accessors only after pdata->init() ! */
2417         fsl_set_accessors(pdata);
2418
2419         if (pdata->have_sysif_regs)
2420                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2421
2422         /* Read Device Controller Capability Parameters register */
2423         dccparams = fsl_readl(&dr_regs->dccparams);
2424         if (!(dccparams & DCCPARAMS_DC)) {
2425                 ERR("This SOC doesn't support device role\n");
2426                 ret = -ENODEV;
2427                 goto err_exit;
2428         }
2429         /* Get max device endpoints */
2430         /* DEN is bidirectional ep number, max_ep doubles the number */
2431         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2432
2433         ret = platform_get_irq(pdev, 0);
2434         if (ret <= 0) {
2435                 ret = ret ? : -ENODEV;
2436                 goto err_exit;
2437         }
2438         udc_controller->irq = ret;
2439
2440         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2441                         driver_name, udc_controller);
2442         if (ret != 0) {
2443                 ERR("cannot request irq %d err %d\n",
2444                                 udc_controller->irq, ret);
2445                 goto err_exit;
2446         }
2447
2448         /* Initialize the udc structure including QH member and other member */
2449         if (struct_udc_setup(udc_controller, pdev)) {
2450                 ERR("Can't initialize udc data structure\n");
2451                 ret = -ENOMEM;
2452                 goto err_free_irq;
2453         }
2454
2455         if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2456                 /* initialize usb hw reg except for regs for EP,
2457                  * leave usbintr reg untouched */
2458                 dr_controller_setup(udc_controller);
2459         }
2460
2461         /* Setup gadget structure */
2462         udc_controller->gadget.ops = &fsl_gadget_ops;
2463         udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2464         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2465         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2466         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2467         udc_controller->gadget.name = driver_name;
2468
2469         /* Setup gadget.dev and register with kernel */
2470         dev_set_name(&udc_controller->gadget.dev, "gadget");
2471         udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2472
2473         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2474                 udc_controller->gadget.is_otg = 1;
2475
2476         /* setup QH and epctrl for ep0 */
2477         ep0_setup(udc_controller);
2478
2479         /* setup udc->eps[] for ep0 */
2480         struct_ep_setup(udc_controller, 0, "ep0", 0);
2481         /* for ep0: the desc defined here;
2482          * for other eps, gadget layer called ep_enable with defined desc
2483          */
2484         udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2485         usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2486                                    USB_MAX_CTRL_PAYLOAD);
2487
2488         /* setup the udc->eps[] for non-control endpoints and link
2489          * to gadget.ep_list */
2490         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2491                 char name[14];
2492
2493                 sprintf(name, "ep%dout", i);
2494                 struct_ep_setup(udc_controller, i * 2, name, 1);
2495                 sprintf(name, "ep%din", i);
2496                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2497         }
2498
2499         /* use dma_pool for TD management */
2500         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2501                         sizeof(struct ep_td_struct),
2502                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2503         if (udc_controller->td_pool == NULL) {
2504                 ret = -ENOMEM;
2505                 goto err_free_irq;
2506         }
2507
2508         ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2509                         fsl_udc_release);
2510         if (ret)
2511                 goto err_del_udc;
2512
2513         create_proc_file();
2514         return 0;
2515
2516 err_del_udc:
2517         dma_pool_destroy(udc_controller->td_pool);
2518 err_free_irq:
2519         free_irq(udc_controller->irq, udc_controller);
2520 err_exit:
2521         if (pdata->exit)
2522                 pdata->exit(pdev);
2523 err_iounmap:
2524         iounmap(dr_regs);
2525 err_release_mem_region:
2526         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2527                 release_mem_region(res->start, resource_size(res));
2528 err_kfree:
2529         kfree(udc_controller);
2530         udc_controller = NULL;
2531         return ret;
2532 }
2533
2534 /* Driver removal function
2535  * Free resources and finish pending transactions
2536  */
2537 static int fsl_udc_remove(struct platform_device *pdev)
2538 {
2539         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2540         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2541
2542         DECLARE_COMPLETION_ONSTACK(done);
2543
2544         if (!udc_controller)
2545                 return -ENODEV;
2546
2547         udc_controller->done = &done;
2548         usb_del_gadget_udc(&udc_controller->gadget);
2549
2550         /* DR has been stopped in usb_gadget_unregister_driver() */
2551         remove_proc_file();
2552
2553         /* Free allocated memory */
2554         kfree(udc_controller->status_req->req.buf);
2555         kfree(udc_controller->status_req);
2556         kfree(udc_controller->eps);
2557
2558         dma_pool_destroy(udc_controller->td_pool);
2559         free_irq(udc_controller->irq, udc_controller);
2560         iounmap(dr_regs);
2561         if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2562                 release_mem_region(res->start, resource_size(res));
2563
2564         /* free udc --wait for the release() finished */
2565         wait_for_completion(&done);
2566
2567         /*
2568          * do platform specific un-initialization:
2569          * release iomux pins, etc.
2570          */
2571         if (pdata->exit)
2572                 pdata->exit(pdev);
2573
2574         return 0;
2575 }
2576
2577 /*-----------------------------------------------------------------
2578  * Modify Power management attributes
2579  * Used by OTG statemachine to disable gadget temporarily
2580  -----------------------------------------------------------------*/
2581 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2582 {
2583         dr_controller_stop(udc_controller);
2584         return 0;
2585 }
2586
2587 /*-----------------------------------------------------------------
2588  * Invoked on USB resume. May be called in_interrupt.
2589  * Here we start the DR controller and enable the irq
2590  *-----------------------------------------------------------------*/
2591 static int fsl_udc_resume(struct platform_device *pdev)
2592 {
2593         /* Enable DR irq reg and set controller Run */
2594         if (udc_controller->stopped) {
2595                 dr_controller_setup(udc_controller);
2596                 dr_controller_run(udc_controller);
2597         }
2598         udc_controller->usb_state = USB_STATE_ATTACHED;
2599         udc_controller->ep0_state = WAIT_FOR_SETUP;
2600         udc_controller->ep0_dir = 0;
2601         return 0;
2602 }
2603
2604 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2605 {
2606         struct fsl_udc *udc = udc_controller;
2607         u32 mode, usbcmd;
2608
2609         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2610
2611         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2612
2613         /*
2614          * If the controller is already stopped, then this must be a
2615          * PM suspend.  Remember this fact, so that we will leave the
2616          * controller stopped at PM resume time.
2617          */
2618         if (udc->stopped) {
2619                 pr_debug("gadget already stopped, leaving early\n");
2620                 udc->already_stopped = 1;
2621                 return 0;
2622         }
2623
2624         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2625                 pr_debug("gadget not in device mode, leaving early\n");
2626                 return 0;
2627         }
2628
2629         /* stop the controller */
2630         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2631         fsl_writel(usbcmd, &dr_regs->usbcmd);
2632
2633         udc->stopped = 1;
2634
2635         pr_info("USB Gadget suspended\n");
2636
2637         return 0;
2638 }
2639
2640 static int fsl_udc_otg_resume(struct device *dev)
2641 {
2642         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2643                  udc_controller->stopped, udc_controller->already_stopped);
2644
2645         /*
2646          * If the controller was stopped at suspend time, then
2647          * don't resume it now.
2648          */
2649         if (udc_controller->already_stopped) {
2650                 udc_controller->already_stopped = 0;
2651                 pr_debug("gadget was already stopped, leaving early\n");
2652                 return 0;
2653         }
2654
2655         pr_info("USB Gadget resume\n");
2656
2657         return fsl_udc_resume(NULL);
2658 }
2659 /*-------------------------------------------------------------------------
2660         Register entry point for the peripheral controller driver
2661 --------------------------------------------------------------------------*/
2662 static const struct platform_device_id fsl_udc_devtype[] = {
2663         {
2664                 .name = "fsl-usb2-udc",
2665         }, {
2666                 /* sentinel */
2667         }
2668 };
2669 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2670 static struct platform_driver udc_driver = {
2671         .remove         = fsl_udc_remove,
2672         .id_table       = fsl_udc_devtype,
2673         /* these suspend and resume are not usb suspend and resume */
2674         .suspend        = fsl_udc_suspend,
2675         .resume         = fsl_udc_resume,
2676         .driver         = {
2677                         .name = driver_name,
2678                         /* udc suspend/resume called from OTG driver */
2679                         .suspend = fsl_udc_otg_suspend,
2680                         .resume  = fsl_udc_otg_resume,
2681         },
2682 };
2683
2684 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2685
2686 MODULE_DESCRIPTION(DRIVER_DESC);
2687 MODULE_AUTHOR(DRIVER_AUTHOR);
2688 MODULE_LICENSE("GPL");
2689 MODULE_ALIAS("platform:fsl-usb2-udc");