1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021 Aspeed Technology Inc.
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/prefetch.h>
15 #include <linux/usb/ch9.h>
16 #include <linux/usb/gadget.h>
17 #include <linux/slab.h>
19 #define AST_UDC_NUM_ENDPOINTS (1 + 4)
20 #define AST_UDC_EP0_MAX_PACKET 64 /* EP0's max packet size */
21 #define AST_UDC_EPn_MAX_PACKET 1024 /* Generic EPs max packet size */
22 #define AST_UDC_DESCS_COUNT 256 /* Use 256 stages descriptor mode (32/256) */
23 #define AST_UDC_DESC_MODE 1 /* Single/Multiple Stage(s) Descriptor Mode */
25 #define AST_UDC_EP_DMA_SIZE (AST_UDC_EPn_MAX_PACKET + 8 * AST_UDC_DESCS_COUNT)
27 /*****************************
29 * UDC register definitions *
31 *****************************/
33 #define AST_UDC_FUNC_CTRL 0x00 /* Root Function Control & Status Register */
34 #define AST_UDC_CONFIG 0x04 /* Root Configuration Setting Register */
35 #define AST_UDC_IER 0x08 /* Interrupt Control Register */
36 #define AST_UDC_ISR 0x0C /* Interrupt Status Register */
37 #define AST_UDC_EP_ACK_IER 0x10 /* Programmable ep Pool ACK Interrupt Enable Reg */
38 #define AST_UDC_EP_NAK_IER 0x14 /* Programmable ep Pool NAK Interrupt Enable Reg */
39 #define AST_UDC_EP_ACK_ISR 0x18 /* Programmable ep Pool ACK Interrupt Status Reg */
40 #define AST_UDC_EP_NAK_ISR 0x1C /* Programmable ep Pool NAK Interrupt Status Reg */
41 #define AST_UDC_DEV_RESET 0x20 /* Device Controller Soft Reset Enable Register */
42 #define AST_UDC_STS 0x24 /* USB Status Register */
43 #define AST_VHUB_EP_DATA 0x28 /* Programmable ep Pool Data Toggle Value Set */
44 #define AST_VHUB_ISO_TX_FAIL 0x2C /* Isochronous Transaction Fail Accumulator */
45 #define AST_UDC_EP0_CTRL 0x30 /* Endpoint 0 Control/Status Register */
46 #define AST_UDC_EP0_DATA_BUFF 0x34 /* Base Address of ep0 IN/OUT Data Buffer Reg */
47 #define AST_UDC_SETUP0 0x80 /* Root Device Setup Data Buffer0 */
48 #define AST_UDC_SETUP1 0x84 /* Root Device Setup Data Buffer1 */
51 /* Main control reg */
52 #define USB_PHY_CLK_EN BIT(31)
53 #define USB_FIFO_DYN_PWRD_EN BIT(19)
54 #define USB_EP_LONG_DESC BIT(18)
55 #define USB_BIST_TEST_PASS BIT(13)
56 #define USB_BIST_TURN_ON BIT(12)
57 #define USB_PHY_RESET_DIS BIT(11)
58 #define USB_TEST_MODE(x) ((x) << 8)
59 #define USB_FORCE_TIMER_HS BIT(7)
60 #define USB_FORCE_HS BIT(6)
61 #define USB_REMOTE_WAKEUP_12MS BIT(5)
62 #define USB_REMOTE_WAKEUP_EN BIT(4)
63 #define USB_AUTO_REMOTE_WAKEUP_EN BIT(3)
64 #define USB_STOP_CLK_IN_SUPEND BIT(2)
65 #define USB_UPSTREAM_FS BIT(1)
66 #define USB_UPSTREAM_EN BIT(0)
69 #define UDC_CFG_SET_ADDR(x) ((x) & 0x3f)
70 #define UDC_CFG_ADDR_MASK (0x3f)
72 /* Interrupt ctrl & status reg */
73 #define UDC_IRQ_EP_POOL_NAK BIT(17)
74 #define UDC_IRQ_EP_POOL_ACK_STALL BIT(16)
75 #define UDC_IRQ_BUS_RESUME BIT(8)
76 #define UDC_IRQ_BUS_SUSPEND BIT(7)
77 #define UDC_IRQ_BUS_RESET BIT(6)
78 #define UDC_IRQ_EP0_IN_DATA_NAK BIT(4)
79 #define UDC_IRQ_EP0_IN_ACK_STALL BIT(3)
80 #define UDC_IRQ_EP0_OUT_NAK BIT(2)
81 #define UDC_IRQ_EP0_OUT_ACK_STALL BIT(1)
82 #define UDC_IRQ_EP0_SETUP BIT(0)
83 #define UDC_IRQ_ACK_ALL (0x1ff)
86 #define USB_EP3_ISR BIT(3)
87 #define USB_EP2_ISR BIT(2)
88 #define USB_EP1_ISR BIT(1)
89 #define USB_EP0_ISR BIT(0)
90 #define UDC_IRQ_EP_ACK_ALL (0xf)
93 #define ROOT_UDC_SOFT_RESET BIT(0)
96 #define UDC_STS_HIGHSPEED BIT(27)
98 /* Programmable EP data toggle */
99 #define EP_TOGGLE_SET_EPNUM(x) ((x) & 0x3)
102 #define EP0_GET_RX_LEN(x) ((x >> 16) & 0x7f)
103 #define EP0_TX_LEN(x) ((x & 0x7f) << 8)
104 #define EP0_RX_BUFF_RDY BIT(2)
105 #define EP0_TX_BUFF_RDY BIT(1)
106 #define EP0_STALL BIT(0)
108 /*************************************
110 * per-endpoint register definitions *
112 *************************************/
114 #define AST_UDC_EP_CONFIG 0x00 /* Endpoint Configuration Register */
115 #define AST_UDC_EP_DMA_CTRL 0x04 /* DMA Descriptor List Control/Status Register */
116 #define AST_UDC_EP_DMA_BUFF 0x08 /* DMA Descriptor/Buffer Base Address */
117 #define AST_UDC_EP_DMA_STS 0x0C /* DMA Descriptor List R/W Pointer and Status */
119 #define AST_UDC_EP_BASE 0x200
120 #define AST_UDC_EP_OFFSET 0x10
123 #define EP_SET_MAX_PKT(x) ((x & 0x3ff) << 16)
124 #define EP_DATA_FETCH_CTRL(x) ((x & 0x3) << 14)
125 #define EP_AUTO_DATA_DISABLE (0x1 << 13)
126 #define EP_SET_EP_STALL (0x1 << 12)
127 #define EP_SET_EP_NUM(x) ((x & 0xf) << 8)
128 #define EP_SET_TYPE_MASK(x) ((x) << 5)
129 #define EP_TYPE_BULK (0x1)
130 #define EP_TYPE_INT (0x2)
131 #define EP_TYPE_ISO (0x3)
132 #define EP_DIR_OUT (0x1 << 4)
133 #define EP_ALLOCATED_MASK (0x7 << 1)
134 #define EP_ENABLE BIT(0)
136 /* EP DMA ctrl reg */
137 #define EP_DMA_CTRL_GET_PROC_STS(x) ((x >> 4) & 0xf)
138 #define EP_DMA_CTRL_STS_RX_IDLE 0x0
139 #define EP_DMA_CTRL_STS_TX_IDLE 0x8
140 #define EP_DMA_CTRL_IN_LONG_MODE (0x1 << 3)
141 #define EP_DMA_CTRL_RESET (0x1 << 2)
142 #define EP_DMA_SINGLE_STAGE (0x1 << 1)
143 #define EP_DMA_DESC_MODE (0x1 << 0)
145 /* EP DMA status reg */
146 #define EP_DMA_SET_TX_SIZE(x) ((x & 0x7ff) << 16)
147 #define EP_DMA_GET_TX_SIZE(x) (((x) >> 16) & 0x7ff)
148 #define EP_DMA_GET_RPTR(x) (((x) >> 8) & 0xff)
149 #define EP_DMA_GET_WPTR(x) ((x) & 0xff)
150 #define EP_DMA_SINGLE_KICK (1 << 0) /* WPTR = 1 for single mode */
153 #define AST_EP_DMA_DESC_INTR_ENABLE BIT(31)
154 #define AST_EP_DMA_DESC_PID_DATA0 (0 << 14)
155 #define AST_EP_DMA_DESC_PID_DATA2 BIT(14)
156 #define AST_EP_DMA_DESC_PID_DATA1 (2 << 14)
157 #define AST_EP_DMA_DESC_PID_MDATA (3 << 14)
158 #define EP_DESC1_IN_LEN(x) ((x) & 0x1fff)
159 #define AST_EP_DMA_DESC_MAX_LEN (7680) /* Max packet length for trasmit in 1 desc */
161 struct ast_udc_request {
162 struct usb_request req;
163 struct list_head queue;
165 unsigned int actual_dma_length;
169 #define to_ast_req(__req) container_of(__req, struct ast_udc_request, req)
171 struct ast_dma_desc {
180 struct list_head queue;
182 struct ast_udc_dev *udc;
183 void __iomem *ep_reg;
185 dma_addr_t epn_buf_dma;
186 const struct usb_endpoint_descriptor *desc;
188 /* DMA Descriptors */
189 struct ast_dma_desc *descs;
190 dma_addr_t descs_dma;
199 #define to_ast_ep(__ep) container_of(__ep, struct ast_udc_ep, ep)
202 struct platform_device *pdev;
207 struct work_struct wake_work;
209 /* EP0 DMA buffers allocated in one chunk */
211 dma_addr_t ep0_buf_dma;
212 struct ast_udc_ep ep[AST_UDC_NUM_ENDPOINTS];
214 struct usb_gadget gadget;
215 struct usb_gadget_driver *driver;
217 enum usb_device_state suspended_from;
220 /* Force full speed only */
222 unsigned is_control_tx:1;
226 #define to_ast_dev(__g) container_of(__g, struct ast_udc_dev, gadget)
228 static const char * const ast_ep_name[] = {
229 "ep0", "ep1", "ep2", "ep3", "ep4"
232 #ifdef AST_UDC_DEBUG_ALL
233 #define AST_UDC_DEBUG
234 #define AST_SETUP_DEBUG
236 #define AST_ISR_DEBUG
239 #ifdef AST_SETUP_DEBUG
240 #define SETUP_DBG(u, fmt, ...) \
241 dev_dbg(&(u)->pdev->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
243 #define SETUP_DBG(u, fmt, ...)
247 #define EP_DBG(e, fmt, ...) \
248 dev_dbg(&(e)->udc->pdev->dev, "%s():%s " fmt, __func__, \
249 (e)->ep.name, ##__VA_ARGS__)
251 #define EP_DBG(ep, fmt, ...) ((void)(ep))
255 #define UDC_DBG(u, fmt, ...) \
256 dev_dbg(&(u)->pdev->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
258 #define UDC_DBG(u, fmt, ...)
262 #define ISR_DBG(u, fmt, ...) \
263 dev_dbg(&(u)->pdev->dev, "%s() " fmt, __func__, ##__VA_ARGS__)
265 #define ISR_DBG(u, fmt, ...)
268 /*-------------------------------------------------------------------------*/
269 #define ast_udc_read(udc, offset) \
270 readl((udc)->reg + (offset))
271 #define ast_udc_write(udc, val, offset) \
272 writel((val), (udc)->reg + (offset))
274 #define ast_ep_read(ep, reg) \
275 readl((ep)->ep_reg + (reg))
276 #define ast_ep_write(ep, val, reg) \
277 writel((val), (ep)->ep_reg + (reg))
279 /*-------------------------------------------------------------------------*/
281 static void ast_udc_done(struct ast_udc_ep *ep, struct ast_udc_request *req,
284 struct ast_udc_dev *udc = ep->udc;
286 EP_DBG(ep, "req @%p, len (%d/%d), buf:0x%x, dir:0x%x\n",
287 req, req->req.actual, req->req.length,
288 (u32)req->req.buf, ep->dir_in);
290 list_del(&req->queue);
292 if (req->req.status == -EINPROGRESS)
293 req->req.status = status;
295 status = req->req.status;
297 if (status && status != -ESHUTDOWN)
298 EP_DBG(ep, "done req:%p, status:%d\n", req, status);
300 spin_unlock(&udc->lock);
301 usb_gadget_giveback_request(&ep->ep, &req->req);
302 spin_lock(&udc->lock);
305 static void ast_udc_nuke(struct ast_udc_ep *ep, int status)
309 while (!list_empty(&ep->queue)) {
310 struct ast_udc_request *req;
312 req = list_entry(ep->queue.next, struct ast_udc_request,
314 ast_udc_done(ep, req, status);
319 EP_DBG(ep, "Nuked %d request(s)\n", count);
323 * Stop activity on all endpoints.
324 * Device controller for which EP activity is to be stopped.
326 * All the endpoints are stopped and any pending transfer requests if any on
327 * the endpoint are terminated.
329 static void ast_udc_stop_activity(struct ast_udc_dev *udc)
331 struct ast_udc_ep *ep;
334 for (i = 0; i < AST_UDC_NUM_ENDPOINTS; i++) {
337 ast_udc_nuke(ep, -ESHUTDOWN);
341 static int ast_udc_ep_enable(struct usb_ep *_ep,
342 const struct usb_endpoint_descriptor *desc)
344 u16 maxpacket = usb_endpoint_maxp(desc);
345 struct ast_udc_ep *ep = to_ast_ep(_ep);
346 struct ast_udc_dev *udc = ep->udc;
347 u8 epnum = usb_endpoint_num(desc);
353 if (!_ep || !ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT ||
354 maxpacket == 0 || maxpacket > ep->ep.maxpacket) {
355 EP_DBG(ep, "Failed, invalid EP enable param\n");
360 EP_DBG(ep, "bogus device state\n");
364 EP_DBG(ep, "maxpacket:0x%x\n", maxpacket);
366 spin_lock_irqsave(&udc->lock, flags);
370 ep->ep.maxpacket = maxpacket;
371 ep->chunk_max = AST_EP_DMA_DESC_MAX_LEN;
373 if (maxpacket < AST_UDC_EPn_MAX_PACKET)
374 ep_conf = EP_SET_MAX_PKT(maxpacket);
376 ep_conf |= EP_SET_EP_NUM(epnum);
378 type = usb_endpoint_type(desc);
379 dir_in = usb_endpoint_dir_in(desc);
382 ep_conf |= EP_DIR_OUT;
384 EP_DBG(ep, "type %d, dir_in %d\n", type, dir_in);
386 case USB_ENDPOINT_XFER_ISOC:
387 ep_conf |= EP_SET_TYPE_MASK(EP_TYPE_ISO);
390 case USB_ENDPOINT_XFER_BULK:
391 ep_conf |= EP_SET_TYPE_MASK(EP_TYPE_BULK);
394 case USB_ENDPOINT_XFER_INT:
395 ep_conf |= EP_SET_TYPE_MASK(EP_TYPE_INT);
399 ep->desc_mode = udc->desc_mode && ep->descs_dma && ep->dir_in;
401 ast_ep_write(ep, EP_DMA_CTRL_RESET, AST_UDC_EP_DMA_CTRL);
402 ast_ep_write(ep, 0, AST_UDC_EP_DMA_STS);
403 ast_ep_write(ep, ep->descs_dma, AST_UDC_EP_DMA_BUFF);
405 /* Enable Long Descriptor Mode */
406 ast_ep_write(ep, EP_DMA_CTRL_IN_LONG_MODE | EP_DMA_DESC_MODE,
407 AST_UDC_EP_DMA_CTRL);
412 ast_ep_write(ep, EP_DMA_CTRL_RESET, AST_UDC_EP_DMA_CTRL);
413 ast_ep_write(ep, EP_DMA_SINGLE_STAGE, AST_UDC_EP_DMA_CTRL);
414 ast_ep_write(ep, 0, AST_UDC_EP_DMA_STS);
417 /* Cleanup data toggle just in case */
418 ast_udc_write(udc, EP_TOGGLE_SET_EPNUM(epnum), AST_VHUB_EP_DATA);
421 ast_ep_write(ep, ep_conf | EP_ENABLE, AST_UDC_EP_CONFIG);
423 EP_DBG(ep, "ep_config: 0x%x\n", ast_ep_read(ep, AST_UDC_EP_CONFIG));
425 spin_unlock_irqrestore(&udc->lock, flags);
430 static int ast_udc_ep_disable(struct usb_ep *_ep)
432 struct ast_udc_ep *ep = to_ast_ep(_ep);
433 struct ast_udc_dev *udc = ep->udc;
436 spin_lock_irqsave(&udc->lock, flags);
441 ast_udc_nuke(ep, -ESHUTDOWN);
442 ast_ep_write(ep, 0, AST_UDC_EP_CONFIG);
444 spin_unlock_irqrestore(&udc->lock, flags);
449 static struct usb_request *ast_udc_ep_alloc_request(struct usb_ep *_ep,
452 struct ast_udc_ep *ep = to_ast_ep(_ep);
453 struct ast_udc_request *req;
455 req = kzalloc(sizeof(struct ast_udc_request), gfp_flags);
457 EP_DBG(ep, "request allocation failed\n");
461 INIT_LIST_HEAD(&req->queue);
466 static void ast_udc_ep_free_request(struct usb_ep *_ep,
467 struct usb_request *_req)
469 struct ast_udc_request *req = to_ast_req(_req);
474 static int ast_dma_descriptor_setup(struct ast_udc_ep *ep, u32 dma_buf,
475 u16 tx_len, struct ast_udc_request *req)
477 struct ast_udc_dev *udc = ep->udc;
478 struct device *dev = &udc->pdev->dev;
484 dev_warn(dev, "%s: Empty DMA descs list failure\n",
492 EP_DBG(ep, "req @%p, %s:%d, %s:0x%x, %s:0x%x\n", req,
493 "wptr", ep->descs_wptr, "dma_buf", dma_buf,
496 /* Create Descriptor Lists */
497 while (chunk >= 0 && !last && count < AST_UDC_DESCS_COUNT) {
499 ep->descs[ep->descs_wptr].des_0 = dma_buf + offset;
501 if (chunk > ep->chunk_max) {
502 ep->descs[ep->descs_wptr].des_1 = ep->chunk_max;
504 ep->descs[ep->descs_wptr].des_1 = chunk;
508 chunk -= ep->chunk_max;
510 EP_DBG(ep, "descs[%d]: 0x%x 0x%x\n",
512 ep->descs[ep->descs_wptr].des_0,
513 ep->descs[ep->descs_wptr].des_1);
516 req->saved_dma_wptr = ep->descs_wptr;
521 if (ep->descs_wptr >= AST_UDC_DESCS_COUNT)
524 offset = ep->chunk_max * count;
530 static void ast_udc_epn_kick(struct ast_udc_ep *ep, struct ast_udc_request *req)
535 last = req->req.length - req->req.actual;
536 tx_len = last > ep->ep.maxpacket ? ep->ep.maxpacket : last;
538 EP_DBG(ep, "kick req @%p, len:%d, dir:%d\n",
539 req, tx_len, ep->dir_in);
541 ast_ep_write(ep, req->req.dma + req->req.actual, AST_UDC_EP_DMA_BUFF);
544 ast_ep_write(ep, EP_DMA_SET_TX_SIZE(tx_len), AST_UDC_EP_DMA_STS);
545 ast_ep_write(ep, EP_DMA_SET_TX_SIZE(tx_len) | EP_DMA_SINGLE_KICK,
549 static void ast_udc_epn_kick_desc(struct ast_udc_ep *ep,
550 struct ast_udc_request *req)
556 descs_max_size = AST_EP_DMA_DESC_MAX_LEN * AST_UDC_DESCS_COUNT;
558 last = req->req.length - req->req.actual;
559 tx_len = last > descs_max_size ? descs_max_size : last;
561 EP_DBG(ep, "kick req @%p, %s:%d, %s:0x%x, %s:0x%x (%d/%d), %s:0x%x\n",
562 req, "tx_len", tx_len, "dir_in", ep->dir_in,
563 "dma", req->req.dma + req->req.actual,
564 req->req.actual, req->req.length,
565 "descs_max_size", descs_max_size);
567 if (!ast_dma_descriptor_setup(ep, req->req.dma + req->req.actual,
569 req->actual_dma_length += tx_len;
571 /* make sure CPU done everything before triggering DMA */
574 ast_ep_write(ep, ep->descs_wptr, AST_UDC_EP_DMA_STS);
576 EP_DBG(ep, "descs_wptr:%d, dstat:0x%x, dctrl:0x%x\n",
578 ast_ep_read(ep, AST_UDC_EP_DMA_STS),
579 ast_ep_read(ep, AST_UDC_EP_DMA_CTRL));
582 static void ast_udc_ep0_queue(struct ast_udc_ep *ep,
583 struct ast_udc_request *req)
585 struct ast_udc_dev *udc = ep->udc;
589 last = req->req.length - req->req.actual;
590 tx_len = last > ep->ep.maxpacket ? ep->ep.maxpacket : last;
592 ast_udc_write(udc, req->req.dma + req->req.actual,
593 AST_UDC_EP0_DATA_BUFF);
596 /* IN requests, send data */
597 SETUP_DBG(udc, "IN: %s:0x%x, %s:0x%x, %s:%d (%d/%d), %s:%d\n",
598 "buf", (u32)req->req.buf,
599 "dma", req->req.dma + req->req.actual,
601 req->req.actual, req->req.length,
602 "dir_in", ep->dir_in);
604 req->req.actual += tx_len;
605 ast_udc_write(udc, EP0_TX_LEN(tx_len), AST_UDC_EP0_CTRL);
606 ast_udc_write(udc, EP0_TX_LEN(tx_len) | EP0_TX_BUFF_RDY,
610 /* OUT requests, receive data */
611 SETUP_DBG(udc, "OUT: %s:%x, %s:%x, %s:(%d/%d), %s:%d\n",
612 "buf", (u32)req->req.buf,
613 "dma", req->req.dma + req->req.actual,
614 "len", req->req.actual, req->req.length,
615 "dir_in", ep->dir_in);
617 if (!req->req.length) {
618 /* 0 len request, send tx as completion */
619 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL);
622 ast_udc_write(udc, EP0_RX_BUFF_RDY, AST_UDC_EP0_CTRL);
626 static int ast_udc_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
629 struct ast_udc_request *req = to_ast_req(_req);
630 struct ast_udc_ep *ep = to_ast_ep(_ep);
631 struct ast_udc_dev *udc = ep->udc;
632 struct device *dev = &udc->pdev->dev;
636 if (unlikely(!_req || !_req->complete || !_req->buf || !_ep)) {
637 dev_warn(dev, "Invalid EP request !\n");
642 dev_warn(dev, "%s is already stopped !\n", _ep->name);
646 spin_lock_irqsave(&udc->lock, flags);
648 list_add_tail(&req->queue, &ep->queue);
651 req->req.status = -EINPROGRESS;
652 req->actual_dma_length = 0;
654 rc = usb_gadget_map_request(&udc->gadget, &req->req, ep->dir_in);
656 EP_DBG(ep, "Request mapping failure %d\n", rc);
657 dev_warn(dev, "Request mapping failure %d\n", rc);
661 EP_DBG(ep, "enqueue req @%p\n", req);
662 EP_DBG(ep, "l=%d, dma:0x%x, zero:%d, is_in:%d\n",
663 _req->length, _req->dma, _req->zero, ep->dir_in);
665 /* EP0 request enqueue */
666 if (ep->ep.desc == NULL) {
667 if ((req->req.dma % 4) != 0) {
668 dev_warn(dev, "EP0 req dma alignment error\n");
673 ast_udc_ep0_queue(ep, req);
677 /* EPn request enqueue */
678 if (list_is_singular(&ep->queue)) {
680 ast_udc_epn_kick_desc(ep, req);
682 ast_udc_epn_kick(ep, req);
686 spin_unlock_irqrestore(&udc->lock, flags);
691 static int ast_udc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
693 struct ast_udc_ep *ep = to_ast_ep(_ep);
694 struct ast_udc_dev *udc = ep->udc;
695 struct ast_udc_request *req;
699 spin_lock_irqsave(&udc->lock, flags);
701 /* make sure it's actually queued on this endpoint */
702 list_for_each_entry(req, &ep->queue, queue) {
703 if (&req->req == _req) {
704 list_del_init(&req->queue);
705 ast_udc_done(ep, req, -ESHUTDOWN);
706 _req->status = -ECONNRESET;
711 /* dequeue request not found */
712 if (&req->req != _req)
715 spin_unlock_irqrestore(&udc->lock, flags);
720 static int ast_udc_ep_set_halt(struct usb_ep *_ep, int value)
722 struct ast_udc_ep *ep = to_ast_ep(_ep);
723 struct ast_udc_dev *udc = ep->udc;
728 EP_DBG(ep, "val:%d\n", value);
730 spin_lock_irqsave(&udc->lock, flags);
732 epnum = usb_endpoint_num(ep->desc);
736 ctrl = ast_udc_read(udc, AST_UDC_EP0_CTRL);
742 ast_udc_write(udc, ctrl, AST_UDC_EP0_CTRL);
746 ctrl = ast_udc_read(udc, AST_UDC_EP_CONFIG);
748 ctrl |= EP_SET_EP_STALL;
750 ctrl &= ~EP_SET_EP_STALL;
752 ast_ep_write(ep, ctrl, AST_UDC_EP_CONFIG);
754 /* only epn is stopped and waits for clear */
755 ep->stopped = value ? 1 : 0;
758 spin_unlock_irqrestore(&udc->lock, flags);
763 static const struct usb_ep_ops ast_udc_ep_ops = {
764 .enable = ast_udc_ep_enable,
765 .disable = ast_udc_ep_disable,
766 .alloc_request = ast_udc_ep_alloc_request,
767 .free_request = ast_udc_ep_free_request,
768 .queue = ast_udc_ep_queue,
769 .dequeue = ast_udc_ep_dequeue,
770 .set_halt = ast_udc_ep_set_halt,
771 /* there's only imprecise fifo status reporting */
774 static void ast_udc_ep0_rx(struct ast_udc_dev *udc)
776 ast_udc_write(udc, udc->ep0_buf_dma, AST_UDC_EP0_DATA_BUFF);
777 ast_udc_write(udc, EP0_RX_BUFF_RDY, AST_UDC_EP0_CTRL);
780 static void ast_udc_ep0_tx(struct ast_udc_dev *udc)
782 ast_udc_write(udc, udc->ep0_buf_dma, AST_UDC_EP0_DATA_BUFF);
783 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL);
786 static void ast_udc_ep0_out(struct ast_udc_dev *udc)
788 struct device *dev = &udc->pdev->dev;
789 struct ast_udc_ep *ep = &udc->ep[0];
790 struct ast_udc_request *req;
793 if (list_empty(&ep->queue))
796 req = list_entry(ep->queue.next, struct ast_udc_request, queue);
798 rx_len = EP0_GET_RX_LEN(ast_udc_read(udc, AST_UDC_EP0_CTRL));
799 req->req.actual += rx_len;
801 SETUP_DBG(udc, "req %p (%d/%d)\n", req,
802 req->req.actual, req->req.length);
804 if ((rx_len < ep->ep.maxpacket) ||
805 (req->req.actual == req->req.length)) {
808 ast_udc_done(ep, req, 0);
811 if (rx_len > req->req.length) {
813 dev_warn(dev, "Something wrong (%d/%d)\n",
814 req->req.actual, req->req.length);
816 ast_udc_done(ep, req, 0);
823 ast_udc_ep0_queue(ep, req);
827 static void ast_udc_ep0_in(struct ast_udc_dev *udc)
829 struct ast_udc_ep *ep = &udc->ep[0];
830 struct ast_udc_request *req;
832 if (list_empty(&ep->queue)) {
833 if (udc->is_control_tx) {
835 udc->is_control_tx = 0;
841 req = list_entry(ep->queue.next, struct ast_udc_request, queue);
843 SETUP_DBG(udc, "req %p (%d/%d)\n", req,
844 req->req.actual, req->req.length);
846 if (req->req.length == req->req.actual) {
851 ast_udc_done(ep, req, 0);
855 ast_udc_ep0_queue(ep, req);
859 static void ast_udc_epn_handle(struct ast_udc_dev *udc, u16 ep_num)
861 struct ast_udc_ep *ep = &udc->ep[ep_num];
862 struct ast_udc_request *req;
865 if (list_empty(&ep->queue))
868 req = list_first_entry(&ep->queue, struct ast_udc_request, queue);
870 len = EP_DMA_GET_TX_SIZE(ast_ep_read(ep, AST_UDC_EP_DMA_STS));
871 req->req.actual += len;
873 EP_DBG(ep, "req @%p, length:(%d/%d), %s:0x%x\n", req,
874 req->req.actual, req->req.length, "len", len);
876 /* Done this request */
877 if (req->req.length == req->req.actual) {
878 ast_udc_done(ep, req, 0);
879 req = list_first_entry_or_null(&ep->queue,
880 struct ast_udc_request,
884 /* Check for short packet */
885 if (len < ep->ep.maxpacket) {
886 ast_udc_done(ep, req, 0);
887 req = list_first_entry_or_null(&ep->queue,
888 struct ast_udc_request,
895 ast_udc_epn_kick(ep, req);
898 static void ast_udc_epn_handle_desc(struct ast_udc_dev *udc, u16 ep_num)
900 struct ast_udc_ep *ep = &udc->ep[ep_num];
901 struct device *dev = &udc->pdev->dev;
902 struct ast_udc_request *req;
903 u32 proc_sts, wr_ptr, rd_ptr;
904 u32 len_in_desc, ctrl;
908 if (list_empty(&ep->queue)) {
909 dev_warn(dev, "%s request queue empty!\n", ep->ep.name);
913 req = list_first_entry(&ep->queue, struct ast_udc_request, queue);
915 ctrl = ast_ep_read(ep, AST_UDC_EP_DMA_CTRL);
916 proc_sts = EP_DMA_CTRL_GET_PROC_STS(ctrl);
918 /* Check processing status is idle */
919 if (proc_sts != EP_DMA_CTRL_STS_RX_IDLE &&
920 proc_sts != EP_DMA_CTRL_STS_TX_IDLE) {
921 dev_warn(dev, "EP DMA CTRL: 0x%x, PS:0x%x\n",
922 ast_ep_read(ep, AST_UDC_EP_DMA_CTRL),
927 ctrl = ast_ep_read(ep, AST_UDC_EP_DMA_STS);
928 rd_ptr = EP_DMA_GET_RPTR(ctrl);
929 wr_ptr = EP_DMA_GET_WPTR(ctrl);
931 if (rd_ptr != wr_ptr) {
932 dev_warn(dev, "desc list is not empty ! %s:%d, %s:%d\n",
933 "rptr", rd_ptr, "wptr", wr_ptr);
937 EP_DBG(ep, "rd_ptr:%d, wr_ptr:%d\n", rd_ptr, wr_ptr);
938 i = req->saved_dma_wptr;
941 len_in_desc = EP_DESC1_IN_LEN(ep->descs[i].des_1);
942 EP_DBG(ep, "desc[%d] len: %d\n", i, len_in_desc);
943 total_len += len_in_desc;
945 if (i >= AST_UDC_DESCS_COUNT)
948 } while (i != wr_ptr);
950 req->req.actual += total_len;
952 EP_DBG(ep, "req @%p, length:(%d/%d), %s:0x%x\n", req,
953 req->req.actual, req->req.length, "len", total_len);
955 /* Done this request */
956 if (req->req.length == req->req.actual) {
957 ast_udc_done(ep, req, 0);
958 req = list_first_entry_or_null(&ep->queue,
959 struct ast_udc_request,
963 /* Check for short packet */
964 if (total_len < ep->ep.maxpacket) {
965 ast_udc_done(ep, req, 0);
966 req = list_first_entry_or_null(&ep->queue,
967 struct ast_udc_request,
972 /* More requests & dma descs not setup yet */
973 if (req && (req->actual_dma_length == req->req.actual)) {
974 EP_DBG(ep, "More requests\n");
975 ast_udc_epn_kick_desc(ep, req);
979 static void ast_udc_ep0_data_tx(struct ast_udc_dev *udc, u8 *tx_data, u32 len)
982 memcpy(udc->ep0_buf, tx_data, len);
984 ast_udc_write(udc, udc->ep0_buf_dma, AST_UDC_EP0_DATA_BUFF);
985 ast_udc_write(udc, EP0_TX_LEN(len), AST_UDC_EP0_CTRL);
986 ast_udc_write(udc, EP0_TX_LEN(len) | EP0_TX_BUFF_RDY,
988 udc->is_control_tx = 1;
991 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL);
994 static void ast_udc_getstatus(struct ast_udc_dev *udc)
996 struct usb_ctrlrequest crq;
997 struct ast_udc_ep *ep;
1001 memcpy_fromio(&crq, udc->creq, sizeof(crq));
1003 switch (crq.bRequestType & USB_RECIP_MASK) {
1004 case USB_RECIP_DEVICE:
1005 /* Get device status */
1006 status = 1 << USB_DEVICE_SELF_POWERED;
1008 case USB_RECIP_INTERFACE:
1010 case USB_RECIP_ENDPOINT:
1011 epnum = crq.wIndex & USB_ENDPOINT_NUMBER_MASK;
1012 status = udc->ep[epnum].stopped;
1018 ep = &udc->ep[epnum];
1019 EP_DBG(ep, "status: 0x%x\n", status);
1020 ast_udc_ep0_data_tx(udc, (u8 *)&status, sizeof(status));
1025 EP_DBG(ep, "Can't respond request\n");
1026 ast_udc_write(udc, ast_udc_read(udc, AST_UDC_EP0_CTRL) | EP0_STALL,
1030 static void ast_udc_ep0_handle_setup(struct ast_udc_dev *udc)
1032 struct ast_udc_ep *ep = &udc->ep[0];
1033 struct ast_udc_request *req;
1034 struct usb_ctrlrequest crq;
1039 memcpy_fromio(&crq, udc->creq, sizeof(crq));
1041 SETUP_DBG(udc, "SETUP packet: %02x/%02x/%04x/%04x/%04x\n",
1042 crq.bRequestType, crq.bRequest, le16_to_cpu(crq.wValue),
1043 le16_to_cpu(crq.wIndex), le16_to_cpu(crq.wLength));
1046 * Cleanup ep0 request(s) in queue because
1047 * there is a new control setup comes.
1049 list_for_each_entry(req, &udc->ep[0].queue, queue) {
1051 EP_DBG(ep, "there is req %p in ep0 queue !\n", req);
1055 ast_udc_nuke(&udc->ep[0], -ETIMEDOUT);
1057 udc->ep[0].dir_in = crq.bRequestType & USB_DIR_IN;
1059 if ((crq.bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1060 switch (crq.bRequest) {
1061 case USB_REQ_SET_ADDRESS:
1062 if (ast_udc_read(udc, AST_UDC_STS) & UDC_STS_HIGHSPEED)
1063 udc->gadget.speed = USB_SPEED_HIGH;
1065 udc->gadget.speed = USB_SPEED_FULL;
1067 SETUP_DBG(udc, "set addr: 0x%x\n", crq.wValue);
1068 reg = ast_udc_read(udc, AST_UDC_CONFIG);
1069 reg &= ~UDC_CFG_ADDR_MASK;
1070 reg |= UDC_CFG_SET_ADDR(crq.wValue);
1071 ast_udc_write(udc, reg, AST_UDC_CONFIG);
1074 case USB_REQ_CLEAR_FEATURE:
1075 SETUP_DBG(udc, "ep0: CLEAR FEATURE\n");
1078 case USB_REQ_SET_FEATURE:
1079 SETUP_DBG(udc, "ep0: SET FEATURE\n");
1082 case USB_REQ_GET_STATUS:
1083 ast_udc_getstatus(udc);
1094 SETUP_DBG(udc, "Forwarding %s to gadget...\n",
1097 spin_unlock(&udc->lock);
1098 rc = udc->driver->setup(&udc->gadget, &crq);
1099 spin_lock(&udc->lock);
1102 SETUP_DBG(udc, "No gadget for request !\n");
1108 /* Stall if gadget failed */
1109 SETUP_DBG(udc, "Stalling, rc:0x%x\n", rc);
1110 ast_udc_write(udc, ast_udc_read(udc, AST_UDC_EP0_CTRL) | EP0_STALL,
1115 SETUP_DBG(udc, "ep0: Sending IN status without data\n");
1116 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL);
1119 static irqreturn_t ast_udc_isr(int irq, void *data)
1121 struct ast_udc_dev *udc = (struct ast_udc_dev *)data;
1122 struct ast_udc_ep *ep;
1126 spin_lock(&udc->lock);
1128 isr = ast_udc_read(udc, AST_UDC_ISR);
1132 /* Ack interrupts */
1133 ast_udc_write(udc, isr, AST_UDC_ISR);
1135 if (isr & UDC_IRQ_BUS_RESET) {
1136 ISR_DBG(udc, "UDC_IRQ_BUS_RESET\n");
1137 udc->gadget.speed = USB_SPEED_UNKNOWN;
1140 EP_DBG(ep, "dctrl:0x%x\n",
1141 ast_ep_read(ep, AST_UDC_EP_DMA_CTRL));
1143 if (udc->driver && udc->driver->reset) {
1144 spin_unlock(&udc->lock);
1145 udc->driver->reset(&udc->gadget);
1146 spin_lock(&udc->lock);
1150 if (isr & UDC_IRQ_BUS_SUSPEND) {
1151 ISR_DBG(udc, "UDC_IRQ_BUS_SUSPEND\n");
1152 udc->suspended_from = udc->gadget.state;
1153 usb_gadget_set_state(&udc->gadget, USB_STATE_SUSPENDED);
1155 if (udc->driver && udc->driver->suspend) {
1156 spin_unlock(&udc->lock);
1157 udc->driver->suspend(&udc->gadget);
1158 spin_lock(&udc->lock);
1162 if (isr & UDC_IRQ_BUS_RESUME) {
1163 ISR_DBG(udc, "UDC_IRQ_BUS_RESUME\n");
1164 usb_gadget_set_state(&udc->gadget, udc->suspended_from);
1166 if (udc->driver && udc->driver->resume) {
1167 spin_unlock(&udc->lock);
1168 udc->driver->resume(&udc->gadget);
1169 spin_lock(&udc->lock);
1173 if (isr & UDC_IRQ_EP0_IN_ACK_STALL) {
1174 ISR_DBG(udc, "UDC_IRQ_EP0_IN_ACK_STALL\n");
1175 ast_udc_ep0_in(udc);
1178 if (isr & UDC_IRQ_EP0_OUT_ACK_STALL) {
1179 ISR_DBG(udc, "UDC_IRQ_EP0_OUT_ACK_STALL\n");
1180 ast_udc_ep0_out(udc);
1183 if (isr & UDC_IRQ_EP0_SETUP) {
1184 ISR_DBG(udc, "UDC_IRQ_EP0_SETUP\n");
1185 ast_udc_ep0_handle_setup(udc);
1188 if (isr & UDC_IRQ_EP_POOL_ACK_STALL) {
1189 ISR_DBG(udc, "UDC_IRQ_EP_POOL_ACK_STALL\n");
1190 ep_isr = ast_udc_read(udc, AST_UDC_EP_ACK_ISR);
1192 /* Ack EP interrupts */
1193 ast_udc_write(udc, ep_isr, AST_UDC_EP_ACK_ISR);
1195 /* Handle each EP */
1196 for (i = 0; i < AST_UDC_NUM_ENDPOINTS - 1; i++) {
1197 if (ep_isr & (0x1 << i)) {
1198 ep = &udc->ep[i + 1];
1200 ast_udc_epn_handle_desc(udc, i + 1);
1202 ast_udc_epn_handle(udc, i + 1);
1208 spin_unlock(&udc->lock);
1212 static int ast_udc_gadget_getframe(struct usb_gadget *gadget)
1214 struct ast_udc_dev *udc = to_ast_dev(gadget);
1216 return (ast_udc_read(udc, AST_UDC_STS) >> 16) & 0x7ff;
1219 static void ast_udc_wake_work(struct work_struct *work)
1221 struct ast_udc_dev *udc = container_of(work, struct ast_udc_dev,
1223 unsigned long flags;
1226 spin_lock_irqsave(&udc->lock, flags);
1228 UDC_DBG(udc, "Wakeup Host !\n");
1229 ctrl = ast_udc_read(udc, AST_UDC_FUNC_CTRL);
1230 ast_udc_write(udc, ctrl | USB_REMOTE_WAKEUP_EN, AST_UDC_FUNC_CTRL);
1232 spin_unlock_irqrestore(&udc->lock, flags);
1235 static void ast_udc_wakeup_all(struct ast_udc_dev *udc)
1238 * A device is trying to wake the world, because this
1239 * can recurse into the device, we break the call chain
1240 * using a work queue
1242 schedule_work(&udc->wake_work);
1245 static int ast_udc_wakeup(struct usb_gadget *gadget)
1247 struct ast_udc_dev *udc = to_ast_dev(gadget);
1248 unsigned long flags;
1251 spin_lock_irqsave(&udc->lock, flags);
1253 if (!udc->wakeup_en) {
1254 UDC_DBG(udc, "Remote Wakeup is disabled\n");
1259 UDC_DBG(udc, "Device initiated wakeup\n");
1260 ast_udc_wakeup_all(udc);
1263 spin_unlock_irqrestore(&udc->lock, flags);
1268 * Activate/Deactivate link with host
1270 static int ast_udc_pullup(struct usb_gadget *gadget, int is_on)
1272 struct ast_udc_dev *udc = to_ast_dev(gadget);
1273 unsigned long flags;
1276 spin_lock_irqsave(&udc->lock, flags);
1278 UDC_DBG(udc, "is_on: %d\n", is_on);
1280 ctrl = ast_udc_read(udc, AST_UDC_FUNC_CTRL) | USB_UPSTREAM_EN;
1282 ctrl = ast_udc_read(udc, AST_UDC_FUNC_CTRL) & ~USB_UPSTREAM_EN;
1284 ast_udc_write(udc, ctrl, AST_UDC_FUNC_CTRL);
1286 spin_unlock_irqrestore(&udc->lock, flags);
1291 static int ast_udc_start(struct usb_gadget *gadget,
1292 struct usb_gadget_driver *driver)
1294 struct ast_udc_dev *udc = to_ast_dev(gadget);
1295 struct ast_udc_ep *ep;
1296 unsigned long flags;
1299 spin_lock_irqsave(&udc->lock, flags);
1302 udc->driver = driver;
1303 udc->gadget.dev.of_node = udc->pdev->dev.of_node;
1305 for (i = 0; i < AST_UDC_NUM_ENDPOINTS; i++) {
1310 spin_unlock_irqrestore(&udc->lock, flags);
1315 static int ast_udc_stop(struct usb_gadget *gadget)
1317 struct ast_udc_dev *udc = to_ast_dev(gadget);
1318 unsigned long flags;
1321 spin_lock_irqsave(&udc->lock, flags);
1324 ctrl = ast_udc_read(udc, AST_UDC_FUNC_CTRL) & ~USB_UPSTREAM_EN;
1325 ast_udc_write(udc, ctrl, AST_UDC_FUNC_CTRL);
1327 udc->gadget.speed = USB_SPEED_UNKNOWN;
1330 ast_udc_stop_activity(udc);
1331 usb_gadget_set_state(&udc->gadget, USB_STATE_NOTATTACHED);
1333 spin_unlock_irqrestore(&udc->lock, flags);
1338 static const struct usb_gadget_ops ast_udc_ops = {
1339 .get_frame = ast_udc_gadget_getframe,
1340 .wakeup = ast_udc_wakeup,
1341 .pullup = ast_udc_pullup,
1342 .udc_start = ast_udc_start,
1343 .udc_stop = ast_udc_stop,
1347 * Support 1 Control Endpoint.
1348 * Support multiple programmable endpoints that can be configured to
1349 * Bulk IN/OUT, Interrupt IN/OUT, and Isochronous IN/OUT type endpoint.
1351 static void ast_udc_init_ep(struct ast_udc_dev *udc)
1353 struct ast_udc_ep *ep;
1356 for (i = 0; i < AST_UDC_NUM_ENDPOINTS; i++) {
1358 ep->ep.name = ast_ep_name[i];
1360 ep->ep.caps.type_control = true;
1362 ep->ep.caps.type_iso = true;
1363 ep->ep.caps.type_bulk = true;
1364 ep->ep.caps.type_int = true;
1366 ep->ep.caps.dir_in = true;
1367 ep->ep.caps.dir_out = true;
1369 ep->ep.ops = &ast_udc_ep_ops;
1372 INIT_LIST_HEAD(&ep->queue);
1375 usb_ep_set_maxpacket_limit(&ep->ep,
1376 AST_UDC_EP0_MAX_PACKET);
1380 ep->ep_reg = udc->reg + AST_UDC_EP_BASE +
1381 (AST_UDC_EP_OFFSET * (i - 1));
1383 ep->epn_buf = udc->ep0_buf + (i * AST_UDC_EP_DMA_SIZE);
1384 ep->epn_buf_dma = udc->ep0_buf_dma + (i * AST_UDC_EP_DMA_SIZE);
1385 usb_ep_set_maxpacket_limit(&ep->ep, AST_UDC_EPn_MAX_PACKET);
1387 ep->descs = ep->epn_buf + AST_UDC_EPn_MAX_PACKET;
1388 ep->descs_dma = ep->epn_buf_dma + AST_UDC_EPn_MAX_PACKET;
1391 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1395 static void ast_udc_init_dev(struct ast_udc_dev *udc)
1397 INIT_WORK(&udc->wake_work, ast_udc_wake_work);
1400 static void ast_udc_init_hw(struct ast_udc_dev *udc)
1405 ctrl = USB_PHY_CLK_EN | USB_PHY_RESET_DIS;
1406 ast_udc_write(udc, ctrl, AST_UDC_FUNC_CTRL);
1409 ast_udc_write(udc, 0, AST_UDC_DEV_RESET);
1411 /* Set descriptor ring size */
1412 if (AST_UDC_DESCS_COUNT == 256) {
1413 ctrl |= USB_EP_LONG_DESC;
1414 ast_udc_write(udc, ctrl, AST_UDC_FUNC_CTRL);
1417 /* Mask & ack all interrupts before installing the handler */
1418 ast_udc_write(udc, 0, AST_UDC_IER);
1419 ast_udc_write(udc, UDC_IRQ_ACK_ALL, AST_UDC_ISR);
1421 /* Enable some interrupts */
1422 ctrl = UDC_IRQ_EP_POOL_ACK_STALL | UDC_IRQ_BUS_RESUME |
1423 UDC_IRQ_BUS_SUSPEND | UDC_IRQ_BUS_RESET |
1424 UDC_IRQ_EP0_IN_ACK_STALL | UDC_IRQ_EP0_OUT_ACK_STALL |
1426 ast_udc_write(udc, ctrl, AST_UDC_IER);
1428 /* Cleanup and enable ep ACK interrupts */
1429 ast_udc_write(udc, UDC_IRQ_EP_ACK_ALL, AST_UDC_EP_ACK_IER);
1430 ast_udc_write(udc, UDC_IRQ_EP_ACK_ALL, AST_UDC_EP_ACK_ISR);
1432 ast_udc_write(udc, 0, AST_UDC_EP0_CTRL);
1435 static void ast_udc_remove(struct platform_device *pdev)
1437 struct ast_udc_dev *udc = platform_get_drvdata(pdev);
1438 unsigned long flags;
1441 usb_del_gadget_udc(&udc->gadget);
1444 * This is broken as only some cleanup is skipped, *udev is
1445 * freed and the register mapping goes away. Any further usage
1446 * probably crashes. Also the device is unbound, so the skipped
1447 * cleanup is never catched up later.
1449 dev_alert(&pdev->dev,
1450 "Driver is busy and still going away. Fasten your seat belts!\n");
1454 spin_lock_irqsave(&udc->lock, flags);
1456 /* Disable upstream port connection */
1457 ctrl = ast_udc_read(udc, AST_UDC_FUNC_CTRL) & ~USB_UPSTREAM_EN;
1458 ast_udc_write(udc, ctrl, AST_UDC_FUNC_CTRL);
1460 clk_disable_unprepare(udc->clk);
1462 spin_unlock_irqrestore(&udc->lock, flags);
1465 dma_free_coherent(&pdev->dev,
1466 AST_UDC_EP_DMA_SIZE * AST_UDC_NUM_ENDPOINTS,
1470 udc->ep0_buf = NULL;
1473 static int ast_udc_probe(struct platform_device *pdev)
1475 enum usb_device_speed max_speed;
1476 struct device *dev = &pdev->dev;
1477 struct ast_udc_dev *udc;
1480 udc = devm_kzalloc(&pdev->dev, sizeof(struct ast_udc_dev), GFP_KERNEL);
1484 udc->gadget.dev.parent = dev;
1486 spin_lock_init(&udc->lock);
1488 udc->gadget.ops = &ast_udc_ops;
1489 udc->gadget.ep0 = &udc->ep[0].ep;
1490 udc->gadget.name = "aspeed-udc";
1491 udc->gadget.dev.init_name = "gadget";
1493 udc->reg = devm_platform_ioremap_resource(pdev, 0);
1494 if (IS_ERR(udc->reg)) {
1495 dev_err(&pdev->dev, "Failed to map resources\n");
1496 return PTR_ERR(udc->reg);
1499 platform_set_drvdata(pdev, udc);
1501 udc->clk = devm_clk_get(&pdev->dev, NULL);
1502 if (IS_ERR(udc->clk)) {
1503 rc = PTR_ERR(udc->clk);
1506 rc = clk_prepare_enable(udc->clk);
1508 dev_err(&pdev->dev, "Failed to enable clock (0x%x)\n", rc);
1512 /* Check if we need to limit the HW to USB1 */
1513 max_speed = usb_get_maximum_speed(&pdev->dev);
1514 if (max_speed != USB_SPEED_UNKNOWN && max_speed < USB_SPEED_HIGH)
1515 udc->force_usb1 = true;
1518 * Allocate DMA buffers for all EPs in one chunk
1520 udc->ep0_buf = dma_alloc_coherent(&pdev->dev,
1521 AST_UDC_EP_DMA_SIZE *
1522 AST_UDC_NUM_ENDPOINTS,
1523 &udc->ep0_buf_dma, GFP_KERNEL);
1525 udc->gadget.speed = USB_SPEED_UNKNOWN;
1526 udc->gadget.max_speed = USB_SPEED_HIGH;
1527 udc->creq = udc->reg + AST_UDC_SETUP0;
1530 * Support single stage mode or 32/256 stages descriptor mode.
1531 * Set default as Descriptor Mode.
1533 udc->desc_mode = AST_UDC_DESC_MODE;
1535 dev_info(&pdev->dev, "DMA %s\n", udc->desc_mode ?
1536 "descriptor mode" : "single mode");
1538 INIT_LIST_HEAD(&udc->gadget.ep_list);
1539 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1541 /* Initialized udc ep */
1542 ast_udc_init_ep(udc);
1544 /* Initialized udc device */
1545 ast_udc_init_dev(udc);
1547 /* Initialized udc hardware */
1548 ast_udc_init_hw(udc);
1550 /* Find interrupt and install handler */
1551 udc->irq = platform_get_irq(pdev, 0);
1557 rc = devm_request_irq(&pdev->dev, udc->irq, ast_udc_isr, 0,
1558 KBUILD_MODNAME, udc);
1560 dev_err(&pdev->dev, "Failed to request interrupt\n");
1564 rc = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
1566 dev_err(&pdev->dev, "Failed to add gadget udc\n");
1570 dev_info(&pdev->dev, "Initialized udc in USB%s mode\n",
1571 udc->force_usb1 ? "1" : "2");
1576 dev_err(&pdev->dev, "Failed to udc probe, rc:0x%x\n", rc);
1577 ast_udc_remove(pdev);
1582 static const struct of_device_id ast_udc_of_dt_ids[] = {
1583 { .compatible = "aspeed,ast2600-udc", },
1587 MODULE_DEVICE_TABLE(of, ast_udc_of_dt_ids);
1589 static struct platform_driver ast_udc_driver = {
1590 .probe = ast_udc_probe,
1591 .remove_new = ast_udc_remove,
1593 .name = KBUILD_MODNAME,
1594 .of_match_table = ast_udc_of_dt_ids,
1598 module_platform_driver(ast_udc_driver);
1600 MODULE_DESCRIPTION("ASPEED UDC driver");
1601 MODULE_AUTHOR("Neal Liu <neal_liu@aspeedtech.com>");
1602 MODULE_LICENSE("GPL");