1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8 *index)
153 if (*index == (DWC3_TRB_NUM - 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
178 struct dwc3 *dwc = dep->dwc;
180 list_del(&req->list);
182 req->needs_extra_trb = false;
185 if (req->request.status == -EINPROGRESS)
186 req->request.status = status;
189 usb_gadget_unmap_request_by_dev(dwc->sysdev,
190 &req->request, req->direction);
193 trace_dwc3_gadget_giveback(req);
196 pm_runtime_put(dwc->dev);
200 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
201 * @dep: The endpoint to whom the request belongs to
202 * @req: The request we're giving back
203 * @status: completion code for the request
205 * Must be called with controller's lock held and interrupts disabled. This
206 * function will unmap @req and call its ->complete() callback to notify upper
207 * layers that it has completed.
209 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
212 struct dwc3 *dwc = dep->dwc;
214 dwc3_gadget_del_and_unmap_request(dep, req, status);
215 req->status = DWC3_REQUEST_STATUS_COMPLETED;
217 spin_unlock(&dwc->lock);
218 usb_gadget_giveback_request(&dep->endpoint, &req->request);
219 spin_lock(&dwc->lock);
223 * dwc3_send_gadget_generic_command - issue a generic command for the controller
224 * @dwc: pointer to the controller context
225 * @cmd: the command to be issued
226 * @param: command parameter
228 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
229 * and wait for its completion.
231 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
239 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
240 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
243 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
244 if (!(reg & DWC3_DGCMD_CMDACT)) {
245 status = DWC3_DGCMD_STATUS(reg);
257 trace_dwc3_gadget_generic_cmd(cmd, param, status);
262 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
265 * dwc3_send_gadget_ep_cmd - issue an endpoint command
266 * @dep: the endpoint to which the command is going to be issued
267 * @cmd: the command to be issued
268 * @params: parameters to the command
270 * Caller should handle locking. This function will issue @cmd with given
271 * @params to @dep and wait for its completion.
273 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
274 struct dwc3_gadget_ep_cmd_params *params)
276 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
277 struct dwc3 *dwc = dep->dwc;
279 u32 saved_config = 0;
286 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
287 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
290 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
291 * settings. Restore them after the command is completed.
293 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
295 if (dwc->gadget->speed <= USB_SPEED_HIGH ||
296 DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
297 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
298 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
299 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
300 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
303 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
304 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
305 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
309 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
312 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
316 * Initiate remote wakeup if the link state is in U3 when
317 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
318 * link state is in U1/U2, no remote wakeup is needed. The Start
319 * Transfer command will initiate the link recovery.
321 link_state = dwc3_gadget_get_link_state(dwc);
322 switch (link_state) {
323 case DWC3_LINK_STATE_U2:
324 if (dwc->gadget->speed >= USB_SPEED_SUPER)
328 case DWC3_LINK_STATE_U3:
329 ret = __dwc3_gadget_wakeup(dwc);
330 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
336 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
337 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
338 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
341 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
342 * not relying on XferNotReady, we can make use of a special "No
343 * Response Update Transfer" command where we should clear both CmdAct
346 * With this, we don't need to wait for command completion and can
347 * straight away issue further commands to the endpoint.
349 * NOTICE: We're making an assumption that control endpoints will never
350 * make use of Update Transfer command. This is a safe assumption
351 * because we can never have more than one request at a time with
352 * Control Endpoints. If anybody changes that assumption, this chunk
353 * needs to be updated accordingly.
355 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
356 !usb_endpoint_xfer_isoc(desc))
357 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
359 cmd |= DWC3_DEPCMD_CMDACT;
361 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
363 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
364 if (!(reg & DWC3_DEPCMD_CMDACT)) {
365 cmd_status = DWC3_DEPCMD_STATUS(reg);
367 switch (cmd_status) {
371 case DEPEVT_TRANSFER_NO_RESOURCE:
372 dev_WARN(dwc->dev, "No resource for %s\n",
376 case DEPEVT_TRANSFER_BUS_EXPIRY:
378 * SW issues START TRANSFER command to
379 * isochronous ep with future frame interval. If
380 * future interval time has already passed when
381 * core receives the command, it will respond
382 * with an error status of 'Bus Expiry'.
384 * Instead of always returning -EINVAL, let's
385 * give a hint to the gadget driver that this is
386 * the case by returning -EAGAIN.
391 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
400 cmd_status = -ETIMEDOUT;
403 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
405 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
407 dep->flags |= DWC3_EP_TRANSFER_STARTED;
409 if (ret != -ETIMEDOUT)
410 dwc3_gadget_ep_get_transfer_index(dep);
414 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
416 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
422 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
424 struct dwc3 *dwc = dep->dwc;
425 struct dwc3_gadget_ep_cmd_params params;
426 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
429 * As of core revision 2.60a the recommended programming model
430 * is to set the ClearPendIN bit when issuing a Clear Stall EP
431 * command for IN endpoints. This is to prevent an issue where
432 * some (non-compliant) hosts may not send ACK TPs for pending
433 * IN transfers due to a mishandled error condition. Synopsys
436 if (dep->direction &&
437 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
438 (dwc->gadget->speed >= USB_SPEED_SUPER))
439 cmd |= DWC3_DEPCMD_CLEARPENDIN;
441 memset(¶ms, 0, sizeof(params));
443 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
446 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
447 struct dwc3_trb *trb)
449 u32 offset = (char *) trb - (char *) dep->trb_pool;
451 return dep->trb_pool_dma + offset;
454 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
456 struct dwc3 *dwc = dep->dwc;
461 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
462 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
463 &dep->trb_pool_dma, GFP_KERNEL);
464 if (!dep->trb_pool) {
465 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
473 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
475 struct dwc3 *dwc = dep->dwc;
477 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
478 dep->trb_pool, dep->trb_pool_dma);
480 dep->trb_pool = NULL;
481 dep->trb_pool_dma = 0;
484 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
486 struct dwc3_gadget_ep_cmd_params params;
488 memset(¶ms, 0x00, sizeof(params));
490 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
492 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
497 * dwc3_gadget_start_config - configure ep resources
498 * @dep: endpoint that is being enabled
500 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
501 * completion, it will set Transfer Resource for all available endpoints.
503 * The assignment of transfer resources cannot perfectly follow the data book
504 * due to the fact that the controller driver does not have all knowledge of the
505 * configuration in advance. It is given this information piecemeal by the
506 * composite gadget framework after every SET_CONFIGURATION and
507 * SET_INTERFACE. Trying to follow the databook programming model in this
508 * scenario can cause errors. For two reasons:
510 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
511 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
512 * incorrect in the scenario of multiple interfaces.
514 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
515 * endpoint on alt setting (8.1.6).
517 * The following simplified method is used instead:
519 * All hardware endpoints can be assigned a transfer resource and this setting
520 * will stay persistent until either a core reset or hibernation. So whenever we
521 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
522 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
523 * guaranteed that there are as many transfer resources as endpoints.
525 * This function is called for each endpoint when it is being enabled but is
526 * triggered only when called for EP0-out, which always happens first, and which
527 * should only happen in one of the above conditions.
529 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
531 struct dwc3_gadget_ep_cmd_params params;
540 memset(¶ms, 0x00, sizeof(params));
541 cmd = DWC3_DEPCMD_DEPSTARTCFG;
544 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
548 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
549 struct dwc3_ep *dep = dwc->eps[i];
554 ret = dwc3_gadget_set_xfer_resource(dep);
562 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
564 const struct usb_ss_ep_comp_descriptor *comp_desc;
565 const struct usb_endpoint_descriptor *desc;
566 struct dwc3_gadget_ep_cmd_params params;
567 struct dwc3 *dwc = dep->dwc;
569 comp_desc = dep->endpoint.comp_desc;
570 desc = dep->endpoint.desc;
572 memset(¶ms, 0x00, sizeof(params));
574 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
575 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
577 /* Burst size is only needed in SuperSpeed mode */
578 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
579 u32 burst = dep->endpoint.maxburst;
581 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
584 params.param0 |= action;
585 if (action == DWC3_DEPCFG_ACTION_RESTORE)
586 params.param2 |= dep->saved_state;
588 if (usb_endpoint_xfer_control(desc))
589 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
591 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
592 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
594 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
595 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
596 | DWC3_DEPCFG_XFER_COMPLETE_EN
597 | DWC3_DEPCFG_STREAM_EVENT_EN;
598 dep->stream_capable = true;
601 if (!usb_endpoint_xfer_control(desc))
602 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
605 * We are doing 1:1 mapping for endpoints, meaning
606 * Physical Endpoints 2 maps to Logical Endpoint 2 and
607 * so on. We consider the direction bit as part of the physical
608 * endpoint number. So USB endpoint 0x81 is 0x03.
610 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
613 * We must use the lower 16 TX FIFOs even though
617 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
619 if (desc->bInterval) {
623 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
625 * NOTE: The programming guide incorrectly stated bInterval_m1
626 * must be set to 0 when operating in fullspeed. Internally the
627 * controller does not have this limitation. See DWC_usb3x
628 * programming guide section 3.2.2.1.
630 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
632 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
633 dwc->gadget->speed == USB_SPEED_FULL)
634 dep->interval = desc->bInterval;
636 dep->interval = 1 << (desc->bInterval - 1);
638 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
641 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
644 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
648 * __dwc3_gadget_ep_enable - initializes a hw endpoint
649 * @dep: endpoint to be initialized
650 * @action: one of INIT, MODIFY or RESTORE
652 * Caller should take care of locking. Execute all necessary commands to
653 * initialize a HW endpoint so it can be used by a gadget driver.
655 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
657 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
658 struct dwc3 *dwc = dep->dwc;
663 if (!(dep->flags & DWC3_EP_ENABLED)) {
664 ret = dwc3_gadget_start_config(dep);
669 ret = dwc3_gadget_set_ep_config(dep, action);
673 if (!(dep->flags & DWC3_EP_ENABLED)) {
674 struct dwc3_trb *trb_st_hw;
675 struct dwc3_trb *trb_link;
677 dep->type = usb_endpoint_type(desc);
678 dep->flags |= DWC3_EP_ENABLED;
680 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
681 reg |= DWC3_DALEPENA_EP(dep->number);
682 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
684 if (usb_endpoint_xfer_control(desc))
687 /* Initialize the TRB ring */
688 dep->trb_dequeue = 0;
689 dep->trb_enqueue = 0;
690 memset(dep->trb_pool, 0,
691 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
693 /* Link TRB. The HWO bit is never reset */
694 trb_st_hw = &dep->trb_pool[0];
696 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
697 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
698 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
699 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
700 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
704 * Issue StartTransfer here with no-op TRB so we can always rely on No
705 * Response Update Transfer command.
707 if (usb_endpoint_xfer_bulk(desc) ||
708 usb_endpoint_xfer_int(desc)) {
709 struct dwc3_gadget_ep_cmd_params params;
710 struct dwc3_trb *trb;
714 memset(¶ms, 0, sizeof(params));
715 trb = &dep->trb_pool[0];
716 trb_dma = dwc3_trb_dma_offset(dep, trb);
718 params.param0 = upper_32_bits(trb_dma);
719 params.param1 = lower_32_bits(trb_dma);
721 cmd = DWC3_DEPCMD_STARTTRANSFER;
723 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
727 if (dep->stream_capable) {
729 * For streams, at start, there maybe a race where the
730 * host primes the endpoint before the function driver
731 * queues a request to initiate a stream. In that case,
732 * the controller will not see the prime to generate the
733 * ERDY and start stream. To workaround this, issue a
734 * no-op TRB as normal, but end it immediately. As a
735 * result, when the function driver queues the request,
736 * the next START_TRANSFER command will cause the
737 * controller to generate an ERDY to initiate the
740 dwc3_stop_active_transfer(dep, true, true);
743 * All stream eps will reinitiate stream on NoStream
744 * rejection until we can determine that the host can
745 * prime after the first transfer.
747 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
752 trace_dwc3_gadget_ep_enable(dep);
757 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
759 struct dwc3_request *req;
761 dwc3_stop_active_transfer(dep, true, false);
763 /* - giveback all requests to gadget driver */
764 while (!list_empty(&dep->started_list)) {
765 req = next_request(&dep->started_list);
767 dwc3_gadget_giveback(dep, req, status);
770 while (!list_empty(&dep->pending_list)) {
771 req = next_request(&dep->pending_list);
773 dwc3_gadget_giveback(dep, req, status);
776 while (!list_empty(&dep->cancelled_list)) {
777 req = next_request(&dep->cancelled_list);
779 dwc3_gadget_giveback(dep, req, status);
784 * __dwc3_gadget_ep_disable - disables a hw endpoint
785 * @dep: the endpoint to disable
787 * This function undoes what __dwc3_gadget_ep_enable did and also removes
788 * requests which are currently being processed by the hardware and those which
789 * are not yet scheduled.
791 * Caller should take care of locking.
793 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
795 struct dwc3 *dwc = dep->dwc;
798 trace_dwc3_gadget_ep_disable(dep);
800 /* make sure HW endpoint isn't stalled */
801 if (dep->flags & DWC3_EP_STALL)
802 __dwc3_gadget_ep_set_halt(dep, 0, false);
804 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
805 reg &= ~DWC3_DALEPENA_EP(dep->number);
806 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
808 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
810 dep->stream_capable = false;
814 /* Clear out the ep descriptors for non-ep0 */
815 if (dep->number > 1) {
816 dep->endpoint.comp_desc = NULL;
817 dep->endpoint.desc = NULL;
823 /* -------------------------------------------------------------------------- */
825 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
826 const struct usb_endpoint_descriptor *desc)
831 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
836 /* -------------------------------------------------------------------------- */
838 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
839 const struct usb_endpoint_descriptor *desc)
846 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
847 pr_debug("dwc3: invalid parameters\n");
851 if (!desc->wMaxPacketSize) {
852 pr_debug("dwc3: missing wMaxPacketSize\n");
856 dep = to_dwc3_ep(ep);
859 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
860 "%s is already enabled\n",
864 spin_lock_irqsave(&dwc->lock, flags);
865 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
866 spin_unlock_irqrestore(&dwc->lock, flags);
871 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
879 pr_debug("dwc3: invalid parameters\n");
883 dep = to_dwc3_ep(ep);
886 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
887 "%s is already disabled\n",
891 spin_lock_irqsave(&dwc->lock, flags);
892 ret = __dwc3_gadget_ep_disable(dep);
893 spin_unlock_irqrestore(&dwc->lock, flags);
898 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
901 struct dwc3_request *req;
902 struct dwc3_ep *dep = to_dwc3_ep(ep);
904 req = kzalloc(sizeof(*req), gfp_flags);
908 req->direction = dep->direction;
909 req->epnum = dep->number;
911 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
913 trace_dwc3_alloc_request(req);
915 return &req->request;
918 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
919 struct usb_request *request)
921 struct dwc3_request *req = to_dwc3_request(request);
923 trace_dwc3_free_request(req);
928 * dwc3_ep_prev_trb - returns the previous TRB in the ring
929 * @dep: The endpoint with the TRB ring
930 * @index: The index of the current TRB in the ring
932 * Returns the TRB prior to the one pointed to by the index. If the
933 * index is 0, we will wrap backwards, skip the link TRB, and return
934 * the one just before that.
936 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
941 tmp = DWC3_TRB_NUM - 1;
943 return &dep->trb_pool[tmp - 1];
946 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
951 * If the enqueue & dequeue are equal then the TRB ring is either full
952 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
953 * pending to be processed by the driver.
955 if (dep->trb_enqueue == dep->trb_dequeue) {
957 * If there is any request remained in the started_list at
958 * this point, that means there is no TRB available.
960 if (!list_empty(&dep->started_list))
963 return DWC3_TRB_NUM - 1;
966 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
967 trbs_left &= (DWC3_TRB_NUM - 1);
969 if (dep->trb_dequeue < dep->trb_enqueue)
976 * dwc3_prepare_one_trb - setup one TRB from one request
977 * @dep: endpoint for which this request is prepared
978 * @req: dwc3_request pointer
979 * @trb_length: buffer size of the TRB
980 * @chain: should this TRB be chained to the next?
981 * @node: only for isochronous endpoints. First TRB needs different type.
982 * @use_bounce_buffer: set to use bounce buffer
983 * @must_interrupt: set to interrupt on TRB completion
985 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
986 struct dwc3_request *req, unsigned int trb_length,
987 unsigned int chain, unsigned int node, bool use_bounce_buffer,
990 struct dwc3_trb *trb;
992 unsigned int stream_id = req->request.stream_id;
993 unsigned int short_not_ok = req->request.short_not_ok;
994 unsigned int no_interrupt = req->request.no_interrupt;
995 unsigned int is_last = req->request.is_last;
996 struct dwc3 *dwc = dep->dwc;
997 struct usb_gadget *gadget = dwc->gadget;
998 enum usb_device_speed speed = gadget->speed;
1000 if (use_bounce_buffer)
1001 dma = dep->dwc->bounce_addr;
1002 else if (req->request.num_sgs > 0)
1003 dma = sg_dma_address(req->start_sg);
1005 dma = req->request.dma;
1007 trb = &dep->trb_pool[dep->trb_enqueue];
1010 dwc3_gadget_move_started_request(req);
1012 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1017 trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1018 trb->bpl = lower_32_bits(dma);
1019 trb->bph = upper_32_bits(dma);
1021 switch (usb_endpoint_type(dep->endpoint.desc)) {
1022 case USB_ENDPOINT_XFER_CONTROL:
1023 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1026 case USB_ENDPOINT_XFER_ISOC:
1028 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1031 * USB Specification 2.0 Section 5.9.2 states that: "If
1032 * there is only a single transaction in the microframe,
1033 * only a DATA0 data packet PID is used. If there are
1034 * two transactions per microframe, DATA1 is used for
1035 * the first transaction data packet and DATA0 is used
1036 * for the second transaction data packet. If there are
1037 * three transactions per microframe, DATA2 is used for
1038 * the first transaction data packet, DATA1 is used for
1039 * the second, and DATA0 is used for the third."
1041 * IOW, we should satisfy the following cases:
1043 * 1) length <= maxpacket
1046 * 2) maxpacket < length <= (2 * maxpacket)
1049 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1050 * - DATA2, DATA1, DATA0
1052 if (speed == USB_SPEED_HIGH) {
1053 struct usb_ep *ep = &dep->endpoint;
1054 unsigned int mult = 2;
1055 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1057 if (req->request.length <= (2 * maxp))
1060 if (req->request.length <= maxp)
1063 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1066 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1069 if (!no_interrupt && !chain)
1070 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1073 case USB_ENDPOINT_XFER_BULK:
1074 case USB_ENDPOINT_XFER_INT:
1075 trb->ctrl = DWC3_TRBCTL_NORMAL;
1079 * This is only possible with faulty memory because we
1080 * checked it already :)
1082 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1083 usb_endpoint_type(dep->endpoint.desc));
1087 * Enable Continue on Short Packet
1088 * when endpoint is not a stream capable
1090 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1091 if (!dep->stream_capable)
1092 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1095 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1098 if ((!no_interrupt && !chain) || must_interrupt)
1099 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1102 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1103 else if (dep->stream_capable && is_last)
1104 trb->ctrl |= DWC3_TRB_CTRL_LST;
1106 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1107 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1110 * As per data book 4.2.3.2TRB Control Bit Rules section
1112 * The controller autonomously checks the HWO field of a TRB to determine if the
1113 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1114 * is valid before setting the HWO field to '1'. In most systems, this means that
1115 * software must update the fourth DWORD of a TRB last.
1117 * However there is a possibility of CPU re-ordering here which can cause
1118 * controller to observe the HWO bit set prematurely.
1119 * Add a write memory barrier to prevent CPU re-ordering.
1122 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1124 dwc3_ep_inc_enq(dep);
1126 trace_dwc3_prepare_trb(dep, trb);
1129 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1131 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1132 unsigned int rem = req->request.length % maxp;
1134 if ((req->request.length && req->request.zero && !rem &&
1135 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1136 (!req->direction && rem))
1143 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1144 * @dep: The endpoint that the request belongs to
1145 * @req: The request to prepare
1146 * @entry_length: The last SG entry size
1147 * @node: Indicates whether this is not the first entry (for isoc only)
1149 * Return the number of TRBs prepared.
1151 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1152 struct dwc3_request *req, unsigned int entry_length,
1155 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1156 unsigned int rem = req->request.length % maxp;
1157 unsigned int num_trbs = 1;
1159 if (dwc3_needs_extra_trb(dep, req))
1162 if (dwc3_calc_trbs_left(dep) < num_trbs)
1165 req->needs_extra_trb = num_trbs > 1;
1167 /* Prepare a normal TRB */
1168 if (req->direction || req->request.length)
1169 dwc3_prepare_one_trb(dep, req, entry_length,
1170 req->needs_extra_trb, node, false, false);
1172 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1173 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1174 dwc3_prepare_one_trb(dep, req,
1175 req->direction ? 0 : maxp - rem,
1176 false, 1, true, false);
1181 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1182 struct dwc3_request *req)
1184 struct scatterlist *sg = req->start_sg;
1185 struct scatterlist *s;
1187 unsigned int length = req->request.length;
1188 unsigned int remaining = req->request.num_mapped_sgs
1189 - req->num_queued_sgs;
1190 unsigned int num_trbs = req->num_trbs;
1191 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1194 * If we resume preparing the request, then get the remaining length of
1195 * the request and resume where we left off.
1197 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1198 length -= sg_dma_len(s);
1200 for_each_sg(sg, s, remaining, i) {
1201 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1202 unsigned int trb_length;
1203 bool must_interrupt = false;
1204 bool last_sg = false;
1206 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1208 length -= trb_length;
1211 * IOMMU driver is coalescing the list of sgs which shares a
1212 * page boundary into one and giving it to USB driver. With
1213 * this the number of sgs mapped is not equal to the number of
1214 * sgs passed. So mark the chain bit to false if it isthe last
1217 if ((i == remaining - 1) || !length)
1224 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1228 * Look ahead to check if we have enough TRBs for the
1229 * next SG entry. If not, set interrupt on this TRB to
1230 * resume preparing the next SG entry when more TRBs are
1233 if (num_trbs_left == 1 || (needs_extra_trb &&
1234 num_trbs_left <= 2 &&
1235 sg_dma_len(sg_next(s)) >= length))
1236 must_interrupt = true;
1238 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1243 * There can be a situation where all sgs in sglist are not
1244 * queued because of insufficient trb number. To handle this
1245 * case, update start_sg to next sg to be queued, so that
1246 * we have free trbs we can continue queuing from where we
1247 * previously stopped
1250 req->start_sg = sg_next(s);
1252 req->num_queued_sgs++;
1253 req->num_pending_sgs--;
1256 * The number of pending SG entries may not correspond to the
1257 * number of mapped SG entries. If all the data are queued, then
1258 * don't include unused SG entries.
1261 req->num_pending_sgs = 0;
1269 return req->num_trbs - num_trbs;
1272 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1273 struct dwc3_request *req)
1275 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1279 * dwc3_prepare_trbs - setup TRBs from requests
1280 * @dep: endpoint for which requests are being prepared
1282 * The function goes through the requests list and sets up TRBs for the
1283 * transfers. The function returns once there are no more TRBs available or
1284 * it runs out of requests.
1286 * Returns the number of TRBs prepared or negative errno.
1288 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1290 struct dwc3_request *req, *n;
1293 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1296 * We can get in a situation where there's a request in the started list
1297 * but there weren't enough TRBs to fully kick it in the first time
1298 * around, so it has been waiting for more TRBs to be freed up.
1300 * In that case, we should check if we have a request with pending_sgs
1301 * in the started list and prepare TRBs for that request first,
1302 * otherwise we will prepare TRBs completely out of order and that will
1305 list_for_each_entry(req, &dep->started_list, list) {
1306 if (req->num_pending_sgs > 0) {
1307 ret = dwc3_prepare_trbs_sg(dep, req);
1308 if (!ret || req->num_pending_sgs)
1312 if (!dwc3_calc_trbs_left(dep))
1316 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1317 * burst capability may try to read and use TRBs beyond the
1318 * active transfer instead of stopping.
1320 if (dep->stream_capable && req->request.is_last)
1324 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1325 struct dwc3 *dwc = dep->dwc;
1327 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1332 req->sg = req->request.sg;
1333 req->start_sg = req->sg;
1334 req->num_queued_sgs = 0;
1335 req->num_pending_sgs = req->request.num_mapped_sgs;
1337 if (req->num_pending_sgs > 0) {
1338 ret = dwc3_prepare_trbs_sg(dep, req);
1339 if (req->num_pending_sgs)
1342 ret = dwc3_prepare_trbs_linear(dep, req);
1345 if (!ret || !dwc3_calc_trbs_left(dep))
1349 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1350 * burst capability may try to read and use TRBs beyond the
1351 * active transfer instead of stopping.
1353 if (dep->stream_capable && req->request.is_last)
1360 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1362 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1364 struct dwc3_gadget_ep_cmd_params params;
1365 struct dwc3_request *req;
1371 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1372 * This happens when we need to stop and restart a transfer such as in
1373 * the case of reinitiating a stream or retrying an isoc transfer.
1375 ret = dwc3_prepare_trbs(dep);
1379 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1382 * If there's no new TRB prepared and we don't need to restart a
1383 * transfer, there's no need to update the transfer.
1385 if (!ret && !starting)
1388 req = next_request(&dep->started_list);
1390 dep->flags |= DWC3_EP_PENDING_REQUEST;
1394 memset(¶ms, 0, sizeof(params));
1397 params.param0 = upper_32_bits(req->trb_dma);
1398 params.param1 = lower_32_bits(req->trb_dma);
1399 cmd = DWC3_DEPCMD_STARTTRANSFER;
1401 if (dep->stream_capable)
1402 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1404 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1405 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1407 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1408 DWC3_DEPCMD_PARAM(dep->resource_index);
1411 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1413 struct dwc3_request *tmp;
1418 dwc3_stop_active_transfer(dep, true, true);
1420 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1421 dwc3_gadget_move_cancelled_request(req);
1423 /* If ep isn't started, then there's no end transfer pending */
1424 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1425 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1430 if (dep->stream_capable && req->request.is_last)
1431 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1436 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1440 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1441 return DWC3_DSTS_SOFFN(reg);
1445 * __dwc3_stop_active_transfer - stop the current active transfer
1446 * @dep: isoc endpoint
1447 * @force: set forcerm bit in the command
1448 * @interrupt: command complete interrupt after End Transfer command
1450 * When setting force, the ForceRM bit will be set. In that case
1451 * the controller won't update the TRB progress on command
1452 * completion. It also won't clear the HWO bit in the TRB.
1453 * The command will also not complete immediately in that case.
1455 static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1457 struct dwc3 *dwc = dep->dwc;
1458 struct dwc3_gadget_ep_cmd_params params;
1462 cmd = DWC3_DEPCMD_ENDTRANSFER;
1463 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1464 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1465 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1466 memset(¶ms, 0, sizeof(params));
1467 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1469 dep->resource_index = 0;
1472 if (!DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC3, 310A))
1474 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1476 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1483 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1484 * @dep: isoc endpoint
1486 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1487 * microframe number reported by the XferNotReady event for the future frame
1488 * number to start the isoc transfer.
1490 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1491 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1492 * XferNotReady event are invalid. The driver uses this number to schedule the
1493 * isochronous transfer and passes it to the START TRANSFER command. Because
1494 * this number is invalid, the command may fail. If BIT[15:14] matches the
1495 * internal 16-bit microframe, the START TRANSFER command will pass and the
1496 * transfer will start at the scheduled time, if it is off by 1, the command
1497 * will still pass, but the transfer will start 2 seconds in the future. For all
1498 * other conditions, the START TRANSFER command will fail with bus-expiry.
1500 * In order to workaround this issue, we can test for the correct combination of
1501 * BIT[15:14] by sending START TRANSFER commands with different values of
1502 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1503 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1504 * As the result, within the 4 possible combinations for BIT[15:14], there will
1505 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1506 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1507 * value is the correct combination.
1509 * Since there are only 4 outcomes and the results are ordered, we can simply
1510 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1511 * deduce the smaller successful combination.
1513 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1514 * of BIT[15:14]. The correct combination is as follow:
1516 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1517 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1518 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1519 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1521 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1524 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1530 while (dep->combo_num < 2) {
1531 struct dwc3_gadget_ep_cmd_params params;
1532 u32 test_frame_number;
1536 * Check if we can start isoc transfer on the next interval or
1537 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1539 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1540 test_frame_number |= dep->combo_num << 14;
1541 test_frame_number += max_t(u32, 4, dep->interval);
1543 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1544 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1546 cmd = DWC3_DEPCMD_STARTTRANSFER;
1547 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1548 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1550 /* Redo if some other failure beside bus-expiry is received */
1551 if (cmd_status && cmd_status != -EAGAIN) {
1552 dep->start_cmd_status = 0;
1557 /* Store the first test status */
1558 if (dep->combo_num == 0)
1559 dep->start_cmd_status = cmd_status;
1564 * End the transfer if the START_TRANSFER command is successful
1565 * to wait for the next XferNotReady to test the command again
1567 if (cmd_status == 0) {
1568 dwc3_stop_active_transfer(dep, true, true);
1573 /* test0 and test1 are both completed at this point */
1574 test0 = (dep->start_cmd_status == 0);
1575 test1 = (cmd_status == 0);
1577 if (!test0 && test1)
1579 else if (!test0 && !test1)
1581 else if (test0 && !test1)
1583 else if (test0 && test1)
1586 dep->frame_number &= DWC3_FRNUMBER_MASK;
1587 dep->frame_number |= dep->combo_num << 14;
1588 dep->frame_number += max_t(u32, 4, dep->interval);
1590 /* Reinitialize test variables */
1591 dep->start_cmd_status = 0;
1594 return __dwc3_gadget_kick_transfer(dep);
1597 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1599 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1600 struct dwc3 *dwc = dep->dwc;
1604 if (list_empty(&dep->pending_list) &&
1605 list_empty(&dep->started_list)) {
1606 dep->flags |= DWC3_EP_PENDING_REQUEST;
1610 if (!dwc->dis_start_transfer_quirk &&
1611 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1612 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1613 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1614 return dwc3_gadget_start_isoc_quirk(dep);
1617 if (desc->bInterval <= 14 &&
1618 dwc->gadget->speed >= USB_SPEED_HIGH) {
1619 u32 frame = __dwc3_gadget_get_frame(dwc);
1620 bool rollover = frame <
1621 (dep->frame_number & DWC3_FRNUMBER_MASK);
1624 * frame_number is set from XferNotReady and may be already
1625 * out of date. DSTS only provides the lower 14 bit of the
1626 * current frame number. So add the upper two bits of
1627 * frame_number and handle a possible rollover.
1628 * This will provide the correct frame_number unless more than
1629 * rollover has happened since XferNotReady.
1632 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1635 dep->frame_number += BIT(14);
1638 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1639 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1641 ret = __dwc3_gadget_kick_transfer(dep);
1647 * After a number of unsuccessful start attempts due to bus-expiry
1648 * status, issue END_TRANSFER command and retry on the next XferNotReady
1652 ret = __dwc3_stop_active_transfer(dep, false, true);
1657 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1659 struct dwc3 *dwc = dep->dwc;
1661 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1662 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1667 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1668 &req->request, req->dep->name))
1671 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1672 "%s: request %pK already in flight\n",
1673 dep->name, &req->request))
1676 pm_runtime_get(dwc->dev);
1678 req->request.actual = 0;
1679 req->request.status = -EINPROGRESS;
1681 trace_dwc3_ep_queue(req);
1683 list_add_tail(&req->list, &dep->pending_list);
1684 req->status = DWC3_REQUEST_STATUS_QUEUED;
1686 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1690 * Start the transfer only after the END_TRANSFER is completed
1691 * and endpoint STALL is cleared.
1693 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1694 (dep->flags & DWC3_EP_WEDGE) ||
1695 (dep->flags & DWC3_EP_STALL)) {
1696 dep->flags |= DWC3_EP_DELAY_START;
1701 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1702 * wait for a XferNotReady event so we will know what's the current
1703 * (micro-)frame number.
1705 * Without this trick, we are very, very likely gonna get Bus Expiry
1706 * errors which will force us issue EndTransfer command.
1708 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1709 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1710 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1713 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1714 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1715 return __dwc3_gadget_start_isoc(dep);
1719 __dwc3_gadget_kick_transfer(dep);
1724 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1727 struct dwc3_request *req = to_dwc3_request(request);
1728 struct dwc3_ep *dep = to_dwc3_ep(ep);
1729 struct dwc3 *dwc = dep->dwc;
1731 unsigned long flags;
1735 spin_lock_irqsave(&dwc->lock, flags);
1736 ret = __dwc3_gadget_ep_queue(dep, req);
1737 spin_unlock_irqrestore(&dwc->lock, flags);
1742 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1746 /* If req->trb is not set, then the request has not started */
1751 * If request was already started, this means we had to
1752 * stop the transfer. With that we also need to ignore
1753 * all TRBs used by the request, however TRBs can only
1754 * be modified after completion of END_TRANSFER
1755 * command. So what we do here is that we wait for
1756 * END_TRANSFER completion and only after that, we jump
1757 * over TRBs by clearing HWO and incrementing dequeue
1760 for (i = 0; i < req->num_trbs; i++) {
1761 struct dwc3_trb *trb;
1763 trb = &dep->trb_pool[dep->trb_dequeue];
1764 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1765 dwc3_ep_inc_deq(dep);
1771 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1773 struct dwc3_request *req;
1774 struct dwc3_request *tmp;
1776 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1777 dwc3_gadget_ep_skip_trbs(dep, req);
1778 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1782 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1783 struct usb_request *request)
1785 struct dwc3_request *req = to_dwc3_request(request);
1786 struct dwc3_request *r = NULL;
1788 struct dwc3_ep *dep = to_dwc3_ep(ep);
1789 struct dwc3 *dwc = dep->dwc;
1791 unsigned long flags;
1794 trace_dwc3_ep_dequeue(req);
1796 spin_lock_irqsave(&dwc->lock, flags);
1798 list_for_each_entry(r, &dep->cancelled_list, list) {
1803 list_for_each_entry(r, &dep->pending_list, list) {
1805 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1810 list_for_each_entry(r, &dep->started_list, list) {
1812 struct dwc3_request *t;
1814 /* wait until it is processed */
1815 dwc3_stop_active_transfer(dep, true, true);
1818 * Remove any started request if the transfer is
1821 list_for_each_entry_safe(r, t, &dep->started_list, list)
1822 dwc3_gadget_move_cancelled_request(r);
1824 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
1830 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1834 spin_unlock_irqrestore(&dwc->lock, flags);
1839 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1841 struct dwc3_gadget_ep_cmd_params params;
1842 struct dwc3 *dwc = dep->dwc;
1843 struct dwc3_request *req;
1844 struct dwc3_request *tmp;
1847 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1848 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1852 memset(¶ms, 0x00, sizeof(params));
1855 struct dwc3_trb *trb;
1857 unsigned int transfer_in_flight;
1858 unsigned int started;
1860 if (dep->number > 1)
1861 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1863 trb = &dwc->ep0_trb[dep->trb_enqueue];
1865 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1866 started = !list_empty(&dep->started_list);
1868 if (!protocol && ((dep->direction && transfer_in_flight) ||
1869 (!dep->direction && started))) {
1873 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1876 dev_err(dwc->dev, "failed to set STALL on %s\n",
1879 dep->flags |= DWC3_EP_STALL;
1882 * Don't issue CLEAR_STALL command to control endpoints. The
1883 * controller automatically clears the STALL when it receives
1886 if (dep->number <= 1) {
1887 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1891 dwc3_stop_active_transfer(dep, true, true);
1893 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1894 dwc3_gadget_move_cancelled_request(req);
1896 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
1897 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
1901 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1903 ret = dwc3_send_clear_stall_ep_cmd(dep);
1905 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1910 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1912 if ((dep->flags & DWC3_EP_DELAY_START) &&
1913 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
1914 __dwc3_gadget_kick_transfer(dep);
1916 dep->flags &= ~DWC3_EP_DELAY_START;
1922 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1924 struct dwc3_ep *dep = to_dwc3_ep(ep);
1925 struct dwc3 *dwc = dep->dwc;
1927 unsigned long flags;
1931 spin_lock_irqsave(&dwc->lock, flags);
1932 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1933 spin_unlock_irqrestore(&dwc->lock, flags);
1938 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1940 struct dwc3_ep *dep = to_dwc3_ep(ep);
1941 struct dwc3 *dwc = dep->dwc;
1942 unsigned long flags;
1945 spin_lock_irqsave(&dwc->lock, flags);
1946 dep->flags |= DWC3_EP_WEDGE;
1948 if (dep->number == 0 || dep->number == 1)
1949 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1951 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1952 spin_unlock_irqrestore(&dwc->lock, flags);
1957 /* -------------------------------------------------------------------------- */
1959 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1960 .bLength = USB_DT_ENDPOINT_SIZE,
1961 .bDescriptorType = USB_DT_ENDPOINT,
1962 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1965 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1966 .enable = dwc3_gadget_ep0_enable,
1967 .disable = dwc3_gadget_ep0_disable,
1968 .alloc_request = dwc3_gadget_ep_alloc_request,
1969 .free_request = dwc3_gadget_ep_free_request,
1970 .queue = dwc3_gadget_ep0_queue,
1971 .dequeue = dwc3_gadget_ep_dequeue,
1972 .set_halt = dwc3_gadget_ep0_set_halt,
1973 .set_wedge = dwc3_gadget_ep_set_wedge,
1976 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1977 .enable = dwc3_gadget_ep_enable,
1978 .disable = dwc3_gadget_ep_disable,
1979 .alloc_request = dwc3_gadget_ep_alloc_request,
1980 .free_request = dwc3_gadget_ep_free_request,
1981 .queue = dwc3_gadget_ep_queue,
1982 .dequeue = dwc3_gadget_ep_dequeue,
1983 .set_halt = dwc3_gadget_ep_set_halt,
1984 .set_wedge = dwc3_gadget_ep_set_wedge,
1987 /* -------------------------------------------------------------------------- */
1989 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1991 struct dwc3 *dwc = gadget_to_dwc(g);
1993 return __dwc3_gadget_get_frame(dwc);
1996 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
2006 * According to the Databook Remote wakeup request should
2007 * be issued only when the device is in early suspend state.
2009 * We can check that via USB Link State bits in DSTS register.
2011 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2013 link_state = DWC3_DSTS_USBLNKST(reg);
2015 switch (link_state) {
2016 case DWC3_LINK_STATE_RESET:
2017 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2018 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2019 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2020 case DWC3_LINK_STATE_U1:
2021 case DWC3_LINK_STATE_RESUME:
2027 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2029 dev_err(dwc->dev, "failed to put link in Recovery\n");
2033 /* Recent versions do this automatically */
2034 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2035 /* write zeroes to Link Change Request */
2036 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2037 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2038 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2041 /* poll until Link State changes to ON */
2045 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2047 /* in HS, means ON */
2048 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2052 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2053 dev_err(dwc->dev, "failed to send remote wakeup\n");
2060 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2062 struct dwc3 *dwc = gadget_to_dwc(g);
2063 unsigned long flags;
2066 spin_lock_irqsave(&dwc->lock, flags);
2067 ret = __dwc3_gadget_wakeup(dwc);
2068 spin_unlock_irqrestore(&dwc->lock, flags);
2073 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2076 struct dwc3 *dwc = gadget_to_dwc(g);
2077 unsigned long flags;
2079 spin_lock_irqsave(&dwc->lock, flags);
2080 g->is_selfpowered = !!is_selfpowered;
2081 spin_unlock_irqrestore(&dwc->lock, flags);
2086 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2090 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2091 struct dwc3_ep *dep;
2093 dep = dwc->eps[epnum];
2097 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2101 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2106 if (pm_runtime_suspended(dwc->dev))
2109 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2111 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2112 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2113 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2116 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2117 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2118 reg |= DWC3_DCTL_RUN_STOP;
2120 if (dwc->has_hibernation)
2121 reg |= DWC3_DCTL_KEEP_CONNECT;
2123 dwc->pullups_connected = true;
2125 reg &= ~DWC3_DCTL_RUN_STOP;
2127 if (dwc->has_hibernation && !suspend)
2128 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2130 dwc->pullups_connected = false;
2133 dwc3_gadget_dctl_write_safe(dwc, reg);
2136 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2137 reg &= DWC3_DSTS_DEVCTRLHLT;
2138 } while (--timeout && !(!is_on ^ !reg));
2146 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2147 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2148 static int __dwc3_gadget_start(struct dwc3 *dwc);
2150 static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2152 unsigned long flags;
2154 spin_lock_irqsave(&dwc->lock, flags);
2155 dwc->connected = false;
2158 * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2159 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2160 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2161 * command for any active transfers" before clearing the RunStop
2164 dwc3_stop_active_transfers(dwc);
2165 __dwc3_gadget_stop(dwc);
2166 spin_unlock_irqrestore(&dwc->lock, flags);
2169 * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2170 * driver needs to acknowledge them before the controller can halt.
2171 * Simply let the interrupt handler acknowledges and handle the
2172 * remaining event generated by the controller while polling for
2175 return dwc3_gadget_run_stop(dwc, false, false);
2178 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2180 struct dwc3 *dwc = gadget_to_dwc(g);
2185 dwc->softconnect = is_on;
2187 * Per databook, when we want to stop the gadget, if a control transfer
2188 * is still in process, complete it and get the core into setup phase.
2190 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2191 reinit_completion(&dwc->ep0_in_setup);
2193 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2194 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2196 dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2200 * Avoid issuing a runtime resume if the device is already in the
2201 * suspended state during gadget disconnect. DWC3 gadget was already
2202 * halted/stopped during runtime suspend.
2205 pm_runtime_barrier(dwc->dev);
2206 if (pm_runtime_suspended(dwc->dev))
2211 * Check the return value for successful resume, or error. For a
2212 * successful resume, the DWC3 runtime PM resume routine will handle
2213 * the run stop sequence, so avoid duplicate operations here.
2215 ret = pm_runtime_get_sync(dwc->dev);
2216 if (!ret || ret < 0) {
2217 pm_runtime_put(dwc->dev);
2219 pm_runtime_set_suspended(dwc->dev);
2223 if (dwc->pullups_connected == is_on) {
2224 pm_runtime_put(dwc->dev);
2229 ret = dwc3_gadget_soft_disconnect(dwc);
2232 * In the Synopsys DWC_usb31 1.90a programming guide section
2233 * 4.1.9, it specifies that for a reconnect after a
2234 * device-initiated disconnect requires a core soft reset
2235 * (DCTL.CSftRst) before enabling the run/stop bit.
2237 dwc3_core_soft_reset(dwc);
2239 dwc3_event_buffers_setup(dwc);
2240 __dwc3_gadget_start(dwc);
2241 ret = dwc3_gadget_run_stop(dwc, true, false);
2244 pm_runtime_put(dwc->dev);
2249 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2253 /* Enable all but Start and End of Frame IRQs */
2254 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2255 DWC3_DEVTEN_EVNTOVERFLOWEN |
2256 DWC3_DEVTEN_CMDCMPLTEN |
2257 DWC3_DEVTEN_ERRTICERREN |
2258 DWC3_DEVTEN_WKUPEVTEN |
2259 DWC3_DEVTEN_CONNECTDONEEN |
2260 DWC3_DEVTEN_USBRSTEN |
2261 DWC3_DEVTEN_DISCONNEVTEN);
2263 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2264 reg |= DWC3_DEVTEN_ULSTCNGEN;
2266 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2267 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2268 reg |= DWC3_DEVTEN_EOPFEN;
2270 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2273 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2275 /* mask all interrupts */
2276 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2279 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2280 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2283 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2284 * @dwc: pointer to our context structure
2286 * The following looks like complex but it's actually very simple. In order to
2287 * calculate the number of packets we can burst at once on OUT transfers, we're
2288 * gonna use RxFIFO size.
2290 * To calculate RxFIFO size we need two numbers:
2291 * MDWIDTH = size, in bits, of the internal memory bus
2292 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2294 * Given these two numbers, the formula is simple:
2296 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2298 * 24 bytes is for 3x SETUP packets
2299 * 16 bytes is a clock domain crossing tolerance
2301 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2303 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2310 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2311 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
2312 if (DWC3_IP_IS(DWC32))
2313 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2315 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2316 nump = min_t(u32, nump, 16);
2319 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2320 reg &= ~DWC3_DCFG_NUMP_MASK;
2321 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2322 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2325 static int __dwc3_gadget_start(struct dwc3 *dwc)
2327 struct dwc3_ep *dep;
2332 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2333 * the core supports IMOD, disable it.
2335 if (dwc->imod_interval) {
2336 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2337 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2338 } else if (dwc3_has_imod(dwc)) {
2339 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2343 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2344 * field instead of letting dwc3 itself calculate that automatically.
2346 * This way, we maximize the chances that we'll be able to get several
2347 * bursts of data without going through any sort of endpoint throttling.
2349 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2350 if (DWC3_IP_IS(DWC3))
2351 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2353 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2355 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2357 dwc3_gadget_setup_nump(dwc);
2359 /* Start with SuperSpeed Default */
2360 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2363 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2365 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2370 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2372 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2376 /* begin to receive SETUP packets */
2377 dwc->ep0state = EP0_SETUP_PHASE;
2378 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2379 dwc->delayed_status = false;
2380 dwc3_ep0_out_start(dwc);
2382 dwc3_gadget_enable_irq(dwc);
2387 __dwc3_gadget_ep_disable(dwc->eps[0]);
2393 static int dwc3_gadget_start(struct usb_gadget *g,
2394 struct usb_gadget_driver *driver)
2396 struct dwc3 *dwc = gadget_to_dwc(g);
2397 unsigned long flags;
2401 irq = dwc->irq_gadget;
2402 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2403 IRQF_SHARED, "dwc3", dwc->ev_buf);
2405 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2410 spin_lock_irqsave(&dwc->lock, flags);
2411 if (dwc->gadget_driver) {
2412 dev_err(dwc->dev, "%s is already bound to %s\n",
2414 dwc->gadget_driver->driver.name);
2419 dwc->gadget_driver = driver;
2420 spin_unlock_irqrestore(&dwc->lock, flags);
2425 spin_unlock_irqrestore(&dwc->lock, flags);
2432 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2434 dwc3_gadget_disable_irq(dwc);
2435 __dwc3_gadget_ep_disable(dwc->eps[0]);
2436 __dwc3_gadget_ep_disable(dwc->eps[1]);
2439 static int dwc3_gadget_stop(struct usb_gadget *g)
2441 struct dwc3 *dwc = gadget_to_dwc(g);
2442 unsigned long flags;
2444 spin_lock_irqsave(&dwc->lock, flags);
2445 dwc->gadget_driver = NULL;
2446 spin_unlock_irqrestore(&dwc->lock, flags);
2448 free_irq(dwc->irq_gadget, dwc->ev_buf);
2453 static void dwc3_gadget_config_params(struct usb_gadget *g,
2454 struct usb_dcd_config_params *params)
2456 struct dwc3 *dwc = gadget_to_dwc(g);
2458 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2459 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2461 /* Recommended BESL */
2462 if (!dwc->dis_enblslpm_quirk) {
2464 * If the recommended BESL baseline is 0 or if the BESL deep is
2465 * less than 2, Microsoft's Windows 10 host usb stack will issue
2466 * a usb reset immediately after it receives the extended BOS
2467 * descriptor and the enumeration will fail. To maintain
2468 * compatibility with the Windows' usb stack, let's set the
2469 * recommended BESL baseline to 1 and clamp the BESL deep to be
2472 params->besl_baseline = 1;
2473 if (dwc->is_utmi_l1_suspend)
2475 clamp_t(u8, dwc->hird_threshold, 2, 15);
2478 /* U1 Device exit Latency */
2479 if (dwc->dis_u1_entry_quirk)
2480 params->bU1devExitLat = 0;
2482 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2484 /* U2 Device exit Latency */
2485 if (dwc->dis_u2_entry_quirk)
2486 params->bU2DevExitLat = 0;
2488 params->bU2DevExitLat =
2489 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2492 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2493 enum usb_device_speed speed)
2495 struct dwc3 *dwc = gadget_to_dwc(g);
2496 unsigned long flags;
2499 spin_lock_irqsave(&dwc->lock, flags);
2500 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2501 reg &= ~(DWC3_DCFG_SPEED_MASK);
2504 * WORKAROUND: DWC3 revision < 2.20a have an issue
2505 * which would cause metastability state on Run/Stop
2506 * bit if we try to force the IP to USB2-only mode.
2508 * Because of that, we cannot configure the IP to any
2509 * speed other than the SuperSpeed
2513 * STAR#9000525659: Clock Domain Crossing on DCTL in
2516 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2517 !dwc->dis_metastability_quirk) {
2518 reg |= DWC3_DCFG_SUPERSPEED;
2522 reg |= DWC3_DCFG_LOWSPEED;
2524 case USB_SPEED_FULL:
2525 reg |= DWC3_DCFG_FULLSPEED;
2527 case USB_SPEED_HIGH:
2528 reg |= DWC3_DCFG_HIGHSPEED;
2530 case USB_SPEED_SUPER:
2531 reg |= DWC3_DCFG_SUPERSPEED;
2533 case USB_SPEED_SUPER_PLUS:
2534 if (DWC3_IP_IS(DWC3))
2535 reg |= DWC3_DCFG_SUPERSPEED;
2537 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2540 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2542 if (DWC3_IP_IS(DWC3))
2543 reg |= DWC3_DCFG_SUPERSPEED;
2545 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2548 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2550 spin_unlock_irqrestore(&dwc->lock, flags);
2553 static const struct usb_gadget_ops dwc3_gadget_ops = {
2554 .get_frame = dwc3_gadget_get_frame,
2555 .wakeup = dwc3_gadget_wakeup,
2556 .set_selfpowered = dwc3_gadget_set_selfpowered,
2557 .pullup = dwc3_gadget_pullup,
2558 .udc_start = dwc3_gadget_start,
2559 .udc_stop = dwc3_gadget_stop,
2560 .udc_set_speed = dwc3_gadget_set_speed,
2561 .get_config_params = dwc3_gadget_config_params,
2564 /* -------------------------------------------------------------------------- */
2566 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2568 struct dwc3 *dwc = dep->dwc;
2570 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2571 dep->endpoint.maxburst = 1;
2572 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2573 if (!dep->direction)
2574 dwc->gadget->ep0 = &dep->endpoint;
2576 dep->endpoint.caps.type_control = true;
2581 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2583 struct dwc3 *dwc = dep->dwc;
2587 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2588 if (DWC3_IP_IS(DWC32))
2589 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2591 /* MDWIDTH is represented in bits, we need it in bytes */
2594 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2595 if (DWC3_IP_IS(DWC3))
2596 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2598 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2600 /* FIFO Depth is in MDWDITH bytes. Multiply */
2604 * To meet performance requirement, a minimum TxFIFO size of 3x
2605 * MaxPacketSize is recommended for endpoints that support burst and a
2606 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2607 * support burst. Use those numbers and we can calculate the max packet
2610 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2615 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2617 dep->endpoint.max_streams = 16;
2618 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2619 list_add_tail(&dep->endpoint.ep_list,
2620 &dwc->gadget->ep_list);
2621 dep->endpoint.caps.type_iso = true;
2622 dep->endpoint.caps.type_bulk = true;
2623 dep->endpoint.caps.type_int = true;
2625 return dwc3_alloc_trb_pool(dep);
2628 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2630 struct dwc3 *dwc = dep->dwc;
2634 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2635 if (DWC3_IP_IS(DWC32))
2636 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2638 /* MDWIDTH is represented in bits, convert to bytes */
2641 /* All OUT endpoints share a single RxFIFO space */
2642 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2643 if (DWC3_IP_IS(DWC3))
2644 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2646 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2648 /* FIFO depth is in MDWDITH bytes */
2652 * To meet performance requirement, a minimum recommended RxFIFO size
2653 * is defined as follow:
2654 * RxFIFO size >= (3 x MaxPacketSize) +
2655 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2657 * Then calculate the max packet limit as below.
2659 size -= (3 * 8) + 16;
2665 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2666 dep->endpoint.max_streams = 16;
2667 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2668 list_add_tail(&dep->endpoint.ep_list,
2669 &dwc->gadget->ep_list);
2670 dep->endpoint.caps.type_iso = true;
2671 dep->endpoint.caps.type_bulk = true;
2672 dep->endpoint.caps.type_int = true;
2674 return dwc3_alloc_trb_pool(dep);
2677 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2679 struct dwc3_ep *dep;
2680 bool direction = epnum & 1;
2682 u8 num = epnum >> 1;
2684 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2689 dep->number = epnum;
2690 dep->direction = direction;
2691 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2692 dwc->eps[epnum] = dep;
2694 dep->start_cmd_status = 0;
2696 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2697 direction ? "in" : "out");
2699 dep->endpoint.name = dep->name;
2701 if (!(dep->number > 1)) {
2702 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2703 dep->endpoint.comp_desc = NULL;
2707 ret = dwc3_gadget_init_control_endpoint(dep);
2709 ret = dwc3_gadget_init_in_endpoint(dep);
2711 ret = dwc3_gadget_init_out_endpoint(dep);
2716 dep->endpoint.caps.dir_in = direction;
2717 dep->endpoint.caps.dir_out = !direction;
2719 INIT_LIST_HEAD(&dep->pending_list);
2720 INIT_LIST_HEAD(&dep->started_list);
2721 INIT_LIST_HEAD(&dep->cancelled_list);
2723 dwc3_debugfs_create_endpoint_dir(dep);
2728 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2732 INIT_LIST_HEAD(&dwc->gadget->ep_list);
2734 for (epnum = 0; epnum < total; epnum++) {
2737 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2745 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2747 struct dwc3_ep *dep;
2750 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2751 dep = dwc->eps[epnum];
2755 * Physical endpoints 0 and 1 are special; they form the
2756 * bi-directional USB endpoint 0.
2758 * For those two physical endpoints, we don't allocate a TRB
2759 * pool nor do we add them the endpoints list. Due to that, we
2760 * shouldn't do these two operations otherwise we would end up
2761 * with all sorts of bugs when removing dwc3.ko.
2763 if (epnum != 0 && epnum != 1) {
2764 dwc3_free_trb_pool(dep);
2765 list_del(&dep->endpoint.ep_list);
2768 debugfs_remove_recursive(debugfs_lookup(dep->name, dwc->root));
2773 /* -------------------------------------------------------------------------- */
2775 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2776 struct dwc3_request *req, struct dwc3_trb *trb,
2777 const struct dwc3_event_depevt *event, int status, int chain)
2781 dwc3_ep_inc_deq(dep);
2783 trace_dwc3_complete_trb(dep, trb);
2787 * If we're in the middle of series of chained TRBs and we
2788 * receive a short transfer along the way, DWC3 will skip
2789 * through all TRBs including the last TRB in the chain (the
2790 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2791 * bit and SW has to do it manually.
2793 * We're going to do that here to avoid problems of HW trying
2794 * to use bogus TRBs for transfers.
2796 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2797 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2800 * For isochronous transfers, the first TRB in a service interval must
2801 * have the Isoc-First type. Track and report its interval frame number.
2803 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2804 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2805 unsigned int frame_number;
2807 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2808 frame_number &= ~(dep->interval - 1);
2809 req->request.frame_number = frame_number;
2813 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
2814 * this TRB points to the bounce buffer address, it's a MPS alignment
2815 * TRB. Don't add it to req->remaining calculation.
2817 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
2818 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
2819 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2823 count = trb->size & DWC3_TRB_SIZE_MASK;
2824 req->remaining += count;
2826 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2829 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2832 if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
2833 DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
2836 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2837 (trb->ctrl & DWC3_TRB_CTRL_LST))
2843 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2844 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2847 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2848 struct scatterlist *sg = req->sg;
2849 struct scatterlist *s;
2850 unsigned int num_queued = req->num_queued_sgs;
2854 for_each_sg(sg, s, num_queued, i) {
2855 trb = &dep->trb_pool[dep->trb_dequeue];
2857 req->sg = sg_next(s);
2858 req->num_queued_sgs--;
2860 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2861 trb, event, status, true);
2869 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2870 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2873 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2875 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2876 event, status, false);
2879 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2881 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
2884 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2885 const struct dwc3_event_depevt *event,
2886 struct dwc3_request *req, int status)
2891 if (req->request.num_mapped_sgs)
2892 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2895 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2898 req->request.actual = req->request.length - req->remaining;
2900 if (!dwc3_gadget_ep_request_completed(req))
2903 if (req->needs_extra_trb) {
2904 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2906 req->needs_extra_trb = false;
2910 * The event status only reflects the status of the TRB with IOC set.
2911 * For the requests that don't set interrupt on completion, the driver
2912 * needs to check and return the status of the completed TRBs associated
2913 * with the request. Use the status of the last TRB of the request.
2915 if (req->request.no_interrupt) {
2916 struct dwc3_trb *trb;
2918 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
2919 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
2920 case DWC3_TRBSTS_MISSED_ISOC:
2921 /* Isoc endpoint only */
2922 request_status = -EXDEV;
2924 case DWC3_TRB_STS_XFER_IN_PROG:
2925 /* Applicable when End Transfer with ForceRM=0 */
2926 case DWC3_TRBSTS_SETUP_PENDING:
2927 /* Control endpoint only */
2928 case DWC3_TRBSTS_OK:
2934 request_status = status;
2937 dwc3_gadget_giveback(dep, req, request_status);
2943 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2944 const struct dwc3_event_depevt *event, int status)
2946 struct dwc3_request *req;
2947 struct dwc3_request *tmp;
2949 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2952 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2959 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2961 struct dwc3_request *req;
2963 if (!list_empty(&dep->pending_list))
2967 * We only need to check the first entry of the started list. We can
2968 * assume the completed requests are removed from the started list.
2970 req = next_request(&dep->started_list);
2974 return !dwc3_gadget_ep_request_completed(req);
2977 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2978 const struct dwc3_event_depevt *event)
2980 dep->frame_number = event->parameters;
2983 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
2984 const struct dwc3_event_depevt *event, int status)
2986 struct dwc3 *dwc = dep->dwc;
2987 bool no_started_trb = true;
2989 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2991 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
2994 if (!dep->endpoint.desc)
2995 return no_started_trb;
2997 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2998 list_empty(&dep->started_list) &&
2999 (list_empty(&dep->pending_list) || status == -EXDEV))
3000 dwc3_stop_active_transfer(dep, true, true);
3001 else if (dwc3_gadget_ep_should_continue(dep))
3002 if (__dwc3_gadget_kick_transfer(dep) == 0)
3003 no_started_trb = false;
3007 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3008 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3010 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3014 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3017 if (!(dep->flags & DWC3_EP_ENABLED))
3020 if (!list_empty(&dep->started_list))
3021 return no_started_trb;
3024 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3026 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3031 return no_started_trb;
3034 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3035 const struct dwc3_event_depevt *event)
3039 if (!dep->endpoint.desc)
3042 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3043 dwc3_gadget_endpoint_frame_from_event(dep, event);
3045 if (event->status & DEPEVT_STATUS_BUSERR)
3046 status = -ECONNRESET;
3048 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3051 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3054 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3055 const struct dwc3_event_depevt *event)
3059 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3061 if (event->status & DEPEVT_STATUS_BUSERR)
3062 status = -ECONNRESET;
3064 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3065 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3068 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3069 const struct dwc3_event_depevt *event)
3071 dwc3_gadget_endpoint_frame_from_event(dep, event);
3074 * The XferNotReady event is generated only once before the endpoint
3075 * starts. It will be generated again when END_TRANSFER command is
3076 * issued. For some controller versions, the XferNotReady event may be
3077 * generated while the END_TRANSFER command is still in process. Ignore
3078 * it and wait for the next XferNotReady event after the command is
3081 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3084 (void) __dwc3_gadget_start_isoc(dep);
3087 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3088 const struct dwc3_event_depevt *event)
3090 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3092 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3096 * The END_TRANSFER command will cause the controller to generate a
3097 * NoStream Event, and it's not due to the host DP NoStream rejection.
3098 * Ignore the next NoStream event.
3100 if (dep->stream_capable)
3101 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3103 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3104 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3105 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3107 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3108 struct dwc3 *dwc = dep->dwc;
3110 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3111 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3112 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3114 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3115 if (dwc->delayed_status)
3116 __dwc3_gadget_ep0_set_halt(ep0, 1);
3120 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3121 if (dwc->delayed_status)
3122 dwc3_ep0_send_delayed_status(dwc);
3125 if ((dep->flags & DWC3_EP_DELAY_START) &&
3126 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3127 __dwc3_gadget_kick_transfer(dep);
3129 dep->flags &= ~DWC3_EP_DELAY_START;
3132 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3133 const struct dwc3_event_depevt *event)
3135 struct dwc3 *dwc = dep->dwc;
3137 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3138 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3142 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3143 switch (event->parameters) {
3144 case DEPEVT_STREAM_PRIME:
3146 * If the host can properly transition the endpoint state from
3147 * idle to prime after a NoStream rejection, there's no need to
3148 * force restarting the endpoint to reinitiate the stream. To
3149 * simplify the check, assume the host follows the USB spec if
3150 * it primed the endpoint more than once.
3152 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3153 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3154 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3156 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3160 case DEPEVT_STREAM_NOSTREAM:
3161 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3162 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3163 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3167 * If the host rejects a stream due to no active stream, by the
3168 * USB and xHCI spec, the endpoint will be put back to idle
3169 * state. When the host is ready (buffer added/updated), it will
3170 * prime the endpoint to inform the usb device controller. This
3171 * triggers the device controller to issue ERDY to restart the
3172 * stream. However, some hosts don't follow this and keep the
3173 * endpoint in the idle state. No prime will come despite host
3174 * streams are updated, and the device controller will not be
3175 * triggered to generate ERDY to move the next stream data. To
3176 * workaround this and maintain compatibility with various
3177 * hosts, force to reinitate the stream until the host is ready
3178 * instead of waiting for the host to prime the endpoint.
3180 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3181 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3183 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3185 dep->flags |= DWC3_EP_DELAY_START;
3186 dwc3_stop_active_transfer(dep, true, true);
3193 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3196 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3197 const struct dwc3_event_depevt *event)
3199 struct dwc3_ep *dep;
3200 u8 epnum = event->endpoint_number;
3202 dep = dwc->eps[epnum];
3204 if (!(dep->flags & DWC3_EP_ENABLED)) {
3205 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3208 /* Handle only EPCMDCMPLT when EP disabled */
3209 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3213 if (epnum == 0 || epnum == 1) {
3214 dwc3_ep0_interrupt(dwc, event);
3218 switch (event->endpoint_event) {
3219 case DWC3_DEPEVT_XFERINPROGRESS:
3220 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3222 case DWC3_DEPEVT_XFERNOTREADY:
3223 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3225 case DWC3_DEPEVT_EPCMDCMPLT:
3226 dwc3_gadget_endpoint_command_complete(dep, event);
3228 case DWC3_DEPEVT_XFERCOMPLETE:
3229 dwc3_gadget_endpoint_transfer_complete(dep, event);
3231 case DWC3_DEPEVT_STREAMEVT:
3232 dwc3_gadget_endpoint_stream_event(dep, event);
3234 case DWC3_DEPEVT_RXTXFIFOEVT:
3239 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3241 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
3242 spin_unlock(&dwc->lock);
3243 dwc->gadget_driver->disconnect(dwc->gadget);
3244 spin_lock(&dwc->lock);
3248 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3250 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
3251 spin_unlock(&dwc->lock);
3252 dwc->gadget_driver->suspend(dwc->gadget);
3253 spin_lock(&dwc->lock);
3257 static void dwc3_resume_gadget(struct dwc3 *dwc)
3259 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
3260 spin_unlock(&dwc->lock);
3261 dwc->gadget_driver->resume(dwc->gadget);
3262 spin_lock(&dwc->lock);
3266 static void dwc3_reset_gadget(struct dwc3 *dwc)
3268 if (!dwc->gadget_driver)
3271 if (dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3272 spin_unlock(&dwc->lock);
3273 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3274 spin_lock(&dwc->lock);
3278 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3281 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3282 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3286 * NOTICE: We are violating what the Databook says about the
3287 * EndTransfer command. Ideally we would _always_ wait for the
3288 * EndTransfer Command Completion IRQ, but that's causing too
3289 * much trouble synchronizing between us and gadget driver.
3291 * We have discussed this with the IP Provider and it was
3292 * suggested to giveback all requests here.
3294 * Note also that a similar handling was tested by Synopsys
3295 * (thanks a lot Paul) and nothing bad has come out of it.
3296 * In short, what we're doing is issuing EndTransfer with
3297 * CMDIOC bit set and delay kicking transfer until the
3298 * EndTransfer command had completed.
3300 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3301 * supports a mode to work around the above limitation. The
3302 * software can poll the CMDACT bit in the DEPCMD register
3303 * after issuing a EndTransfer command. This mode is enabled
3304 * by writing GUCTL2[14]. This polling is already done in the
3305 * dwc3_send_gadget_ep_cmd() function so if the mode is
3306 * enabled, the EndTransfer command will have completed upon
3307 * returning from this function.
3309 * This mode is NOT available on the DWC_usb31 IP. In this
3310 * case, if the IOC bit is not set, then delay by 1ms
3311 * after issuing the EndTransfer command. This allows for the
3312 * controller to handle the command completely before DWC3
3313 * remove requests attempts to unmap USB request buffers.
3316 __dwc3_stop_active_transfer(dep, force, interrupt);
3319 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3323 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3324 struct dwc3_ep *dep;
3327 dep = dwc->eps[epnum];
3331 if (!(dep->flags & DWC3_EP_STALL))
3334 dep->flags &= ~DWC3_EP_STALL;
3336 ret = dwc3_send_clear_stall_ep_cmd(dep);
3341 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3345 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3347 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3348 reg &= ~DWC3_DCTL_INITU1ENA;
3349 reg &= ~DWC3_DCTL_INITU2ENA;
3350 dwc3_gadget_dctl_write_safe(dwc, reg);
3352 dwc3_disconnect_gadget(dwc);
3354 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3355 dwc->setup_packet_pending = false;
3356 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3358 dwc->connected = false;
3361 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3366 * Ideally, dwc3_reset_gadget() would trigger the function
3367 * drivers to stop any active transfers through ep disable.
3368 * However, for functions which defer ep disable, such as mass
3369 * storage, we will need to rely on the call to stop active
3370 * transfers here, and avoid allowing of request queuing.
3372 dwc->connected = false;
3375 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3376 * would cause a missing Disconnect Event if there's a
3377 * pending Setup Packet in the FIFO.
3379 * There's no suggested workaround on the official Bug
3380 * report, which states that "unless the driver/application
3381 * is doing any special handling of a disconnect event,
3382 * there is no functional issue".
3384 * Unfortunately, it turns out that we _do_ some special
3385 * handling of a disconnect event, namely complete all
3386 * pending transfers, notify gadget driver of the
3387 * disconnection, and so on.
3389 * Our suggested workaround is to follow the Disconnect
3390 * Event steps here, instead, based on a setup_packet_pending
3391 * flag. Such flag gets set whenever we have a SETUP_PENDING
3392 * status for EP0 TRBs and gets cleared on XferComplete for the
3397 * STAR#9000466709: RTL: Device : Disconnect event not
3398 * generated if setup packet pending in FIFO
3400 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3401 if (dwc->setup_packet_pending)
3402 dwc3_gadget_disconnect_interrupt(dwc);
3405 dwc3_reset_gadget(dwc);
3407 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3408 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3409 * needs to ensure that it sends "a DEPENDXFER command for any active
3412 dwc3_stop_active_transfers(dwc);
3413 dwc->connected = true;
3415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3416 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3417 dwc3_gadget_dctl_write_safe(dwc, reg);
3418 dwc->test_mode = false;
3419 dwc3_clear_stall_all_ep(dwc);
3421 /* Reset device address to zero */
3422 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3423 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3424 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3427 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3429 struct dwc3_ep *dep;
3434 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3435 speed = reg & DWC3_DSTS_CONNECTSPD;
3439 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3440 * each time on Connect Done.
3442 * Currently we always use the reset value. If any platform
3443 * wants to set this to a different value, we need to add a
3444 * setting and update GCTL.RAMCLKSEL here.
3448 case DWC3_DSTS_SUPERSPEED_PLUS:
3449 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3450 dwc->gadget->ep0->maxpacket = 512;
3451 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3453 case DWC3_DSTS_SUPERSPEED:
3455 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3456 * would cause a missing USB3 Reset event.
3458 * In such situations, we should force a USB3 Reset
3459 * event by calling our dwc3_gadget_reset_interrupt()
3464 * STAR#9000483510: RTL: SS : USB3 reset event may
3465 * not be generated always when the link enters poll
3467 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3468 dwc3_gadget_reset_interrupt(dwc);
3470 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3471 dwc->gadget->ep0->maxpacket = 512;
3472 dwc->gadget->speed = USB_SPEED_SUPER;
3474 case DWC3_DSTS_HIGHSPEED:
3475 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3476 dwc->gadget->ep0->maxpacket = 64;
3477 dwc->gadget->speed = USB_SPEED_HIGH;
3479 case DWC3_DSTS_FULLSPEED:
3480 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3481 dwc->gadget->ep0->maxpacket = 64;
3482 dwc->gadget->speed = USB_SPEED_FULL;
3484 case DWC3_DSTS_LOWSPEED:
3485 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
3486 dwc->gadget->ep0->maxpacket = 8;
3487 dwc->gadget->speed = USB_SPEED_LOW;
3491 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3493 /* Enable USB2 LPM Capability */
3495 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3496 !dwc->usb2_gadget_lpm_disable &&
3497 (speed != DWC3_DSTS_SUPERSPEED) &&
3498 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3499 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3500 reg |= DWC3_DCFG_LPM_CAP;
3501 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3503 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3504 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3506 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3507 (dwc->is_utmi_l1_suspend << 4));
3510 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3511 * DCFG.LPMCap is set, core responses with an ACK and the
3512 * BESL value in the LPM token is less than or equal to LPM
3515 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3516 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3518 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3519 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3521 dwc3_gadget_dctl_write_safe(dwc, reg);
3523 if (dwc->usb2_gadget_lpm_disable) {
3524 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3525 reg &= ~DWC3_DCFG_LPM_CAP;
3526 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3529 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3530 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3531 dwc3_gadget_dctl_write_safe(dwc, reg);
3535 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3537 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3542 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3544 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3549 * Configure PHY via GUSB3PIPECTLn if required.
3551 * Update GTXFIFOSIZn
3553 * In both cases reset values should be sufficient.
3557 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3560 * TODO take core out of low power mode when that's
3564 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
3565 spin_unlock(&dwc->lock);
3566 dwc->gadget_driver->resume(dwc->gadget);
3567 spin_lock(&dwc->lock);
3571 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3572 unsigned int evtinfo)
3574 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3575 unsigned int pwropt;
3578 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3579 * Hibernation mode enabled which would show up when device detects
3580 * host-initiated U3 exit.
3582 * In that case, device will generate a Link State Change Interrupt
3583 * from U3 to RESUME which is only necessary if Hibernation is
3586 * There are no functional changes due to such spurious event and we
3587 * just need to ignore it.
3591 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3594 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3595 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3596 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3597 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3598 (next == DWC3_LINK_STATE_RESUME)) {
3604 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3605 * on the link partner, the USB session might do multiple entry/exit
3606 * of low power states before a transfer takes place.
3608 * Due to this problem, we might experience lower throughput. The
3609 * suggested workaround is to disable DCTL[12:9] bits if we're
3610 * transitioning from U1/U2 to U0 and enable those bits again
3611 * after a transfer completes and there are no pending transfers
3612 * on any of the enabled endpoints.
3614 * This is the first half of that workaround.
3618 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3619 * core send LGO_Ux entering U0
3621 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3622 if (next == DWC3_LINK_STATE_U0) {
3626 switch (dwc->link_state) {
3627 case DWC3_LINK_STATE_U1:
3628 case DWC3_LINK_STATE_U2:
3629 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3630 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3631 | DWC3_DCTL_ACCEPTU2ENA
3632 | DWC3_DCTL_INITU1ENA
3633 | DWC3_DCTL_ACCEPTU1ENA);
3636 dwc->u1u2 = reg & u1u2;
3640 dwc3_gadget_dctl_write_safe(dwc, reg);
3650 case DWC3_LINK_STATE_U1:
3651 if (dwc->speed == USB_SPEED_SUPER)
3652 dwc3_suspend_gadget(dwc);
3654 case DWC3_LINK_STATE_U2:
3655 case DWC3_LINK_STATE_U3:
3656 dwc3_suspend_gadget(dwc);
3658 case DWC3_LINK_STATE_RESUME:
3659 dwc3_resume_gadget(dwc);
3666 dwc->link_state = next;
3669 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3670 unsigned int evtinfo)
3672 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3674 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3675 dwc3_suspend_gadget(dwc);
3677 dwc->link_state = next;
3680 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3681 unsigned int evtinfo)
3683 unsigned int is_ss = evtinfo & BIT(4);
3686 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3687 * have a known issue which can cause USB CV TD.9.23 to fail
3690 * Because of this issue, core could generate bogus hibernation
3691 * events which SW needs to ignore.
3695 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3696 * Device Fallback from SuperSpeed
3698 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3701 /* enter hibernation here */
3704 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3705 const struct dwc3_event_devt *event)
3707 switch (event->type) {
3708 case DWC3_DEVICE_EVENT_DISCONNECT:
3709 dwc3_gadget_disconnect_interrupt(dwc);
3711 case DWC3_DEVICE_EVENT_RESET:
3712 dwc3_gadget_reset_interrupt(dwc);
3714 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3715 dwc3_gadget_conndone_interrupt(dwc);
3717 case DWC3_DEVICE_EVENT_WAKEUP:
3718 dwc3_gadget_wakeup_interrupt(dwc);
3720 case DWC3_DEVICE_EVENT_HIBER_REQ:
3721 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3722 "unexpected hibernation event\n"))
3725 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3727 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3728 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3730 case DWC3_DEVICE_EVENT_EOPF:
3731 /* It changed to be suspend event for version 2.30a and above */
3732 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
3733 dwc3_gadget_suspend_interrupt(dwc, event->event_info);
3735 case DWC3_DEVICE_EVENT_SOF:
3736 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3737 case DWC3_DEVICE_EVENT_CMD_CMPL:
3738 case DWC3_DEVICE_EVENT_OVERFLOW:
3741 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3745 static void dwc3_process_event_entry(struct dwc3 *dwc,
3746 const union dwc3_event *event)
3748 trace_dwc3_event(event->raw, dwc);
3750 if (!event->type.is_devspec)
3751 dwc3_endpoint_interrupt(dwc, &event->depevt);
3752 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3753 dwc3_gadget_interrupt(dwc, &event->devt);
3755 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3758 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3760 struct dwc3 *dwc = evt->dwc;
3761 irqreturn_t ret = IRQ_NONE;
3767 if (!(evt->flags & DWC3_EVENT_PENDING))
3771 union dwc3_event event;
3773 event.raw = *(u32 *) (evt->cache + evt->lpos);
3775 dwc3_process_event_entry(dwc, &event);
3778 * FIXME we wrap around correctly to the next entry as
3779 * almost all entries are 4 bytes in size. There is one
3780 * entry which has 12 bytes which is a regular entry
3781 * followed by 8 bytes data. ATM I don't know how
3782 * things are organized if we get next to the a
3783 * boundary so I worry about that once we try to handle
3786 evt->lpos = (evt->lpos + 4) % evt->length;
3793 /* Unmask interrupt */
3794 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3795 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3796 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3798 if (dwc->imod_interval) {
3799 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3800 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3803 /* Keep the clearing of DWC3_EVENT_PENDING at the end */
3804 evt->flags &= ~DWC3_EVENT_PENDING;
3809 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3811 struct dwc3_event_buffer *evt = _evt;
3812 struct dwc3 *dwc = evt->dwc;
3813 unsigned long flags;
3814 irqreturn_t ret = IRQ_NONE;
3817 spin_lock_irqsave(&dwc->lock, flags);
3818 ret = dwc3_process_event_buf(evt);
3819 spin_unlock_irqrestore(&dwc->lock, flags);
3825 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3827 struct dwc3 *dwc = evt->dwc;
3832 if (pm_runtime_suspended(dwc->dev)) {
3833 dwc->pending_events = true;
3835 * Trigger runtime resume. The get() function will be balanced
3836 * after processing the pending events in dwc3_process_pending
3839 pm_runtime_get(dwc->dev);
3840 disable_irq_nosync(dwc->irq_gadget);
3845 * With PCIe legacy interrupt, test shows that top-half irq handler can
3846 * be called again after HW interrupt deassertion. Check if bottom-half
3847 * irq event handler completes before caching new event to prevent
3850 if (evt->flags & DWC3_EVENT_PENDING)
3853 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3854 count &= DWC3_GEVNTCOUNT_MASK;
3859 evt->flags |= DWC3_EVENT_PENDING;
3861 /* Mask interrupt */
3862 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3863 reg |= DWC3_GEVNTSIZ_INTMASK;
3864 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3866 amount = min(count, evt->length - evt->lpos);
3867 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3870 memcpy(evt->cache, evt->buf, count - amount);
3872 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3874 return IRQ_WAKE_THREAD;
3877 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3879 struct dwc3_event_buffer *evt = _evt;
3881 return dwc3_check_event_buf(evt);
3884 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3886 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3889 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3893 if (irq == -EPROBE_DEFER)
3896 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3900 if (irq == -EPROBE_DEFER)
3903 irq = platform_get_irq(dwc3_pdev, 0);
3914 static void dwc_gadget_release(struct device *dev)
3916 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
3922 * dwc3_gadget_init - initializes gadget related registers
3923 * @dwc: pointer to our controller context structure
3925 * Returns 0 on success otherwise negative errno.
3927 int dwc3_gadget_init(struct dwc3 *dwc)
3933 irq = dwc3_gadget_get_irq(dwc);
3939 dwc->irq_gadget = irq;
3941 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3942 sizeof(*dwc->ep0_trb) * 2,
3943 &dwc->ep0_trb_addr, GFP_KERNEL);
3944 if (!dwc->ep0_trb) {
3945 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3950 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3951 if (!dwc->setup_buf) {
3956 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3957 &dwc->bounce_addr, GFP_KERNEL);
3963 init_completion(&dwc->ep0_in_setup);
3964 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
3971 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
3972 dev = &dwc->gadget->dev;
3973 dev->platform_data = dwc;
3974 dwc->gadget->ops = &dwc3_gadget_ops;
3975 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3976 dwc->gadget->sg_supported = true;
3977 dwc->gadget->name = "dwc3-gadget";
3978 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
3981 * FIXME We might be setting max_speed to <SUPER, however versions
3982 * <2.20a of dwc3 have an issue with metastability (documented
3983 * elsewhere in this driver) which tells us we can't set max speed to
3984 * anything lower than SUPER.
3986 * Because gadget.max_speed is only used by composite.c and function
3987 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3988 * to happen so we avoid sending SuperSpeed Capability descriptor
3989 * together with our BOS descriptor as that could confuse host into
3990 * thinking we can handle super speed.
3992 * Note that, in fact, we won't even support GetBOS requests when speed
3993 * is less than super speed because we don't have means, yet, to tell
3994 * composite.c that we are USB 2.0 + LPM ECN.
3996 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
3997 !dwc->dis_metastability_quirk)
3998 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4001 dwc->gadget->max_speed = dwc->maximum_speed;
4004 * REVISIT: Here we should clear all pending IRQs to be
4005 * sure we're starting from a well known location.
4008 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4012 ret = usb_add_gadget(dwc->gadget);
4014 dev_err(dwc->dev, "failed to add gadget\n");
4018 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4023 dwc3_gadget_free_endpoints(dwc);
4025 usb_put_gadget(dwc->gadget);
4028 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4032 kfree(dwc->setup_buf);
4035 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4036 dwc->ep0_trb, dwc->ep0_trb_addr);
4042 /* -------------------------------------------------------------------------- */
4044 void dwc3_gadget_exit(struct dwc3 *dwc)
4049 usb_del_gadget(dwc->gadget);
4050 dwc3_gadget_free_endpoints(dwc);
4051 usb_put_gadget(dwc->gadget);
4052 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4054 kfree(dwc->setup_buf);
4055 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4056 dwc->ep0_trb, dwc->ep0_trb_addr);
4059 int dwc3_gadget_suspend(struct dwc3 *dwc)
4061 if (!dwc->gadget_driver)
4064 dwc3_gadget_run_stop(dwc, false, false);
4065 dwc3_disconnect_gadget(dwc);
4066 __dwc3_gadget_stop(dwc);
4071 int dwc3_gadget_resume(struct dwc3 *dwc)
4075 if (!dwc->gadget_driver || !dwc->softconnect)
4078 ret = __dwc3_gadget_start(dwc);
4082 ret = dwc3_gadget_run_stop(dwc, true, false);
4089 __dwc3_gadget_stop(dwc);
4095 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4097 if (dwc->pending_events) {
4098 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4099 dwc3_thread_interrupt(dwc->irq_gadget, dwc->ev_buf);
4100 pm_runtime_put(dwc->dev);
4101 dwc->pending_events = false;
4102 enable_irq(dwc->irq_gadget);