1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
142 static void dwc3_ep0_reset_state(struct dwc3 *dwc)
146 if (dwc->ep0state != EP0_SETUP_PHASE) {
147 dir = !!dwc->ep0_expect_in;
148 if (dwc->ep0state == EP0_DATA_PHASE)
149 dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
151 dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
153 dwc->eps[0]->trb_enqueue = 0;
154 dwc->eps[1]->trb_enqueue = 0;
156 dwc3_ep0_stall_and_restart(dwc);
161 * dwc3_ep_inc_trb - increment a trb index.
162 * @index: Pointer to the TRB index to increment.
164 * The index should never point to the link TRB. After incrementing,
165 * if it is point to the link TRB, wrap around to the beginning. The
166 * link TRB is always at the last TRB entry.
168 static void dwc3_ep_inc_trb(u8 *index)
171 if (*index == (DWC3_TRB_NUM - 1))
176 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
177 * @dep: The endpoint whose enqueue pointer we're incrementing
179 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
181 dwc3_ep_inc_trb(&dep->trb_enqueue);
185 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
186 * @dep: The endpoint whose enqueue pointer we're incrementing
188 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
190 dwc3_ep_inc_trb(&dep->trb_dequeue);
193 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
194 struct dwc3_request *req, int status)
196 struct dwc3 *dwc = dep->dwc;
198 list_del(&req->list);
200 req->needs_extra_trb = false;
203 if (req->request.status == -EINPROGRESS)
204 req->request.status = status;
207 usb_gadget_unmap_request_by_dev(dwc->sysdev,
208 &req->request, req->direction);
211 trace_dwc3_gadget_giveback(req);
214 pm_runtime_put(dwc->dev);
218 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
219 * @dep: The endpoint to whom the request belongs to
220 * @req: The request we're giving back
221 * @status: completion code for the request
223 * Must be called with controller's lock held and interrupts disabled. This
224 * function will unmap @req and call its ->complete() callback to notify upper
225 * layers that it has completed.
227 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
230 struct dwc3 *dwc = dep->dwc;
232 dwc3_gadget_del_and_unmap_request(dep, req, status);
233 req->status = DWC3_REQUEST_STATUS_COMPLETED;
235 spin_unlock(&dwc->lock);
236 usb_gadget_giveback_request(&dep->endpoint, &req->request);
237 spin_lock(&dwc->lock);
241 * dwc3_send_gadget_generic_command - issue a generic command for the controller
242 * @dwc: pointer to the controller context
243 * @cmd: the command to be issued
244 * @param: command parameter
246 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
247 * and wait for its completion.
249 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
257 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
258 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
261 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
262 if (!(reg & DWC3_DGCMD_CMDACT)) {
263 status = DWC3_DGCMD_STATUS(reg);
275 trace_dwc3_gadget_generic_cmd(cmd, param, status);
280 static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
283 * dwc3_send_gadget_ep_cmd - issue an endpoint command
284 * @dep: the endpoint to which the command is going to be issued
285 * @cmd: the command to be issued
286 * @params: parameters to the command
288 * Caller should handle locking. This function will issue @cmd with given
289 * @params to @dep and wait for its completion.
291 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
292 struct dwc3_gadget_ep_cmd_params *params)
294 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
295 struct dwc3 *dwc = dep->dwc;
297 u32 saved_config = 0;
304 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
305 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
308 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
309 * settings. Restore them after the command is completed.
311 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
313 if (dwc->gadget->speed <= USB_SPEED_HIGH ||
314 DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
315 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
316 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
317 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
318 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
321 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
322 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
323 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
327 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
330 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
334 * Initiate remote wakeup if the link state is in U3 when
335 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
336 * link state is in U1/U2, no remote wakeup is needed. The Start
337 * Transfer command will initiate the link recovery.
339 link_state = dwc3_gadget_get_link_state(dwc);
340 switch (link_state) {
341 case DWC3_LINK_STATE_U2:
342 if (dwc->gadget->speed >= USB_SPEED_SUPER)
346 case DWC3_LINK_STATE_U3:
347 ret = __dwc3_gadget_wakeup(dwc, false);
348 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
355 * For some commands such as Update Transfer command, DEPCMDPARn
356 * registers are reserved. Since the driver often sends Update Transfer
357 * command, don't write to DEPCMDPARn to avoid register write delays and
358 * improve performance.
360 if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
361 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
362 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
363 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
367 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
368 * not relying on XferNotReady, we can make use of a special "No
369 * Response Update Transfer" command where we should clear both CmdAct
372 * With this, we don't need to wait for command completion and can
373 * straight away issue further commands to the endpoint.
375 * NOTICE: We're making an assumption that control endpoints will never
376 * make use of Update Transfer command. This is a safe assumption
377 * because we can never have more than one request at a time with
378 * Control Endpoints. If anybody changes that assumption, this chunk
379 * needs to be updated accordingly.
381 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
382 !usb_endpoint_xfer_isoc(desc))
383 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
385 cmd |= DWC3_DEPCMD_CMDACT;
387 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
389 if (!(cmd & DWC3_DEPCMD_CMDACT) ||
390 (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
391 !(cmd & DWC3_DEPCMD_CMDIOC))) {
397 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
398 if (!(reg & DWC3_DEPCMD_CMDACT)) {
399 cmd_status = DWC3_DEPCMD_STATUS(reg);
401 switch (cmd_status) {
405 case DEPEVT_TRANSFER_NO_RESOURCE:
406 dev_WARN(dwc->dev, "No resource for %s\n",
410 case DEPEVT_TRANSFER_BUS_EXPIRY:
412 * SW issues START TRANSFER command to
413 * isochronous ep with future frame interval. If
414 * future interval time has already passed when
415 * core receives the command, it will respond
416 * with an error status of 'Bus Expiry'.
418 * Instead of always returning -EINVAL, let's
419 * give a hint to the gadget driver that this is
420 * the case by returning -EAGAIN.
425 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
434 cmd_status = -ETIMEDOUT;
438 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
440 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
442 dep->flags |= DWC3_EP_TRANSFER_STARTED;
444 if (ret != -ETIMEDOUT)
445 dwc3_gadget_ep_get_transfer_index(dep);
449 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
451 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
457 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
459 struct dwc3 *dwc = dep->dwc;
460 struct dwc3_gadget_ep_cmd_params params;
461 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
464 * As of core revision 2.60a the recommended programming model
465 * is to set the ClearPendIN bit when issuing a Clear Stall EP
466 * command for IN endpoints. This is to prevent an issue where
467 * some (non-compliant) hosts may not send ACK TPs for pending
468 * IN transfers due to a mishandled error condition. Synopsys
471 if (dep->direction &&
472 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
473 (dwc->gadget->speed >= USB_SPEED_SUPER))
474 cmd |= DWC3_DEPCMD_CLEARPENDIN;
476 memset(¶ms, 0, sizeof(params));
478 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
481 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
482 struct dwc3_trb *trb)
484 u32 offset = (char *) trb - (char *) dep->trb_pool;
486 return dep->trb_pool_dma + offset;
489 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
491 struct dwc3 *dwc = dep->dwc;
496 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
497 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
498 &dep->trb_pool_dma, GFP_KERNEL);
499 if (!dep->trb_pool) {
500 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
508 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
510 struct dwc3 *dwc = dep->dwc;
512 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
513 dep->trb_pool, dep->trb_pool_dma);
515 dep->trb_pool = NULL;
516 dep->trb_pool_dma = 0;
519 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
521 struct dwc3_gadget_ep_cmd_params params;
523 memset(¶ms, 0x00, sizeof(params));
525 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
527 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
532 * dwc3_gadget_start_config - configure ep resources
533 * @dep: endpoint that is being enabled
535 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
536 * completion, it will set Transfer Resource for all available endpoints.
538 * The assignment of transfer resources cannot perfectly follow the data book
539 * due to the fact that the controller driver does not have all knowledge of the
540 * configuration in advance. It is given this information piecemeal by the
541 * composite gadget framework after every SET_CONFIGURATION and
542 * SET_INTERFACE. Trying to follow the databook programming model in this
543 * scenario can cause errors. For two reasons:
545 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
546 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
547 * incorrect in the scenario of multiple interfaces.
549 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
550 * endpoint on alt setting (8.1.6).
552 * The following simplified method is used instead:
554 * All hardware endpoints can be assigned a transfer resource and this setting
555 * will stay persistent until either a core reset or hibernation. So whenever we
556 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
557 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
558 * guaranteed that there are as many transfer resources as endpoints.
560 * This function is called for each endpoint when it is being enabled but is
561 * triggered only when called for EP0-out, which always happens first, and which
562 * should only happen in one of the above conditions.
564 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
566 struct dwc3_gadget_ep_cmd_params params;
575 memset(¶ms, 0x00, sizeof(params));
576 cmd = DWC3_DEPCMD_DEPSTARTCFG;
579 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
583 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
584 struct dwc3_ep *dep = dwc->eps[i];
589 ret = dwc3_gadget_set_xfer_resource(dep);
597 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
599 const struct usb_ss_ep_comp_descriptor *comp_desc;
600 const struct usb_endpoint_descriptor *desc;
601 struct dwc3_gadget_ep_cmd_params params;
602 struct dwc3 *dwc = dep->dwc;
604 comp_desc = dep->endpoint.comp_desc;
605 desc = dep->endpoint.desc;
607 memset(¶ms, 0x00, sizeof(params));
609 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
610 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
612 /* Burst size is only needed in SuperSpeed mode */
613 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
614 u32 burst = dep->endpoint.maxburst;
616 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
619 params.param0 |= action;
620 if (action == DWC3_DEPCFG_ACTION_RESTORE)
621 params.param2 |= dep->saved_state;
623 if (usb_endpoint_xfer_control(desc))
624 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
626 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
627 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
629 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
630 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
631 | DWC3_DEPCFG_XFER_COMPLETE_EN
632 | DWC3_DEPCFG_STREAM_EVENT_EN;
633 dep->stream_capable = true;
636 if (!usb_endpoint_xfer_control(desc))
637 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
640 * We are doing 1:1 mapping for endpoints, meaning
641 * Physical Endpoints 2 maps to Logical Endpoint 2 and
642 * so on. We consider the direction bit as part of the physical
643 * endpoint number. So USB endpoint 0x81 is 0x03.
645 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
648 * We must use the lower 16 TX FIFOs even though
652 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
654 if (desc->bInterval) {
658 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
660 * NOTE: The programming guide incorrectly stated bInterval_m1
661 * must be set to 0 when operating in fullspeed. Internally the
662 * controller does not have this limitation. See DWC_usb3x
663 * programming guide section 3.2.2.1.
665 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
667 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
668 dwc->gadget->speed == USB_SPEED_FULL)
669 dep->interval = desc->bInterval;
671 dep->interval = 1 << (desc->bInterval - 1);
673 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
676 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
680 * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
681 * @dwc: pointer to the DWC3 context
682 * @mult: multiplier to be used when calculating the fifo_size
684 * Calculates the size value based on the equation below:
686 * DWC3 revision 280A and prior:
687 * fifo_size = mult * (max_packet / mdwidth) + 1;
689 * DWC3 revision 290A and onwards:
690 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
692 * The max packet size is set to 1024, as the txfifo requirements mainly apply
693 * to super speed USB use cases. However, it is safe to overestimate the fifo
694 * allocations for other scenarios, i.e. high speed USB.
696 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
698 int max_packet = 1024;
702 mdwidth = dwc3_mdwidth(dwc);
704 /* MDWIDTH is represented in bits, we need it in bytes */
707 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
708 fifo_size = mult * (max_packet / mdwidth) + 1;
710 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
715 * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
716 * @dwc: pointer to the DWC3 context
718 * Iterates through all the endpoint registers and clears the previous txfifo
721 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
728 if (!dwc->do_fifo_resize)
731 /* Read ep0IN related TXFIFO size */
733 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
734 if (DWC3_IP_IS(DWC3))
735 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
737 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
739 dwc->last_fifo_depth = fifo_depth;
740 /* Clear existing TXFIFO for all IN eps except ep0 */
741 for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
744 /* Don't change TXFRAMNUM on usb31 version */
745 size = DWC3_IP_IS(DWC3) ? 0 :
746 dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
747 DWC31_GTXFIFOSIZ_TXFRAMNUM;
749 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
750 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
752 dwc->num_ep_resized = 0;
756 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
757 * @dwc: pointer to our context structure
759 * This function will a best effort FIFO allocation in order
760 * to improve FIFO usage and throughput, while still allowing
761 * us to enable as many endpoints as possible.
763 * Keep in mind that this operation will be highly dependent
764 * on the configured size for RAM1 - which contains TxFifo -,
765 * the amount of endpoints enabled on coreConsultant tool, and
766 * the width of the Master Bus.
768 * In general, FIFO depths are represented with the following equation:
770 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
772 * In conjunction with dwc3_gadget_check_config(), this resizing logic will
773 * ensure that all endpoints will have enough internal memory for one max
774 * packet per endpoint.
776 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
778 struct dwc3 *dwc = dep->dwc;
789 if (!dwc->do_fifo_resize)
792 /* resize IN endpoints except ep0 */
793 if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
796 /* bail if already resized */
797 if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
800 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
802 if ((dep->endpoint.maxburst > 1 &&
803 usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
804 usb_endpoint_xfer_isoc(dep->endpoint.desc))
807 if (dep->endpoint.maxburst > 6 &&
808 (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
809 usb_endpoint_xfer_isoc(dep->endpoint.desc)) && DWC3_IP_IS(DWC31))
810 num_fifos = dwc->tx_fifo_resize_max_num;
812 /* FIFO size for a single buffer */
813 fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
815 /* Calculate the number of remaining EPs w/o any FIFO */
816 num_in_ep = dwc->max_cfg_eps;
817 num_in_ep -= dwc->num_ep_resized;
819 /* Reserve at least one FIFO for the number of IN EPs */
820 min_depth = num_in_ep * (fifo + 1);
821 remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
822 remaining = max_t(int, 0, remaining);
824 * We've already reserved 1 FIFO per EP, so check what we can fit in
825 * addition to it. If there is not enough remaining space, allocate
826 * all the remaining space to the EP.
828 fifo_size = (num_fifos - 1) * fifo;
829 if (remaining < fifo_size)
830 fifo_size = remaining;
833 /* Last increment according to the TX FIFO size equation */
836 /* Check if TXFIFOs start at non-zero addr */
837 tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
838 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
840 fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
841 if (DWC3_IP_IS(DWC3))
842 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
844 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
846 /* Check fifo size allocation doesn't exceed available RAM size. */
847 if (dwc->last_fifo_depth >= ram1_depth) {
848 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
849 dwc->last_fifo_depth, ram1_depth,
850 dep->endpoint.name, fifo_size);
851 if (DWC3_IP_IS(DWC3))
852 fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
854 fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
856 dwc->last_fifo_depth -= fifo_size;
860 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
861 dep->flags |= DWC3_EP_TXFIFO_RESIZED;
862 dwc->num_ep_resized++;
868 * __dwc3_gadget_ep_enable - initializes a hw endpoint
869 * @dep: endpoint to be initialized
870 * @action: one of INIT, MODIFY or RESTORE
872 * Caller should take care of locking. Execute all necessary commands to
873 * initialize a HW endpoint so it can be used by a gadget driver.
875 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
877 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
878 struct dwc3 *dwc = dep->dwc;
883 if (!(dep->flags & DWC3_EP_ENABLED)) {
884 ret = dwc3_gadget_resize_tx_fifos(dep);
888 ret = dwc3_gadget_start_config(dep);
893 ret = dwc3_gadget_set_ep_config(dep, action);
897 if (!(dep->flags & DWC3_EP_ENABLED)) {
898 struct dwc3_trb *trb_st_hw;
899 struct dwc3_trb *trb_link;
901 dep->type = usb_endpoint_type(desc);
902 dep->flags |= DWC3_EP_ENABLED;
904 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
905 reg |= DWC3_DALEPENA_EP(dep->number);
906 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
908 dep->trb_dequeue = 0;
909 dep->trb_enqueue = 0;
911 if (usb_endpoint_xfer_control(desc))
914 /* Initialize the TRB ring */
915 memset(dep->trb_pool, 0,
916 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
918 /* Link TRB. The HWO bit is never reset */
919 trb_st_hw = &dep->trb_pool[0];
921 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
922 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
923 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
924 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
925 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
929 * Issue StartTransfer here with no-op TRB so we can always rely on No
930 * Response Update Transfer command.
932 if (usb_endpoint_xfer_bulk(desc) ||
933 usb_endpoint_xfer_int(desc)) {
934 struct dwc3_gadget_ep_cmd_params params;
935 struct dwc3_trb *trb;
939 memset(¶ms, 0, sizeof(params));
940 trb = &dep->trb_pool[0];
941 trb_dma = dwc3_trb_dma_offset(dep, trb);
943 params.param0 = upper_32_bits(trb_dma);
944 params.param1 = lower_32_bits(trb_dma);
946 cmd = DWC3_DEPCMD_STARTTRANSFER;
948 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
952 if (dep->stream_capable) {
954 * For streams, at start, there maybe a race where the
955 * host primes the endpoint before the function driver
956 * queues a request to initiate a stream. In that case,
957 * the controller will not see the prime to generate the
958 * ERDY and start stream. To workaround this, issue a
959 * no-op TRB as normal, but end it immediately. As a
960 * result, when the function driver queues the request,
961 * the next START_TRANSFER command will cause the
962 * controller to generate an ERDY to initiate the
965 dwc3_stop_active_transfer(dep, true, true);
968 * All stream eps will reinitiate stream on NoStream
969 * rejection until we can determine that the host can
970 * prime after the first transfer.
972 * However, if the controller is capable of
973 * TXF_FLUSH_BYPASS, then IN direction endpoints will
974 * automatically restart the stream without the driver
977 if (!dep->direction ||
978 !(dwc->hwparams.hwparams9 &
979 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
980 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
985 trace_dwc3_gadget_ep_enable(dep);
990 void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
992 struct dwc3_request *req;
994 dwc3_stop_active_transfer(dep, true, false);
996 /* If endxfer is delayed, avoid unmapping requests */
997 if (dep->flags & DWC3_EP_DELAY_STOP)
1000 /* - giveback all requests to gadget driver */
1001 while (!list_empty(&dep->started_list)) {
1002 req = next_request(&dep->started_list);
1004 dwc3_gadget_giveback(dep, req, status);
1007 while (!list_empty(&dep->pending_list)) {
1008 req = next_request(&dep->pending_list);
1010 dwc3_gadget_giveback(dep, req, status);
1013 while (!list_empty(&dep->cancelled_list)) {
1014 req = next_request(&dep->cancelled_list);
1016 dwc3_gadget_giveback(dep, req, status);
1021 * __dwc3_gadget_ep_disable - disables a hw endpoint
1022 * @dep: the endpoint to disable
1024 * This function undoes what __dwc3_gadget_ep_enable did and also removes
1025 * requests which are currently being processed by the hardware and those which
1026 * are not yet scheduled.
1028 * Caller should take care of locking.
1030 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1032 struct dwc3 *dwc = dep->dwc;
1036 trace_dwc3_gadget_ep_disable(dep);
1038 /* make sure HW endpoint isn't stalled */
1039 if (dep->flags & DWC3_EP_STALL)
1040 __dwc3_gadget_ep_set_halt(dep, 0, false);
1042 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1043 reg &= ~DWC3_DALEPENA_EP(dep->number);
1044 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1046 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1048 dep->stream_capable = false;
1050 mask = DWC3_EP_TXFIFO_RESIZED;
1052 * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
1053 * set. Do not clear DEP flags, so that the end transfer command will
1054 * be reattempted during the next SETUP stage.
1056 if (dep->flags & DWC3_EP_DELAY_STOP)
1057 mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
1060 /* Clear out the ep descriptors for non-ep0 */
1061 if (dep->number > 1) {
1062 dep->endpoint.comp_desc = NULL;
1063 dep->endpoint.desc = NULL;
1069 /* -------------------------------------------------------------------------- */
1071 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1072 const struct usb_endpoint_descriptor *desc)
1077 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1082 /* -------------------------------------------------------------------------- */
1084 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1085 const struct usb_endpoint_descriptor *desc)
1087 struct dwc3_ep *dep;
1089 unsigned long flags;
1092 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1093 pr_debug("dwc3: invalid parameters\n");
1097 if (!desc->wMaxPacketSize) {
1098 pr_debug("dwc3: missing wMaxPacketSize\n");
1102 dep = to_dwc3_ep(ep);
1105 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1106 "%s is already enabled\n",
1110 spin_lock_irqsave(&dwc->lock, flags);
1111 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1112 spin_unlock_irqrestore(&dwc->lock, flags);
1117 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1119 struct dwc3_ep *dep;
1121 unsigned long flags;
1125 pr_debug("dwc3: invalid parameters\n");
1129 dep = to_dwc3_ep(ep);
1132 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1133 "%s is already disabled\n",
1137 spin_lock_irqsave(&dwc->lock, flags);
1138 ret = __dwc3_gadget_ep_disable(dep);
1139 spin_unlock_irqrestore(&dwc->lock, flags);
1144 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1147 struct dwc3_request *req;
1148 struct dwc3_ep *dep = to_dwc3_ep(ep);
1150 req = kzalloc(sizeof(*req), gfp_flags);
1154 req->direction = dep->direction;
1155 req->epnum = dep->number;
1157 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
1159 trace_dwc3_alloc_request(req);
1161 return &req->request;
1164 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1165 struct usb_request *request)
1167 struct dwc3_request *req = to_dwc3_request(request);
1169 trace_dwc3_free_request(req);
1174 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1175 * @dep: The endpoint with the TRB ring
1176 * @index: The index of the current TRB in the ring
1178 * Returns the TRB prior to the one pointed to by the index. If the
1179 * index is 0, we will wrap backwards, skip the link TRB, and return
1180 * the one just before that.
1182 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1187 tmp = DWC3_TRB_NUM - 1;
1189 return &dep->trb_pool[tmp - 1];
1192 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1197 * If the enqueue & dequeue are equal then the TRB ring is either full
1198 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1199 * pending to be processed by the driver.
1201 if (dep->trb_enqueue == dep->trb_dequeue) {
1203 * If there is any request remained in the started_list at
1204 * this point, that means there is no TRB available.
1206 if (!list_empty(&dep->started_list))
1209 return DWC3_TRB_NUM - 1;
1212 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1213 trbs_left &= (DWC3_TRB_NUM - 1);
1215 if (dep->trb_dequeue < dep->trb_enqueue)
1222 * dwc3_prepare_one_trb - setup one TRB from one request
1223 * @dep: endpoint for which this request is prepared
1224 * @req: dwc3_request pointer
1225 * @trb_length: buffer size of the TRB
1226 * @chain: should this TRB be chained to the next?
1227 * @node: only for isochronous endpoints. First TRB needs different type.
1228 * @use_bounce_buffer: set to use bounce buffer
1229 * @must_interrupt: set to interrupt on TRB completion
1231 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1232 struct dwc3_request *req, unsigned int trb_length,
1233 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1234 bool must_interrupt)
1236 struct dwc3_trb *trb;
1238 unsigned int stream_id = req->request.stream_id;
1239 unsigned int short_not_ok = req->request.short_not_ok;
1240 unsigned int no_interrupt = req->request.no_interrupt;
1241 unsigned int is_last = req->request.is_last;
1242 struct dwc3 *dwc = dep->dwc;
1243 struct usb_gadget *gadget = dwc->gadget;
1244 enum usb_device_speed speed = gadget->speed;
1246 if (use_bounce_buffer)
1247 dma = dep->dwc->bounce_addr;
1248 else if (req->request.num_sgs > 0)
1249 dma = sg_dma_address(req->start_sg);
1251 dma = req->request.dma;
1253 trb = &dep->trb_pool[dep->trb_enqueue];
1256 dwc3_gadget_move_started_request(req);
1258 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1263 trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1264 trb->bpl = lower_32_bits(dma);
1265 trb->bph = upper_32_bits(dma);
1267 switch (usb_endpoint_type(dep->endpoint.desc)) {
1268 case USB_ENDPOINT_XFER_CONTROL:
1269 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1272 case USB_ENDPOINT_XFER_ISOC:
1274 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1277 * USB Specification 2.0 Section 5.9.2 states that: "If
1278 * there is only a single transaction in the microframe,
1279 * only a DATA0 data packet PID is used. If there are
1280 * two transactions per microframe, DATA1 is used for
1281 * the first transaction data packet and DATA0 is used
1282 * for the second transaction data packet. If there are
1283 * three transactions per microframe, DATA2 is used for
1284 * the first transaction data packet, DATA1 is used for
1285 * the second, and DATA0 is used for the third."
1287 * IOW, we should satisfy the following cases:
1289 * 1) length <= maxpacket
1292 * 2) maxpacket < length <= (2 * maxpacket)
1295 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1296 * - DATA2, DATA1, DATA0
1298 if (speed == USB_SPEED_HIGH) {
1299 struct usb_ep *ep = &dep->endpoint;
1300 unsigned int mult = 2;
1301 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1303 if (req->request.length <= (2 * maxp))
1306 if (req->request.length <= maxp)
1309 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1312 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1315 if (!no_interrupt && !chain)
1316 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1319 case USB_ENDPOINT_XFER_BULK:
1320 case USB_ENDPOINT_XFER_INT:
1321 trb->ctrl = DWC3_TRBCTL_NORMAL;
1325 * This is only possible with faulty memory because we
1326 * checked it already :)
1328 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1329 usb_endpoint_type(dep->endpoint.desc));
1333 * Enable Continue on Short Packet
1334 * when endpoint is not a stream capable
1336 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1337 if (!dep->stream_capable)
1338 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1341 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1344 /* All TRBs setup for MST must set CSP=1 when LST=0 */
1345 if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1346 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1348 if ((!no_interrupt && !chain) || must_interrupt)
1349 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1352 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1353 else if (dep->stream_capable && is_last &&
1354 !DWC3_MST_CAPABLE(&dwc->hwparams))
1355 trb->ctrl |= DWC3_TRB_CTRL_LST;
1357 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1358 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1361 * As per data book 4.2.3.2TRB Control Bit Rules section
1363 * The controller autonomously checks the HWO field of a TRB to determine if the
1364 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1365 * is valid before setting the HWO field to '1'. In most systems, this means that
1366 * software must update the fourth DWORD of a TRB last.
1368 * However there is a possibility of CPU re-ordering here which can cause
1369 * controller to observe the HWO bit set prematurely.
1370 * Add a write memory barrier to prevent CPU re-ordering.
1373 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1375 dwc3_ep_inc_enq(dep);
1377 trace_dwc3_prepare_trb(dep, trb);
1380 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1382 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1383 unsigned int rem = req->request.length % maxp;
1385 if ((req->request.length && req->request.zero && !rem &&
1386 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1387 (!req->direction && rem))
1394 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1395 * @dep: The endpoint that the request belongs to
1396 * @req: The request to prepare
1397 * @entry_length: The last SG entry size
1398 * @node: Indicates whether this is not the first entry (for isoc only)
1400 * Return the number of TRBs prepared.
1402 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1403 struct dwc3_request *req, unsigned int entry_length,
1406 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1407 unsigned int rem = req->request.length % maxp;
1408 unsigned int num_trbs = 1;
1410 if (dwc3_needs_extra_trb(dep, req))
1413 if (dwc3_calc_trbs_left(dep) < num_trbs)
1416 req->needs_extra_trb = num_trbs > 1;
1418 /* Prepare a normal TRB */
1419 if (req->direction || req->request.length)
1420 dwc3_prepare_one_trb(dep, req, entry_length,
1421 req->needs_extra_trb, node, false, false);
1423 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1424 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1425 dwc3_prepare_one_trb(dep, req,
1426 req->direction ? 0 : maxp - rem,
1427 false, 1, true, false);
1432 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1433 struct dwc3_request *req)
1435 struct scatterlist *sg = req->start_sg;
1436 struct scatterlist *s;
1438 unsigned int length = req->request.length;
1439 unsigned int remaining = req->request.num_mapped_sgs
1440 - req->num_queued_sgs;
1441 unsigned int num_trbs = req->num_trbs;
1442 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1445 * If we resume preparing the request, then get the remaining length of
1446 * the request and resume where we left off.
1448 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1449 length -= sg_dma_len(s);
1451 for_each_sg(sg, s, remaining, i) {
1452 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1453 unsigned int trb_length;
1454 bool must_interrupt = false;
1455 bool last_sg = false;
1457 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1459 length -= trb_length;
1462 * IOMMU driver is coalescing the list of sgs which shares a
1463 * page boundary into one and giving it to USB driver. With
1464 * this the number of sgs mapped is not equal to the number of
1465 * sgs passed. So mark the chain bit to false if it isthe last
1468 if ((i == remaining - 1) || !length)
1475 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1479 * Look ahead to check if we have enough TRBs for the
1480 * next SG entry. If not, set interrupt on this TRB to
1481 * resume preparing the next SG entry when more TRBs are
1484 if (num_trbs_left == 1 || (needs_extra_trb &&
1485 num_trbs_left <= 2 &&
1486 sg_dma_len(sg_next(s)) >= length)) {
1487 struct dwc3_request *r;
1489 /* Check if previous requests already set IOC */
1490 list_for_each_entry(r, &dep->started_list, list) {
1491 if (r != req && !r->request.no_interrupt)
1495 must_interrupt = true;
1499 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1504 * There can be a situation where all sgs in sglist are not
1505 * queued because of insufficient trb number. To handle this
1506 * case, update start_sg to next sg to be queued, so that
1507 * we have free trbs we can continue queuing from where we
1508 * previously stopped
1511 req->start_sg = sg_next(s);
1513 req->num_queued_sgs++;
1514 req->num_pending_sgs--;
1517 * The number of pending SG entries may not correspond to the
1518 * number of mapped SG entries. If all the data are queued, then
1519 * don't include unused SG entries.
1522 req->num_pending_sgs = 0;
1530 return req->num_trbs - num_trbs;
1533 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1534 struct dwc3_request *req)
1536 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1540 * dwc3_prepare_trbs - setup TRBs from requests
1541 * @dep: endpoint for which requests are being prepared
1543 * The function goes through the requests list and sets up TRBs for the
1544 * transfers. The function returns once there are no more TRBs available or
1545 * it runs out of requests.
1547 * Returns the number of TRBs prepared or negative errno.
1549 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1551 struct dwc3_request *req, *n;
1554 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1557 * We can get in a situation where there's a request in the started list
1558 * but there weren't enough TRBs to fully kick it in the first time
1559 * around, so it has been waiting for more TRBs to be freed up.
1561 * In that case, we should check if we have a request with pending_sgs
1562 * in the started list and prepare TRBs for that request first,
1563 * otherwise we will prepare TRBs completely out of order and that will
1566 list_for_each_entry(req, &dep->started_list, list) {
1567 if (req->num_pending_sgs > 0) {
1568 ret = dwc3_prepare_trbs_sg(dep, req);
1569 if (!ret || req->num_pending_sgs)
1573 if (!dwc3_calc_trbs_left(dep))
1577 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1578 * burst capability may try to read and use TRBs beyond the
1579 * active transfer instead of stopping.
1581 if (dep->stream_capable && req->request.is_last &&
1582 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1586 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1587 struct dwc3 *dwc = dep->dwc;
1589 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1594 req->sg = req->request.sg;
1595 req->start_sg = req->sg;
1596 req->num_queued_sgs = 0;
1597 req->num_pending_sgs = req->request.num_mapped_sgs;
1599 if (req->num_pending_sgs > 0) {
1600 ret = dwc3_prepare_trbs_sg(dep, req);
1601 if (req->num_pending_sgs)
1604 ret = dwc3_prepare_trbs_linear(dep, req);
1607 if (!ret || !dwc3_calc_trbs_left(dep))
1611 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1612 * burst capability may try to read and use TRBs beyond the
1613 * active transfer instead of stopping.
1615 if (dep->stream_capable && req->request.is_last &&
1616 !DWC3_MST_CAPABLE(&dwc->hwparams))
1623 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1625 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1627 struct dwc3_gadget_ep_cmd_params params;
1628 struct dwc3_request *req;
1634 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1635 * This happens when we need to stop and restart a transfer such as in
1636 * the case of reinitiating a stream or retrying an isoc transfer.
1638 ret = dwc3_prepare_trbs(dep);
1642 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1645 * If there's no new TRB prepared and we don't need to restart a
1646 * transfer, there's no need to update the transfer.
1648 if (!ret && !starting)
1651 req = next_request(&dep->started_list);
1653 dep->flags |= DWC3_EP_PENDING_REQUEST;
1657 memset(¶ms, 0, sizeof(params));
1660 params.param0 = upper_32_bits(req->trb_dma);
1661 params.param1 = lower_32_bits(req->trb_dma);
1662 cmd = DWC3_DEPCMD_STARTTRANSFER;
1664 if (dep->stream_capable)
1665 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1667 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1668 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1670 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1671 DWC3_DEPCMD_PARAM(dep->resource_index);
1674 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1676 struct dwc3_request *tmp;
1681 dwc3_stop_active_transfer(dep, true, true);
1683 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1684 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1686 /* If ep isn't started, then there's no end transfer pending */
1687 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1688 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1693 if (dep->stream_capable && req->request.is_last &&
1694 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1695 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1700 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1704 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1705 return DWC3_DSTS_SOFFN(reg);
1709 * __dwc3_stop_active_transfer - stop the current active transfer
1710 * @dep: isoc endpoint
1711 * @force: set forcerm bit in the command
1712 * @interrupt: command complete interrupt after End Transfer command
1714 * When setting force, the ForceRM bit will be set. In that case
1715 * the controller won't update the TRB progress on command
1716 * completion. It also won't clear the HWO bit in the TRB.
1717 * The command will also not complete immediately in that case.
1719 static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1721 struct dwc3 *dwc = dep->dwc;
1722 struct dwc3_gadget_ep_cmd_params params;
1726 cmd = DWC3_DEPCMD_ENDTRANSFER;
1727 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1728 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1729 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1730 memset(¶ms, 0, sizeof(params));
1731 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1733 * If the End Transfer command was timed out while the device is
1734 * not in SETUP phase, it's possible that an incoming Setup packet
1735 * may prevent the command's completion. Let's retry when the
1736 * ep0state returns to EP0_SETUP_PHASE.
1738 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
1739 dep->flags |= DWC3_EP_DELAY_STOP;
1743 dep->resource_index = 0;
1746 if (!DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC3, 310A))
1748 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1750 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1753 dep->flags &= ~DWC3_EP_DELAY_STOP;
1758 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1759 * @dep: isoc endpoint
1761 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1762 * microframe number reported by the XferNotReady event for the future frame
1763 * number to start the isoc transfer.
1765 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1766 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1767 * XferNotReady event are invalid. The driver uses this number to schedule the
1768 * isochronous transfer and passes it to the START TRANSFER command. Because
1769 * this number is invalid, the command may fail. If BIT[15:14] matches the
1770 * internal 16-bit microframe, the START TRANSFER command will pass and the
1771 * transfer will start at the scheduled time, if it is off by 1, the command
1772 * will still pass, but the transfer will start 2 seconds in the future. For all
1773 * other conditions, the START TRANSFER command will fail with bus-expiry.
1775 * In order to workaround this issue, we can test for the correct combination of
1776 * BIT[15:14] by sending START TRANSFER commands with different values of
1777 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1778 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1779 * As the result, within the 4 possible combinations for BIT[15:14], there will
1780 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1781 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1782 * value is the correct combination.
1784 * Since there are only 4 outcomes and the results are ordered, we can simply
1785 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1786 * deduce the smaller successful combination.
1788 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1789 * of BIT[15:14]. The correct combination is as follow:
1791 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1792 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1793 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1794 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1796 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1799 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1805 while (dep->combo_num < 2) {
1806 struct dwc3_gadget_ep_cmd_params params;
1807 u32 test_frame_number;
1811 * Check if we can start isoc transfer on the next interval or
1812 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1814 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1815 test_frame_number |= dep->combo_num << 14;
1816 test_frame_number += max_t(u32, 4, dep->interval);
1818 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1819 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1821 cmd = DWC3_DEPCMD_STARTTRANSFER;
1822 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1823 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1825 /* Redo if some other failure beside bus-expiry is received */
1826 if (cmd_status && cmd_status != -EAGAIN) {
1827 dep->start_cmd_status = 0;
1832 /* Store the first test status */
1833 if (dep->combo_num == 0)
1834 dep->start_cmd_status = cmd_status;
1839 * End the transfer if the START_TRANSFER command is successful
1840 * to wait for the next XferNotReady to test the command again
1842 if (cmd_status == 0) {
1843 dwc3_stop_active_transfer(dep, true, true);
1848 /* test0 and test1 are both completed at this point */
1849 test0 = (dep->start_cmd_status == 0);
1850 test1 = (cmd_status == 0);
1852 if (!test0 && test1)
1854 else if (!test0 && !test1)
1856 else if (test0 && !test1)
1858 else if (test0 && test1)
1861 dep->frame_number &= DWC3_FRNUMBER_MASK;
1862 dep->frame_number |= dep->combo_num << 14;
1863 dep->frame_number += max_t(u32, 4, dep->interval);
1865 /* Reinitialize test variables */
1866 dep->start_cmd_status = 0;
1869 return __dwc3_gadget_kick_transfer(dep);
1872 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1874 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1875 struct dwc3 *dwc = dep->dwc;
1879 if (list_empty(&dep->pending_list) &&
1880 list_empty(&dep->started_list)) {
1881 dep->flags |= DWC3_EP_PENDING_REQUEST;
1885 if (!dwc->dis_start_transfer_quirk &&
1886 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1887 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1888 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1889 return dwc3_gadget_start_isoc_quirk(dep);
1892 if (desc->bInterval <= 14 &&
1893 dwc->gadget->speed >= USB_SPEED_HIGH) {
1894 u32 frame = __dwc3_gadget_get_frame(dwc);
1895 bool rollover = frame <
1896 (dep->frame_number & DWC3_FRNUMBER_MASK);
1899 * frame_number is set from XferNotReady and may be already
1900 * out of date. DSTS only provides the lower 14 bit of the
1901 * current frame number. So add the upper two bits of
1902 * frame_number and handle a possible rollover.
1903 * This will provide the correct frame_number unless more than
1904 * rollover has happened since XferNotReady.
1907 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1910 dep->frame_number += BIT(14);
1913 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1914 int future_interval = i + 1;
1916 /* Give the controller at least 500us to schedule transfers */
1917 if (desc->bInterval < 3)
1918 future_interval += 3 - desc->bInterval;
1920 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1922 ret = __dwc3_gadget_kick_transfer(dep);
1928 * After a number of unsuccessful start attempts due to bus-expiry
1929 * status, issue END_TRANSFER command and retry on the next XferNotReady
1933 ret = __dwc3_stop_active_transfer(dep, false, true);
1938 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1940 struct dwc3 *dwc = dep->dwc;
1942 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1943 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1948 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1949 &req->request, req->dep->name))
1952 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1953 "%s: request %pK already in flight\n",
1954 dep->name, &req->request))
1957 pm_runtime_get(dwc->dev);
1959 req->request.actual = 0;
1960 req->request.status = -EINPROGRESS;
1962 trace_dwc3_ep_queue(req);
1964 list_add_tail(&req->list, &dep->pending_list);
1965 req->status = DWC3_REQUEST_STATUS_QUEUED;
1967 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1971 * Start the transfer only after the END_TRANSFER is completed
1972 * and endpoint STALL is cleared.
1974 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1975 (dep->flags & DWC3_EP_WEDGE) ||
1976 (dep->flags & DWC3_EP_DELAY_STOP) ||
1977 (dep->flags & DWC3_EP_STALL)) {
1978 dep->flags |= DWC3_EP_DELAY_START;
1983 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1984 * wait for a XferNotReady event so we will know what's the current
1985 * (micro-)frame number.
1987 * Without this trick, we are very, very likely gonna get Bus Expiry
1988 * errors which will force us issue EndTransfer command.
1990 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1991 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1992 if ((dep->flags & DWC3_EP_PENDING_REQUEST))
1993 return __dwc3_gadget_start_isoc(dep);
1999 __dwc3_gadget_kick_transfer(dep);
2004 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
2007 struct dwc3_request *req = to_dwc3_request(request);
2008 struct dwc3_ep *dep = to_dwc3_ep(ep);
2009 struct dwc3 *dwc = dep->dwc;
2011 unsigned long flags;
2015 spin_lock_irqsave(&dwc->lock, flags);
2016 ret = __dwc3_gadget_ep_queue(dep, req);
2017 spin_unlock_irqrestore(&dwc->lock, flags);
2022 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
2026 /* If req->trb is not set, then the request has not started */
2031 * If request was already started, this means we had to
2032 * stop the transfer. With that we also need to ignore
2033 * all TRBs used by the request, however TRBs can only
2034 * be modified after completion of END_TRANSFER
2035 * command. So what we do here is that we wait for
2036 * END_TRANSFER completion and only after that, we jump
2037 * over TRBs by clearing HWO and incrementing dequeue
2040 for (i = 0; i < req->num_trbs; i++) {
2041 struct dwc3_trb *trb;
2043 trb = &dep->trb_pool[dep->trb_dequeue];
2044 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2045 dwc3_ep_inc_deq(dep);
2051 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2053 struct dwc3_request *req;
2054 struct dwc3 *dwc = dep->dwc;
2056 while (!list_empty(&dep->cancelled_list)) {
2057 req = next_request(&dep->cancelled_list);
2058 dwc3_gadget_ep_skip_trbs(dep, req);
2059 switch (req->status) {
2060 case DWC3_REQUEST_STATUS_DISCONNECTED:
2061 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2063 case DWC3_REQUEST_STATUS_DEQUEUED:
2064 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2066 case DWC3_REQUEST_STATUS_STALLED:
2067 dwc3_gadget_giveback(dep, req, -EPIPE);
2070 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2071 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2075 * The endpoint is disabled, let the dwc3_remove_requests()
2076 * handle the cleanup.
2078 if (!dep->endpoint.desc)
2083 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2084 struct usb_request *request)
2086 struct dwc3_request *req = to_dwc3_request(request);
2087 struct dwc3_request *r = NULL;
2089 struct dwc3_ep *dep = to_dwc3_ep(ep);
2090 struct dwc3 *dwc = dep->dwc;
2092 unsigned long flags;
2095 trace_dwc3_ep_dequeue(req);
2097 spin_lock_irqsave(&dwc->lock, flags);
2099 list_for_each_entry(r, &dep->cancelled_list, list) {
2104 list_for_each_entry(r, &dep->pending_list, list) {
2107 * Explicitly check for EP0/1 as dequeue for those
2108 * EPs need to be handled differently. Control EP
2109 * only deals with one USB req, and giveback will
2110 * occur during dwc3_ep0_stall_and_restart(). EP0
2111 * requests are never added to started_list.
2113 if (dep->number > 1)
2114 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2116 dwc3_ep0_reset_state(dwc);
2121 list_for_each_entry(r, &dep->started_list, list) {
2123 struct dwc3_request *t;
2125 /* wait until it is processed */
2126 dwc3_stop_active_transfer(dep, true, true);
2129 * Remove any started request if the transfer is
2132 list_for_each_entry_safe(r, t, &dep->started_list, list)
2133 dwc3_gadget_move_cancelled_request(r,
2134 DWC3_REQUEST_STATUS_DEQUEUED);
2136 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2142 dev_err(dwc->dev, "request %pK was not queued to %s\n",
2146 spin_unlock_irqrestore(&dwc->lock, flags);
2151 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2153 struct dwc3_gadget_ep_cmd_params params;
2154 struct dwc3 *dwc = dep->dwc;
2155 struct dwc3_request *req;
2156 struct dwc3_request *tmp;
2159 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2160 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2164 memset(¶ms, 0x00, sizeof(params));
2167 struct dwc3_trb *trb;
2169 unsigned int transfer_in_flight;
2170 unsigned int started;
2172 if (dep->number > 1)
2173 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2175 trb = &dwc->ep0_trb[dep->trb_enqueue];
2177 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2178 started = !list_empty(&dep->started_list);
2180 if (!protocol && ((dep->direction && transfer_in_flight) ||
2181 (!dep->direction && started))) {
2185 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2188 dev_err(dwc->dev, "failed to set STALL on %s\n",
2191 dep->flags |= DWC3_EP_STALL;
2194 * Don't issue CLEAR_STALL command to control endpoints. The
2195 * controller automatically clears the STALL when it receives
2198 if (dep->number <= 1) {
2199 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2203 dwc3_stop_active_transfer(dep, true, true);
2205 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2206 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2208 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2209 (dep->flags & DWC3_EP_DELAY_STOP)) {
2210 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2212 dwc->clear_stall_protocol = dep->number;
2217 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2219 ret = dwc3_send_clear_stall_ep_cmd(dep);
2221 dev_err(dwc->dev, "failed to clear STALL on %s\n",
2226 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2228 if ((dep->flags & DWC3_EP_DELAY_START) &&
2229 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2230 __dwc3_gadget_kick_transfer(dep);
2232 dep->flags &= ~DWC3_EP_DELAY_START;
2238 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2240 struct dwc3_ep *dep = to_dwc3_ep(ep);
2241 struct dwc3 *dwc = dep->dwc;
2243 unsigned long flags;
2247 spin_lock_irqsave(&dwc->lock, flags);
2248 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2249 spin_unlock_irqrestore(&dwc->lock, flags);
2254 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2256 struct dwc3_ep *dep = to_dwc3_ep(ep);
2257 struct dwc3 *dwc = dep->dwc;
2258 unsigned long flags;
2261 spin_lock_irqsave(&dwc->lock, flags);
2262 dep->flags |= DWC3_EP_WEDGE;
2264 if (dep->number == 0 || dep->number == 1)
2265 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2267 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2268 spin_unlock_irqrestore(&dwc->lock, flags);
2273 /* -------------------------------------------------------------------------- */
2275 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2276 .bLength = USB_DT_ENDPOINT_SIZE,
2277 .bDescriptorType = USB_DT_ENDPOINT,
2278 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2281 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2282 .enable = dwc3_gadget_ep0_enable,
2283 .disable = dwc3_gadget_ep0_disable,
2284 .alloc_request = dwc3_gadget_ep_alloc_request,
2285 .free_request = dwc3_gadget_ep_free_request,
2286 .queue = dwc3_gadget_ep0_queue,
2287 .dequeue = dwc3_gadget_ep_dequeue,
2288 .set_halt = dwc3_gadget_ep0_set_halt,
2289 .set_wedge = dwc3_gadget_ep_set_wedge,
2292 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2293 .enable = dwc3_gadget_ep_enable,
2294 .disable = dwc3_gadget_ep_disable,
2295 .alloc_request = dwc3_gadget_ep_alloc_request,
2296 .free_request = dwc3_gadget_ep_free_request,
2297 .queue = dwc3_gadget_ep_queue,
2298 .dequeue = dwc3_gadget_ep_dequeue,
2299 .set_halt = dwc3_gadget_ep_set_halt,
2300 .set_wedge = dwc3_gadget_ep_set_wedge,
2303 /* -------------------------------------------------------------------------- */
2305 static void dwc3_gadget_enable_linksts_evts(struct dwc3 *dwc, bool set)
2309 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2312 reg = dwc3_readl(dwc->regs, DWC3_DEVTEN);
2314 reg |= DWC3_DEVTEN_ULSTCNGEN;
2316 reg &= ~DWC3_DEVTEN_ULSTCNGEN;
2318 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2321 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2323 struct dwc3 *dwc = gadget_to_dwc(g);
2325 return __dwc3_gadget_get_frame(dwc);
2328 static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async)
2338 * According to the Databook Remote wakeup request should
2339 * be issued only when the device is in early suspend state.
2341 * We can check that via USB Link State bits in DSTS register.
2343 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2345 link_state = DWC3_DSTS_USBLNKST(reg);
2347 switch (link_state) {
2348 case DWC3_LINK_STATE_RESET:
2349 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2350 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2351 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2352 case DWC3_LINK_STATE_U1:
2353 case DWC3_LINK_STATE_RESUME:
2360 dwc3_gadget_enable_linksts_evts(dwc, true);
2362 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2364 dev_err(dwc->dev, "failed to put link in Recovery\n");
2365 dwc3_gadget_enable_linksts_evts(dwc, false);
2369 /* Recent versions do this automatically */
2370 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2371 /* write zeroes to Link Change Request */
2372 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2373 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2374 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2378 * Since link status change events are enabled we will receive
2379 * an U0 event when wakeup is successful. So bail out.
2384 /* poll until Link State changes to ON */
2388 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2390 /* in HS, means ON */
2391 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2395 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2396 dev_err(dwc->dev, "failed to send remote wakeup\n");
2403 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2405 struct dwc3 *dwc = gadget_to_dwc(g);
2406 unsigned long flags;
2409 if (!dwc->wakeup_configured) {
2410 dev_err(dwc->dev, "remote wakeup not configured\n");
2414 spin_lock_irqsave(&dwc->lock, flags);
2415 if (!dwc->gadget->wakeup_armed) {
2416 dev_err(dwc->dev, "not armed for remote wakeup\n");
2417 spin_unlock_irqrestore(&dwc->lock, flags);
2420 ret = __dwc3_gadget_wakeup(dwc, true);
2422 spin_unlock_irqrestore(&dwc->lock, flags);
2427 static void dwc3_resume_gadget(struct dwc3 *dwc);
2429 static int dwc3_gadget_func_wakeup(struct usb_gadget *g, int intf_id)
2431 struct dwc3 *dwc = gadget_to_dwc(g);
2432 unsigned long flags;
2436 if (!dwc->wakeup_configured) {
2437 dev_err(dwc->dev, "remote wakeup not configured\n");
2441 spin_lock_irqsave(&dwc->lock, flags);
2443 * If the link is in U3, signal for remote wakeup and wait for the
2444 * link to transition to U0 before sending device notification.
2446 link_state = dwc3_gadget_get_link_state(dwc);
2447 if (link_state == DWC3_LINK_STATE_U3) {
2448 ret = __dwc3_gadget_wakeup(dwc, false);
2450 spin_unlock_irqrestore(&dwc->lock, flags);
2453 dwc3_resume_gadget(dwc);
2454 dwc->suspended = false;
2455 dwc->link_state = DWC3_LINK_STATE_U0;
2458 ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_DEV_NOTIFICATION,
2459 DWC3_DGCMDPAR_DN_FUNC_WAKE |
2460 DWC3_DGCMDPAR_INTF_SEL(intf_id));
2462 dev_err(dwc->dev, "function remote wakeup failed, ret:%d\n", ret);
2464 spin_unlock_irqrestore(&dwc->lock, flags);
2469 static int dwc3_gadget_set_remote_wakeup(struct usb_gadget *g, int set)
2471 struct dwc3 *dwc = gadget_to_dwc(g);
2472 unsigned long flags;
2474 spin_lock_irqsave(&dwc->lock, flags);
2475 dwc->wakeup_configured = !!set;
2476 spin_unlock_irqrestore(&dwc->lock, flags);
2481 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2484 struct dwc3 *dwc = gadget_to_dwc(g);
2485 unsigned long flags;
2487 spin_lock_irqsave(&dwc->lock, flags);
2488 g->is_selfpowered = !!is_selfpowered;
2489 spin_unlock_irqrestore(&dwc->lock, flags);
2494 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2498 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2499 struct dwc3_ep *dep;
2501 dep = dwc->eps[epnum];
2505 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2509 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2511 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2514 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2515 ssp_rate = dwc->max_ssp_rate;
2517 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2518 reg &= ~DWC3_DCFG_SPEED_MASK;
2519 reg &= ~DWC3_DCFG_NUMLANES(~0);
2521 if (ssp_rate == USB_SSP_GEN_1x2)
2522 reg |= DWC3_DCFG_SUPERSPEED;
2523 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2524 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2526 if (ssp_rate != USB_SSP_GEN_2x1 &&
2527 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2528 reg |= DWC3_DCFG_NUMLANES(1);
2530 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2533 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2535 enum usb_device_speed speed;
2538 speed = dwc->gadget_max_speed;
2539 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2540 speed = dwc->maximum_speed;
2542 if (speed == USB_SPEED_SUPER_PLUS &&
2543 DWC3_IP_IS(DWC32)) {
2544 __dwc3_gadget_set_ssp_rate(dwc);
2548 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2549 reg &= ~(DWC3_DCFG_SPEED_MASK);
2552 * WORKAROUND: DWC3 revision < 2.20a have an issue
2553 * which would cause metastability state on Run/Stop
2554 * bit if we try to force the IP to USB2-only mode.
2556 * Because of that, we cannot configure the IP to any
2557 * speed other than the SuperSpeed
2561 * STAR#9000525659: Clock Domain Crossing on DCTL in
2564 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2565 !dwc->dis_metastability_quirk) {
2566 reg |= DWC3_DCFG_SUPERSPEED;
2569 case USB_SPEED_FULL:
2570 reg |= DWC3_DCFG_FULLSPEED;
2572 case USB_SPEED_HIGH:
2573 reg |= DWC3_DCFG_HIGHSPEED;
2575 case USB_SPEED_SUPER:
2576 reg |= DWC3_DCFG_SUPERSPEED;
2578 case USB_SPEED_SUPER_PLUS:
2579 if (DWC3_IP_IS(DWC3))
2580 reg |= DWC3_DCFG_SUPERSPEED;
2582 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2585 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2587 if (DWC3_IP_IS(DWC3))
2588 reg |= DWC3_DCFG_SUPERSPEED;
2590 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2594 if (DWC3_IP_IS(DWC32) &&
2595 speed > USB_SPEED_UNKNOWN &&
2596 speed < USB_SPEED_SUPER_PLUS)
2597 reg &= ~DWC3_DCFG_NUMLANES(~0);
2599 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2602 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
2607 if (pm_runtime_suspended(dwc->dev))
2610 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2612 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2613 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2614 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2617 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2618 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2619 reg |= DWC3_DCTL_RUN_STOP;
2621 __dwc3_gadget_set_speed(dwc);
2622 dwc->pullups_connected = true;
2624 reg &= ~DWC3_DCTL_RUN_STOP;
2626 dwc->pullups_connected = false;
2629 dwc3_gadget_dctl_write_safe(dwc, reg);
2632 usleep_range(1000, 2000);
2633 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2634 reg &= DWC3_DSTS_DEVCTRLHLT;
2635 } while (--timeout && !(!is_on ^ !reg));
2643 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2644 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2645 static int __dwc3_gadget_start(struct dwc3 *dwc);
2647 static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2649 unsigned long flags;
2652 spin_lock_irqsave(&dwc->lock, flags);
2653 if (!dwc->pullups_connected) {
2654 spin_unlock_irqrestore(&dwc->lock, flags);
2658 dwc->connected = false;
2661 * Attempt to end pending SETUP status phase, and not wait for the
2662 * function to do so.
2664 if (dwc->delayed_status)
2665 dwc3_ep0_send_delayed_status(dwc);
2668 * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2669 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2670 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2671 * command for any active transfers" before clearing the RunStop
2674 dwc3_stop_active_transfers(dwc);
2675 spin_unlock_irqrestore(&dwc->lock, flags);
2678 * Per databook, when we want to stop the gadget, if a control transfer
2679 * is still in process, complete it and get the core into setup phase.
2680 * In case the host is unresponsive to a SETUP transaction, forcefully
2681 * stall the transfer, and move back to the SETUP phase, so that any
2682 * pending endxfers can be executed.
2684 if (dwc->ep0state != EP0_SETUP_PHASE) {
2685 reinit_completion(&dwc->ep0_in_setup);
2687 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2688 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2690 dev_warn(dwc->dev, "wait for SETUP phase timed out\n");
2691 spin_lock_irqsave(&dwc->lock, flags);
2692 dwc3_ep0_reset_state(dwc);
2693 spin_unlock_irqrestore(&dwc->lock, flags);
2698 * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2699 * driver needs to acknowledge them before the controller can halt.
2700 * Simply let the interrupt handler acknowledges and handle the
2701 * remaining event generated by the controller while polling for
2704 ret = dwc3_gadget_run_stop(dwc, false);
2707 * Stop the gadget after controller is halted, so that if needed, the
2708 * events to update EP0 state can still occur while the run/stop
2709 * routine polls for the halted state. DEVTEN is cleared as part of
2712 spin_lock_irqsave(&dwc->lock, flags);
2713 __dwc3_gadget_stop(dwc);
2714 spin_unlock_irqrestore(&dwc->lock, flags);
2719 static int dwc3_gadget_soft_connect(struct dwc3 *dwc)
2724 * In the Synopsys DWC_usb31 1.90a programming guide section
2725 * 4.1.9, it specifies that for a reconnect after a
2726 * device-initiated disconnect requires a core soft reset
2727 * (DCTL.CSftRst) before enabling the run/stop bit.
2729 ret = dwc3_core_soft_reset(dwc);
2733 dwc3_event_buffers_setup(dwc);
2734 __dwc3_gadget_start(dwc);
2735 return dwc3_gadget_run_stop(dwc, true);
2738 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2740 struct dwc3 *dwc = gadget_to_dwc(g);
2745 dwc->softconnect = is_on;
2748 * Avoid issuing a runtime resume if the device is already in the
2749 * suspended state during gadget disconnect. DWC3 gadget was already
2750 * halted/stopped during runtime suspend.
2753 pm_runtime_barrier(dwc->dev);
2754 if (pm_runtime_suspended(dwc->dev))
2759 * Check the return value for successful resume, or error. For a
2760 * successful resume, the DWC3 runtime PM resume routine will handle
2761 * the run stop sequence, so avoid duplicate operations here.
2763 ret = pm_runtime_get_sync(dwc->dev);
2764 if (!ret || ret < 0) {
2765 pm_runtime_put(dwc->dev);
2767 pm_runtime_set_suspended(dwc->dev);
2771 if (dwc->pullups_connected == is_on) {
2772 pm_runtime_put(dwc->dev);
2776 synchronize_irq(dwc->irq_gadget);
2779 ret = dwc3_gadget_soft_disconnect(dwc);
2781 ret = dwc3_gadget_soft_connect(dwc);
2783 pm_runtime_put(dwc->dev);
2788 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2792 /* Enable all but Start and End of Frame IRQs */
2793 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2794 DWC3_DEVTEN_CMDCMPLTEN |
2795 DWC3_DEVTEN_ERRTICERREN |
2796 DWC3_DEVTEN_WKUPEVTEN |
2797 DWC3_DEVTEN_CONNECTDONEEN |
2798 DWC3_DEVTEN_USBRSTEN |
2799 DWC3_DEVTEN_DISCONNEVTEN);
2801 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2802 reg |= DWC3_DEVTEN_ULSTCNGEN;
2804 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2805 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2806 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2808 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2811 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2813 /* mask all interrupts */
2814 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2817 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2818 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2821 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2822 * @dwc: pointer to our context structure
2824 * The following looks like complex but it's actually very simple. In order to
2825 * calculate the number of packets we can burst at once on OUT transfers, we're
2826 * gonna use RxFIFO size.
2828 * To calculate RxFIFO size we need two numbers:
2829 * MDWIDTH = size, in bits, of the internal memory bus
2830 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2832 * Given these two numbers, the formula is simple:
2834 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2836 * 24 bytes is for 3x SETUP packets
2837 * 16 bytes is a clock domain crossing tolerance
2839 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2841 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2848 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2849 mdwidth = dwc3_mdwidth(dwc);
2851 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2852 nump = min_t(u32, nump, 16);
2855 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2856 reg &= ~DWC3_DCFG_NUMP_MASK;
2857 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2858 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2861 static int __dwc3_gadget_start(struct dwc3 *dwc)
2863 struct dwc3_ep *dep;
2868 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2869 * the core supports IMOD, disable it.
2871 if (dwc->imod_interval) {
2872 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2873 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2874 } else if (dwc3_has_imod(dwc)) {
2875 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2879 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2880 * field instead of letting dwc3 itself calculate that automatically.
2882 * This way, we maximize the chances that we'll be able to get several
2883 * bursts of data without going through any sort of endpoint throttling.
2885 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2886 if (DWC3_IP_IS(DWC3))
2887 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2889 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2891 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2893 dwc3_gadget_setup_nump(dwc);
2896 * Currently the controller handles single stream only. So, Ignore
2897 * Packet Pending bit for stream selection and don't search for another
2898 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2899 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2900 * the stream performance.
2902 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2903 reg |= DWC3_DCFG_IGNSTRMPP;
2904 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2906 /* Enable MST by default if the device is capable of MST */
2907 if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2908 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2909 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2910 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2913 /* Start with SuperSpeed Default */
2914 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2918 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2920 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2926 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2928 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2932 /* begin to receive SETUP packets */
2933 dwc->ep0state = EP0_SETUP_PHASE;
2934 dwc->ep0_bounced = false;
2935 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2936 dwc->delayed_status = false;
2937 dwc3_ep0_out_start(dwc);
2939 dwc3_gadget_enable_irq(dwc);
2944 __dwc3_gadget_ep_disable(dwc->eps[0]);
2950 static int dwc3_gadget_start(struct usb_gadget *g,
2951 struct usb_gadget_driver *driver)
2953 struct dwc3 *dwc = gadget_to_dwc(g);
2954 unsigned long flags;
2958 irq = dwc->irq_gadget;
2959 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2960 IRQF_SHARED, "dwc3", dwc->ev_buf);
2962 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2967 spin_lock_irqsave(&dwc->lock, flags);
2968 dwc->gadget_driver = driver;
2969 spin_unlock_irqrestore(&dwc->lock, flags);
2974 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2976 dwc3_gadget_disable_irq(dwc);
2977 __dwc3_gadget_ep_disable(dwc->eps[0]);
2978 __dwc3_gadget_ep_disable(dwc->eps[1]);
2981 static int dwc3_gadget_stop(struct usb_gadget *g)
2983 struct dwc3 *dwc = gadget_to_dwc(g);
2984 unsigned long flags;
2986 spin_lock_irqsave(&dwc->lock, flags);
2987 dwc->gadget_driver = NULL;
2988 dwc->max_cfg_eps = 0;
2989 spin_unlock_irqrestore(&dwc->lock, flags);
2991 free_irq(dwc->irq_gadget, dwc->ev_buf);
2996 static void dwc3_gadget_config_params(struct usb_gadget *g,
2997 struct usb_dcd_config_params *params)
2999 struct dwc3 *dwc = gadget_to_dwc(g);
3001 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
3002 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
3004 /* Recommended BESL */
3005 if (!dwc->dis_enblslpm_quirk) {
3007 * If the recommended BESL baseline is 0 or if the BESL deep is
3008 * less than 2, Microsoft's Windows 10 host usb stack will issue
3009 * a usb reset immediately after it receives the extended BOS
3010 * descriptor and the enumeration will fail. To maintain
3011 * compatibility with the Windows' usb stack, let's set the
3012 * recommended BESL baseline to 1 and clamp the BESL deep to be
3015 params->besl_baseline = 1;
3016 if (dwc->is_utmi_l1_suspend)
3018 clamp_t(u8, dwc->hird_threshold, 2, 15);
3021 /* U1 Device exit Latency */
3022 if (dwc->dis_u1_entry_quirk)
3023 params->bU1devExitLat = 0;
3025 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
3027 /* U2 Device exit Latency */
3028 if (dwc->dis_u2_entry_quirk)
3029 params->bU2DevExitLat = 0;
3031 params->bU2DevExitLat =
3032 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
3035 static void dwc3_gadget_set_speed(struct usb_gadget *g,
3036 enum usb_device_speed speed)
3038 struct dwc3 *dwc = gadget_to_dwc(g);
3039 unsigned long flags;
3041 spin_lock_irqsave(&dwc->lock, flags);
3042 dwc->gadget_max_speed = speed;
3043 spin_unlock_irqrestore(&dwc->lock, flags);
3046 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
3047 enum usb_ssp_rate rate)
3049 struct dwc3 *dwc = gadget_to_dwc(g);
3050 unsigned long flags;
3052 spin_lock_irqsave(&dwc->lock, flags);
3053 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
3054 dwc->gadget_ssp_rate = rate;
3055 spin_unlock_irqrestore(&dwc->lock, flags);
3058 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
3060 struct dwc3 *dwc = gadget_to_dwc(g);
3061 union power_supply_propval val = {0};
3065 return usb_phy_set_power(dwc->usb2_phy, mA);
3070 val.intval = 1000 * mA;
3071 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
3077 * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
3078 * @g: pointer to the USB gadget
3080 * Used to record the maximum number of endpoints being used in a USB composite
3081 * device. (across all configurations) This is to be used in the calculation
3082 * of the TXFIFO sizes when resizing internal memory for individual endpoints.
3083 * It will help ensured that the resizing logic reserves enough space for at
3084 * least one max packet.
3086 static int dwc3_gadget_check_config(struct usb_gadget *g)
3088 struct dwc3 *dwc = gadget_to_dwc(g);
3094 if (!dwc->do_fifo_resize)
3097 list_for_each_entry(ep, &g->ep_list, ep_list) {
3098 /* Only interested in the IN endpoints */
3099 if (ep->claimed && (ep->address & USB_DIR_IN))
3103 if (ep_num <= dwc->max_cfg_eps)
3106 /* Update the max number of eps in the composition */
3107 dwc->max_cfg_eps = ep_num;
3109 fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
3110 /* Based on the equation, increment by one for every ep */
3111 fifo_size += dwc->max_cfg_eps;
3113 /* Check if we can fit a single fifo per endpoint */
3114 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
3115 if (fifo_size > ram1_depth)
3121 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
3123 struct dwc3 *dwc = gadget_to_dwc(g);
3124 unsigned long flags;
3126 spin_lock_irqsave(&dwc->lock, flags);
3127 dwc->async_callbacks = enable;
3128 spin_unlock_irqrestore(&dwc->lock, flags);
3131 static const struct usb_gadget_ops dwc3_gadget_ops = {
3132 .get_frame = dwc3_gadget_get_frame,
3133 .wakeup = dwc3_gadget_wakeup,
3134 .func_wakeup = dwc3_gadget_func_wakeup,
3135 .set_remote_wakeup = dwc3_gadget_set_remote_wakeup,
3136 .set_selfpowered = dwc3_gadget_set_selfpowered,
3137 .pullup = dwc3_gadget_pullup,
3138 .udc_start = dwc3_gadget_start,
3139 .udc_stop = dwc3_gadget_stop,
3140 .udc_set_speed = dwc3_gadget_set_speed,
3141 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
3142 .get_config_params = dwc3_gadget_config_params,
3143 .vbus_draw = dwc3_gadget_vbus_draw,
3144 .check_config = dwc3_gadget_check_config,
3145 .udc_async_callbacks = dwc3_gadget_async_callbacks,
3148 /* -------------------------------------------------------------------------- */
3150 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
3152 struct dwc3 *dwc = dep->dwc;
3154 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
3155 dep->endpoint.maxburst = 1;
3156 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
3157 if (!dep->direction)
3158 dwc->gadget->ep0 = &dep->endpoint;
3160 dep->endpoint.caps.type_control = true;
3165 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
3167 struct dwc3 *dwc = dep->dwc;
3172 mdwidth = dwc3_mdwidth(dwc);
3174 /* MDWIDTH is represented in bits, we need it in bytes */
3177 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3178 if (DWC3_IP_IS(DWC3))
3179 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3181 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
3184 * maxpacket size is determined as part of the following, after assuming
3185 * a mult value of one maxpacket:
3186 * DWC3 revision 280A and prior:
3187 * fifo_size = mult * (max_packet / mdwidth) + 1;
3188 * maxpacket = mdwidth * (fifo_size - 1);
3190 * DWC3 revision 290A and onwards:
3191 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3192 * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3194 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3195 maxpacket = mdwidth * (size - 1);
3197 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3199 /* Functionally, space for one max packet is sufficient */
3200 size = min_t(int, maxpacket, 1024);
3201 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3203 dep->endpoint.max_streams = 16;
3204 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3205 list_add_tail(&dep->endpoint.ep_list,
3206 &dwc->gadget->ep_list);
3207 dep->endpoint.caps.type_iso = true;
3208 dep->endpoint.caps.type_bulk = true;
3209 dep->endpoint.caps.type_int = true;
3211 return dwc3_alloc_trb_pool(dep);
3214 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3216 struct dwc3 *dwc = dep->dwc;
3220 mdwidth = dwc3_mdwidth(dwc);
3222 /* MDWIDTH is represented in bits, convert to bytes */
3225 /* All OUT endpoints share a single RxFIFO space */
3226 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3227 if (DWC3_IP_IS(DWC3))
3228 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3230 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3232 /* FIFO depth is in MDWDITH bytes */
3236 * To meet performance requirement, a minimum recommended RxFIFO size
3237 * is defined as follow:
3238 * RxFIFO size >= (3 x MaxPacketSize) +
3239 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3241 * Then calculate the max packet limit as below.
3243 size -= (3 * 8) + 16;
3249 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3250 dep->endpoint.max_streams = 16;
3251 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3252 list_add_tail(&dep->endpoint.ep_list,
3253 &dwc->gadget->ep_list);
3254 dep->endpoint.caps.type_iso = true;
3255 dep->endpoint.caps.type_bulk = true;
3256 dep->endpoint.caps.type_int = true;
3258 return dwc3_alloc_trb_pool(dep);
3261 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3263 struct dwc3_ep *dep;
3264 bool direction = epnum & 1;
3266 u8 num = epnum >> 1;
3268 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3273 dep->number = epnum;
3274 dep->direction = direction;
3275 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3276 dwc->eps[epnum] = dep;
3278 dep->start_cmd_status = 0;
3280 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3281 direction ? "in" : "out");
3283 dep->endpoint.name = dep->name;
3285 if (!(dep->number > 1)) {
3286 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3287 dep->endpoint.comp_desc = NULL;
3291 ret = dwc3_gadget_init_control_endpoint(dep);
3293 ret = dwc3_gadget_init_in_endpoint(dep);
3295 ret = dwc3_gadget_init_out_endpoint(dep);
3300 dep->endpoint.caps.dir_in = direction;
3301 dep->endpoint.caps.dir_out = !direction;
3303 INIT_LIST_HEAD(&dep->pending_list);
3304 INIT_LIST_HEAD(&dep->started_list);
3305 INIT_LIST_HEAD(&dep->cancelled_list);
3307 dwc3_debugfs_create_endpoint_dir(dep);
3312 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3316 INIT_LIST_HEAD(&dwc->gadget->ep_list);
3318 for (epnum = 0; epnum < total; epnum++) {
3321 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3329 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3331 struct dwc3_ep *dep;
3334 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3335 dep = dwc->eps[epnum];
3339 * Physical endpoints 0 and 1 are special; they form the
3340 * bi-directional USB endpoint 0.
3342 * For those two physical endpoints, we don't allocate a TRB
3343 * pool nor do we add them the endpoints list. Due to that, we
3344 * shouldn't do these two operations otherwise we would end up
3345 * with all sorts of bugs when removing dwc3.ko.
3347 if (epnum != 0 && epnum != 1) {
3348 dwc3_free_trb_pool(dep);
3349 list_del(&dep->endpoint.ep_list);
3352 dwc3_debugfs_remove_endpoint_dir(dep);
3357 /* -------------------------------------------------------------------------- */
3359 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3360 struct dwc3_request *req, struct dwc3_trb *trb,
3361 const struct dwc3_event_depevt *event, int status, int chain)
3365 dwc3_ep_inc_deq(dep);
3367 trace_dwc3_complete_trb(dep, trb);
3371 * If we're in the middle of series of chained TRBs and we
3372 * receive a short transfer along the way, DWC3 will skip
3373 * through all TRBs including the last TRB in the chain (the
3374 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3375 * bit and SW has to do it manually.
3377 * We're going to do that here to avoid problems of HW trying
3378 * to use bogus TRBs for transfers.
3380 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3381 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3384 * For isochronous transfers, the first TRB in a service interval must
3385 * have the Isoc-First type. Track and report its interval frame number.
3387 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3388 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3389 unsigned int frame_number;
3391 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3392 frame_number &= ~(dep->interval - 1);
3393 req->request.frame_number = frame_number;
3397 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3398 * this TRB points to the bounce buffer address, it's a MPS alignment
3399 * TRB. Don't add it to req->remaining calculation.
3401 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3402 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3403 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3407 count = trb->size & DWC3_TRB_SIZE_MASK;
3408 req->remaining += count;
3410 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3413 if (event->status & DEPEVT_STATUS_SHORT && !chain)
3416 if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3417 DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3420 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3421 (trb->ctrl & DWC3_TRB_CTRL_LST))
3427 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3428 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3431 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3432 struct scatterlist *sg = req->sg;
3433 struct scatterlist *s;
3434 unsigned int num_queued = req->num_queued_sgs;
3438 for_each_sg(sg, s, num_queued, i) {
3439 trb = &dep->trb_pool[dep->trb_dequeue];
3441 req->sg = sg_next(s);
3442 req->num_queued_sgs--;
3444 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3445 trb, event, status, true);
3453 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3454 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3457 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3459 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3460 event, status, false);
3463 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3465 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3468 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3469 const struct dwc3_event_depevt *event,
3470 struct dwc3_request *req, int status)
3475 if (req->request.num_mapped_sgs)
3476 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3479 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3482 req->request.actual = req->request.length - req->remaining;
3484 if (!dwc3_gadget_ep_request_completed(req))
3487 if (req->needs_extra_trb) {
3488 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3490 req->needs_extra_trb = false;
3494 * The event status only reflects the status of the TRB with IOC set.
3495 * For the requests that don't set interrupt on completion, the driver
3496 * needs to check and return the status of the completed TRBs associated
3497 * with the request. Use the status of the last TRB of the request.
3499 if (req->request.no_interrupt) {
3500 struct dwc3_trb *trb;
3502 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3503 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3504 case DWC3_TRBSTS_MISSED_ISOC:
3505 /* Isoc endpoint only */
3506 request_status = -EXDEV;
3508 case DWC3_TRB_STS_XFER_IN_PROG:
3509 /* Applicable when End Transfer with ForceRM=0 */
3510 case DWC3_TRBSTS_SETUP_PENDING:
3511 /* Control endpoint only */
3512 case DWC3_TRBSTS_OK:
3518 request_status = status;
3521 dwc3_gadget_giveback(dep, req, request_status);
3527 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3528 const struct dwc3_event_depevt *event, int status)
3530 struct dwc3_request *req;
3532 while (!list_empty(&dep->started_list)) {
3535 req = next_request(&dep->started_list);
3536 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3541 * The endpoint is disabled, let the dwc3_remove_requests()
3542 * handle the cleanup.
3544 if (!dep->endpoint.desc)
3549 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3551 struct dwc3_request *req;
3552 struct dwc3 *dwc = dep->dwc;
3554 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3558 if (!list_empty(&dep->pending_list))
3562 * We only need to check the first entry of the started list. We can
3563 * assume the completed requests are removed from the started list.
3565 req = next_request(&dep->started_list);
3569 return !dwc3_gadget_ep_request_completed(req);
3572 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3573 const struct dwc3_event_depevt *event)
3575 dep->frame_number = event->parameters;
3578 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3579 const struct dwc3_event_depevt *event, int status)
3581 struct dwc3 *dwc = dep->dwc;
3582 bool no_started_trb = true;
3584 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3586 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3589 if (!dep->endpoint.desc)
3590 return no_started_trb;
3592 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3593 list_empty(&dep->started_list) &&
3594 (list_empty(&dep->pending_list) || status == -EXDEV))
3595 dwc3_stop_active_transfer(dep, true, true);
3596 else if (dwc3_gadget_ep_should_continue(dep))
3597 if (__dwc3_gadget_kick_transfer(dep) == 0)
3598 no_started_trb = false;
3602 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3603 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3605 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3609 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3612 if (!(dep->flags & DWC3_EP_ENABLED))
3615 if (!list_empty(&dep->started_list))
3616 return no_started_trb;
3619 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3621 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3626 return no_started_trb;
3629 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3630 const struct dwc3_event_depevt *event)
3634 if (!dep->endpoint.desc)
3637 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3638 dwc3_gadget_endpoint_frame_from_event(dep, event);
3640 if (event->status & DEPEVT_STATUS_BUSERR)
3641 status = -ECONNRESET;
3643 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3646 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3649 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3650 const struct dwc3_event_depevt *event)
3654 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3656 if (event->status & DEPEVT_STATUS_BUSERR)
3657 status = -ECONNRESET;
3659 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3660 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3663 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3664 const struct dwc3_event_depevt *event)
3666 dwc3_gadget_endpoint_frame_from_event(dep, event);
3669 * The XferNotReady event is generated only once before the endpoint
3670 * starts. It will be generated again when END_TRANSFER command is
3671 * issued. For some controller versions, the XferNotReady event may be
3672 * generated while the END_TRANSFER command is still in process. Ignore
3673 * it and wait for the next XferNotReady event after the command is
3676 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3679 (void) __dwc3_gadget_start_isoc(dep);
3682 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3683 const struct dwc3_event_depevt *event)
3685 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3687 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3691 * The END_TRANSFER command will cause the controller to generate a
3692 * NoStream Event, and it's not due to the host DP NoStream rejection.
3693 * Ignore the next NoStream event.
3695 if (dep->stream_capable)
3696 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3698 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3699 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3700 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3702 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3703 struct dwc3 *dwc = dep->dwc;
3705 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3706 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3707 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3709 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3710 if (dwc->delayed_status)
3711 __dwc3_gadget_ep0_set_halt(ep0, 1);
3715 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3716 if (dwc->clear_stall_protocol == dep->number)
3717 dwc3_ep0_send_delayed_status(dwc);
3720 if ((dep->flags & DWC3_EP_DELAY_START) &&
3721 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3722 __dwc3_gadget_kick_transfer(dep);
3724 dep->flags &= ~DWC3_EP_DELAY_START;
3727 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3728 const struct dwc3_event_depevt *event)
3730 struct dwc3 *dwc = dep->dwc;
3732 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3733 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3737 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3738 switch (event->parameters) {
3739 case DEPEVT_STREAM_PRIME:
3741 * If the host can properly transition the endpoint state from
3742 * idle to prime after a NoStream rejection, there's no need to
3743 * force restarting the endpoint to reinitiate the stream. To
3744 * simplify the check, assume the host follows the USB spec if
3745 * it primed the endpoint more than once.
3747 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3748 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3749 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3751 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3755 case DEPEVT_STREAM_NOSTREAM:
3756 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3757 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3758 (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3759 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3763 * If the host rejects a stream due to no active stream, by the
3764 * USB and xHCI spec, the endpoint will be put back to idle
3765 * state. When the host is ready (buffer added/updated), it will
3766 * prime the endpoint to inform the usb device controller. This
3767 * triggers the device controller to issue ERDY to restart the
3768 * stream. However, some hosts don't follow this and keep the
3769 * endpoint in the idle state. No prime will come despite host
3770 * streams are updated, and the device controller will not be
3771 * triggered to generate ERDY to move the next stream data. To
3772 * workaround this and maintain compatibility with various
3773 * hosts, force to reinitiate the stream until the host is ready
3774 * instead of waiting for the host to prime the endpoint.
3776 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3777 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3779 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3781 dep->flags |= DWC3_EP_DELAY_START;
3782 dwc3_stop_active_transfer(dep, true, true);
3789 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3792 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3793 const struct dwc3_event_depevt *event)
3795 struct dwc3_ep *dep;
3796 u8 epnum = event->endpoint_number;
3798 dep = dwc->eps[epnum];
3800 if (!(dep->flags & DWC3_EP_ENABLED)) {
3801 if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
3804 /* Handle only EPCMDCMPLT when EP disabled */
3805 if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
3806 !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
3810 if (epnum == 0 || epnum == 1) {
3811 dwc3_ep0_interrupt(dwc, event);
3815 switch (event->endpoint_event) {
3816 case DWC3_DEPEVT_XFERINPROGRESS:
3817 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3819 case DWC3_DEPEVT_XFERNOTREADY:
3820 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3822 case DWC3_DEPEVT_EPCMDCMPLT:
3823 dwc3_gadget_endpoint_command_complete(dep, event);
3825 case DWC3_DEPEVT_XFERCOMPLETE:
3826 dwc3_gadget_endpoint_transfer_complete(dep, event);
3828 case DWC3_DEPEVT_STREAMEVT:
3829 dwc3_gadget_endpoint_stream_event(dep, event);
3831 case DWC3_DEPEVT_RXTXFIFOEVT:
3834 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
3839 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3841 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3842 spin_unlock(&dwc->lock);
3843 dwc->gadget_driver->disconnect(dwc->gadget);
3844 spin_lock(&dwc->lock);
3848 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3850 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3851 spin_unlock(&dwc->lock);
3852 dwc->gadget_driver->suspend(dwc->gadget);
3853 spin_lock(&dwc->lock);
3857 static void dwc3_resume_gadget(struct dwc3 *dwc)
3859 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3860 spin_unlock(&dwc->lock);
3861 dwc->gadget_driver->resume(dwc->gadget);
3862 spin_lock(&dwc->lock);
3866 static void dwc3_reset_gadget(struct dwc3 *dwc)
3868 if (!dwc->gadget_driver)
3871 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3872 spin_unlock(&dwc->lock);
3873 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3874 spin_lock(&dwc->lock);
3878 void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3881 struct dwc3 *dwc = dep->dwc;
3884 * Only issue End Transfer command to the control endpoint of a started
3885 * Data Phase. Typically we should only do so in error cases such as
3886 * invalid/unexpected direction as described in the control transfer
3887 * flow of the programming guide.
3889 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3892 if (interrupt && (dep->flags & DWC3_EP_DELAY_STOP))
3895 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3896 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3900 * If a Setup packet is received but yet to DMA out, the controller will
3901 * not process the End Transfer command of any endpoint. Polling of its
3902 * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3903 * timeout. Delay issuing the End Transfer command until the Setup TRB is
3906 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3907 dep->flags |= DWC3_EP_DELAY_STOP;
3912 * NOTICE: We are violating what the Databook says about the
3913 * EndTransfer command. Ideally we would _always_ wait for the
3914 * EndTransfer Command Completion IRQ, but that's causing too
3915 * much trouble synchronizing between us and gadget driver.
3917 * We have discussed this with the IP Provider and it was
3918 * suggested to giveback all requests here.
3920 * Note also that a similar handling was tested by Synopsys
3921 * (thanks a lot Paul) and nothing bad has come out of it.
3922 * In short, what we're doing is issuing EndTransfer with
3923 * CMDIOC bit set and delay kicking transfer until the
3924 * EndTransfer command had completed.
3926 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3927 * supports a mode to work around the above limitation. The
3928 * software can poll the CMDACT bit in the DEPCMD register
3929 * after issuing a EndTransfer command. This mode is enabled
3930 * by writing GUCTL2[14]. This polling is already done in the
3931 * dwc3_send_gadget_ep_cmd() function so if the mode is
3932 * enabled, the EndTransfer command will have completed upon
3933 * returning from this function.
3935 * This mode is NOT available on the DWC_usb31 IP. In this
3936 * case, if the IOC bit is not set, then delay by 1ms
3937 * after issuing the EndTransfer command. This allows for the
3938 * controller to handle the command completely before DWC3
3939 * remove requests attempts to unmap USB request buffers.
3942 __dwc3_stop_active_transfer(dep, force, interrupt);
3945 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3949 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3950 struct dwc3_ep *dep;
3953 dep = dwc->eps[epnum];
3957 if (!(dep->flags & DWC3_EP_STALL))
3960 dep->flags &= ~DWC3_EP_STALL;
3962 ret = dwc3_send_clear_stall_ep_cmd(dep);
3967 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3971 dwc->suspended = false;
3973 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3975 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3976 reg &= ~DWC3_DCTL_INITU1ENA;
3977 reg &= ~DWC3_DCTL_INITU2ENA;
3978 dwc3_gadget_dctl_write_safe(dwc, reg);
3980 dwc->connected = false;
3982 dwc3_disconnect_gadget(dwc);
3984 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3985 dwc->setup_packet_pending = false;
3986 dwc->gadget->wakeup_armed = false;
3987 dwc3_gadget_enable_linksts_evts(dwc, false);
3988 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3990 dwc3_ep0_reset_state(dwc);
3993 * Request PM idle to address condition where usage count is
3994 * already decremented to zero, but waiting for the disconnect
3995 * interrupt to set dwc->connected to FALSE.
3997 pm_request_idle(dwc->dev);
4000 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
4004 dwc->suspended = false;
4007 * Ideally, dwc3_reset_gadget() would trigger the function
4008 * drivers to stop any active transfers through ep disable.
4009 * However, for functions which defer ep disable, such as mass
4010 * storage, we will need to rely on the call to stop active
4011 * transfers here, and avoid allowing of request queuing.
4013 dwc->connected = false;
4016 * WORKAROUND: DWC3 revisions <1.88a have an issue which
4017 * would cause a missing Disconnect Event if there's a
4018 * pending Setup Packet in the FIFO.
4020 * There's no suggested workaround on the official Bug
4021 * report, which states that "unless the driver/application
4022 * is doing any special handling of a disconnect event,
4023 * there is no functional issue".
4025 * Unfortunately, it turns out that we _do_ some special
4026 * handling of a disconnect event, namely complete all
4027 * pending transfers, notify gadget driver of the
4028 * disconnection, and so on.
4030 * Our suggested workaround is to follow the Disconnect
4031 * Event steps here, instead, based on a setup_packet_pending
4032 * flag. Such flag gets set whenever we have a SETUP_PENDING
4033 * status for EP0 TRBs and gets cleared on XferComplete for the
4038 * STAR#9000466709: RTL: Device : Disconnect event not
4039 * generated if setup packet pending in FIFO
4041 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
4042 if (dwc->setup_packet_pending)
4043 dwc3_gadget_disconnect_interrupt(dwc);
4046 dwc3_reset_gadget(dwc);
4049 * From SNPS databook section 8.1.2, the EP0 should be in setup
4050 * phase. So ensure that EP0 is in setup phase by issuing a stall
4051 * and restart if EP0 is not in setup phase.
4053 dwc3_ep0_reset_state(dwc);
4056 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
4057 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
4058 * needs to ensure that it sends "a DEPENDXFER command for any active
4061 dwc3_stop_active_transfers(dwc);
4062 dwc->connected = true;
4064 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4065 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
4066 dwc3_gadget_dctl_write_safe(dwc, reg);
4067 dwc->test_mode = false;
4068 dwc->gadget->wakeup_armed = false;
4069 dwc3_gadget_enable_linksts_evts(dwc, false);
4070 dwc3_clear_stall_all_ep(dwc);
4072 /* Reset device address to zero */
4073 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4074 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
4075 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4078 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
4080 struct dwc3_ep *dep;
4086 if (!dwc->softconnect)
4089 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
4090 speed = reg & DWC3_DSTS_CONNECTSPD;
4093 if (DWC3_IP_IS(DWC32))
4094 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
4096 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4099 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
4100 * each time on Connect Done.
4102 * Currently we always use the reset value. If any platform
4103 * wants to set this to a different value, we need to add a
4104 * setting and update GCTL.RAMCLKSEL here.
4108 case DWC3_DSTS_SUPERSPEED_PLUS:
4109 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4110 dwc->gadget->ep0->maxpacket = 512;
4111 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4114 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
4116 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
4118 case DWC3_DSTS_SUPERSPEED:
4120 * WORKAROUND: DWC3 revisions <1.90a have an issue which
4121 * would cause a missing USB3 Reset event.
4123 * In such situations, we should force a USB3 Reset
4124 * event by calling our dwc3_gadget_reset_interrupt()
4129 * STAR#9000483510: RTL: SS : USB3 reset event may
4130 * not be generated always when the link enters poll
4132 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4133 dwc3_gadget_reset_interrupt(dwc);
4135 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4136 dwc->gadget->ep0->maxpacket = 512;
4137 dwc->gadget->speed = USB_SPEED_SUPER;
4140 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4141 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
4144 case DWC3_DSTS_HIGHSPEED:
4145 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4146 dwc->gadget->ep0->maxpacket = 64;
4147 dwc->gadget->speed = USB_SPEED_HIGH;
4149 case DWC3_DSTS_FULLSPEED:
4150 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4151 dwc->gadget->ep0->maxpacket = 64;
4152 dwc->gadget->speed = USB_SPEED_FULL;
4156 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
4158 /* Enable USB2 LPM Capability */
4160 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
4161 !dwc->usb2_gadget_lpm_disable &&
4162 (speed != DWC3_DSTS_SUPERSPEED) &&
4163 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4164 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4165 reg |= DWC3_DCFG_LPM_CAP;
4166 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4168 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4169 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4171 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
4172 (dwc->is_utmi_l1_suspend << 4));
4175 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
4176 * DCFG.LPMCap is set, core responses with an ACK and the
4177 * BESL value in the LPM token is less than or equal to LPM
4180 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
4181 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
4183 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
4184 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
4186 dwc3_gadget_dctl_write_safe(dwc, reg);
4188 if (dwc->usb2_gadget_lpm_disable) {
4189 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4190 reg &= ~DWC3_DCFG_LPM_CAP;
4191 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4194 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4195 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4196 dwc3_gadget_dctl_write_safe(dwc, reg);
4200 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4202 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4207 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4209 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4214 * Configure PHY via GUSB3PIPECTLn if required.
4216 * Update GTXFIFOSIZn
4218 * In both cases reset values should be sufficient.
4222 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc, unsigned int evtinfo)
4224 dwc->suspended = false;
4227 * TODO take core out of low power mode when that's
4231 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4232 spin_unlock(&dwc->lock);
4233 dwc->gadget_driver->resume(dwc->gadget);
4234 spin_lock(&dwc->lock);
4237 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
4240 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4241 unsigned int evtinfo)
4243 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4244 unsigned int pwropt;
4247 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4248 * Hibernation mode enabled which would show up when device detects
4249 * host-initiated U3 exit.
4251 * In that case, device will generate a Link State Change Interrupt
4252 * from U3 to RESUME which is only necessary if Hibernation is
4255 * There are no functional changes due to such spurious event and we
4256 * just need to ignore it.
4260 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4263 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4264 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4265 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4266 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4267 (next == DWC3_LINK_STATE_RESUME)) {
4273 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4274 * on the link partner, the USB session might do multiple entry/exit
4275 * of low power states before a transfer takes place.
4277 * Due to this problem, we might experience lower throughput. The
4278 * suggested workaround is to disable DCTL[12:9] bits if we're
4279 * transitioning from U1/U2 to U0 and enable those bits again
4280 * after a transfer completes and there are no pending transfers
4281 * on any of the enabled endpoints.
4283 * This is the first half of that workaround.
4287 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4288 * core send LGO_Ux entering U0
4290 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4291 if (next == DWC3_LINK_STATE_U0) {
4295 switch (dwc->link_state) {
4296 case DWC3_LINK_STATE_U1:
4297 case DWC3_LINK_STATE_U2:
4298 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4299 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4300 | DWC3_DCTL_ACCEPTU2ENA
4301 | DWC3_DCTL_INITU1ENA
4302 | DWC3_DCTL_ACCEPTU1ENA);
4305 dwc->u1u2 = reg & u1u2;
4309 dwc3_gadget_dctl_write_safe(dwc, reg);
4319 case DWC3_LINK_STATE_U0:
4320 if (dwc->gadget->wakeup_armed) {
4321 dwc3_gadget_enable_linksts_evts(dwc, false);
4322 dwc3_resume_gadget(dwc);
4323 dwc->suspended = false;
4326 case DWC3_LINK_STATE_U1:
4327 if (dwc->speed == USB_SPEED_SUPER)
4328 dwc3_suspend_gadget(dwc);
4330 case DWC3_LINK_STATE_U2:
4331 case DWC3_LINK_STATE_U3:
4332 dwc3_suspend_gadget(dwc);
4334 case DWC3_LINK_STATE_RESUME:
4335 dwc3_resume_gadget(dwc);
4342 dwc->link_state = next;
4345 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4346 unsigned int evtinfo)
4348 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4350 if (!dwc->suspended && next == DWC3_LINK_STATE_U3) {
4351 dwc->suspended = true;
4352 dwc3_suspend_gadget(dwc);
4355 dwc->link_state = next;
4358 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4359 const struct dwc3_event_devt *event)
4361 switch (event->type) {
4362 case DWC3_DEVICE_EVENT_DISCONNECT:
4363 dwc3_gadget_disconnect_interrupt(dwc);
4365 case DWC3_DEVICE_EVENT_RESET:
4366 dwc3_gadget_reset_interrupt(dwc);
4368 case DWC3_DEVICE_EVENT_CONNECT_DONE:
4369 dwc3_gadget_conndone_interrupt(dwc);
4371 case DWC3_DEVICE_EVENT_WAKEUP:
4372 dwc3_gadget_wakeup_interrupt(dwc, event->event_info);
4374 case DWC3_DEVICE_EVENT_HIBER_REQ:
4375 dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n");
4377 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4378 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4380 case DWC3_DEVICE_EVENT_SUSPEND:
4381 /* It changed to be suspend event for version 2.30a and above */
4382 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
4383 dwc3_gadget_suspend_interrupt(dwc, event->event_info);
4385 case DWC3_DEVICE_EVENT_SOF:
4386 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4387 case DWC3_DEVICE_EVENT_CMD_CMPL:
4388 case DWC3_DEVICE_EVENT_OVERFLOW:
4391 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4395 static void dwc3_process_event_entry(struct dwc3 *dwc,
4396 const union dwc3_event *event)
4398 trace_dwc3_event(event->raw, dwc);
4400 if (!event->type.is_devspec)
4401 dwc3_endpoint_interrupt(dwc, &event->depevt);
4402 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4403 dwc3_gadget_interrupt(dwc, &event->devt);
4405 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4408 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4410 struct dwc3 *dwc = evt->dwc;
4411 irqreturn_t ret = IRQ_NONE;
4416 if (!(evt->flags & DWC3_EVENT_PENDING))
4420 union dwc3_event event;
4422 event.raw = *(u32 *) (evt->cache + evt->lpos);
4424 dwc3_process_event_entry(dwc, &event);
4427 * FIXME we wrap around correctly to the next entry as
4428 * almost all entries are 4 bytes in size. There is one
4429 * entry which has 12 bytes which is a regular entry
4430 * followed by 8 bytes data. ATM I don't know how
4431 * things are organized if we get next to the a
4432 * boundary so I worry about that once we try to handle
4435 evt->lpos = (evt->lpos + 4) % evt->length;
4442 /* Unmask interrupt */
4443 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4444 DWC3_GEVNTSIZ_SIZE(evt->length));
4446 if (dwc->imod_interval) {
4447 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4448 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4451 /* Keep the clearing of DWC3_EVENT_PENDING at the end */
4452 evt->flags &= ~DWC3_EVENT_PENDING;
4457 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4459 struct dwc3_event_buffer *evt = _evt;
4460 struct dwc3 *dwc = evt->dwc;
4461 unsigned long flags;
4462 irqreturn_t ret = IRQ_NONE;
4465 spin_lock_irqsave(&dwc->lock, flags);
4466 ret = dwc3_process_event_buf(evt);
4467 spin_unlock_irqrestore(&dwc->lock, flags);
4473 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4475 struct dwc3 *dwc = evt->dwc;
4479 if (pm_runtime_suspended(dwc->dev)) {
4480 dwc->pending_events = true;
4482 * Trigger runtime resume. The get() function will be balanced
4483 * after processing the pending events in dwc3_process_pending
4486 pm_runtime_get(dwc->dev);
4487 disable_irq_nosync(dwc->irq_gadget);
4492 * With PCIe legacy interrupt, test shows that top-half irq handler can
4493 * be called again after HW interrupt deassertion. Check if bottom-half
4494 * irq event handler completes before caching new event to prevent
4497 if (evt->flags & DWC3_EVENT_PENDING)
4500 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4501 count &= DWC3_GEVNTCOUNT_MASK;
4506 evt->flags |= DWC3_EVENT_PENDING;
4508 /* Mask interrupt */
4509 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4510 DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4512 amount = min(count, evt->length - evt->lpos);
4513 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4516 memcpy(evt->cache, evt->buf, count - amount);
4518 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4520 return IRQ_WAKE_THREAD;
4523 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4525 struct dwc3_event_buffer *evt = _evt;
4527 return dwc3_check_event_buf(evt);
4530 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4532 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4535 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4539 if (irq == -EPROBE_DEFER)
4542 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4546 if (irq == -EPROBE_DEFER)
4549 irq = platform_get_irq(dwc3_pdev, 0);
4555 static void dwc_gadget_release(struct device *dev)
4557 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4563 * dwc3_gadget_init - initializes gadget related registers
4564 * @dwc: pointer to our controller context structure
4566 * Returns 0 on success otherwise negative errno.
4568 int dwc3_gadget_init(struct dwc3 *dwc)
4574 irq = dwc3_gadget_get_irq(dwc);
4580 dwc->irq_gadget = irq;
4582 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4583 sizeof(*dwc->ep0_trb) * 2,
4584 &dwc->ep0_trb_addr, GFP_KERNEL);
4585 if (!dwc->ep0_trb) {
4586 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4591 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4592 if (!dwc->setup_buf) {
4597 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4598 &dwc->bounce_addr, GFP_KERNEL);
4604 init_completion(&dwc->ep0_in_setup);
4605 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4612 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4613 dev = &dwc->gadget->dev;
4614 dev->platform_data = dwc;
4615 dwc->gadget->ops = &dwc3_gadget_ops;
4616 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4617 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4618 dwc->gadget->sg_supported = true;
4619 dwc->gadget->name = "dwc3-gadget";
4620 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4621 dwc->gadget->wakeup_capable = true;
4624 * FIXME We might be setting max_speed to <SUPER, however versions
4625 * <2.20a of dwc3 have an issue with metastability (documented
4626 * elsewhere in this driver) which tells us we can't set max speed to
4627 * anything lower than SUPER.
4629 * Because gadget.max_speed is only used by composite.c and function
4630 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4631 * to happen so we avoid sending SuperSpeed Capability descriptor
4632 * together with our BOS descriptor as that could confuse host into
4633 * thinking we can handle super speed.
4635 * Note that, in fact, we won't even support GetBOS requests when speed
4636 * is less than super speed because we don't have means, yet, to tell
4637 * composite.c that we are USB 2.0 + LPM ECN.
4639 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4640 !dwc->dis_metastability_quirk)
4641 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4644 dwc->gadget->max_speed = dwc->maximum_speed;
4645 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4648 * REVISIT: Here we should clear all pending IRQs to be
4649 * sure we're starting from a well known location.
4652 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4656 ret = usb_add_gadget(dwc->gadget);
4658 dev_err(dwc->dev, "failed to add gadget\n");
4662 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4663 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4665 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4670 dwc3_gadget_free_endpoints(dwc);
4672 usb_put_gadget(dwc->gadget);
4675 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4679 kfree(dwc->setup_buf);
4682 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4683 dwc->ep0_trb, dwc->ep0_trb_addr);
4689 /* -------------------------------------------------------------------------- */
4691 void dwc3_gadget_exit(struct dwc3 *dwc)
4696 usb_del_gadget(dwc->gadget);
4697 dwc3_gadget_free_endpoints(dwc);
4698 usb_put_gadget(dwc->gadget);
4699 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4701 kfree(dwc->setup_buf);
4702 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4703 dwc->ep0_trb, dwc->ep0_trb_addr);
4706 int dwc3_gadget_suspend(struct dwc3 *dwc)
4708 unsigned long flags;
4711 ret = dwc3_gadget_soft_disconnect(dwc);
4715 spin_lock_irqsave(&dwc->lock, flags);
4716 if (dwc->gadget_driver)
4717 dwc3_disconnect_gadget(dwc);
4718 spin_unlock_irqrestore(&dwc->lock, flags);
4724 * Attempt to reset the controller's state. Likely no
4725 * communication can be established until the host
4726 * performs a port reset.
4728 if (dwc->softconnect)
4729 dwc3_gadget_soft_connect(dwc);
4734 int dwc3_gadget_resume(struct dwc3 *dwc)
4736 if (!dwc->gadget_driver || !dwc->softconnect)
4739 return dwc3_gadget_soft_connect(dwc);
4742 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4744 if (dwc->pending_events) {
4745 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4746 dwc3_thread_interrupt(dwc->irq_gadget, dwc->ev_buf);
4747 pm_runtime_put(dwc->dev);
4748 dwc->pending_events = false;
4749 enable_irq(dwc->irq_gadget);