1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d) (((d)->frame_number + (d)->interval) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
60 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (dwc->revision >= DWC3_REVISION_194A) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set requested state */
115 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
119 * The following code is racy when called from dwc3_gadget_wakeup,
120 * and is not needed, at least on newer versions
122 if (dwc->revision >= DWC3_REVISION_194A)
125 /* wait for a change in DSTS */
128 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
130 if (DWC3_DSTS_USBLNKST(reg) == state)
140 * dwc3_ep_inc_trb - increment a trb index.
141 * @index: Pointer to the TRB index to increment.
143 * The index should never point to the link TRB. After incrementing,
144 * if it is point to the link TRB, wrap around to the beginning. The
145 * link TRB is always at the last TRB entry.
147 static void dwc3_ep_inc_trb(u8 *index)
150 if (*index == (DWC3_TRB_NUM - 1))
155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156 * @dep: The endpoint whose enqueue pointer we're incrementing
158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
160 dwc3_ep_inc_trb(&dep->trb_enqueue);
164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165 * @dep: The endpoint whose enqueue pointer we're incrementing
167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
169 dwc3_ep_inc_trb(&dep->trb_dequeue);
172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 struct dwc3_request *req, int status)
175 struct dwc3 *dwc = dep->dwc;
177 req->started = false;
178 list_del(&req->list);
180 req->needs_extra_trb = false;
182 if (req->request.status == -EINPROGRESS)
183 req->request.status = status;
186 usb_gadget_unmap_request_by_dev(dwc->sysdev,
187 &req->request, req->direction);
190 trace_dwc3_gadget_giveback(req);
193 pm_runtime_put(dwc->dev);
197 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
198 * @dep: The endpoint to whom the request belongs to
199 * @req: The request we're giving back
200 * @status: completion code for the request
202 * Must be called with controller's lock held and interrupts disabled. This
203 * function will unmap @req and call its ->complete() callback to notify upper
204 * layers that it has completed.
206 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
209 struct dwc3 *dwc = dep->dwc;
211 dwc3_gadget_del_and_unmap_request(dep, req, status);
213 spin_unlock(&dwc->lock);
214 usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 spin_lock(&dwc->lock);
219 * dwc3_send_gadget_generic_command - issue a generic command for the controller
220 * @dwc: pointer to the controller context
221 * @cmd: the command to be issued
222 * @param: command parameter
224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225 * and wait for its completion.
227 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 if (!(reg & DWC3_DGCMD_CMDACT)) {
240 status = DWC3_DGCMD_STATUS(reg);
252 trace_dwc3_gadget_generic_cmd(cmd, param, status);
257 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
260 * dwc3_send_gadget_ep_cmd - issue an endpoint command
261 * @dep: the endpoint to which the command is going to be issued
262 * @cmd: the command to be issued
263 * @params: parameters to the command
265 * Caller should handle locking. This function will issue @cmd with given
266 * @params to @dep and wait for its completion.
268 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 struct dwc3_gadget_ep_cmd_params *params)
271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 struct dwc3 *dwc = dep->dwc;
274 u32 saved_config = 0;
281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 * settings. Restore them after the command is completed.
288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
290 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
309 link_state = dwc3_gadget_get_link_state(dwc);
310 if (link_state == DWC3_LINK_STATE_U1 ||
311 link_state == DWC3_LINK_STATE_U2 ||
312 link_state == DWC3_LINK_STATE_U3) {
313 ret = __dwc3_gadget_wakeup(dwc);
314 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
319 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
324 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
325 * not relying on XferNotReady, we can make use of a special "No
326 * Response Update Transfer" command where we should clear both CmdAct
329 * With this, we don't need to wait for command completion and can
330 * straight away issue further commands to the endpoint.
332 * NOTICE: We're making an assumption that control endpoints will never
333 * make use of Update Transfer command. This is a safe assumption
334 * because we can never have more than one request at a time with
335 * Control Endpoints. If anybody changes that assumption, this chunk
336 * needs to be updated accordingly.
338 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
339 !usb_endpoint_xfer_isoc(desc))
340 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 cmd |= DWC3_DEPCMD_CMDACT;
344 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
347 if (!(reg & DWC3_DEPCMD_CMDACT)) {
348 cmd_status = DWC3_DEPCMD_STATUS(reg);
350 switch (cmd_status) {
354 case DEPEVT_TRANSFER_NO_RESOURCE:
357 case DEPEVT_TRANSFER_BUS_EXPIRY:
359 * SW issues START TRANSFER command to
360 * isochronous ep with future frame interval. If
361 * future interval time has already passed when
362 * core receives the command, it will respond
363 * with an error status of 'Bus Expiry'.
365 * Instead of always returning -EINVAL, let's
366 * give a hint to the gadget driver that this is
367 * the case by returning -EAGAIN.
372 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
381 cmd_status = -ETIMEDOUT;
384 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
386 if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
387 dep->flags |= DWC3_EP_TRANSFER_STARTED;
388 dwc3_gadget_ep_get_transfer_index(dep);
392 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
394 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
400 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402 struct dwc3 *dwc = dep->dwc;
403 struct dwc3_gadget_ep_cmd_params params;
404 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
407 * As of core revision 2.60a the recommended programming model
408 * is to set the ClearPendIN bit when issuing a Clear Stall EP
409 * command for IN endpoints. This is to prevent an issue where
410 * some (non-compliant) hosts may not send ACK TPs for pending
411 * IN transfers due to a mishandled error condition. Synopsys
414 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
415 (dwc->gadget.speed >= USB_SPEED_SUPER))
416 cmd |= DWC3_DEPCMD_CLEARPENDIN;
418 memset(¶ms, 0, sizeof(params));
420 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
423 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
424 struct dwc3_trb *trb)
426 u32 offset = (char *) trb - (char *) dep->trb_pool;
428 return dep->trb_pool_dma + offset;
431 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433 struct dwc3 *dwc = dep->dwc;
438 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
439 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
440 &dep->trb_pool_dma, GFP_KERNEL);
441 if (!dep->trb_pool) {
442 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
450 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452 struct dwc3 *dwc = dep->dwc;
454 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
455 dep->trb_pool, dep->trb_pool_dma);
457 dep->trb_pool = NULL;
458 dep->trb_pool_dma = 0;
461 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463 struct dwc3_gadget_ep_cmd_params params;
465 memset(¶ms, 0x00, sizeof(params));
467 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
474 * dwc3_gadget_start_config - configure ep resources
475 * @dep: endpoint that is being enabled
477 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
478 * completion, it will set Transfer Resource for all available endpoints.
480 * The assignment of transfer resources cannot perfectly follow the data book
481 * due to the fact that the controller driver does not have all knowledge of the
482 * configuration in advance. It is given this information piecemeal by the
483 * composite gadget framework after every SET_CONFIGURATION and
484 * SET_INTERFACE. Trying to follow the databook programming model in this
485 * scenario can cause errors. For two reasons:
487 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
488 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
489 * incorrect in the scenario of multiple interfaces.
491 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
492 * endpoint on alt setting (8.1.6).
494 * The following simplified method is used instead:
496 * All hardware endpoints can be assigned a transfer resource and this setting
497 * will stay persistent until either a core reset or hibernation. So whenever we
498 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
499 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
500 * guaranteed that there are as many transfer resources as endpoints.
502 * This function is called for each endpoint when it is being enabled but is
503 * triggered only when called for EP0-out, which always happens first, and which
504 * should only happen in one of the above conditions.
506 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
508 struct dwc3_gadget_ep_cmd_params params;
517 memset(¶ms, 0x00, sizeof(params));
518 cmd = DWC3_DEPCMD_DEPSTARTCFG;
521 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
525 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
526 struct dwc3_ep *dep = dwc->eps[i];
531 ret = dwc3_gadget_set_xfer_resource(dep);
539 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
541 const struct usb_ss_ep_comp_descriptor *comp_desc;
542 const struct usb_endpoint_descriptor *desc;
543 struct dwc3_gadget_ep_cmd_params params;
544 struct dwc3 *dwc = dep->dwc;
546 comp_desc = dep->endpoint.comp_desc;
547 desc = dep->endpoint.desc;
549 memset(¶ms, 0x00, sizeof(params));
551 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
552 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
554 /* Burst size is only needed in SuperSpeed mode */
555 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
556 u32 burst = dep->endpoint.maxburst;
557 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
560 params.param0 |= action;
561 if (action == DWC3_DEPCFG_ACTION_RESTORE)
562 params.param2 |= dep->saved_state;
564 if (usb_endpoint_xfer_control(desc))
565 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
567 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
568 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
570 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
571 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
572 | DWC3_DEPCFG_STREAM_EVENT_EN;
573 dep->stream_capable = true;
576 if (!usb_endpoint_xfer_control(desc))
577 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
580 * We are doing 1:1 mapping for endpoints, meaning
581 * Physical Endpoints 2 maps to Logical Endpoint 2 and
582 * so on. We consider the direction bit as part of the physical
583 * endpoint number. So USB endpoint 0x81 is 0x03.
585 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
588 * We must use the lower 16 TX FIFOs even though
592 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
594 if (desc->bInterval) {
598 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13, and it
599 * must be set to 0 when the controller operates in full-speed.
601 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
602 if (dwc->gadget.speed == USB_SPEED_FULL)
605 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
606 dwc->gadget.speed == USB_SPEED_FULL)
607 dep->interval = desc->bInterval;
609 dep->interval = 1 << (desc->bInterval - 1);
611 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
614 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
618 * __dwc3_gadget_ep_enable - initializes a hw endpoint
619 * @dep: endpoint to be initialized
620 * @action: one of INIT, MODIFY or RESTORE
622 * Caller should take care of locking. Execute all necessary commands to
623 * initialize a HW endpoint so it can be used by a gadget driver.
625 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
627 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
628 struct dwc3 *dwc = dep->dwc;
633 if (!(dep->flags & DWC3_EP_ENABLED)) {
634 ret = dwc3_gadget_start_config(dep);
639 ret = dwc3_gadget_set_ep_config(dep, action);
643 if (!(dep->flags & DWC3_EP_ENABLED)) {
644 struct dwc3_trb *trb_st_hw;
645 struct dwc3_trb *trb_link;
647 dep->type = usb_endpoint_type(desc);
648 dep->flags |= DWC3_EP_ENABLED;
649 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
651 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
652 reg |= DWC3_DALEPENA_EP(dep->number);
653 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
655 if (usb_endpoint_xfer_control(desc))
658 /* Initialize the TRB ring */
659 dep->trb_dequeue = 0;
660 dep->trb_enqueue = 0;
661 memset(dep->trb_pool, 0,
662 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
664 /* Link TRB. The HWO bit is never reset */
665 trb_st_hw = &dep->trb_pool[0];
667 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
668 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
669 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
670 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
671 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
675 * Issue StartTransfer here with no-op TRB so we can always rely on No
676 * Response Update Transfer command.
678 if (usb_endpoint_xfer_bulk(desc) ||
679 usb_endpoint_xfer_int(desc)) {
680 struct dwc3_gadget_ep_cmd_params params;
681 struct dwc3_trb *trb;
685 memset(¶ms, 0, sizeof(params));
686 trb = &dep->trb_pool[0];
687 trb_dma = dwc3_trb_dma_offset(dep, trb);
689 params.param0 = upper_32_bits(trb_dma);
690 params.param1 = lower_32_bits(trb_dma);
692 cmd = DWC3_DEPCMD_STARTTRANSFER;
694 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
700 trace_dwc3_gadget_ep_enable(dep);
705 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
707 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
709 struct dwc3_request *req;
711 dwc3_stop_active_transfer(dep, true, false);
713 /* - giveback all requests to gadget driver */
714 while (!list_empty(&dep->started_list)) {
715 req = next_request(&dep->started_list);
717 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
720 while (!list_empty(&dep->pending_list)) {
721 req = next_request(&dep->pending_list);
723 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
726 while (!list_empty(&dep->cancelled_list)) {
727 req = next_request(&dep->cancelled_list);
729 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
734 * __dwc3_gadget_ep_disable - disables a hw endpoint
735 * @dep: the endpoint to disable
737 * This function undoes what __dwc3_gadget_ep_enable did and also removes
738 * requests which are currently being processed by the hardware and those which
739 * are not yet scheduled.
741 * Caller should take care of locking.
743 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
745 struct dwc3 *dwc = dep->dwc;
748 trace_dwc3_gadget_ep_disable(dep);
750 dwc3_remove_requests(dwc, dep);
752 /* make sure HW endpoint isn't stalled */
753 if (dep->flags & DWC3_EP_STALL)
754 __dwc3_gadget_ep_set_halt(dep, 0, false);
756 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
757 reg &= ~DWC3_DALEPENA_EP(dep->number);
758 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
760 dep->stream_capable = false;
762 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
764 /* Clear out the ep descriptors for non-ep0 */
765 if (dep->number > 1) {
766 dep->endpoint.comp_desc = NULL;
767 dep->endpoint.desc = NULL;
773 /* -------------------------------------------------------------------------- */
775 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
776 const struct usb_endpoint_descriptor *desc)
781 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
786 /* -------------------------------------------------------------------------- */
788 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
789 const struct usb_endpoint_descriptor *desc)
796 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
797 pr_debug("dwc3: invalid parameters\n");
801 if (!desc->wMaxPacketSize) {
802 pr_debug("dwc3: missing wMaxPacketSize\n");
806 dep = to_dwc3_ep(ep);
809 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
810 "%s is already enabled\n",
814 spin_lock_irqsave(&dwc->lock, flags);
815 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
816 spin_unlock_irqrestore(&dwc->lock, flags);
821 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
829 pr_debug("dwc3: invalid parameters\n");
833 dep = to_dwc3_ep(ep);
836 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
837 "%s is already disabled\n",
841 spin_lock_irqsave(&dwc->lock, flags);
842 ret = __dwc3_gadget_ep_disable(dep);
843 spin_unlock_irqrestore(&dwc->lock, flags);
848 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
851 struct dwc3_request *req;
852 struct dwc3_ep *dep = to_dwc3_ep(ep);
854 req = kzalloc(sizeof(*req), gfp_flags);
858 req->direction = dep->direction;
859 req->epnum = dep->number;
862 trace_dwc3_alloc_request(req);
864 return &req->request;
867 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
868 struct usb_request *request)
870 struct dwc3_request *req = to_dwc3_request(request);
872 trace_dwc3_free_request(req);
877 * dwc3_ep_prev_trb - returns the previous TRB in the ring
878 * @dep: The endpoint with the TRB ring
879 * @index: The index of the current TRB in the ring
881 * Returns the TRB prior to the one pointed to by the index. If the
882 * index is 0, we will wrap backwards, skip the link TRB, and return
883 * the one just before that.
885 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
890 tmp = DWC3_TRB_NUM - 1;
892 return &dep->trb_pool[tmp - 1];
895 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
900 * If the enqueue & dequeue are equal then the TRB ring is either full
901 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
902 * pending to be processed by the driver.
904 if (dep->trb_enqueue == dep->trb_dequeue) {
906 * If there is any request remained in the started_list at
907 * this point, that means there is no TRB available.
909 if (!list_empty(&dep->started_list))
912 return DWC3_TRB_NUM - 1;
915 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
916 trbs_left &= (DWC3_TRB_NUM - 1);
918 if (dep->trb_dequeue < dep->trb_enqueue)
924 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
925 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
926 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
928 struct dwc3 *dwc = dep->dwc;
929 struct usb_gadget *gadget = &dwc->gadget;
930 enum usb_device_speed speed = gadget->speed;
932 trb->size = DWC3_TRB_SIZE_LENGTH(length);
933 trb->bpl = lower_32_bits(dma);
934 trb->bph = upper_32_bits(dma);
936 switch (usb_endpoint_type(dep->endpoint.desc)) {
937 case USB_ENDPOINT_XFER_CONTROL:
938 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
941 case USB_ENDPOINT_XFER_ISOC:
943 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
946 * USB Specification 2.0 Section 5.9.2 states that: "If
947 * there is only a single transaction in the microframe,
948 * only a DATA0 data packet PID is used. If there are
949 * two transactions per microframe, DATA1 is used for
950 * the first transaction data packet and DATA0 is used
951 * for the second transaction data packet. If there are
952 * three transactions per microframe, DATA2 is used for
953 * the first transaction data packet, DATA1 is used for
954 * the second, and DATA0 is used for the third."
956 * IOW, we should satisfy the following cases:
958 * 1) length <= maxpacket
961 * 2) maxpacket < length <= (2 * maxpacket)
964 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
965 * - DATA2, DATA1, DATA0
967 if (speed == USB_SPEED_HIGH) {
968 struct usb_ep *ep = &dep->endpoint;
969 unsigned int mult = 2;
970 unsigned int maxp = usb_endpoint_maxp(ep->desc);
972 if (length <= (2 * maxp))
978 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
981 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
984 /* always enable Interrupt on Missed ISOC */
985 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
988 case USB_ENDPOINT_XFER_BULK:
989 case USB_ENDPOINT_XFER_INT:
990 trb->ctrl = DWC3_TRBCTL_NORMAL;
994 * This is only possible with faulty memory because we
995 * checked it already :)
997 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
998 usb_endpoint_type(dep->endpoint.desc));
1002 * Enable Continue on Short Packet
1003 * when endpoint is not a stream capable
1005 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1006 if (!dep->stream_capable)
1007 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1010 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1013 if ((!no_interrupt && !chain) ||
1014 (dwc3_calc_trbs_left(dep) == 1))
1015 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1018 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1020 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1021 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1023 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1025 dwc3_ep_inc_enq(dep);
1027 trace_dwc3_prepare_trb(dep, trb);
1031 * dwc3_prepare_one_trb - setup one TRB from one request
1032 * @dep: endpoint for which this request is prepared
1033 * @req: dwc3_request pointer
1034 * @trb_length: buffer size of the TRB
1035 * @chain: should this TRB be chained to the next?
1036 * @node: only for isochronous endpoints. First TRB needs different type.
1038 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1039 struct dwc3_request *req, unsigned int trb_length,
1040 unsigned chain, unsigned node)
1042 struct dwc3_trb *trb;
1044 unsigned stream_id = req->request.stream_id;
1045 unsigned short_not_ok = req->request.short_not_ok;
1046 unsigned no_interrupt = req->request.no_interrupt;
1048 if (req->request.num_sgs > 0)
1049 dma = sg_dma_address(req->start_sg);
1051 dma = req->request.dma;
1053 trb = &dep->trb_pool[dep->trb_enqueue];
1056 dwc3_gadget_move_started_request(req);
1058 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1063 __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1064 stream_id, short_not_ok, no_interrupt);
1067 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1068 struct dwc3_request *req)
1070 struct scatterlist *sg = req->start_sg;
1071 struct scatterlist *s;
1073 unsigned int length = req->request.length;
1074 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1075 unsigned int rem = length % maxp;
1076 unsigned int remaining = req->request.num_mapped_sgs
1077 - req->num_queued_sgs;
1080 * If we resume preparing the request, then get the remaining length of
1081 * the request and resume where we left off.
1083 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1084 length -= sg_dma_len(s);
1086 for_each_sg(sg, s, remaining, i) {
1087 unsigned int trb_length;
1088 unsigned chain = true;
1090 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1092 length -= trb_length;
1095 * IOMMU driver is coalescing the list of sgs which shares a
1096 * page boundary into one and giving it to USB driver. With
1097 * this the number of sgs mapped is not equal to the number of
1098 * sgs passed. So mark the chain bit to false if it isthe last
1101 if ((i == remaining - 1) || !length)
1104 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1105 struct dwc3 *dwc = dep->dwc;
1106 struct dwc3_trb *trb;
1108 req->needs_extra_trb = true;
1110 /* prepare normal TRB */
1111 dwc3_prepare_one_trb(dep, req, trb_length, true, i);
1113 /* Now prepare one extra TRB to align transfer size */
1114 trb = &dep->trb_pool[dep->trb_enqueue];
1116 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1117 maxp - rem, false, 1,
1118 req->request.stream_id,
1119 req->request.short_not_ok,
1120 req->request.no_interrupt);
1121 } else if (req->request.zero && req->request.length &&
1122 !usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1124 struct dwc3 *dwc = dep->dwc;
1125 struct dwc3_trb *trb;
1127 req->needs_extra_trb = true;
1129 /* Prepare normal TRB */
1130 dwc3_prepare_one_trb(dep, req, trb_length, true, i);
1132 /* Prepare one extra TRB to handle ZLP */
1133 trb = &dep->trb_pool[dep->trb_enqueue];
1135 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1137 req->request.stream_id,
1138 req->request.short_not_ok,
1139 req->request.no_interrupt);
1141 /* Prepare one more TRB to handle MPS alignment */
1142 if (!req->direction) {
1143 trb = &dep->trb_pool[dep->trb_enqueue];
1145 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp,
1146 false, 1, req->request.stream_id,
1147 req->request.short_not_ok,
1148 req->request.no_interrupt);
1151 dwc3_prepare_one_trb(dep, req, trb_length, chain, i);
1155 * There can be a situation where all sgs in sglist are not
1156 * queued because of insufficient trb number. To handle this
1157 * case, update start_sg to next sg to be queued, so that
1158 * we have free trbs we can continue queuing from where we
1159 * previously stopped
1162 req->start_sg = sg_next(s);
1164 req->num_queued_sgs++;
1165 req->num_pending_sgs--;
1168 * The number of pending SG entries may not correspond to the
1169 * number of mapped SG entries. If all the data are queued, then
1170 * don't include unused SG entries.
1173 req->num_pending_sgs = 0;
1177 if (!dwc3_calc_trbs_left(dep))
1182 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1183 struct dwc3_request *req)
1185 unsigned int length = req->request.length;
1186 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1187 unsigned int rem = length % maxp;
1189 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1190 struct dwc3 *dwc = dep->dwc;
1191 struct dwc3_trb *trb;
1193 req->needs_extra_trb = true;
1195 /* prepare normal TRB */
1196 dwc3_prepare_one_trb(dep, req, length, true, 0);
1198 /* Now prepare one extra TRB to align transfer size */
1199 trb = &dep->trb_pool[dep->trb_enqueue];
1201 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1202 false, 1, req->request.stream_id,
1203 req->request.short_not_ok,
1204 req->request.no_interrupt);
1205 } else if (req->request.zero && req->request.length &&
1206 !usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1207 (IS_ALIGNED(req->request.length, maxp))) {
1208 struct dwc3 *dwc = dep->dwc;
1209 struct dwc3_trb *trb;
1211 req->needs_extra_trb = true;
1213 /* prepare normal TRB */
1214 dwc3_prepare_one_trb(dep, req, length, true, 0);
1216 /* Prepare one extra TRB to handle ZLP */
1217 trb = &dep->trb_pool[dep->trb_enqueue];
1219 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1220 !req->direction, 1, req->request.stream_id,
1221 req->request.short_not_ok,
1222 req->request.no_interrupt);
1224 /* Prepare one more TRB to handle MPS alignment for OUT */
1225 if (!req->direction) {
1226 trb = &dep->trb_pool[dep->trb_enqueue];
1228 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp,
1229 false, 1, req->request.stream_id,
1230 req->request.short_not_ok,
1231 req->request.no_interrupt);
1234 dwc3_prepare_one_trb(dep, req, length, false, 0);
1239 * dwc3_prepare_trbs - setup TRBs from requests
1240 * @dep: endpoint for which requests are being prepared
1242 * The function goes through the requests list and sets up TRBs for the
1243 * transfers. The function returns once there are no more TRBs available or
1244 * it runs out of requests.
1246 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1248 struct dwc3_request *req, *n;
1250 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1253 * We can get in a situation where there's a request in the started list
1254 * but there weren't enough TRBs to fully kick it in the first time
1255 * around, so it has been waiting for more TRBs to be freed up.
1257 * In that case, we should check if we have a request with pending_sgs
1258 * in the started list and prepare TRBs for that request first,
1259 * otherwise we will prepare TRBs completely out of order and that will
1262 list_for_each_entry(req, &dep->started_list, list) {
1263 if (req->num_pending_sgs > 0)
1264 dwc3_prepare_one_trb_sg(dep, req);
1266 if (!dwc3_calc_trbs_left(dep))
1270 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1271 struct dwc3 *dwc = dep->dwc;
1274 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1279 req->sg = req->request.sg;
1280 req->start_sg = req->sg;
1281 req->num_queued_sgs = 0;
1282 req->num_pending_sgs = req->request.num_mapped_sgs;
1284 if (req->num_pending_sgs > 0)
1285 dwc3_prepare_one_trb_sg(dep, req);
1287 dwc3_prepare_one_trb_linear(dep, req);
1289 if (!dwc3_calc_trbs_left(dep))
1294 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1296 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1298 struct dwc3_gadget_ep_cmd_params params;
1299 struct dwc3_request *req;
1304 if (!dwc3_calc_trbs_left(dep))
1307 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1309 dwc3_prepare_trbs(dep);
1310 req = next_request(&dep->started_list);
1312 dep->flags |= DWC3_EP_PENDING_REQUEST;
1316 memset(¶ms, 0, sizeof(params));
1319 params.param0 = upper_32_bits(req->trb_dma);
1320 params.param1 = lower_32_bits(req->trb_dma);
1321 cmd = DWC3_DEPCMD_STARTTRANSFER;
1323 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1324 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1326 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1327 DWC3_DEPCMD_PARAM(dep->resource_index);
1330 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1332 struct dwc3_request *tmp;
1337 dwc3_stop_active_transfer(dep, true, true);
1339 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1340 dwc3_gadget_move_cancelled_request(req);
1342 /* If ep isn't started, then there's no end transfer pending */
1343 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1344 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1352 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1356 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1357 return DWC3_DSTS_SOFFN(reg);
1360 static void __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1362 if (list_empty(&dep->pending_list)) {
1363 dev_info(dep->dwc->dev, "%s: ran out of requests\n",
1365 dep->flags |= DWC3_EP_PENDING_REQUEST;
1369 dep->frame_number = DWC3_ALIGN_FRAME(dep);
1370 __dwc3_gadget_kick_transfer(dep);
1373 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1375 struct dwc3 *dwc = dep->dwc;
1377 if (!dep->endpoint.desc) {
1378 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1383 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1384 &req->request, req->dep->name))
1387 pm_runtime_get(dwc->dev);
1389 req->request.actual = 0;
1390 req->request.status = -EINPROGRESS;
1392 trace_dwc3_ep_queue(req);
1394 list_add_tail(&req->list, &dep->pending_list);
1397 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1398 * wait for a XferNotReady event so we will know what's the current
1399 * (micro-)frame number.
1401 * Without this trick, we are very, very likely gonna get Bus Expiry
1402 * errors which will force us issue EndTransfer command.
1404 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1405 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1406 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1409 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1410 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1411 __dwc3_gadget_start_isoc(dep);
1417 __dwc3_gadget_kick_transfer(dep);
1422 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1425 struct dwc3_request *req = to_dwc3_request(request);
1426 struct dwc3_ep *dep = to_dwc3_ep(ep);
1427 struct dwc3 *dwc = dep->dwc;
1429 unsigned long flags;
1433 spin_lock_irqsave(&dwc->lock, flags);
1434 ret = __dwc3_gadget_ep_queue(dep, req);
1435 spin_unlock_irqrestore(&dwc->lock, flags);
1440 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1445 * If request was already started, this means we had to
1446 * stop the transfer. With that we also need to ignore
1447 * all TRBs used by the request, however TRBs can only
1448 * be modified after completion of END_TRANSFER
1449 * command. So what we do here is that we wait for
1450 * END_TRANSFER completion and only after that, we jump
1451 * over TRBs by clearing HWO and incrementing dequeue
1454 for (i = 0; i < req->num_trbs; i++) {
1455 struct dwc3_trb *trb;
1457 trb = &dep->trb_pool[dep->trb_dequeue];
1458 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1459 dwc3_ep_inc_deq(dep);
1465 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1467 struct dwc3_request *req;
1468 struct dwc3_request *tmp;
1470 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1471 dwc3_gadget_ep_skip_trbs(dep, req);
1472 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1476 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1477 struct usb_request *request)
1479 struct dwc3_request *req = to_dwc3_request(request);
1480 struct dwc3_request *r = NULL;
1482 struct dwc3_ep *dep = to_dwc3_ep(ep);
1483 struct dwc3 *dwc = dep->dwc;
1485 unsigned long flags;
1488 trace_dwc3_ep_dequeue(req);
1490 spin_lock_irqsave(&dwc->lock, flags);
1492 list_for_each_entry(r, &dep->pending_list, list) {
1498 list_for_each_entry(r, &dep->started_list, list) {
1503 /* wait until it is processed */
1504 dwc3_stop_active_transfer(dep, true, true);
1509 dwc3_gadget_move_cancelled_request(req);
1510 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
1515 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1522 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1525 spin_unlock_irqrestore(&dwc->lock, flags);
1530 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1532 struct dwc3_gadget_ep_cmd_params params;
1533 struct dwc3 *dwc = dep->dwc;
1536 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1537 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1541 memset(¶ms, 0x00, sizeof(params));
1544 struct dwc3_trb *trb;
1546 unsigned transfer_in_flight;
1549 if (dep->number > 1)
1550 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1552 trb = &dwc->ep0_trb[dep->trb_enqueue];
1554 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1555 started = !list_empty(&dep->started_list);
1557 if (!protocol && ((dep->direction && transfer_in_flight) ||
1558 (!dep->direction && started))) {
1562 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1565 dev_err(dwc->dev, "failed to set STALL on %s\n",
1568 dep->flags |= DWC3_EP_STALL;
1571 ret = dwc3_send_clear_stall_ep_cmd(dep);
1573 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1576 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1582 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1584 struct dwc3_ep *dep = to_dwc3_ep(ep);
1585 struct dwc3 *dwc = dep->dwc;
1587 unsigned long flags;
1591 spin_lock_irqsave(&dwc->lock, flags);
1592 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1593 spin_unlock_irqrestore(&dwc->lock, flags);
1598 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1600 struct dwc3_ep *dep = to_dwc3_ep(ep);
1601 struct dwc3 *dwc = dep->dwc;
1602 unsigned long flags;
1605 spin_lock_irqsave(&dwc->lock, flags);
1606 dep->flags |= DWC3_EP_WEDGE;
1608 if (dep->number == 0 || dep->number == 1)
1609 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1611 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1612 spin_unlock_irqrestore(&dwc->lock, flags);
1617 /* -------------------------------------------------------------------------- */
1619 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1620 .bLength = USB_DT_ENDPOINT_SIZE,
1621 .bDescriptorType = USB_DT_ENDPOINT,
1622 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1625 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1626 .enable = dwc3_gadget_ep0_enable,
1627 .disable = dwc3_gadget_ep0_disable,
1628 .alloc_request = dwc3_gadget_ep_alloc_request,
1629 .free_request = dwc3_gadget_ep_free_request,
1630 .queue = dwc3_gadget_ep0_queue,
1631 .dequeue = dwc3_gadget_ep_dequeue,
1632 .set_halt = dwc3_gadget_ep0_set_halt,
1633 .set_wedge = dwc3_gadget_ep_set_wedge,
1636 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1637 .enable = dwc3_gadget_ep_enable,
1638 .disable = dwc3_gadget_ep_disable,
1639 .alloc_request = dwc3_gadget_ep_alloc_request,
1640 .free_request = dwc3_gadget_ep_free_request,
1641 .queue = dwc3_gadget_ep_queue,
1642 .dequeue = dwc3_gadget_ep_dequeue,
1643 .set_halt = dwc3_gadget_ep_set_halt,
1644 .set_wedge = dwc3_gadget_ep_set_wedge,
1647 /* -------------------------------------------------------------------------- */
1649 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1651 struct dwc3 *dwc = gadget_to_dwc(g);
1653 return __dwc3_gadget_get_frame(dwc);
1656 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1666 * According to the Databook Remote wakeup request should
1667 * be issued only when the device is in early suspend state.
1669 * We can check that via USB Link State bits in DSTS register.
1671 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1673 link_state = DWC3_DSTS_USBLNKST(reg);
1675 switch (link_state) {
1676 case DWC3_LINK_STATE_RESET:
1677 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1678 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1679 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
1680 case DWC3_LINK_STATE_U1:
1681 case DWC3_LINK_STATE_RESUME:
1687 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1689 dev_err(dwc->dev, "failed to put link in Recovery\n");
1693 /* Recent versions do this automatically */
1694 if (dwc->revision < DWC3_REVISION_194A) {
1695 /* write zeroes to Link Change Request */
1696 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1697 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1698 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1701 /* poll until Link State changes to ON */
1705 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1707 /* in HS, means ON */
1708 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1712 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1713 dev_err(dwc->dev, "failed to send remote wakeup\n");
1720 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1722 struct dwc3 *dwc = gadget_to_dwc(g);
1723 unsigned long flags;
1726 spin_lock_irqsave(&dwc->lock, flags);
1727 ret = __dwc3_gadget_wakeup(dwc);
1728 spin_unlock_irqrestore(&dwc->lock, flags);
1733 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1736 struct dwc3 *dwc = gadget_to_dwc(g);
1737 unsigned long flags;
1739 spin_lock_irqsave(&dwc->lock, flags);
1740 g->is_selfpowered = !!is_selfpowered;
1741 spin_unlock_irqrestore(&dwc->lock, flags);
1746 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1751 if (pm_runtime_suspended(dwc->dev))
1754 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1756 if (dwc->revision <= DWC3_REVISION_187A) {
1757 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1758 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1761 if (dwc->revision >= DWC3_REVISION_194A)
1762 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1763 reg |= DWC3_DCTL_RUN_STOP;
1765 if (dwc->has_hibernation)
1766 reg |= DWC3_DCTL_KEEP_CONNECT;
1768 dwc->pullups_connected = true;
1770 reg &= ~DWC3_DCTL_RUN_STOP;
1772 if (dwc->has_hibernation && !suspend)
1773 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1775 dwc->pullups_connected = false;
1778 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1781 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1782 reg &= DWC3_DSTS_DEVCTRLHLT;
1783 } while (--timeout && !(!is_on ^ !reg));
1791 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1793 struct dwc3 *dwc = gadget_to_dwc(g);
1794 unsigned long flags;
1800 * Per databook, when we want to stop the gadget, if a control transfer
1801 * is still in process, complete it and get the core into setup phase.
1803 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1804 reinit_completion(&dwc->ep0_in_setup);
1806 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1807 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1809 dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
1812 spin_lock_irqsave(&dwc->lock, flags);
1813 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1814 spin_unlock_irqrestore(&dwc->lock, flags);
1819 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1823 /* Enable all but Start and End of Frame IRQs */
1824 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1825 DWC3_DEVTEN_EVNTOVERFLOWEN |
1826 DWC3_DEVTEN_CMDCMPLTEN |
1827 DWC3_DEVTEN_ERRTICERREN |
1828 DWC3_DEVTEN_WKUPEVTEN |
1829 DWC3_DEVTEN_CONNECTDONEEN |
1830 DWC3_DEVTEN_USBRSTEN |
1831 DWC3_DEVTEN_DISCONNEVTEN);
1833 if (dwc->revision < DWC3_REVISION_250A)
1834 reg |= DWC3_DEVTEN_ULSTCNGEN;
1836 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
1837 if (dwc->revision >= DWC3_REVISION_230A)
1838 reg |= DWC3_DEVTEN_EOPFEN;
1840 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1843 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1845 /* mask all interrupts */
1846 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1849 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1850 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1853 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1854 * @dwc: pointer to our context structure
1856 * The following looks like complex but it's actually very simple. In order to
1857 * calculate the number of packets we can burst at once on OUT transfers, we're
1858 * gonna use RxFIFO size.
1860 * To calculate RxFIFO size we need two numbers:
1861 * MDWIDTH = size, in bits, of the internal memory bus
1862 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1864 * Given these two numbers, the formula is simple:
1866 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1868 * 24 bytes is for 3x SETUP packets
1869 * 16 bytes is a clock domain crossing tolerance
1871 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1873 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1880 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1881 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1883 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1884 nump = min_t(u32, nump, 16);
1887 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1888 reg &= ~DWC3_DCFG_NUMP_MASK;
1889 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1890 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1893 static int __dwc3_gadget_start(struct dwc3 *dwc)
1895 struct dwc3_ep *dep;
1900 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1901 * the core supports IMOD, disable it.
1903 if (dwc->imod_interval) {
1904 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1905 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1906 } else if (dwc3_has_imod(dwc)) {
1907 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1911 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1912 * field instead of letting dwc3 itself calculate that automatically.
1914 * This way, we maximize the chances that we'll be able to get several
1915 * bursts of data without going through any sort of endpoint throttling.
1917 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1918 if (dwc3_is_usb31(dwc))
1919 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1921 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1923 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1925 dwc3_gadget_setup_nump(dwc);
1927 /* Start with SuperSpeed Default */
1928 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1931 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1933 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1938 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1940 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1944 /* begin to receive SETUP packets */
1945 dwc->ep0state = EP0_SETUP_PHASE;
1946 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1947 dwc->delayed_status = false;
1948 dwc3_ep0_out_start(dwc);
1950 dwc3_gadget_enable_irq(dwc);
1955 __dwc3_gadget_ep_disable(dwc->eps[0]);
1961 static int dwc3_gadget_start(struct usb_gadget *g,
1962 struct usb_gadget_driver *driver)
1964 struct dwc3 *dwc = gadget_to_dwc(g);
1965 unsigned long flags;
1969 irq = dwc->irq_gadget;
1970 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1971 IRQF_SHARED, "dwc3", dwc->ev_buf);
1973 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1978 spin_lock_irqsave(&dwc->lock, flags);
1979 if (dwc->gadget_driver) {
1980 dev_err(dwc->dev, "%s is already bound to %s\n",
1982 dwc->gadget_driver->driver.name);
1987 dwc->gadget_driver = driver;
1989 if (pm_runtime_active(dwc->dev))
1990 __dwc3_gadget_start(dwc);
1992 spin_unlock_irqrestore(&dwc->lock, flags);
1997 spin_unlock_irqrestore(&dwc->lock, flags);
2004 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2006 dwc3_gadget_disable_irq(dwc);
2007 __dwc3_gadget_ep_disable(dwc->eps[0]);
2008 __dwc3_gadget_ep_disable(dwc->eps[1]);
2011 static int dwc3_gadget_stop(struct usb_gadget *g)
2013 struct dwc3 *dwc = gadget_to_dwc(g);
2014 unsigned long flags;
2016 spin_lock_irqsave(&dwc->lock, flags);
2018 if (pm_runtime_suspended(dwc->dev))
2021 __dwc3_gadget_stop(dwc);
2024 dwc->gadget_driver = NULL;
2025 spin_unlock_irqrestore(&dwc->lock, flags);
2027 free_irq(dwc->irq_gadget, dwc->ev_buf);
2032 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2033 enum usb_device_speed speed)
2035 struct dwc3 *dwc = gadget_to_dwc(g);
2036 unsigned long flags;
2039 spin_lock_irqsave(&dwc->lock, flags);
2040 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2041 reg &= ~(DWC3_DCFG_SPEED_MASK);
2044 * WORKAROUND: DWC3 revision < 2.20a have an issue
2045 * which would cause metastability state on Run/Stop
2046 * bit if we try to force the IP to USB2-only mode.
2048 * Because of that, we cannot configure the IP to any
2049 * speed other than the SuperSpeed
2053 * STAR#9000525659: Clock Domain Crossing on DCTL in
2056 if (dwc->revision < DWC3_REVISION_220A &&
2057 !dwc->dis_metastability_quirk) {
2058 reg |= DWC3_DCFG_SUPERSPEED;
2062 reg |= DWC3_DCFG_LOWSPEED;
2064 case USB_SPEED_FULL:
2065 reg |= DWC3_DCFG_FULLSPEED;
2067 case USB_SPEED_HIGH:
2068 reg |= DWC3_DCFG_HIGHSPEED;
2070 case USB_SPEED_SUPER:
2071 reg |= DWC3_DCFG_SUPERSPEED;
2073 case USB_SPEED_SUPER_PLUS:
2074 if (dwc3_is_usb31(dwc))
2075 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2077 reg |= DWC3_DCFG_SUPERSPEED;
2080 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2082 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2083 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2085 reg |= DWC3_DCFG_SUPERSPEED;
2088 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2090 spin_unlock_irqrestore(&dwc->lock, flags);
2093 static const struct usb_gadget_ops dwc3_gadget_ops = {
2094 .get_frame = dwc3_gadget_get_frame,
2095 .wakeup = dwc3_gadget_wakeup,
2096 .set_selfpowered = dwc3_gadget_set_selfpowered,
2097 .pullup = dwc3_gadget_pullup,
2098 .udc_start = dwc3_gadget_start,
2099 .udc_stop = dwc3_gadget_stop,
2100 .udc_set_speed = dwc3_gadget_set_speed,
2103 /* -------------------------------------------------------------------------- */
2105 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2107 struct dwc3 *dwc = dep->dwc;
2109 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2110 dep->endpoint.maxburst = 1;
2111 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2112 if (!dep->direction)
2113 dwc->gadget.ep0 = &dep->endpoint;
2115 dep->endpoint.caps.type_control = true;
2120 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2122 struct dwc3 *dwc = dep->dwc;
2126 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2127 /* MDWIDTH is represented in bits, we need it in bytes */
2130 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2131 if (dwc3_is_usb31(dwc))
2132 size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2134 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2136 /* FIFO Depth is in MDWDITH bytes. Multiply */
2140 * To meet performance requirement, a minimum TxFIFO size of 3x
2141 * MaxPacketSize is recommended for endpoints that support burst and a
2142 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2143 * support burst. Use those numbers and we can calculate the max packet
2146 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2151 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2153 dep->endpoint.max_streams = 15;
2154 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2155 list_add_tail(&dep->endpoint.ep_list,
2156 &dwc->gadget.ep_list);
2157 dep->endpoint.caps.type_iso = true;
2158 dep->endpoint.caps.type_bulk = true;
2159 dep->endpoint.caps.type_int = true;
2161 return dwc3_alloc_trb_pool(dep);
2164 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2166 struct dwc3 *dwc = dep->dwc;
2170 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2172 /* MDWIDTH is represented in bits, convert to bytes */
2175 /* All OUT endpoints share a single RxFIFO space */
2176 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2177 if (dwc3_is_usb31(dwc))
2178 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2180 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2182 /* FIFO depth is in MDWDITH bytes */
2186 * To meet performance requirement, a minimum recommended RxFIFO size
2187 * is defined as follow:
2188 * RxFIFO size >= (3 x MaxPacketSize) +
2189 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2191 * Then calculate the max packet limit as below.
2193 size -= (3 * 8) + 16;
2199 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2200 dep->endpoint.max_streams = 15;
2201 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2202 list_add_tail(&dep->endpoint.ep_list,
2203 &dwc->gadget.ep_list);
2204 dep->endpoint.caps.type_iso = true;
2205 dep->endpoint.caps.type_bulk = true;
2206 dep->endpoint.caps.type_int = true;
2208 return dwc3_alloc_trb_pool(dep);
2211 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2213 struct dwc3_ep *dep;
2214 bool direction = epnum & 1;
2216 u8 num = epnum >> 1;
2218 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2223 dep->number = epnum;
2224 dep->direction = direction;
2225 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2226 dwc->eps[epnum] = dep;
2228 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2229 direction ? "in" : "out");
2231 dep->endpoint.name = dep->name;
2233 if (!(dep->number > 1)) {
2234 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2235 dep->endpoint.comp_desc = NULL;
2238 spin_lock_init(&dep->lock);
2241 ret = dwc3_gadget_init_control_endpoint(dep);
2243 ret = dwc3_gadget_init_in_endpoint(dep);
2245 ret = dwc3_gadget_init_out_endpoint(dep);
2250 dep->endpoint.caps.dir_in = direction;
2251 dep->endpoint.caps.dir_out = !direction;
2253 INIT_LIST_HEAD(&dep->pending_list);
2254 INIT_LIST_HEAD(&dep->started_list);
2255 INIT_LIST_HEAD(&dep->cancelled_list);
2257 dwc3_debugfs_create_endpoint_dir(dep);
2262 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2266 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2268 for (epnum = 0; epnum < total; epnum++) {
2271 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2279 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2281 struct dwc3_ep *dep;
2284 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2285 dep = dwc->eps[epnum];
2289 * Physical endpoints 0 and 1 are special; they form the
2290 * bi-directional USB endpoint 0.
2292 * For those two physical endpoints, we don't allocate a TRB
2293 * pool nor do we add them the endpoints list. Due to that, we
2294 * shouldn't do these two operations otherwise we would end up
2295 * with all sorts of bugs when removing dwc3.ko.
2297 if (epnum != 0 && epnum != 1) {
2298 dwc3_free_trb_pool(dep);
2299 list_del(&dep->endpoint.ep_list);
2302 debugfs_remove_recursive(debugfs_lookup(dep->name, dwc->root));
2307 /* -------------------------------------------------------------------------- */
2309 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2310 struct dwc3_request *req, struct dwc3_trb *trb,
2311 const struct dwc3_event_depevt *event, int status, int chain)
2315 dwc3_ep_inc_deq(dep);
2317 trace_dwc3_complete_trb(dep, trb);
2321 * If we're in the middle of series of chained TRBs and we
2322 * receive a short transfer along the way, DWC3 will skip
2323 * through all TRBs including the last TRB in the chain (the
2324 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2325 * bit and SW has to do it manually.
2327 * We're going to do that here to avoid problems of HW trying
2328 * to use bogus TRBs for transfers.
2330 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2331 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2334 * If we're dealing with unaligned size OUT transfer, we will be left
2335 * with one TRB pending in the ring. We need to manually clear HWO bit
2339 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2340 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2344 count = trb->size & DWC3_TRB_SIZE_MASK;
2345 req->remaining += count;
2347 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2350 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2353 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2354 (trb->ctrl & DWC3_TRB_CTRL_LST))
2360 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2361 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2364 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2365 struct scatterlist *sg = req->sg;
2366 struct scatterlist *s;
2367 unsigned int num_queued = req->num_queued_sgs;
2371 for_each_sg(sg, s, num_queued, i) {
2372 trb = &dep->trb_pool[dep->trb_dequeue];
2374 req->sg = sg_next(s);
2375 req->num_queued_sgs--;
2377 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2378 trb, event, status, true);
2386 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2387 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2390 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2392 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2393 event, status, false);
2396 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2398 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
2401 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2402 const struct dwc3_event_depevt *event,
2403 struct dwc3_request *req, int status)
2407 if (req->request.num_mapped_sgs)
2408 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2411 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2414 req->request.actual = req->request.length - req->remaining;
2416 if (!dwc3_gadget_ep_request_completed(req))
2419 if (req->needs_extra_trb) {
2420 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
2422 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2425 /* Reclaim MPS padding TRB for ZLP */
2426 if (!req->direction && req->request.zero && req->request.length &&
2427 !usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2428 (IS_ALIGNED(req->request.length, maxp)))
2429 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, status);
2431 req->needs_extra_trb = false;
2434 dwc3_gadget_giveback(dep, req, status);
2440 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2441 const struct dwc3_event_depevt *event, int status)
2443 struct dwc3_request *req;
2444 struct dwc3_request *tmp;
2446 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2449 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2456 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2458 struct dwc3_request *req;
2460 if (!list_empty(&dep->pending_list))
2464 * We only need to check the first entry of the started list. We can
2465 * assume the completed requests are removed from the started list.
2467 req = next_request(&dep->started_list);
2471 return !dwc3_gadget_ep_request_completed(req);
2474 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2475 const struct dwc3_event_depevt *event)
2477 dep->frame_number = event->parameters;
2480 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2481 const struct dwc3_event_depevt *event)
2483 struct dwc3 *dwc = dep->dwc;
2484 unsigned status = 0;
2487 dwc3_gadget_endpoint_frame_from_event(dep, event);
2489 if (event->status & DEPEVT_STATUS_BUSERR)
2490 status = -ECONNRESET;
2492 if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2495 if (list_empty(&dep->started_list))
2499 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2502 dwc3_stop_active_transfer(dep, true, true);
2503 else if (dwc3_gadget_ep_should_continue(dep))
2504 __dwc3_gadget_kick_transfer(dep);
2507 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2508 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2510 if (dwc->revision < DWC3_REVISION_183A) {
2514 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2517 if (!(dep->flags & DWC3_EP_ENABLED))
2520 if (!list_empty(&dep->started_list))
2524 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2526 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2532 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2533 const struct dwc3_event_depevt *event)
2535 dwc3_gadget_endpoint_frame_from_event(dep, event);
2536 __dwc3_gadget_start_isoc(dep);
2539 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2540 const struct dwc3_event_depevt *event)
2542 struct dwc3_ep *dep;
2543 u8 epnum = event->endpoint_number;
2546 dep = dwc->eps[epnum];
2548 if (!(dep->flags & DWC3_EP_ENABLED)) {
2549 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2552 /* Handle only EPCMDCMPLT when EP disabled */
2553 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2557 if (epnum == 0 || epnum == 1) {
2558 dwc3_ep0_interrupt(dwc, event);
2562 switch (event->endpoint_event) {
2563 case DWC3_DEPEVT_XFERINPROGRESS:
2564 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2566 case DWC3_DEPEVT_XFERNOTREADY:
2567 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2569 case DWC3_DEPEVT_EPCMDCMPLT:
2570 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2572 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2573 dep->flags &= ~(DWC3_EP_END_TRANSFER_PENDING |
2574 DWC3_EP_TRANSFER_STARTED);
2575 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2578 case DWC3_DEPEVT_STREAMEVT:
2579 case DWC3_DEPEVT_XFERCOMPLETE:
2580 case DWC3_DEPEVT_RXTXFIFOEVT:
2585 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2587 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2588 spin_unlock(&dwc->lock);
2589 dwc->gadget_driver->disconnect(&dwc->gadget);
2590 spin_lock(&dwc->lock);
2594 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2596 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2597 spin_unlock(&dwc->lock);
2598 dwc->gadget_driver->suspend(&dwc->gadget);
2599 spin_lock(&dwc->lock);
2603 static void dwc3_resume_gadget(struct dwc3 *dwc)
2605 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2606 spin_unlock(&dwc->lock);
2607 dwc->gadget_driver->resume(&dwc->gadget);
2608 spin_lock(&dwc->lock);
2612 static void dwc3_reset_gadget(struct dwc3 *dwc)
2614 if (!dwc->gadget_driver)
2617 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2618 spin_unlock(&dwc->lock);
2619 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2620 spin_lock(&dwc->lock);
2624 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2627 struct dwc3 *dwc = dep->dwc;
2628 struct dwc3_gadget_ep_cmd_params params;
2632 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2633 !dep->resource_index)
2637 * NOTICE: We are violating what the Databook says about the
2638 * EndTransfer command. Ideally we would _always_ wait for the
2639 * EndTransfer Command Completion IRQ, but that's causing too
2640 * much trouble synchronizing between us and gadget driver.
2642 * We have discussed this with the IP Provider and it was
2643 * suggested to giveback all requests here, but give HW some
2644 * extra time to synchronize with the interconnect. We're using
2645 * an arbitrary 100us delay for that.
2647 * Note also that a similar handling was tested by Synopsys
2648 * (thanks a lot Paul) and nothing bad has come out of it.
2649 * In short, what we're doing is:
2651 * - Issue EndTransfer WITH CMDIOC bit set
2654 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2655 * supports a mode to work around the above limitation. The
2656 * software can poll the CMDACT bit in the DEPCMD register
2657 * after issuing a EndTransfer command. This mode is enabled
2658 * by writing GUCTL2[14]. This polling is already done in the
2659 * dwc3_send_gadget_ep_cmd() function so if the mode is
2660 * enabled, the EndTransfer command will have completed upon
2661 * returning from this function and we don't need to delay for
2664 * This mode is NOT available on the DWC_usb31 IP.
2667 cmd = DWC3_DEPCMD_ENDTRANSFER;
2668 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2669 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
2670 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2671 memset(¶ms, 0, sizeof(params));
2672 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2674 dep->resource_index = 0;
2676 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2677 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2682 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2686 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2687 struct dwc3_ep *dep;
2690 dep = dwc->eps[epnum];
2694 if (!(dep->flags & DWC3_EP_STALL))
2697 dep->flags &= ~DWC3_EP_STALL;
2699 ret = dwc3_send_clear_stall_ep_cmd(dep);
2704 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2708 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2709 reg &= ~DWC3_DCTL_INITU1ENA;
2710 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2712 reg &= ~DWC3_DCTL_INITU2ENA;
2713 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2715 dwc3_disconnect_gadget(dwc);
2717 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2718 dwc->setup_packet_pending = false;
2719 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2721 dwc->connected = false;
2724 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2728 dwc->connected = true;
2731 * Ideally, dwc3_reset_gadget() would trigger the function
2732 * drivers to stop any active transfers through ep disable.
2733 * However, for functions which defer ep disable, such as mass
2734 * storage, we will need to rely on the call to stop active
2735 * transfers here, and avoid allowing of request queuing.
2737 dwc->connected = false;
2740 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2741 * would cause a missing Disconnect Event if there's a
2742 * pending Setup Packet in the FIFO.
2744 * There's no suggested workaround on the official Bug
2745 * report, which states that "unless the driver/application
2746 * is doing any special handling of a disconnect event,
2747 * there is no functional issue".
2749 * Unfortunately, it turns out that we _do_ some special
2750 * handling of a disconnect event, namely complete all
2751 * pending transfers, notify gadget driver of the
2752 * disconnection, and so on.
2754 * Our suggested workaround is to follow the Disconnect
2755 * Event steps here, instead, based on a setup_packet_pending
2756 * flag. Such flag gets set whenever we have a SETUP_PENDING
2757 * status for EP0 TRBs and gets cleared on XferComplete for the
2762 * STAR#9000466709: RTL: Device : Disconnect event not
2763 * generated if setup packet pending in FIFO
2765 if (dwc->revision < DWC3_REVISION_188A) {
2766 if (dwc->setup_packet_pending)
2767 dwc3_gadget_disconnect_interrupt(dwc);
2770 dwc3_reset_gadget(dwc);
2772 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2773 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2774 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2775 dwc->test_mode = false;
2776 dwc3_clear_stall_all_ep(dwc);
2778 /* Reset device address to zero */
2779 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2780 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2781 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2784 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2786 struct dwc3_ep *dep;
2791 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2792 speed = reg & DWC3_DSTS_CONNECTSPD;
2796 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2797 * each time on Connect Done.
2799 * Currently we always use the reset value. If any platform
2800 * wants to set this to a different value, we need to add a
2801 * setting and update GCTL.RAMCLKSEL here.
2805 case DWC3_DSTS_SUPERSPEED_PLUS:
2806 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2807 dwc->gadget.ep0->maxpacket = 512;
2808 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2810 case DWC3_DSTS_SUPERSPEED:
2812 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2813 * would cause a missing USB3 Reset event.
2815 * In such situations, we should force a USB3 Reset
2816 * event by calling our dwc3_gadget_reset_interrupt()
2821 * STAR#9000483510: RTL: SS : USB3 reset event may
2822 * not be generated always when the link enters poll
2824 if (dwc->revision < DWC3_REVISION_190A)
2825 dwc3_gadget_reset_interrupt(dwc);
2827 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2828 dwc->gadget.ep0->maxpacket = 512;
2829 dwc->gadget.speed = USB_SPEED_SUPER;
2831 case DWC3_DSTS_HIGHSPEED:
2832 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2833 dwc->gadget.ep0->maxpacket = 64;
2834 dwc->gadget.speed = USB_SPEED_HIGH;
2836 case DWC3_DSTS_FULLSPEED:
2837 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2838 dwc->gadget.ep0->maxpacket = 64;
2839 dwc->gadget.speed = USB_SPEED_FULL;
2841 case DWC3_DSTS_LOWSPEED:
2842 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2843 dwc->gadget.ep0->maxpacket = 8;
2844 dwc->gadget.speed = USB_SPEED_LOW;
2848 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2850 /* Enable USB2 LPM Capability */
2852 if ((dwc->revision > DWC3_REVISION_194A) &&
2853 (speed != DWC3_DSTS_SUPERSPEED) &&
2854 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2855 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2856 reg |= DWC3_DCFG_LPM_CAP;
2857 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2859 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2860 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2862 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2865 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2866 * DCFG.LPMCap is set, core responses with an ACK and the
2867 * BESL value in the LPM token is less than or equal to LPM
2870 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2871 && dwc->has_lpm_erratum,
2872 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2874 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2875 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2877 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2879 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2880 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2881 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2885 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2887 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2892 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2894 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2899 * Configure PHY via GUSB3PIPECTLn if required.
2901 * Update GTXFIFOSIZn
2903 * In both cases reset values should be sufficient.
2907 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2910 * TODO take core out of low power mode when that's
2914 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2915 spin_unlock(&dwc->lock);
2916 dwc->gadget_driver->resume(&dwc->gadget);
2917 spin_lock(&dwc->lock);
2921 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2922 unsigned int evtinfo)
2924 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2925 unsigned int pwropt;
2928 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2929 * Hibernation mode enabled which would show up when device detects
2930 * host-initiated U3 exit.
2932 * In that case, device will generate a Link State Change Interrupt
2933 * from U3 to RESUME which is only necessary if Hibernation is
2936 * There are no functional changes due to such spurious event and we
2937 * just need to ignore it.
2941 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2944 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2945 if ((dwc->revision < DWC3_REVISION_250A) &&
2946 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2947 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2948 (next == DWC3_LINK_STATE_RESUME)) {
2954 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2955 * on the link partner, the USB session might do multiple entry/exit
2956 * of low power states before a transfer takes place.
2958 * Due to this problem, we might experience lower throughput. The
2959 * suggested workaround is to disable DCTL[12:9] bits if we're
2960 * transitioning from U1/U2 to U0 and enable those bits again
2961 * after a transfer completes and there are no pending transfers
2962 * on any of the enabled endpoints.
2964 * This is the first half of that workaround.
2968 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2969 * core send LGO_Ux entering U0
2971 if (dwc->revision < DWC3_REVISION_183A) {
2972 if (next == DWC3_LINK_STATE_U0) {
2976 switch (dwc->link_state) {
2977 case DWC3_LINK_STATE_U1:
2978 case DWC3_LINK_STATE_U2:
2979 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2980 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2981 | DWC3_DCTL_ACCEPTU2ENA
2982 | DWC3_DCTL_INITU1ENA
2983 | DWC3_DCTL_ACCEPTU1ENA);
2986 dwc->u1u2 = reg & u1u2;
2990 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3000 case DWC3_LINK_STATE_U1:
3001 if (dwc->speed == USB_SPEED_SUPER)
3002 dwc3_suspend_gadget(dwc);
3004 case DWC3_LINK_STATE_U2:
3005 case DWC3_LINK_STATE_U3:
3006 dwc3_suspend_gadget(dwc);
3008 case DWC3_LINK_STATE_RESUME:
3009 dwc3_resume_gadget(dwc);
3016 dwc->link_state = next;
3019 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3020 unsigned int evtinfo)
3022 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3024 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3025 dwc3_suspend_gadget(dwc);
3027 dwc->link_state = next;
3030 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3031 unsigned int evtinfo)
3033 unsigned int is_ss = evtinfo & BIT(4);
3036 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3037 * have a known issue which can cause USB CV TD.9.23 to fail
3040 * Because of this issue, core could generate bogus hibernation
3041 * events which SW needs to ignore.
3045 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3046 * Device Fallback from SuperSpeed
3048 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3051 /* enter hibernation here */
3054 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3055 const struct dwc3_event_devt *event)
3057 switch (event->type) {
3058 case DWC3_DEVICE_EVENT_DISCONNECT:
3059 dwc3_gadget_disconnect_interrupt(dwc);
3061 case DWC3_DEVICE_EVENT_RESET:
3062 dwc3_gadget_reset_interrupt(dwc);
3064 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3065 dwc3_gadget_conndone_interrupt(dwc);
3067 case DWC3_DEVICE_EVENT_WAKEUP:
3068 dwc3_gadget_wakeup_interrupt(dwc);
3070 case DWC3_DEVICE_EVENT_HIBER_REQ:
3071 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3072 "unexpected hibernation event\n"))
3075 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3077 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3078 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3080 case DWC3_DEVICE_EVENT_EOPF:
3081 /* It changed to be suspend event for version 2.30a and above */
3082 if (dwc->revision >= DWC3_REVISION_230A) {
3084 * Ignore suspend event until the gadget enters into
3085 * USB_STATE_CONFIGURED state.
3087 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3088 dwc3_gadget_suspend_interrupt(dwc,
3092 case DWC3_DEVICE_EVENT_SOF:
3093 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3094 case DWC3_DEVICE_EVENT_CMD_CMPL:
3095 case DWC3_DEVICE_EVENT_OVERFLOW:
3098 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3102 static void dwc3_process_event_entry(struct dwc3 *dwc,
3103 const union dwc3_event *event)
3105 trace_dwc3_event(event->raw, dwc);
3107 if (!event->type.is_devspec)
3108 dwc3_endpoint_interrupt(dwc, &event->depevt);
3109 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3110 dwc3_gadget_interrupt(dwc, &event->devt);
3112 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3115 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3117 struct dwc3 *dwc = evt->dwc;
3118 irqreturn_t ret = IRQ_NONE;
3124 if (!(evt->flags & DWC3_EVENT_PENDING))
3128 union dwc3_event event;
3130 event.raw = *(u32 *) (evt->cache + evt->lpos);
3132 dwc3_process_event_entry(dwc, &event);
3135 * FIXME we wrap around correctly to the next entry as
3136 * almost all entries are 4 bytes in size. There is one
3137 * entry which has 12 bytes which is a regular entry
3138 * followed by 8 bytes data. ATM I don't know how
3139 * things are organized if we get next to the a
3140 * boundary so I worry about that once we try to handle
3143 evt->lpos = (evt->lpos + 4) % evt->length;
3148 evt->flags &= ~DWC3_EVENT_PENDING;
3151 /* Unmask interrupt */
3152 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3153 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3154 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3156 if (dwc->imod_interval) {
3157 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3158 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3164 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3166 struct dwc3_event_buffer *evt = _evt;
3167 struct dwc3 *dwc = evt->dwc;
3168 unsigned long flags;
3169 irqreturn_t ret = IRQ_NONE;
3171 spin_lock_irqsave(&dwc->lock, flags);
3172 ret = dwc3_process_event_buf(evt);
3173 spin_unlock_irqrestore(&dwc->lock, flags);
3178 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3180 struct dwc3 *dwc = evt->dwc;
3185 if (pm_runtime_suspended(dwc->dev)) {
3186 pm_runtime_get(dwc->dev);
3187 disable_irq_nosync(dwc->irq_gadget);
3188 dwc->pending_events = true;
3193 * With PCIe legacy interrupt, test shows that top-half irq handler can
3194 * be called again after HW interrupt deassertion. Check if bottom-half
3195 * irq event handler completes before caching new event to prevent
3198 if (evt->flags & DWC3_EVENT_PENDING)
3201 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3202 count &= DWC3_GEVNTCOUNT_MASK;
3207 evt->flags |= DWC3_EVENT_PENDING;
3209 /* Mask interrupt */
3210 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3211 reg |= DWC3_GEVNTSIZ_INTMASK;
3212 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3214 amount = min(count, evt->length - evt->lpos);
3215 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3218 memcpy(evt->cache, evt->buf, count - amount);
3220 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3222 return IRQ_WAKE_THREAD;
3225 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3227 struct dwc3_event_buffer *evt = _evt;
3229 return dwc3_check_event_buf(evt);
3232 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3234 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3237 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3241 if (irq == -EPROBE_DEFER)
3244 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3248 if (irq == -EPROBE_DEFER)
3251 irq = platform_get_irq(dwc3_pdev, 0);
3255 if (irq != -EPROBE_DEFER)
3256 dev_err(dwc->dev, "missing peripheral IRQ\n");
3266 * dwc3_gadget_init - initializes gadget related registers
3267 * @dwc: pointer to our controller context structure
3269 * Returns 0 on success otherwise negative errno.
3271 int dwc3_gadget_init(struct dwc3 *dwc)
3276 irq = dwc3_gadget_get_irq(dwc);
3282 dwc->irq_gadget = irq;
3284 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3285 sizeof(*dwc->ep0_trb) * 2,
3286 &dwc->ep0_trb_addr, GFP_KERNEL);
3287 if (!dwc->ep0_trb) {
3288 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3293 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3294 if (!dwc->setup_buf) {
3299 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3300 &dwc->bounce_addr, GFP_KERNEL);
3306 init_completion(&dwc->ep0_in_setup);
3308 dwc->gadget.ops = &dwc3_gadget_ops;
3309 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3310 dwc->gadget.sg_supported = true;
3311 dwc->gadget.name = "dwc3-gadget";
3314 * FIXME We might be setting max_speed to <SUPER, however versions
3315 * <2.20a of dwc3 have an issue with metastability (documented
3316 * elsewhere in this driver) which tells us we can't set max speed to
3317 * anything lower than SUPER.
3319 * Because gadget.max_speed is only used by composite.c and function
3320 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3321 * to happen so we avoid sending SuperSpeed Capability descriptor
3322 * together with our BOS descriptor as that could confuse host into
3323 * thinking we can handle super speed.
3325 * Note that, in fact, we won't even support GetBOS requests when speed
3326 * is less than super speed because we don't have means, yet, to tell
3327 * composite.c that we are USB 2.0 + LPM ECN.
3329 if (dwc->revision < DWC3_REVISION_220A &&
3330 !dwc->dis_metastability_quirk)
3331 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3334 dwc->gadget.max_speed = dwc->maximum_speed;
3337 * REVISIT: Here we should clear all pending IRQs to be
3338 * sure we're starting from a well known location.
3341 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3345 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3347 dev_err(dwc->dev, "failed to register udc\n");
3351 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3356 dwc3_gadget_free_endpoints(dwc);
3359 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3363 kfree(dwc->setup_buf);
3366 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3367 dwc->ep0_trb, dwc->ep0_trb_addr);
3373 /* -------------------------------------------------------------------------- */
3375 void dwc3_gadget_exit(struct dwc3 *dwc)
3377 usb_del_gadget_udc(&dwc->gadget);
3378 dwc3_gadget_free_endpoints(dwc);
3379 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3381 kfree(dwc->setup_buf);
3382 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3383 dwc->ep0_trb, dwc->ep0_trb_addr);
3386 int dwc3_gadget_suspend(struct dwc3 *dwc)
3388 if (!dwc->gadget_driver)
3391 dwc3_gadget_run_stop(dwc, false, false);
3392 dwc3_disconnect_gadget(dwc);
3393 __dwc3_gadget_stop(dwc);
3398 int dwc3_gadget_resume(struct dwc3 *dwc)
3402 if (!dwc->gadget_driver)
3405 ret = __dwc3_gadget_start(dwc);
3409 ret = dwc3_gadget_run_stop(dwc, true, false);
3416 __dwc3_gadget_stop(dwc);
3422 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3424 if (dwc->pending_events) {
3425 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3426 dwc->pending_events = false;
3427 enable_irq(dwc->irq_gadget);