2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - enables usb2 test modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will return 0 on
44 * success or -EINVAL if wrong Test Selector is passed.
46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
71 * dwc3_gadget_get_link_state - gets current state of usb link
72 * @dwc: pointer to our context structure
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83 return DWC3_DSTS_USBLNKST(reg);
87 * dwc3_gadget_set_link_state - sets usb link to a particular state
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
100 * Wait until device controller is ready. Only applies to 1.94a and
103 if (dwc->revision >= DWC3_REVISION_194A) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
127 if (dwc->revision >= DWC3_REVISION_194A)
130 /* wait for a change in DSTS */
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135 if (DWC3_DSTS_USBLNKST(reg) == state)
145 * dwc3_ep_inc_trb - increment a trb index.
146 * @index: Pointer to the TRB index to increment.
148 * The index should never point to the link TRB. After incrementing,
149 * if it is point to the link TRB, wrap around to the beginning. The
150 * link TRB is always at the last TRB entry.
152 static void dwc3_ep_inc_trb(u8 *index)
155 if (*index == (DWC3_TRB_NUM - 1))
160 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
161 * @dep: The endpoint whose enqueue pointer we're incrementing
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
169 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
170 * @dep: The endpoint whose enqueue pointer we're incrementing
172 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
174 dwc3_ep_inc_trb(&dep->trb_dequeue);
177 void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
178 struct dwc3_request *req, int status)
180 struct dwc3 *dwc = dep->dwc;
182 req->started = false;
183 list_del(&req->list);
185 req->unaligned = false;
188 if (req->request.status == -EINPROGRESS)
189 req->request.status = status;
192 usb_gadget_unmap_request_by_dev(dwc->sysdev,
193 &req->request, req->direction);
196 trace_dwc3_gadget_giveback(req);
199 pm_runtime_put(dwc->dev);
203 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
204 * @dep: The endpoint to whom the request belongs to
205 * @req: The request we're giving back
206 * @status: completion code for the request
208 * Must be called with controller's lock held and interrupts disabled. This
209 * function will unmap @req and call its ->complete() callback to notify upper
210 * layers that it has completed.
212 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
215 struct dwc3 *dwc = dep->dwc;
217 dwc3_gadget_del_and_unmap_request(dep, req, status);
219 spin_unlock(&dwc->lock);
220 usb_gadget_giveback_request(&dep->endpoint, &req->request);
221 spin_lock(&dwc->lock);
225 * dwc3_send_gadget_generic_command - issue a generic command for the controller
226 * @dwc: pointer to the controller context
227 * @cmd: the command to be issued
228 * @param: command parameter
230 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
231 * and wait for its completion.
233 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
240 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
241 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
244 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
245 if (!(reg & DWC3_DGCMD_CMDACT)) {
246 status = DWC3_DGCMD_STATUS(reg);
258 trace_dwc3_gadget_generic_cmd(cmd, param, status);
263 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
266 * dwc3_send_gadget_ep_cmd - issue an endpoint command
267 * @dep: the endpoint to which the command is going to be issued
268 * @cmd: the command to be issued
269 * @params: parameters to the command
271 * Caller should handle locking. This function will issue @cmd with given
272 * @params to @dep and wait for its completion.
274 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
275 struct dwc3_gadget_ep_cmd_params *params)
277 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
278 struct dwc3 *dwc = dep->dwc;
280 u32 saved_config = 0;
287 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
288 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
291 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
292 * settings. Restore them after the command is completed.
294 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
296 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
297 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
298 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
299 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
300 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
303 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
304 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
305 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
309 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
312 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
315 link_state = dwc3_gadget_get_link_state(dwc);
316 if (link_state == DWC3_LINK_STATE_U1 ||
317 link_state == DWC3_LINK_STATE_U2 ||
318 link_state == DWC3_LINK_STATE_U3) {
319 ret = __dwc3_gadget_wakeup(dwc);
320 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
325 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
326 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
327 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
330 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
331 * not relying on XferNotReady, we can make use of a special "No
332 * Response Update Transfer" command where we should clear both CmdAct
335 * With this, we don't need to wait for command completion and can
336 * straight away issue further commands to the endpoint.
338 * NOTICE: We're making an assumption that control endpoints will never
339 * make use of Update Transfer command. This is a safe assumption
340 * because we can never have more than one request at a time with
341 * Control Endpoints. If anybody changes that assumption, this chunk
342 * needs to be updated accordingly.
344 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
345 !usb_endpoint_xfer_isoc(desc))
346 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
348 cmd |= DWC3_DEPCMD_CMDACT;
350 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
352 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
353 if (!(reg & DWC3_DEPCMD_CMDACT)) {
354 cmd_status = DWC3_DEPCMD_STATUS(reg);
356 switch (cmd_status) {
360 case DEPEVT_TRANSFER_NO_RESOURCE:
363 case DEPEVT_TRANSFER_BUS_EXPIRY:
365 * SW issues START TRANSFER command to
366 * isochronous ep with future frame interval. If
367 * future interval time has already passed when
368 * core receives the command, it will respond
369 * with an error status of 'Bus Expiry'.
371 * Instead of always returning -EINVAL, let's
372 * give a hint to the gadget driver that this is
373 * the case by returning -EAGAIN.
378 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
387 cmd_status = -ETIMEDOUT;
390 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
393 switch (DWC3_DEPCMD_CMD(cmd)) {
394 case DWC3_DEPCMD_STARTTRANSFER:
395 dep->flags |= DWC3_EP_TRANSFER_STARTED;
397 case DWC3_DEPCMD_ENDTRANSFER:
398 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
407 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
409 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
415 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
417 struct dwc3 *dwc = dep->dwc;
418 struct dwc3_gadget_ep_cmd_params params;
419 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
422 * As of core revision 2.60a the recommended programming model
423 * is to set the ClearPendIN bit when issuing a Clear Stall EP
424 * command for IN endpoints. This is to prevent an issue where
425 * some (non-compliant) hosts may not send ACK TPs for pending
426 * IN transfers due to a mishandled error condition. Synopsys
429 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
430 (dwc->gadget.speed >= USB_SPEED_SUPER))
431 cmd |= DWC3_DEPCMD_CLEARPENDIN;
433 memset(¶ms, 0, sizeof(params));
435 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
438 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
439 struct dwc3_trb *trb)
441 u32 offset = (char *) trb - (char *) dep->trb_pool;
443 return dep->trb_pool_dma + offset;
446 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
448 struct dwc3 *dwc = dep->dwc;
453 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
454 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
455 &dep->trb_pool_dma, GFP_KERNEL);
456 if (!dep->trb_pool) {
457 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
465 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
467 struct dwc3 *dwc = dep->dwc;
469 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
470 dep->trb_pool, dep->trb_pool_dma);
472 dep->trb_pool = NULL;
473 dep->trb_pool_dma = 0;
476 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
479 * dwc3_gadget_start_config - configure ep resources
480 * @dwc: pointer to our controller context structure
481 * @dep: endpoint that is being enabled
483 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
484 * completion, it will set Transfer Resource for all available endpoints.
486 * The assignment of transfer resources cannot perfectly follow the data book
487 * due to the fact that the controller driver does not have all knowledge of the
488 * configuration in advance. It is given this information piecemeal by the
489 * composite gadget framework after every SET_CONFIGURATION and
490 * SET_INTERFACE. Trying to follow the databook programming model in this
491 * scenario can cause errors. For two reasons:
493 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
494 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
495 * incorrect in the scenario of multiple interfaces.
497 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
498 * endpoint on alt setting (8.1.6).
500 * The following simplified method is used instead:
502 * All hardware endpoints can be assigned a transfer resource and this setting
503 * will stay persistent until either a core reset or hibernation. So whenever we
504 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
505 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
506 * guaranteed that there are as many transfer resources as endpoints.
508 * This function is called for each endpoint when it is being enabled but is
509 * triggered only when called for EP0-out, which always happens first, and which
510 * should only happen in one of the above conditions.
512 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
514 struct dwc3_gadget_ep_cmd_params params;
522 memset(¶ms, 0x00, sizeof(params));
523 cmd = DWC3_DEPCMD_DEPSTARTCFG;
525 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
529 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
530 struct dwc3_ep *dep = dwc->eps[i];
535 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
543 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
544 bool modify, bool restore)
546 const struct usb_ss_ep_comp_descriptor *comp_desc;
547 const struct usb_endpoint_descriptor *desc;
548 struct dwc3_gadget_ep_cmd_params params;
550 if (dev_WARN_ONCE(dwc->dev, modify && restore,
551 "Can't modify and restore\n"))
554 comp_desc = dep->endpoint.comp_desc;
555 desc = dep->endpoint.desc;
557 memset(¶ms, 0x00, sizeof(params));
559 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
560 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
562 /* Burst size is only needed in SuperSpeed mode */
563 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
564 u32 burst = dep->endpoint.maxburst;
565 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
569 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
570 } else if (restore) {
571 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
572 params.param2 |= dep->saved_state;
574 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
577 if (usb_endpoint_xfer_control(desc))
578 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
580 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
581 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
583 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
584 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
585 | DWC3_DEPCFG_STREAM_EVENT_EN;
586 dep->stream_capable = true;
589 if (!usb_endpoint_xfer_control(desc))
590 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
593 * We are doing 1:1 mapping for endpoints, meaning
594 * Physical Endpoints 2 maps to Logical Endpoint 2 and
595 * so on. We consider the direction bit as part of the physical
596 * endpoint number. So USB endpoint 0x81 is 0x03.
598 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
601 * We must use the lower 16 TX FIFOs even though
605 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
607 if (desc->bInterval) {
611 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13, and it
612 * must be set to 0 when the controller operates in full-speed.
614 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
615 if (dwc->gadget.speed == USB_SPEED_FULL)
618 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
619 dwc->gadget.speed == USB_SPEED_FULL)
620 dep->interval = desc->bInterval;
622 dep->interval = 1 << (desc->bInterval - 1);
624 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
627 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
630 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
632 struct dwc3_gadget_ep_cmd_params params;
634 memset(¶ms, 0x00, sizeof(params));
636 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
638 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
643 * __dwc3_gadget_ep_enable - initializes a hw endpoint
644 * @dep: endpoint to be initialized
645 * @modify: if true, modify existing endpoint configuration
646 * @restore: if true, restore endpoint configuration from scratch buffer
648 * Caller should take care of locking. Execute all necessary commands to
649 * initialize a HW endpoint so it can be used by a gadget driver.
651 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
652 bool modify, bool restore)
654 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
655 struct dwc3 *dwc = dep->dwc;
660 if (!(dep->flags & DWC3_EP_ENABLED)) {
661 ret = dwc3_gadget_start_config(dwc, dep);
666 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
670 if (!(dep->flags & DWC3_EP_ENABLED)) {
671 struct dwc3_trb *trb_st_hw;
672 struct dwc3_trb *trb_link;
674 dep->type = usb_endpoint_type(desc);
675 dep->flags |= DWC3_EP_ENABLED;
676 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
678 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
679 reg |= DWC3_DALEPENA_EP(dep->number);
680 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
682 init_waitqueue_head(&dep->wait_end_transfer);
684 if (usb_endpoint_xfer_control(desc))
687 /* Initialize the TRB ring */
688 dep->trb_dequeue = 0;
689 dep->trb_enqueue = 0;
690 memset(dep->trb_pool, 0,
691 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
693 /* Link TRB. The HWO bit is never reset */
694 trb_st_hw = &dep->trb_pool[0];
696 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
697 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
698 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
699 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
700 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
704 * Issue StartTransfer here with no-op TRB so we can always rely on No
705 * Response Update Transfer command.
707 if (usb_endpoint_xfer_bulk(desc)) {
708 struct dwc3_gadget_ep_cmd_params params;
709 struct dwc3_trb *trb;
713 memset(¶ms, 0, sizeof(params));
714 trb = &dep->trb_pool[0];
715 trb_dma = dwc3_trb_dma_offset(dep, trb);
717 params.param0 = upper_32_bits(trb_dma);
718 params.param1 = lower_32_bits(trb_dma);
720 cmd = DWC3_DEPCMD_STARTTRANSFER;
722 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
726 dep->flags |= DWC3_EP_BUSY;
728 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
729 WARN_ON_ONCE(!dep->resource_index);
734 trace_dwc3_gadget_ep_enable(dep);
739 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
740 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
742 struct dwc3_request *req;
744 dwc3_stop_active_transfer(dwc, dep->number, true);
746 /* - giveback all requests to gadget driver */
747 while (!list_empty(&dep->started_list)) {
748 req = next_request(&dep->started_list);
750 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
753 while (!list_empty(&dep->pending_list)) {
754 req = next_request(&dep->pending_list);
756 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
761 * __dwc3_gadget_ep_disable - disables a hw endpoint
762 * @dep: the endpoint to disable
764 * This function undoes what __dwc3_gadget_ep_enable did and also removes
765 * requests which are currently being processed by the hardware and those which
766 * are not yet scheduled.
768 * Caller should take care of locking.
770 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
772 struct dwc3 *dwc = dep->dwc;
775 trace_dwc3_gadget_ep_disable(dep);
777 dwc3_remove_requests(dwc, dep);
779 /* make sure HW endpoint isn't stalled */
780 if (dep->flags & DWC3_EP_STALL)
781 __dwc3_gadget_ep_set_halt(dep, 0, false);
783 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
784 reg &= ~DWC3_DALEPENA_EP(dep->number);
785 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
787 dep->stream_capable = false;
789 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
791 /* Clear out the ep descriptors for non-ep0 */
792 if (dep->number > 1) {
793 dep->endpoint.comp_desc = NULL;
794 dep->endpoint.desc = NULL;
800 /* -------------------------------------------------------------------------- */
802 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
803 const struct usb_endpoint_descriptor *desc)
808 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
813 /* -------------------------------------------------------------------------- */
815 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
816 const struct usb_endpoint_descriptor *desc)
823 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
824 pr_debug("dwc3: invalid parameters\n");
828 if (!desc->wMaxPacketSize) {
829 pr_debug("dwc3: missing wMaxPacketSize\n");
833 dep = to_dwc3_ep(ep);
836 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
837 "%s is already enabled\n",
841 spin_lock_irqsave(&dwc->lock, flags);
842 ret = __dwc3_gadget_ep_enable(dep, false, false);
843 spin_unlock_irqrestore(&dwc->lock, flags);
848 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
856 pr_debug("dwc3: invalid parameters\n");
860 dep = to_dwc3_ep(ep);
863 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
864 "%s is already disabled\n",
868 spin_lock_irqsave(&dwc->lock, flags);
869 ret = __dwc3_gadget_ep_disable(dep);
870 spin_unlock_irqrestore(&dwc->lock, flags);
875 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
878 struct dwc3_request *req;
879 struct dwc3_ep *dep = to_dwc3_ep(ep);
881 req = kzalloc(sizeof(*req), gfp_flags);
885 req->epnum = dep->number;
888 dep->allocated_requests++;
890 trace_dwc3_alloc_request(req);
892 return &req->request;
895 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
896 struct usb_request *request)
898 struct dwc3_request *req = to_dwc3_request(request);
899 struct dwc3_ep *dep = to_dwc3_ep(ep);
901 dep->allocated_requests--;
902 trace_dwc3_free_request(req);
906 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
908 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
909 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
910 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
912 struct dwc3 *dwc = dep->dwc;
913 struct usb_gadget *gadget = &dwc->gadget;
914 enum usb_device_speed speed = gadget->speed;
916 trb->size = DWC3_TRB_SIZE_LENGTH(length);
917 trb->bpl = lower_32_bits(dma);
918 trb->bph = upper_32_bits(dma);
920 switch (usb_endpoint_type(dep->endpoint.desc)) {
921 case USB_ENDPOINT_XFER_CONTROL:
922 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 case USB_ENDPOINT_XFER_ISOC:
927 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930 * USB Specification 2.0 Section 5.9.2 states that: "If
931 * there is only a single transaction in the microframe,
932 * only a DATA0 data packet PID is used. If there are
933 * two transactions per microframe, DATA1 is used for
934 * the first transaction data packet and DATA0 is used
935 * for the second transaction data packet. If there are
936 * three transactions per microframe, DATA2 is used for
937 * the first transaction data packet, DATA1 is used for
938 * the second, and DATA0 is used for the third."
940 * IOW, we should satisfy the following cases:
942 * 1) length <= maxpacket
945 * 2) maxpacket < length <= (2 * maxpacket)
948 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
949 * - DATA2, DATA1, DATA0
951 if (speed == USB_SPEED_HIGH) {
952 struct usb_ep *ep = &dep->endpoint;
953 unsigned int mult = ep->mult - 1;
954 unsigned int maxp = usb_endpoint_maxp(ep->desc);
956 if (length <= (2 * maxp))
962 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 /* always enable Interrupt on Missed ISOC */
969 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 case USB_ENDPOINT_XFER_BULK:
973 case USB_ENDPOINT_XFER_INT:
974 trb->ctrl = DWC3_TRBCTL_NORMAL;
978 * This is only possible with faulty memory because we
979 * checked it already :)
981 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
982 usb_endpoint_type(dep->endpoint.desc));
986 * Enable Continue on Short Packet
987 * when endpoint is not a stream capable
989 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
990 if (!dep->stream_capable)
991 trb->ctrl |= DWC3_TRB_CTRL_CSP;
994 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 if ((!no_interrupt && !chain) ||
998 (dwc3_calc_trbs_left(dep) == 1))
999 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1004 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1005 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1007 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1009 dwc3_ep_inc_enq(dep);
1011 trace_dwc3_prepare_trb(dep, trb);
1015 * dwc3_prepare_one_trb - setup one TRB from one request
1016 * @dep: endpoint for which this request is prepared
1017 * @req: dwc3_request pointer
1018 * @chain: should this TRB be chained to the next?
1019 * @node: only for isochronous endpoints. First TRB needs different type.
1021 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1022 struct dwc3_request *req, unsigned chain, unsigned node)
1024 struct dwc3_trb *trb;
1025 unsigned length = req->request.length;
1026 unsigned stream_id = req->request.stream_id;
1027 unsigned short_not_ok = req->request.short_not_ok;
1028 unsigned no_interrupt = req->request.no_interrupt;
1029 dma_addr_t dma = req->request.dma;
1031 trb = &dep->trb_pool[dep->trb_enqueue];
1034 dwc3_gadget_move_started_request(req);
1036 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1037 dep->queued_requests++;
1040 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1041 stream_id, short_not_ok, no_interrupt);
1045 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1046 * @dep: The endpoint with the TRB ring
1047 * @index: The index of the current TRB in the ring
1049 * Returns the TRB prior to the one pointed to by the index. If the
1050 * index is 0, we will wrap backwards, skip the link TRB, and return
1051 * the one just before that.
1053 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1058 tmp = DWC3_TRB_NUM - 1;
1060 return &dep->trb_pool[tmp - 1];
1063 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1068 * If the enqueue & dequeue are equal then the TRB ring is either full
1069 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1070 * pending to be processed by the driver.
1072 if (dep->trb_enqueue == dep->trb_dequeue) {
1074 * If there is any request remained in the started_list at
1075 * this point, that means there is no TRB available.
1077 if (!list_empty(&dep->started_list))
1080 return DWC3_TRB_NUM - 1;
1083 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1084 trbs_left &= (DWC3_TRB_NUM - 1);
1086 if (dep->trb_dequeue < dep->trb_enqueue)
1092 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1093 struct dwc3_request *req)
1095 struct scatterlist *sg = req->sg;
1096 struct scatterlist *s;
1099 for_each_sg(sg, s, req->num_pending_sgs, i) {
1100 unsigned int length = req->request.length;
1101 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1102 unsigned int rem = length % maxp;
1103 unsigned chain = true;
1108 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1109 struct dwc3 *dwc = dep->dwc;
1110 struct dwc3_trb *trb;
1112 req->unaligned = true;
1114 /* prepare normal TRB */
1115 dwc3_prepare_one_trb(dep, req, true, i);
1117 /* Now prepare one extra TRB to align transfer size */
1118 trb = &dep->trb_pool[dep->trb_enqueue];
1119 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1120 maxp - rem, false, 1,
1121 req->request.stream_id,
1122 req->request.short_not_ok,
1123 req->request.no_interrupt);
1125 dwc3_prepare_one_trb(dep, req, chain, i);
1128 if (!dwc3_calc_trbs_left(dep))
1133 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1134 struct dwc3_request *req)
1136 unsigned int length = req->request.length;
1137 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1138 unsigned int rem = length % maxp;
1140 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1141 struct dwc3 *dwc = dep->dwc;
1142 struct dwc3_trb *trb;
1144 req->unaligned = true;
1146 /* prepare normal TRB */
1147 dwc3_prepare_one_trb(dep, req, true, 0);
1149 /* Now prepare one extra TRB to align transfer size */
1150 trb = &dep->trb_pool[dep->trb_enqueue];
1151 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1152 false, 1, req->request.stream_id,
1153 req->request.short_not_ok,
1154 req->request.no_interrupt);
1155 } else if (req->request.zero && req->request.length &&
1156 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1157 struct dwc3 *dwc = dep->dwc;
1158 struct dwc3_trb *trb;
1162 /* prepare normal TRB */
1163 dwc3_prepare_one_trb(dep, req, true, 0);
1165 /* Now prepare one extra TRB to handle ZLP */
1166 trb = &dep->trb_pool[dep->trb_enqueue];
1167 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1168 false, 1, req->request.stream_id,
1169 req->request.short_not_ok,
1170 req->request.no_interrupt);
1172 dwc3_prepare_one_trb(dep, req, false, 0);
1177 * dwc3_prepare_trbs - setup TRBs from requests
1178 * @dep: endpoint for which requests are being prepared
1180 * The function goes through the requests list and sets up TRBs for the
1181 * transfers. The function returns once there are no more TRBs available or
1182 * it runs out of requests.
1184 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1186 struct dwc3_request *req, *n;
1188 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1190 if (!dwc3_calc_trbs_left(dep))
1194 * We can get in a situation where there's a request in the started list
1195 * but there weren't enough TRBs to fully kick it in the first time
1196 * around, so it has been waiting for more TRBs to be freed up.
1198 * In that case, we should check if we have a request with pending_sgs
1199 * in the started list and prepare TRBs for that request first,
1200 * otherwise we will prepare TRBs completely out of order and that will
1203 list_for_each_entry(req, &dep->started_list, list) {
1204 if (req->num_pending_sgs > 0)
1205 dwc3_prepare_one_trb_sg(dep, req);
1207 if (!dwc3_calc_trbs_left(dep))
1211 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1212 struct dwc3 *dwc = dep->dwc;
1215 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1220 req->sg = req->request.sg;
1221 req->num_pending_sgs = req->request.num_mapped_sgs;
1223 if (req->num_pending_sgs > 0)
1224 dwc3_prepare_one_trb_sg(dep, req);
1226 dwc3_prepare_one_trb_linear(dep, req);
1228 if (!dwc3_calc_trbs_left(dep))
1233 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1235 struct dwc3_gadget_ep_cmd_params params;
1236 struct dwc3_request *req;
1241 starting = !(dep->flags & DWC3_EP_BUSY);
1243 dwc3_prepare_trbs(dep);
1244 req = next_request(&dep->started_list);
1246 dep->flags |= DWC3_EP_PENDING_REQUEST;
1250 memset(¶ms, 0, sizeof(params));
1253 params.param0 = upper_32_bits(req->trb_dma);
1254 params.param1 = lower_32_bits(req->trb_dma);
1255 cmd = DWC3_DEPCMD_STARTTRANSFER |
1256 DWC3_DEPCMD_PARAM(cmd_param);
1258 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1259 DWC3_DEPCMD_PARAM(dep->resource_index);
1262 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1265 * FIXME we need to iterate over the list of requests
1266 * here and stop, unmap, free and del each of the linked
1267 * requests instead of what we do now.
1270 memset(req->trb, 0, sizeof(struct dwc3_trb));
1271 dep->queued_requests--;
1272 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1276 dep->flags |= DWC3_EP_BUSY;
1279 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1280 WARN_ON_ONCE(!dep->resource_index);
1286 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1290 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1291 return DWC3_DSTS_SOFFN(reg);
1294 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1295 struct dwc3_ep *dep, u32 cur_uf)
1299 if (list_empty(&dep->pending_list)) {
1300 dev_info(dwc->dev, "%s: ran out of requests\n",
1302 dep->flags |= DWC3_EP_PENDING_REQUEST;
1307 * Schedule the first trb for one interval in the future or at
1308 * least 4 microframes.
1310 uf = cur_uf + max_t(u32, 4, dep->interval);
1312 __dwc3_gadget_kick_transfer(dep, uf);
1315 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1316 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1320 mask = ~(dep->interval - 1);
1321 cur_uf = event->parameters & mask;
1323 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1326 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1328 struct dwc3 *dwc = dep->dwc;
1331 if (!dep->endpoint.desc) {
1332 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1337 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1338 &req->request, req->dep->name))
1341 pm_runtime_get(dwc->dev);
1343 req->request.actual = 0;
1344 req->request.status = -EINPROGRESS;
1345 req->direction = dep->direction;
1346 req->epnum = dep->number;
1348 trace_dwc3_ep_queue(req);
1350 list_add_tail(&req->list, &dep->pending_list);
1353 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1354 * wait for a XferNotReady event so we will know what's the current
1355 * (micro-)frame number.
1357 * Without this trick, we are very, very likely gonna get Bus Expiry
1358 * errors which will force us issue EndTransfer command.
1360 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1361 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1362 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1363 dwc3_stop_active_transfer(dwc, dep->number, true);
1364 dep->flags = DWC3_EP_ENABLED;
1368 cur_uf = __dwc3_gadget_get_frame(dwc);
1369 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1370 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1375 if ((dep->flags & DWC3_EP_BUSY) &&
1376 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1377 WARN_ON_ONCE(!dep->resource_index);
1378 ret = __dwc3_gadget_kick_transfer(dep,
1379 dep->resource_index);
1385 if (!dwc3_calc_trbs_left(dep))
1388 ret = __dwc3_gadget_kick_transfer(dep, 0);
1396 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1399 struct dwc3_request *req = to_dwc3_request(request);
1400 struct dwc3_ep *dep = to_dwc3_ep(ep);
1401 struct dwc3 *dwc = dep->dwc;
1403 unsigned long flags;
1407 spin_lock_irqsave(&dwc->lock, flags);
1408 ret = __dwc3_gadget_ep_queue(dep, req);
1409 spin_unlock_irqrestore(&dwc->lock, flags);
1414 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1415 struct usb_request *request)
1417 struct dwc3_request *req = to_dwc3_request(request);
1418 struct dwc3_request *r = NULL;
1420 struct dwc3_ep *dep = to_dwc3_ep(ep);
1421 struct dwc3 *dwc = dep->dwc;
1423 unsigned long flags;
1426 trace_dwc3_ep_dequeue(req);
1428 spin_lock_irqsave(&dwc->lock, flags);
1430 list_for_each_entry(r, &dep->pending_list, list) {
1436 list_for_each_entry(r, &dep->started_list, list) {
1441 /* wait until it is processed */
1442 dwc3_stop_active_transfer(dwc, dep->number, true);
1445 * If request was already started, this means we had to
1446 * stop the transfer. With that we also need to ignore
1447 * all TRBs used by the request, however TRBs can only
1448 * be modified after completion of END_TRANSFER
1449 * command. So what we do here is that we wait for
1450 * END_TRANSFER completion and only after that, we jump
1451 * over TRBs by clearing HWO and incrementing dequeue
1454 * Note that we have 2 possible types of transfers here:
1456 * i) Linear buffer request
1457 * ii) SG-list based request
1459 * SG-list based requests will have r->num_pending_sgs
1460 * set to a valid number (> 0). Linear requests,
1461 * normally use a single TRB.
1463 * For each of these two cases, if r->unaligned flag is
1464 * set, one extra TRB has been used to align transfer
1465 * size to wMaxPacketSize.
1467 * All of these cases need to be taken into
1468 * consideration so we don't mess up our TRB ring
1471 wait_event_lock_irq(dep->wait_end_transfer,
1472 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1478 if (r->num_pending_sgs) {
1479 struct dwc3_trb *trb;
1482 for (i = 0; i < r->num_pending_sgs; i++) {
1484 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1485 dwc3_ep_inc_deq(dep);
1488 if (r->unaligned || r->zero) {
1489 trb = r->trb + r->num_pending_sgs + 1;
1490 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1491 dwc3_ep_inc_deq(dep);
1494 struct dwc3_trb *trb = r->trb;
1496 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1497 dwc3_ep_inc_deq(dep);
1499 if (r->unaligned || r->zero) {
1501 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1502 dwc3_ep_inc_deq(dep);
1507 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1514 /* giveback the request */
1515 dep->queued_requests--;
1516 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1519 spin_unlock_irqrestore(&dwc->lock, flags);
1524 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1526 struct dwc3_gadget_ep_cmd_params params;
1527 struct dwc3 *dwc = dep->dwc;
1530 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1531 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1535 memset(¶ms, 0x00, sizeof(params));
1538 struct dwc3_trb *trb;
1540 unsigned transfer_in_flight;
1543 if (dep->number > 1)
1544 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1546 trb = &dwc->ep0_trb[dep->trb_enqueue];
1548 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1549 started = !list_empty(&dep->started_list);
1551 if (!protocol && ((dep->direction && transfer_in_flight) ||
1552 (!dep->direction && started))) {
1556 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1559 dev_err(dwc->dev, "failed to set STALL on %s\n",
1562 dep->flags |= DWC3_EP_STALL;
1565 ret = dwc3_send_clear_stall_ep_cmd(dep);
1567 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1570 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1576 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1578 struct dwc3_ep *dep = to_dwc3_ep(ep);
1579 struct dwc3 *dwc = dep->dwc;
1581 unsigned long flags;
1585 spin_lock_irqsave(&dwc->lock, flags);
1586 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1587 spin_unlock_irqrestore(&dwc->lock, flags);
1592 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1594 struct dwc3_ep *dep = to_dwc3_ep(ep);
1595 struct dwc3 *dwc = dep->dwc;
1596 unsigned long flags;
1599 spin_lock_irqsave(&dwc->lock, flags);
1600 dep->flags |= DWC3_EP_WEDGE;
1602 if (dep->number == 0 || dep->number == 1)
1603 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1605 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1606 spin_unlock_irqrestore(&dwc->lock, flags);
1611 /* -------------------------------------------------------------------------- */
1613 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1614 .bLength = USB_DT_ENDPOINT_SIZE,
1615 .bDescriptorType = USB_DT_ENDPOINT,
1616 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1619 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1620 .enable = dwc3_gadget_ep0_enable,
1621 .disable = dwc3_gadget_ep0_disable,
1622 .alloc_request = dwc3_gadget_ep_alloc_request,
1623 .free_request = dwc3_gadget_ep_free_request,
1624 .queue = dwc3_gadget_ep0_queue,
1625 .dequeue = dwc3_gadget_ep_dequeue,
1626 .set_halt = dwc3_gadget_ep0_set_halt,
1627 .set_wedge = dwc3_gadget_ep_set_wedge,
1630 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1631 .enable = dwc3_gadget_ep_enable,
1632 .disable = dwc3_gadget_ep_disable,
1633 .alloc_request = dwc3_gadget_ep_alloc_request,
1634 .free_request = dwc3_gadget_ep_free_request,
1635 .queue = dwc3_gadget_ep_queue,
1636 .dequeue = dwc3_gadget_ep_dequeue,
1637 .set_halt = dwc3_gadget_ep_set_halt,
1638 .set_wedge = dwc3_gadget_ep_set_wedge,
1641 /* -------------------------------------------------------------------------- */
1643 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1645 struct dwc3 *dwc = gadget_to_dwc(g);
1647 return __dwc3_gadget_get_frame(dwc);
1650 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1660 * According to the Databook Remote wakeup request should
1661 * be issued only when the device is in early suspend state.
1663 * We can check that via USB Link State bits in DSTS register.
1665 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1667 link_state = DWC3_DSTS_USBLNKST(reg);
1669 switch (link_state) {
1670 case DWC3_LINK_STATE_RESET:
1671 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1672 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1673 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
1674 case DWC3_LINK_STATE_U1:
1675 case DWC3_LINK_STATE_RESUME:
1681 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1683 dev_err(dwc->dev, "failed to put link in Recovery\n");
1687 /* Recent versions do this automatically */
1688 if (dwc->revision < DWC3_REVISION_194A) {
1689 /* write zeroes to Link Change Request */
1690 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1691 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1692 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1695 /* poll until Link State changes to ON */
1699 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1701 /* in HS, means ON */
1702 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1706 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1707 dev_err(dwc->dev, "failed to send remote wakeup\n");
1714 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1716 struct dwc3 *dwc = gadget_to_dwc(g);
1717 unsigned long flags;
1720 spin_lock_irqsave(&dwc->lock, flags);
1721 ret = __dwc3_gadget_wakeup(dwc);
1722 spin_unlock_irqrestore(&dwc->lock, flags);
1727 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1730 struct dwc3 *dwc = gadget_to_dwc(g);
1731 unsigned long flags;
1733 spin_lock_irqsave(&dwc->lock, flags);
1734 g->is_selfpowered = !!is_selfpowered;
1735 spin_unlock_irqrestore(&dwc->lock, flags);
1740 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1745 if (pm_runtime_suspended(dwc->dev))
1748 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1750 if (dwc->revision <= DWC3_REVISION_187A) {
1751 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1752 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1755 if (dwc->revision >= DWC3_REVISION_194A)
1756 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1757 reg |= DWC3_DCTL_RUN_STOP;
1759 if (dwc->has_hibernation)
1760 reg |= DWC3_DCTL_KEEP_CONNECT;
1762 dwc->pullups_connected = true;
1764 reg &= ~DWC3_DCTL_RUN_STOP;
1766 if (dwc->has_hibernation && !suspend)
1767 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1769 dwc->pullups_connected = false;
1772 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1775 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1776 reg &= DWC3_DSTS_DEVCTRLHLT;
1777 } while (--timeout && !(!is_on ^ !reg));
1785 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1787 struct dwc3 *dwc = gadget_to_dwc(g);
1788 unsigned long flags;
1794 * Per databook, when we want to stop the gadget, if a control transfer
1795 * is still in process, complete it and get the core into setup phase.
1797 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1798 reinit_completion(&dwc->ep0_in_setup);
1800 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1801 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1803 dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
1806 spin_lock_irqsave(&dwc->lock, flags);
1807 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1808 spin_unlock_irqrestore(&dwc->lock, flags);
1813 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1817 /* Enable all but Start and End of Frame IRQs */
1818 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1819 DWC3_DEVTEN_EVNTOVERFLOWEN |
1820 DWC3_DEVTEN_CMDCMPLTEN |
1821 DWC3_DEVTEN_ERRTICERREN |
1822 DWC3_DEVTEN_WKUPEVTEN |
1823 DWC3_DEVTEN_CONNECTDONEEN |
1824 DWC3_DEVTEN_USBRSTEN |
1825 DWC3_DEVTEN_DISCONNEVTEN);
1827 if (dwc->revision < DWC3_REVISION_250A)
1828 reg |= DWC3_DEVTEN_ULSTCNGEN;
1830 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
1831 if (dwc->revision >= DWC3_REVISION_230A)
1832 reg |= DWC3_DEVTEN_EOPFEN;
1834 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1837 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1839 /* mask all interrupts */
1840 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1843 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1844 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1847 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1848 * @dwc: pointer to our context structure
1850 * The following looks like complex but it's actually very simple. In order to
1851 * calculate the number of packets we can burst at once on OUT transfers, we're
1852 * gonna use RxFIFO size.
1854 * To calculate RxFIFO size we need two numbers:
1855 * MDWIDTH = size, in bits, of the internal memory bus
1856 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1858 * Given these two numbers, the formula is simple:
1860 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1862 * 24 bytes is for 3x SETUP packets
1863 * 16 bytes is a clock domain crossing tolerance
1865 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1867 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1874 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1875 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1877 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1878 nump = min_t(u32, nump, 16);
1881 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1882 reg &= ~DWC3_DCFG_NUMP_MASK;
1883 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1884 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1887 static int __dwc3_gadget_start(struct dwc3 *dwc)
1889 struct dwc3_ep *dep;
1894 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1895 * the core supports IMOD, disable it.
1897 if (dwc->imod_interval) {
1898 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1899 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1900 } else if (dwc3_has_imod(dwc)) {
1901 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1905 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1906 * field instead of letting dwc3 itself calculate that automatically.
1908 * This way, we maximize the chances that we'll be able to get several
1909 * bursts of data without going through any sort of endpoint throttling.
1911 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1912 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1913 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1915 dwc3_gadget_setup_nump(dwc);
1917 /* Start with SuperSpeed Default */
1918 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1921 ret = __dwc3_gadget_ep_enable(dep, false, false);
1923 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1928 ret = __dwc3_gadget_ep_enable(dep, false, false);
1930 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1934 /* begin to receive SETUP packets */
1935 dwc->ep0state = EP0_SETUP_PHASE;
1936 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1937 dwc->delayed_status = false;
1938 dwc3_ep0_out_start(dwc);
1940 dwc3_gadget_enable_irq(dwc);
1945 __dwc3_gadget_ep_disable(dwc->eps[0]);
1951 static int dwc3_gadget_start(struct usb_gadget *g,
1952 struct usb_gadget_driver *driver)
1954 struct dwc3 *dwc = gadget_to_dwc(g);
1955 unsigned long flags;
1959 irq = dwc->irq_gadget;
1960 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1961 IRQF_SHARED, "dwc3", dwc->ev_buf);
1963 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1968 spin_lock_irqsave(&dwc->lock, flags);
1969 if (dwc->gadget_driver) {
1970 dev_err(dwc->dev, "%s is already bound to %s\n",
1972 dwc->gadget_driver->driver.name);
1977 dwc->gadget_driver = driver;
1979 if (pm_runtime_active(dwc->dev))
1980 __dwc3_gadget_start(dwc);
1982 spin_unlock_irqrestore(&dwc->lock, flags);
1987 spin_unlock_irqrestore(&dwc->lock, flags);
1994 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1996 dwc3_gadget_disable_irq(dwc);
1997 __dwc3_gadget_ep_disable(dwc->eps[0]);
1998 __dwc3_gadget_ep_disable(dwc->eps[1]);
2001 static int dwc3_gadget_stop(struct usb_gadget *g)
2003 struct dwc3 *dwc = gadget_to_dwc(g);
2004 unsigned long flags;
2007 spin_lock_irqsave(&dwc->lock, flags);
2009 if (pm_runtime_suspended(dwc->dev))
2012 __dwc3_gadget_stop(dwc);
2014 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2015 struct dwc3_ep *dep = dwc->eps[epnum];
2020 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2023 wait_event_lock_irq(dep->wait_end_transfer,
2024 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
2029 dwc->gadget_driver = NULL;
2030 spin_unlock_irqrestore(&dwc->lock, flags);
2032 free_irq(dwc->irq_gadget, dwc->ev_buf);
2037 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2038 enum usb_device_speed speed)
2040 struct dwc3 *dwc = gadget_to_dwc(g);
2041 unsigned long flags;
2044 spin_lock_irqsave(&dwc->lock, flags);
2045 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2046 reg &= ~(DWC3_DCFG_SPEED_MASK);
2049 * WORKAROUND: DWC3 revision < 2.20a have an issue
2050 * which would cause metastability state on Run/Stop
2051 * bit if we try to force the IP to USB2-only mode.
2053 * Because of that, we cannot configure the IP to any
2054 * speed other than the SuperSpeed
2058 * STAR#9000525659: Clock Domain Crossing on DCTL in
2061 if (dwc->revision < DWC3_REVISION_220A &&
2062 !dwc->dis_metastability_quirk) {
2063 reg |= DWC3_DCFG_SUPERSPEED;
2067 reg |= DWC3_DCFG_LOWSPEED;
2069 case USB_SPEED_FULL:
2070 reg |= DWC3_DCFG_FULLSPEED;
2072 case USB_SPEED_HIGH:
2073 reg |= DWC3_DCFG_HIGHSPEED;
2075 case USB_SPEED_SUPER:
2076 reg |= DWC3_DCFG_SUPERSPEED;
2078 case USB_SPEED_SUPER_PLUS:
2079 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2082 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2084 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2085 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2087 reg |= DWC3_DCFG_SUPERSPEED;
2090 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2092 spin_unlock_irqrestore(&dwc->lock, flags);
2095 static const struct usb_gadget_ops dwc3_gadget_ops = {
2096 .get_frame = dwc3_gadget_get_frame,
2097 .wakeup = dwc3_gadget_wakeup,
2098 .set_selfpowered = dwc3_gadget_set_selfpowered,
2099 .pullup = dwc3_gadget_pullup,
2100 .udc_start = dwc3_gadget_start,
2101 .udc_stop = dwc3_gadget_stop,
2102 .udc_set_speed = dwc3_gadget_set_speed,
2105 /* -------------------------------------------------------------------------- */
2107 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2109 struct dwc3_ep *dep;
2112 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2114 for (epnum = 0; epnum < total; epnum++) {
2115 bool direction = epnum & 1;
2116 u8 num = epnum >> 1;
2118 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2123 dep->number = epnum;
2124 dep->direction = direction;
2125 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2126 dwc->eps[epnum] = dep;
2128 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2129 direction ? "in" : "out");
2131 dep->endpoint.name = dep->name;
2133 if (!(dep->number > 1)) {
2134 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2135 dep->endpoint.comp_desc = NULL;
2138 spin_lock_init(&dep->lock);
2141 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2142 dep->endpoint.maxburst = 1;
2143 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2145 dwc->gadget.ep0 = &dep->endpoint;
2146 } else if (direction) {
2152 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2153 /* MDWIDTH is represented in bits, we need it in bytes */
2156 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2157 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2159 /* FIFO Depth is in MDWDITH bytes. Multiply */
2162 kbytes = size / 1024;
2167 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2168 * internal overhead. We don't really know how these are used,
2169 * but documentation say it exists.
2171 size -= mdwidth * (kbytes + 1);
2174 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2176 dep->endpoint.max_streams = 15;
2177 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2178 list_add_tail(&dep->endpoint.ep_list,
2179 &dwc->gadget.ep_list);
2181 ret = dwc3_alloc_trb_pool(dep);
2187 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2188 dep->endpoint.max_streams = 15;
2189 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2190 list_add_tail(&dep->endpoint.ep_list,
2191 &dwc->gadget.ep_list);
2193 ret = dwc3_alloc_trb_pool(dep);
2199 dep->endpoint.caps.type_control = true;
2201 dep->endpoint.caps.type_iso = true;
2202 dep->endpoint.caps.type_bulk = true;
2203 dep->endpoint.caps.type_int = true;
2206 dep->endpoint.caps.dir_in = direction;
2207 dep->endpoint.caps.dir_out = !direction;
2209 INIT_LIST_HEAD(&dep->pending_list);
2210 INIT_LIST_HEAD(&dep->started_list);
2216 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2218 struct dwc3_ep *dep;
2221 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2222 dep = dwc->eps[epnum];
2226 * Physical endpoints 0 and 1 are special; they form the
2227 * bi-directional USB endpoint 0.
2229 * For those two physical endpoints, we don't allocate a TRB
2230 * pool nor do we add them the endpoints list. Due to that, we
2231 * shouldn't do these two operations otherwise we would end up
2232 * with all sorts of bugs when removing dwc3.ko.
2234 if (epnum != 0 && epnum != 1) {
2235 dwc3_free_trb_pool(dep);
2236 list_del(&dep->endpoint.ep_list);
2243 /* -------------------------------------------------------------------------- */
2245 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2246 struct dwc3_request *req, struct dwc3_trb *trb,
2247 const struct dwc3_event_depevt *event, int status,
2251 unsigned int s_pkt = 0;
2252 unsigned int trb_status;
2254 dwc3_ep_inc_deq(dep);
2256 if (req->trb == trb)
2257 dep->queued_requests--;
2259 trace_dwc3_complete_trb(dep, trb);
2262 * If we're in the middle of series of chained TRBs and we
2263 * receive a short transfer along the way, DWC3 will skip
2264 * through all TRBs including the last TRB in the chain (the
2265 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2266 * bit and SW has to do it manually.
2268 * We're going to do that here to avoid problems of HW trying
2269 * to use bogus TRBs for transfers.
2271 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2272 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2275 * If we're dealing with unaligned size OUT transfer, we will be left
2276 * with one TRB pending in the ring. We need to manually clear HWO bit
2279 if ((req->zero || req->unaligned) && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2280 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2284 count = trb->size & DWC3_TRB_SIZE_MASK;
2285 req->remaining += count;
2287 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2290 if (dep->direction) {
2292 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2293 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2295 * If missed isoc occurred and there is
2296 * no request queued then issue END
2297 * TRANSFER, so that core generates
2298 * next xfernotready and we will issue
2299 * a fresh START TRANSFER.
2300 * If there are still queued request
2301 * then wait, do not issue either END
2302 * or UPDATE TRANSFER, just attach next
2303 * request in pending_list during
2304 * giveback.If any future queued request
2305 * is successfully transferred then we
2306 * will issue UPDATE TRANSFER for all
2307 * request in the pending_list.
2309 dep->flags |= DWC3_EP_MISSED_ISOC;
2311 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2313 status = -ECONNRESET;
2316 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2319 if (count && (event->status & DEPEVT_STATUS_SHORT))
2323 if (s_pkt && !chain)
2326 if ((event->status & DEPEVT_STATUS_IOC) &&
2327 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2333 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2334 const struct dwc3_event_depevt *event, int status)
2336 struct dwc3_request *req, *n;
2337 struct dwc3_trb *trb;
2341 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2345 length = req->request.length;
2346 chain = req->num_pending_sgs > 0;
2348 struct scatterlist *sg = req->sg;
2349 struct scatterlist *s;
2350 unsigned int pending = req->num_pending_sgs;
2353 for_each_sg(sg, s, pending, i) {
2354 trb = &dep->trb_pool[dep->trb_dequeue];
2356 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2359 req->sg = sg_next(s);
2360 req->num_pending_sgs--;
2362 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2363 event, status, chain);
2368 trb = &dep->trb_pool[dep->trb_dequeue];
2369 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2370 event, status, chain);
2373 if (req->unaligned || req->zero) {
2374 trb = &dep->trb_pool[dep->trb_dequeue];
2375 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2376 event, status, false);
2377 req->unaligned = false;
2381 req->request.actual = length - req->remaining;
2383 if ((req->request.actual < length) && req->num_pending_sgs)
2384 return __dwc3_gadget_kick_transfer(dep, 0);
2386 dwc3_gadget_giveback(dep, req, status);
2389 if ((event->status & DEPEVT_STATUS_IOC) &&
2390 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2397 * Our endpoint might get disabled by another thread during
2398 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2399 * early on so DWC3_EP_BUSY flag gets cleared
2401 if (!dep->endpoint.desc)
2404 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2405 list_empty(&dep->started_list)) {
2406 if (list_empty(&dep->pending_list)) {
2408 * If there is no entry in request list then do
2409 * not issue END TRANSFER now. Just set PENDING
2410 * flag, so that END TRANSFER is issued when an
2411 * entry is added into request list.
2413 dep->flags = DWC3_EP_PENDING_REQUEST;
2415 dwc3_stop_active_transfer(dwc, dep->number, true);
2416 dep->flags = DWC3_EP_ENABLED;
2421 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2427 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2428 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2430 unsigned status = 0;
2432 u32 is_xfer_complete;
2434 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2436 if (event->status & DEPEVT_STATUS_BUSERR)
2437 status = -ECONNRESET;
2439 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2440 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2441 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2442 dep->flags &= ~DWC3_EP_BUSY;
2445 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2446 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2448 if (dwc->revision < DWC3_REVISION_183A) {
2452 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2455 if (!(dep->flags & DWC3_EP_ENABLED))
2458 if (!list_empty(&dep->started_list))
2462 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2464 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2470 * Our endpoint might get disabled by another thread during
2471 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2472 * early on so DWC3_EP_BUSY flag gets cleared
2474 if (!dep->endpoint.desc)
2477 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2480 ret = __dwc3_gadget_kick_transfer(dep, 0);
2481 if (!ret || ret == -EBUSY)
2486 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2487 const struct dwc3_event_depevt *event)
2489 struct dwc3_ep *dep;
2490 u8 epnum = event->endpoint_number;
2493 dep = dwc->eps[epnum];
2495 if (!(dep->flags & DWC3_EP_ENABLED)) {
2496 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2499 /* Handle only EPCMDCMPLT when EP disabled */
2500 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2504 if (epnum == 0 || epnum == 1) {
2505 dwc3_ep0_interrupt(dwc, event);
2509 switch (event->endpoint_event) {
2510 case DWC3_DEPEVT_XFERCOMPLETE:
2511 dep->resource_index = 0;
2513 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2514 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2518 dwc3_endpoint_transfer_complete(dwc, dep, event);
2520 case DWC3_DEPEVT_XFERINPROGRESS:
2521 dwc3_endpoint_transfer_complete(dwc, dep, event);
2523 case DWC3_DEPEVT_XFERNOTREADY:
2524 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2525 dwc3_gadget_start_isoc(dwc, dep, event);
2529 ret = __dwc3_gadget_kick_transfer(dep, 0);
2530 if (!ret || ret == -EBUSY)
2535 case DWC3_DEPEVT_STREAMEVT:
2536 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2537 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2542 case DWC3_DEPEVT_EPCMDCMPLT:
2543 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2545 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2546 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2547 wake_up(&dep->wait_end_transfer);
2550 case DWC3_DEPEVT_RXTXFIFOEVT:
2555 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2557 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2558 spin_unlock(&dwc->lock);
2559 dwc->gadget_driver->disconnect(&dwc->gadget);
2560 spin_lock(&dwc->lock);
2564 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2566 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2567 spin_unlock(&dwc->lock);
2568 dwc->gadget_driver->suspend(&dwc->gadget);
2569 spin_lock(&dwc->lock);
2573 static void dwc3_resume_gadget(struct dwc3 *dwc)
2575 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2576 spin_unlock(&dwc->lock);
2577 dwc->gadget_driver->resume(&dwc->gadget);
2578 spin_lock(&dwc->lock);
2582 static void dwc3_reset_gadget(struct dwc3 *dwc)
2584 if (!dwc->gadget_driver)
2587 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2588 spin_unlock(&dwc->lock);
2589 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2590 spin_lock(&dwc->lock);
2594 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2596 struct dwc3_ep *dep;
2597 struct dwc3_gadget_ep_cmd_params params;
2601 dep = dwc->eps[epnum];
2603 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2604 !dep->resource_index)
2608 * NOTICE: We are violating what the Databook says about the
2609 * EndTransfer command. Ideally we would _always_ wait for the
2610 * EndTransfer Command Completion IRQ, but that's causing too
2611 * much trouble synchronizing between us and gadget driver.
2613 * We have discussed this with the IP Provider and it was
2614 * suggested to giveback all requests here, but give HW some
2615 * extra time to synchronize with the interconnect. We're using
2616 * an arbitrary 100us delay for that.
2618 * Note also that a similar handling was tested by Synopsys
2619 * (thanks a lot Paul) and nothing bad has come out of it.
2620 * In short, what we're doing is:
2622 * - Issue EndTransfer WITH CMDIOC bit set
2625 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2626 * supports a mode to work around the above limitation. The
2627 * software can poll the CMDACT bit in the DEPCMD register
2628 * after issuing a EndTransfer command. This mode is enabled
2629 * by writing GUCTL2[14]. This polling is already done in the
2630 * dwc3_send_gadget_ep_cmd() function so if the mode is
2631 * enabled, the EndTransfer command will have completed upon
2632 * returning from this function and we don't need to delay for
2635 * This mode is NOT available on the DWC_usb31 IP.
2638 cmd = DWC3_DEPCMD_ENDTRANSFER;
2639 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2640 cmd |= DWC3_DEPCMD_CMDIOC;
2641 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2642 memset(¶ms, 0, sizeof(params));
2643 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2645 dep->resource_index = 0;
2646 dep->flags &= ~DWC3_EP_BUSY;
2648 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2649 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2654 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2658 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2659 struct dwc3_ep *dep;
2662 dep = dwc->eps[epnum];
2666 if (!(dep->flags & DWC3_EP_STALL))
2669 dep->flags &= ~DWC3_EP_STALL;
2671 ret = dwc3_send_clear_stall_ep_cmd(dep);
2676 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2680 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2681 reg &= ~DWC3_DCTL_INITU1ENA;
2682 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2684 reg &= ~DWC3_DCTL_INITU2ENA;
2685 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2687 dwc3_disconnect_gadget(dwc);
2689 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2690 dwc->setup_packet_pending = false;
2691 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2693 dwc->connected = false;
2696 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2700 dwc->connected = true;
2703 * Ideally, dwc3_reset_gadget() would trigger the function
2704 * drivers to stop any active transfers through ep disable.
2705 * However, for functions which defer ep disable, such as mass
2706 * storage, we will need to rely on the call to stop active
2707 * transfers here, and avoid allowing of request queuing.
2709 dwc->connected = false;
2712 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2713 * would cause a missing Disconnect Event if there's a
2714 * pending Setup Packet in the FIFO.
2716 * There's no suggested workaround on the official Bug
2717 * report, which states that "unless the driver/application
2718 * is doing any special handling of a disconnect event,
2719 * there is no functional issue".
2721 * Unfortunately, it turns out that we _do_ some special
2722 * handling of a disconnect event, namely complete all
2723 * pending transfers, notify gadget driver of the
2724 * disconnection, and so on.
2726 * Our suggested workaround is to follow the Disconnect
2727 * Event steps here, instead, based on a setup_packet_pending
2728 * flag. Such flag gets set whenever we have a SETUP_PENDING
2729 * status for EP0 TRBs and gets cleared on XferComplete for the
2734 * STAR#9000466709: RTL: Device : Disconnect event not
2735 * generated if setup packet pending in FIFO
2737 if (dwc->revision < DWC3_REVISION_188A) {
2738 if (dwc->setup_packet_pending)
2739 dwc3_gadget_disconnect_interrupt(dwc);
2742 dwc3_reset_gadget(dwc);
2744 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2745 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2746 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2747 dwc->test_mode = false;
2748 dwc3_clear_stall_all_ep(dwc);
2750 /* Reset device address to zero */
2751 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2752 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2753 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2756 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2758 struct dwc3_ep *dep;
2763 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2764 speed = reg & DWC3_DSTS_CONNECTSPD;
2768 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2769 * each time on Connect Done.
2771 * Currently we always use the reset value. If any platform
2772 * wants to set this to a different value, we need to add a
2773 * setting and update GCTL.RAMCLKSEL here.
2777 case DWC3_DSTS_SUPERSPEED_PLUS:
2778 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2779 dwc->gadget.ep0->maxpacket = 512;
2780 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2782 case DWC3_DSTS_SUPERSPEED:
2784 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2785 * would cause a missing USB3 Reset event.
2787 * In such situations, we should force a USB3 Reset
2788 * event by calling our dwc3_gadget_reset_interrupt()
2793 * STAR#9000483510: RTL: SS : USB3 reset event may
2794 * not be generated always when the link enters poll
2796 if (dwc->revision < DWC3_REVISION_190A)
2797 dwc3_gadget_reset_interrupt(dwc);
2799 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2800 dwc->gadget.ep0->maxpacket = 512;
2801 dwc->gadget.speed = USB_SPEED_SUPER;
2803 case DWC3_DSTS_HIGHSPEED:
2804 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2805 dwc->gadget.ep0->maxpacket = 64;
2806 dwc->gadget.speed = USB_SPEED_HIGH;
2808 case DWC3_DSTS_FULLSPEED:
2809 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2810 dwc->gadget.ep0->maxpacket = 64;
2811 dwc->gadget.speed = USB_SPEED_FULL;
2813 case DWC3_DSTS_LOWSPEED:
2814 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2815 dwc->gadget.ep0->maxpacket = 8;
2816 dwc->gadget.speed = USB_SPEED_LOW;
2820 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2822 /* Enable USB2 LPM Capability */
2824 if ((dwc->revision > DWC3_REVISION_194A) &&
2825 (speed != DWC3_DSTS_SUPERSPEED) &&
2826 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2827 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2828 reg |= DWC3_DCFG_LPM_CAP;
2829 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2831 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2832 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2834 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2837 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2838 * DCFG.LPMCap is set, core responses with an ACK and the
2839 * BESL value in the LPM token is less than or equal to LPM
2842 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2843 && dwc->has_lpm_erratum,
2844 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2846 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2847 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2849 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2851 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2852 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2853 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2857 ret = __dwc3_gadget_ep_enable(dep, true, false);
2859 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2864 ret = __dwc3_gadget_ep_enable(dep, true, false);
2866 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2871 * Configure PHY via GUSB3PIPECTLn if required.
2873 * Update GTXFIFOSIZn
2875 * In both cases reset values should be sufficient.
2879 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2882 * TODO take core out of low power mode when that's
2886 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2887 spin_unlock(&dwc->lock);
2888 dwc->gadget_driver->resume(&dwc->gadget);
2889 spin_lock(&dwc->lock);
2893 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2894 unsigned int evtinfo)
2896 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2897 unsigned int pwropt;
2900 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2901 * Hibernation mode enabled which would show up when device detects
2902 * host-initiated U3 exit.
2904 * In that case, device will generate a Link State Change Interrupt
2905 * from U3 to RESUME which is only necessary if Hibernation is
2908 * There are no functional changes due to such spurious event and we
2909 * just need to ignore it.
2913 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2916 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2917 if ((dwc->revision < DWC3_REVISION_250A) &&
2918 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2919 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2920 (next == DWC3_LINK_STATE_RESUME)) {
2926 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2927 * on the link partner, the USB session might do multiple entry/exit
2928 * of low power states before a transfer takes place.
2930 * Due to this problem, we might experience lower throughput. The
2931 * suggested workaround is to disable DCTL[12:9] bits if we're
2932 * transitioning from U1/U2 to U0 and enable those bits again
2933 * after a transfer completes and there are no pending transfers
2934 * on any of the enabled endpoints.
2936 * This is the first half of that workaround.
2940 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2941 * core send LGO_Ux entering U0
2943 if (dwc->revision < DWC3_REVISION_183A) {
2944 if (next == DWC3_LINK_STATE_U0) {
2948 switch (dwc->link_state) {
2949 case DWC3_LINK_STATE_U1:
2950 case DWC3_LINK_STATE_U2:
2951 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2952 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2953 | DWC3_DCTL_ACCEPTU2ENA
2954 | DWC3_DCTL_INITU1ENA
2955 | DWC3_DCTL_ACCEPTU1ENA);
2958 dwc->u1u2 = reg & u1u2;
2962 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2972 case DWC3_LINK_STATE_U1:
2973 if (dwc->speed == USB_SPEED_SUPER)
2974 dwc3_suspend_gadget(dwc);
2976 case DWC3_LINK_STATE_U2:
2977 case DWC3_LINK_STATE_U3:
2978 dwc3_suspend_gadget(dwc);
2980 case DWC3_LINK_STATE_RESUME:
2981 dwc3_resume_gadget(dwc);
2988 dwc->link_state = next;
2991 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2992 unsigned int evtinfo)
2994 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2996 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2997 dwc3_suspend_gadget(dwc);
2999 dwc->link_state = next;
3002 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3003 unsigned int evtinfo)
3005 unsigned int is_ss = evtinfo & BIT(4);
3008 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3009 * have a known issue which can cause USB CV TD.9.23 to fail
3012 * Because of this issue, core could generate bogus hibernation
3013 * events which SW needs to ignore.
3017 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3018 * Device Fallback from SuperSpeed
3020 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3023 /* enter hibernation here */
3026 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3027 const struct dwc3_event_devt *event)
3029 switch (event->type) {
3030 case DWC3_DEVICE_EVENT_DISCONNECT:
3031 dwc3_gadget_disconnect_interrupt(dwc);
3033 case DWC3_DEVICE_EVENT_RESET:
3034 dwc3_gadget_reset_interrupt(dwc);
3036 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3037 dwc3_gadget_conndone_interrupt(dwc);
3039 case DWC3_DEVICE_EVENT_WAKEUP:
3040 dwc3_gadget_wakeup_interrupt(dwc);
3042 case DWC3_DEVICE_EVENT_HIBER_REQ:
3043 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3044 "unexpected hibernation event\n"))
3047 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3049 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3050 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3052 case DWC3_DEVICE_EVENT_EOPF:
3053 /* It changed to be suspend event for version 2.30a and above */
3054 if (dwc->revision >= DWC3_REVISION_230A) {
3056 * Ignore suspend event until the gadget enters into
3057 * USB_STATE_CONFIGURED state.
3059 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3060 dwc3_gadget_suspend_interrupt(dwc,
3064 case DWC3_DEVICE_EVENT_SOF:
3065 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3066 case DWC3_DEVICE_EVENT_CMD_CMPL:
3067 case DWC3_DEVICE_EVENT_OVERFLOW:
3070 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3074 static void dwc3_process_event_entry(struct dwc3 *dwc,
3075 const union dwc3_event *event)
3077 trace_dwc3_event(event->raw, dwc);
3079 if (!event->type.is_devspec)
3080 dwc3_endpoint_interrupt(dwc, &event->depevt);
3081 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3082 dwc3_gadget_interrupt(dwc, &event->devt);
3084 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3087 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3089 struct dwc3 *dwc = evt->dwc;
3090 irqreturn_t ret = IRQ_NONE;
3096 if (!(evt->flags & DWC3_EVENT_PENDING))
3100 union dwc3_event event;
3102 event.raw = *(u32 *) (evt->cache + evt->lpos);
3104 dwc3_process_event_entry(dwc, &event);
3107 * FIXME we wrap around correctly to the next entry as
3108 * almost all entries are 4 bytes in size. There is one
3109 * entry which has 12 bytes which is a regular entry
3110 * followed by 8 bytes data. ATM I don't know how
3111 * things are organized if we get next to the a
3112 * boundary so I worry about that once we try to handle
3115 evt->lpos = (evt->lpos + 4) % evt->length;
3120 evt->flags &= ~DWC3_EVENT_PENDING;
3123 /* Unmask interrupt */
3124 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3125 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3126 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3128 if (dwc->imod_interval) {
3129 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3130 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3136 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3138 struct dwc3_event_buffer *evt = _evt;
3139 struct dwc3 *dwc = evt->dwc;
3140 unsigned long flags;
3141 irqreturn_t ret = IRQ_NONE;
3143 spin_lock_irqsave(&dwc->lock, flags);
3144 ret = dwc3_process_event_buf(evt);
3145 spin_unlock_irqrestore(&dwc->lock, flags);
3150 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3152 struct dwc3 *dwc = evt->dwc;
3157 if (pm_runtime_suspended(dwc->dev)) {
3158 pm_runtime_get(dwc->dev);
3159 disable_irq_nosync(dwc->irq_gadget);
3160 dwc->pending_events = true;
3165 * With PCIe legacy interrupt, test shows that top-half irq handler can
3166 * be called again after HW interrupt deassertion. Check if bottom-half
3167 * irq event handler completes before caching new event to prevent
3170 if (evt->flags & DWC3_EVENT_PENDING)
3173 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3174 count &= DWC3_GEVNTCOUNT_MASK;
3179 evt->flags |= DWC3_EVENT_PENDING;
3181 /* Mask interrupt */
3182 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3183 reg |= DWC3_GEVNTSIZ_INTMASK;
3184 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3186 amount = min(count, evt->length - evt->lpos);
3187 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3190 memcpy(evt->cache, evt->buf, count - amount);
3192 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3194 return IRQ_WAKE_THREAD;
3197 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3199 struct dwc3_event_buffer *evt = _evt;
3201 return dwc3_check_event_buf(evt);
3204 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3206 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3209 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3213 if (irq == -EPROBE_DEFER)
3216 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3220 if (irq == -EPROBE_DEFER)
3223 irq = platform_get_irq(dwc3_pdev, 0);
3227 if (irq != -EPROBE_DEFER)
3228 dev_err(dwc->dev, "missing peripheral IRQ\n");
3238 * dwc3_gadget_init - initializes gadget related registers
3239 * @dwc: pointer to our controller context structure
3241 * Returns 0 on success otherwise negative errno.
3243 int dwc3_gadget_init(struct dwc3 *dwc)
3248 irq = dwc3_gadget_get_irq(dwc);
3254 dwc->irq_gadget = irq;
3256 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3257 sizeof(*dwc->ep0_trb) * 2,
3258 &dwc->ep0_trb_addr, GFP_KERNEL);
3259 if (!dwc->ep0_trb) {
3260 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3265 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3266 if (!dwc->setup_buf) {
3271 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3272 &dwc->bounce_addr, GFP_KERNEL);
3278 init_completion(&dwc->ep0_in_setup);
3280 dwc->gadget.ops = &dwc3_gadget_ops;
3281 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3282 dwc->gadget.sg_supported = true;
3283 dwc->gadget.name = "dwc3-gadget";
3286 * FIXME We might be setting max_speed to <SUPER, however versions
3287 * <2.20a of dwc3 have an issue with metastability (documented
3288 * elsewhere in this driver) which tells us we can't set max speed to
3289 * anything lower than SUPER.
3291 * Because gadget.max_speed is only used by composite.c and function
3292 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3293 * to happen so we avoid sending SuperSpeed Capability descriptor
3294 * together with our BOS descriptor as that could confuse host into
3295 * thinking we can handle super speed.
3297 * Note that, in fact, we won't even support GetBOS requests when speed
3298 * is less than super speed because we don't have means, yet, to tell
3299 * composite.c that we are USB 2.0 + LPM ECN.
3301 if (dwc->revision < DWC3_REVISION_220A &&
3302 !dwc->dis_metastability_quirk)
3303 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3306 dwc->gadget.max_speed = dwc->maximum_speed;
3309 * REVISIT: Here we should clear all pending IRQs to be
3310 * sure we're starting from a well known location.
3313 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3317 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3319 dev_err(dwc->dev, "failed to register udc\n");
3323 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3328 dwc3_gadget_free_endpoints(dwc);
3331 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3335 kfree(dwc->setup_buf);
3338 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3339 dwc->ep0_trb, dwc->ep0_trb_addr);
3345 /* -------------------------------------------------------------------------- */
3347 void dwc3_gadget_exit(struct dwc3 *dwc)
3349 usb_del_gadget_udc(&dwc->gadget);
3350 dwc3_gadget_free_endpoints(dwc);
3351 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3353 kfree(dwc->setup_buf);
3354 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3355 dwc->ep0_trb, dwc->ep0_trb_addr);
3358 int dwc3_gadget_suspend(struct dwc3 *dwc)
3360 if (!dwc->gadget_driver)
3363 dwc3_gadget_run_stop(dwc, false, false);
3364 dwc3_disconnect_gadget(dwc);
3365 __dwc3_gadget_stop(dwc);
3367 synchronize_irq(dwc->irq_gadget);
3372 int dwc3_gadget_resume(struct dwc3 *dwc)
3376 if (!dwc->gadget_driver)
3379 ret = __dwc3_gadget_start(dwc);
3383 ret = dwc3_gadget_run_stop(dwc, true, false);
3390 __dwc3_gadget_stop(dwc);
3396 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3398 if (dwc->pending_events) {
3399 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3400 dwc->pending_events = false;
3401 enable_irq(dwc->irq_gadget);