1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8 *index)
153 if (*index == (DWC3_TRB_NUM - 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
178 struct dwc3 *dwc = dep->dwc;
180 list_del(&req->list);
182 req->needs_extra_trb = false;
184 if (req->request.status == -EINPROGRESS)
185 req->request.status = status;
188 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 &req->request, req->direction);
192 trace_dwc3_gadget_giveback(req);
195 pm_runtime_put(dwc->dev);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
211 struct dwc3 *dwc = dep->dwc;
213 dwc3_gadget_del_and_unmap_request(dep, req, status);
214 req->status = DWC3_REQUEST_STATUS_COMPLETED;
216 spin_unlock(&dwc->lock);
217 usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 spin_lock(&dwc->lock);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
238 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
242 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243 if (!(reg & DWC3_DGCMD_CMDACT)) {
244 status = DWC3_DGCMD_STATUS(reg);
256 trace_dwc3_gadget_generic_cmd(cmd, param, status);
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
264 * dwc3_send_gadget_ep_cmd - issue an endpoint command
265 * @dep: the endpoint to which the command is going to be issued
266 * @cmd: the command to be issued
267 * @params: parameters to the command
269 * Caller should handle locking. This function will issue @cmd with given
270 * @params to @dep and wait for its completion.
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273 struct dwc3_gadget_ep_cmd_params *params)
275 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276 struct dwc3 *dwc = dep->dwc;
278 u32 saved_config = 0;
285 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
289 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 * settings. Restore them after the command is completed.
292 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
294 if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
301 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
307 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
310 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
314 * Initiate remote wakeup if the link state is in U3 when
315 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
316 * link state is in U1/U2, no remote wakeup is needed. The Start
317 * Transfer command will initiate the link recovery.
319 link_state = dwc3_gadget_get_link_state(dwc);
320 switch (link_state) {
321 case DWC3_LINK_STATE_U2:
322 if (dwc->gadget->speed >= USB_SPEED_SUPER)
326 case DWC3_LINK_STATE_U3:
327 ret = __dwc3_gadget_wakeup(dwc);
328 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
335 * For some commands such as Update Transfer command, DEPCMDPARn
336 * registers are reserved. Since the driver often sends Update Transfer
337 * command, don't write to DEPCMDPARn to avoid register write delays and
338 * improve performance.
340 if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
341 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
342 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
343 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
347 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
348 * not relying on XferNotReady, we can make use of a special "No
349 * Response Update Transfer" command where we should clear both CmdAct
352 * With this, we don't need to wait for command completion and can
353 * straight away issue further commands to the endpoint.
355 * NOTICE: We're making an assumption that control endpoints will never
356 * make use of Update Transfer command. This is a safe assumption
357 * because we can never have more than one request at a time with
358 * Control Endpoints. If anybody changes that assumption, this chunk
359 * needs to be updated accordingly.
361 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
362 !usb_endpoint_xfer_isoc(desc))
363 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
365 cmd |= DWC3_DEPCMD_CMDACT;
367 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
369 if (!(cmd & DWC3_DEPCMD_CMDACT)) {
375 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
376 if (!(reg & DWC3_DEPCMD_CMDACT)) {
377 cmd_status = DWC3_DEPCMD_STATUS(reg);
379 switch (cmd_status) {
383 case DEPEVT_TRANSFER_NO_RESOURCE:
384 dev_WARN(dwc->dev, "No resource for %s\n",
388 case DEPEVT_TRANSFER_BUS_EXPIRY:
390 * SW issues START TRANSFER command to
391 * isochronous ep with future frame interval. If
392 * future interval time has already passed when
393 * core receives the command, it will respond
394 * with an error status of 'Bus Expiry'.
396 * Instead of always returning -EINVAL, let's
397 * give a hint to the gadget driver that this is
398 * the case by returning -EAGAIN.
403 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
412 cmd_status = -ETIMEDOUT;
416 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
418 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
420 dep->flags |= DWC3_EP_TRANSFER_STARTED;
422 if (ret != -ETIMEDOUT)
423 dwc3_gadget_ep_get_transfer_index(dep);
427 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
429 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
435 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
437 struct dwc3 *dwc = dep->dwc;
438 struct dwc3_gadget_ep_cmd_params params;
439 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
442 * As of core revision 2.60a the recommended programming model
443 * is to set the ClearPendIN bit when issuing a Clear Stall EP
444 * command for IN endpoints. This is to prevent an issue where
445 * some (non-compliant) hosts may not send ACK TPs for pending
446 * IN transfers due to a mishandled error condition. Synopsys
449 if (dep->direction &&
450 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
451 (dwc->gadget->speed >= USB_SPEED_SUPER))
452 cmd |= DWC3_DEPCMD_CLEARPENDIN;
454 memset(¶ms, 0, sizeof(params));
456 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
459 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
460 struct dwc3_trb *trb)
462 u32 offset = (char *) trb - (char *) dep->trb_pool;
464 return dep->trb_pool_dma + offset;
467 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
469 struct dwc3 *dwc = dep->dwc;
474 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
475 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
476 &dep->trb_pool_dma, GFP_KERNEL);
477 if (!dep->trb_pool) {
478 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
486 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
488 struct dwc3 *dwc = dep->dwc;
490 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
491 dep->trb_pool, dep->trb_pool_dma);
493 dep->trb_pool = NULL;
494 dep->trb_pool_dma = 0;
497 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
499 struct dwc3_gadget_ep_cmd_params params;
501 memset(¶ms, 0x00, sizeof(params));
503 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
505 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
510 * dwc3_gadget_start_config - configure ep resources
511 * @dep: endpoint that is being enabled
513 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
514 * completion, it will set Transfer Resource for all available endpoints.
516 * The assignment of transfer resources cannot perfectly follow the data book
517 * due to the fact that the controller driver does not have all knowledge of the
518 * configuration in advance. It is given this information piecemeal by the
519 * composite gadget framework after every SET_CONFIGURATION and
520 * SET_INTERFACE. Trying to follow the databook programming model in this
521 * scenario can cause errors. For two reasons:
523 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
524 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
525 * incorrect in the scenario of multiple interfaces.
527 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
528 * endpoint on alt setting (8.1.6).
530 * The following simplified method is used instead:
532 * All hardware endpoints can be assigned a transfer resource and this setting
533 * will stay persistent until either a core reset or hibernation. So whenever we
534 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
535 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
536 * guaranteed that there are as many transfer resources as endpoints.
538 * This function is called for each endpoint when it is being enabled but is
539 * triggered only when called for EP0-out, which always happens first, and which
540 * should only happen in one of the above conditions.
542 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
544 struct dwc3_gadget_ep_cmd_params params;
553 memset(¶ms, 0x00, sizeof(params));
554 cmd = DWC3_DEPCMD_DEPSTARTCFG;
557 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
561 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
562 struct dwc3_ep *dep = dwc->eps[i];
567 ret = dwc3_gadget_set_xfer_resource(dep);
575 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
577 const struct usb_ss_ep_comp_descriptor *comp_desc;
578 const struct usb_endpoint_descriptor *desc;
579 struct dwc3_gadget_ep_cmd_params params;
580 struct dwc3 *dwc = dep->dwc;
582 comp_desc = dep->endpoint.comp_desc;
583 desc = dep->endpoint.desc;
585 memset(¶ms, 0x00, sizeof(params));
587 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
588 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
590 /* Burst size is only needed in SuperSpeed mode */
591 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
592 u32 burst = dep->endpoint.maxburst;
594 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
597 params.param0 |= action;
598 if (action == DWC3_DEPCFG_ACTION_RESTORE)
599 params.param2 |= dep->saved_state;
601 if (usb_endpoint_xfer_control(desc))
602 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
604 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
605 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
607 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
608 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
609 | DWC3_DEPCFG_XFER_COMPLETE_EN
610 | DWC3_DEPCFG_STREAM_EVENT_EN;
611 dep->stream_capable = true;
614 if (!usb_endpoint_xfer_control(desc))
615 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
618 * We are doing 1:1 mapping for endpoints, meaning
619 * Physical Endpoints 2 maps to Logical Endpoint 2 and
620 * so on. We consider the direction bit as part of the physical
621 * endpoint number. So USB endpoint 0x81 is 0x03.
623 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
626 * We must use the lower 16 TX FIFOs even though
630 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
632 if (desc->bInterval) {
636 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
638 * NOTE: The programming guide incorrectly stated bInterval_m1
639 * must be set to 0 when operating in fullspeed. Internally the
640 * controller does not have this limitation. See DWC_usb3x
641 * programming guide section 3.2.2.1.
643 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
645 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
646 dwc->gadget->speed == USB_SPEED_FULL)
647 dep->interval = desc->bInterval;
649 dep->interval = 1 << (desc->bInterval - 1);
651 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
654 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
658 * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
659 * @dwc: pointer to the DWC3 context
661 * Calculates the size value based on the equation below:
663 * DWC3 revision 280A and prior:
664 * fifo_size = mult * (max_packet / mdwidth) + 1;
666 * DWC3 revision 290A and onwards:
667 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
669 * The max packet size is set to 1024, as the txfifo requirements mainly apply
670 * to super speed USB use cases. However, it is safe to overestimate the fifo
671 * allocations for other scenarios, i.e. high speed USB.
673 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
675 int max_packet = 1024;
679 mdwidth = dwc3_mdwidth(dwc);
681 /* MDWIDTH is represented in bits, we need it in bytes */
684 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
685 fifo_size = mult * (max_packet / mdwidth) + 1;
687 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
692 * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
693 * @dwc: pointer to the DWC3 context
695 * Iterates through all the endpoint registers and clears the previous txfifo
698 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
705 if (!dwc->do_fifo_resize)
708 /* Read ep0IN related TXFIFO size */
710 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
711 if (DWC3_IP_IS(DWC3))
712 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
714 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
716 dwc->last_fifo_depth = fifo_depth;
717 /* Clear existing TXFIFO for all IN eps except ep0 */
718 for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
721 /* Don't change TXFRAMNUM on usb31 version */
722 size = DWC3_IP_IS(DWC3) ? 0 :
723 dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
724 DWC31_GTXFIFOSIZ_TXFRAMNUM;
726 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
727 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
729 dwc->num_ep_resized = 0;
733 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
734 * @dwc: pointer to our context structure
736 * This function will a best effort FIFO allocation in order
737 * to improve FIFO usage and throughput, while still allowing
738 * us to enable as many endpoints as possible.
740 * Keep in mind that this operation will be highly dependent
741 * on the configured size for RAM1 - which contains TxFifo -,
742 * the amount of endpoints enabled on coreConsultant tool, and
743 * the width of the Master Bus.
745 * In general, FIFO depths are represented with the following equation:
747 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
749 * In conjunction with dwc3_gadget_check_config(), this resizing logic will
750 * ensure that all endpoints will have enough internal memory for one max
751 * packet per endpoint.
753 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
755 struct dwc3 *dwc = dep->dwc;
766 if (!dwc->do_fifo_resize)
769 /* resize IN endpoints except ep0 */
770 if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
773 /* bail if already resized */
774 if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
777 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
779 if ((dep->endpoint.maxburst > 1 &&
780 usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
781 usb_endpoint_xfer_isoc(dep->endpoint.desc))
784 if (dep->endpoint.maxburst > 6 &&
785 (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
786 usb_endpoint_xfer_isoc(dep->endpoint.desc)) && DWC3_IP_IS(DWC31))
787 num_fifos = dwc->tx_fifo_resize_max_num;
789 /* FIFO size for a single buffer */
790 fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
792 /* Calculate the number of remaining EPs w/o any FIFO */
793 num_in_ep = dwc->max_cfg_eps;
794 num_in_ep -= dwc->num_ep_resized;
796 /* Reserve at least one FIFO for the number of IN EPs */
797 min_depth = num_in_ep * (fifo + 1);
798 remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
799 remaining = max_t(int, 0, remaining);
801 * We've already reserved 1 FIFO per EP, so check what we can fit in
802 * addition to it. If there is not enough remaining space, allocate
803 * all the remaining space to the EP.
805 fifo_size = (num_fifos - 1) * fifo;
806 if (remaining < fifo_size)
807 fifo_size = remaining;
810 /* Last increment according to the TX FIFO size equation */
813 /* Check if TXFIFOs start at non-zero addr */
814 tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
815 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
817 fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
818 if (DWC3_IP_IS(DWC3))
819 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
821 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
823 /* Check fifo size allocation doesn't exceed available RAM size. */
824 if (dwc->last_fifo_depth >= ram1_depth) {
825 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
826 dwc->last_fifo_depth, ram1_depth,
827 dep->endpoint.name, fifo_size);
828 if (DWC3_IP_IS(DWC3))
829 fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
831 fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
833 dwc->last_fifo_depth -= fifo_size;
837 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
838 dep->flags |= DWC3_EP_TXFIFO_RESIZED;
839 dwc->num_ep_resized++;
845 * __dwc3_gadget_ep_enable - initializes a hw endpoint
846 * @dep: endpoint to be initialized
847 * @action: one of INIT, MODIFY or RESTORE
849 * Caller should take care of locking. Execute all necessary commands to
850 * initialize a HW endpoint so it can be used by a gadget driver.
852 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
854 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
855 struct dwc3 *dwc = dep->dwc;
860 if (!(dep->flags & DWC3_EP_ENABLED)) {
861 ret = dwc3_gadget_resize_tx_fifos(dep);
865 ret = dwc3_gadget_start_config(dep);
870 ret = dwc3_gadget_set_ep_config(dep, action);
874 if (!(dep->flags & DWC3_EP_ENABLED)) {
875 struct dwc3_trb *trb_st_hw;
876 struct dwc3_trb *trb_link;
878 dep->type = usb_endpoint_type(desc);
879 dep->flags |= DWC3_EP_ENABLED;
881 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
882 reg |= DWC3_DALEPENA_EP(dep->number);
883 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
885 dep->trb_dequeue = 0;
886 dep->trb_enqueue = 0;
888 if (usb_endpoint_xfer_control(desc))
891 /* Initialize the TRB ring */
892 memset(dep->trb_pool, 0,
893 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
895 /* Link TRB. The HWO bit is never reset */
896 trb_st_hw = &dep->trb_pool[0];
898 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
899 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
900 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
901 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
902 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
906 * Issue StartTransfer here with no-op TRB so we can always rely on No
907 * Response Update Transfer command.
909 if (usb_endpoint_xfer_bulk(desc) ||
910 usb_endpoint_xfer_int(desc)) {
911 struct dwc3_gadget_ep_cmd_params params;
912 struct dwc3_trb *trb;
916 memset(¶ms, 0, sizeof(params));
917 trb = &dep->trb_pool[0];
918 trb_dma = dwc3_trb_dma_offset(dep, trb);
920 params.param0 = upper_32_bits(trb_dma);
921 params.param1 = lower_32_bits(trb_dma);
923 cmd = DWC3_DEPCMD_STARTTRANSFER;
925 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
929 if (dep->stream_capable) {
931 * For streams, at start, there maybe a race where the
932 * host primes the endpoint before the function driver
933 * queues a request to initiate a stream. In that case,
934 * the controller will not see the prime to generate the
935 * ERDY and start stream. To workaround this, issue a
936 * no-op TRB as normal, but end it immediately. As a
937 * result, when the function driver queues the request,
938 * the next START_TRANSFER command will cause the
939 * controller to generate an ERDY to initiate the
942 dwc3_stop_active_transfer(dep, true, true);
945 * All stream eps will reinitiate stream on NoStream
946 * rejection until we can determine that the host can
947 * prime after the first transfer.
949 * However, if the controller is capable of
950 * TXF_FLUSH_BYPASS, then IN direction endpoints will
951 * automatically restart the stream without the driver
954 if (!dep->direction ||
955 !(dwc->hwparams.hwparams9 &
956 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
957 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
962 trace_dwc3_gadget_ep_enable(dep);
967 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
969 struct dwc3_request *req;
971 dwc3_stop_active_transfer(dep, true, false);
973 /* - giveback all requests to gadget driver */
974 while (!list_empty(&dep->started_list)) {
975 req = next_request(&dep->started_list);
977 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
980 while (!list_empty(&dep->pending_list)) {
981 req = next_request(&dep->pending_list);
983 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
986 while (!list_empty(&dep->cancelled_list)) {
987 req = next_request(&dep->cancelled_list);
989 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
994 * __dwc3_gadget_ep_disable - disables a hw endpoint
995 * @dep: the endpoint to disable
997 * This function undoes what __dwc3_gadget_ep_enable did and also removes
998 * requests which are currently being processed by the hardware and those which
999 * are not yet scheduled.
1001 * Caller should take care of locking.
1003 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1005 struct dwc3 *dwc = dep->dwc;
1008 trace_dwc3_gadget_ep_disable(dep);
1010 /* make sure HW endpoint isn't stalled */
1011 if (dep->flags & DWC3_EP_STALL)
1012 __dwc3_gadget_ep_set_halt(dep, 0, false);
1014 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1015 reg &= ~DWC3_DALEPENA_EP(dep->number);
1016 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1018 /* Clear out the ep descriptors for non-ep0 */
1019 if (dep->number > 1) {
1020 dep->endpoint.comp_desc = NULL;
1021 dep->endpoint.desc = NULL;
1024 dwc3_remove_requests(dwc, dep);
1026 dep->stream_capable = false;
1028 dep->flags &= DWC3_EP_TXFIFO_RESIZED;
1033 /* -------------------------------------------------------------------------- */
1035 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1036 const struct usb_endpoint_descriptor *desc)
1041 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1046 /* -------------------------------------------------------------------------- */
1048 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1049 const struct usb_endpoint_descriptor *desc)
1051 struct dwc3_ep *dep;
1053 unsigned long flags;
1056 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1057 pr_debug("dwc3: invalid parameters\n");
1061 if (!desc->wMaxPacketSize) {
1062 pr_debug("dwc3: missing wMaxPacketSize\n");
1066 dep = to_dwc3_ep(ep);
1069 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1070 "%s is already enabled\n",
1074 spin_lock_irqsave(&dwc->lock, flags);
1075 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1076 spin_unlock_irqrestore(&dwc->lock, flags);
1081 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1083 struct dwc3_ep *dep;
1085 unsigned long flags;
1089 pr_debug("dwc3: invalid parameters\n");
1093 dep = to_dwc3_ep(ep);
1096 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1097 "%s is already disabled\n",
1101 spin_lock_irqsave(&dwc->lock, flags);
1102 ret = __dwc3_gadget_ep_disable(dep);
1103 spin_unlock_irqrestore(&dwc->lock, flags);
1108 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1111 struct dwc3_request *req;
1112 struct dwc3_ep *dep = to_dwc3_ep(ep);
1114 req = kzalloc(sizeof(*req), gfp_flags);
1118 req->direction = dep->direction;
1119 req->epnum = dep->number;
1121 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
1123 trace_dwc3_alloc_request(req);
1125 return &req->request;
1128 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1129 struct usb_request *request)
1131 struct dwc3_request *req = to_dwc3_request(request);
1133 trace_dwc3_free_request(req);
1138 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1139 * @dep: The endpoint with the TRB ring
1140 * @index: The index of the current TRB in the ring
1142 * Returns the TRB prior to the one pointed to by the index. If the
1143 * index is 0, we will wrap backwards, skip the link TRB, and return
1144 * the one just before that.
1146 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1151 tmp = DWC3_TRB_NUM - 1;
1153 return &dep->trb_pool[tmp - 1];
1156 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1161 * If the enqueue & dequeue are equal then the TRB ring is either full
1162 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1163 * pending to be processed by the driver.
1165 if (dep->trb_enqueue == dep->trb_dequeue) {
1167 * If there is any request remained in the started_list at
1168 * this point, that means there is no TRB available.
1170 if (!list_empty(&dep->started_list))
1173 return DWC3_TRB_NUM - 1;
1176 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1177 trbs_left &= (DWC3_TRB_NUM - 1);
1179 if (dep->trb_dequeue < dep->trb_enqueue)
1185 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
1186 dma_addr_t dma, unsigned int length, unsigned int chain,
1187 unsigned int node, unsigned int stream_id,
1188 unsigned int short_not_ok, unsigned int no_interrupt,
1189 unsigned int is_last, bool must_interrupt)
1191 struct dwc3 *dwc = dep->dwc;
1192 struct usb_gadget *gadget = dwc->gadget;
1193 enum usb_device_speed speed = gadget->speed;
1195 trb->size = DWC3_TRB_SIZE_LENGTH(length);
1196 trb->bpl = lower_32_bits(dma);
1197 trb->bph = upper_32_bits(dma);
1199 switch (usb_endpoint_type(dep->endpoint.desc)) {
1200 case USB_ENDPOINT_XFER_CONTROL:
1201 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1204 case USB_ENDPOINT_XFER_ISOC:
1206 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1209 * USB Specification 2.0 Section 5.9.2 states that: "If
1210 * there is only a single transaction in the microframe,
1211 * only a DATA0 data packet PID is used. If there are
1212 * two transactions per microframe, DATA1 is used for
1213 * the first transaction data packet and DATA0 is used
1214 * for the second transaction data packet. If there are
1215 * three transactions per microframe, DATA2 is used for
1216 * the first transaction data packet, DATA1 is used for
1217 * the second, and DATA0 is used for the third."
1219 * IOW, we should satisfy the following cases:
1221 * 1) length <= maxpacket
1224 * 2) maxpacket < length <= (2 * maxpacket)
1227 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1228 * - DATA2, DATA1, DATA0
1230 if (speed == USB_SPEED_HIGH) {
1231 struct usb_ep *ep = &dep->endpoint;
1232 unsigned int mult = 2;
1233 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1235 if (length <= (2 * maxp))
1241 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1244 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1247 /* always enable Interrupt on Missed ISOC */
1248 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1251 case USB_ENDPOINT_XFER_BULK:
1252 case USB_ENDPOINT_XFER_INT:
1253 trb->ctrl = DWC3_TRBCTL_NORMAL;
1257 * This is only possible with faulty memory because we
1258 * checked it already :)
1260 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1261 usb_endpoint_type(dep->endpoint.desc));
1265 * Enable Continue on Short Packet
1266 * when endpoint is not a stream capable
1268 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1269 if (!dep->stream_capable)
1270 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1273 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1276 /* All TRBs setup for MST must set CSP=1 when LST=0 */
1277 if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1278 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1280 if ((!no_interrupt && !chain) || must_interrupt)
1281 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1284 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1285 else if (dep->stream_capable && is_last &&
1286 !DWC3_MST_CAPABLE(&dwc->hwparams))
1287 trb->ctrl |= DWC3_TRB_CTRL_LST;
1289 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1290 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1293 * As per data book 4.2.3.2TRB Control Bit Rules section
1295 * The controller autonomously checks the HWO field of a TRB to determine if the
1296 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1297 * is valid before setting the HWO field to '1'. In most systems, this means that
1298 * software must update the fourth DWORD of a TRB last.
1300 * However there is a possibility of CPU re-ordering here which can cause
1301 * controller to observe the HWO bit set prematurely.
1302 * Add a write memory barrier to prevent CPU re-ordering.
1305 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1307 dwc3_ep_inc_enq(dep);
1309 trace_dwc3_prepare_trb(dep, trb);
1313 * dwc3_prepare_one_trb - setup one TRB from one request
1314 * @dep: endpoint for which this request is prepared
1315 * @req: dwc3_request pointer
1316 * @trb_length: buffer size of the TRB
1317 * @chain: should this TRB be chained to the next?
1318 * @node: only for isochronous endpoints. First TRB needs different type.
1319 * @use_bounce_buffer: set to use bounce buffer
1320 * @must_interrupt: set to interrupt on TRB completion
1322 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1323 struct dwc3_request *req, unsigned int trb_length,
1324 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1325 bool must_interrupt)
1327 struct dwc3_trb *trb;
1329 unsigned int stream_id = req->request.stream_id;
1330 unsigned int short_not_ok = req->request.short_not_ok;
1331 unsigned int no_interrupt = req->request.no_interrupt;
1332 unsigned int is_last = req->request.is_last;
1334 if (use_bounce_buffer)
1335 dma = dep->dwc->bounce_addr;
1336 else if (req->request.num_sgs > 0)
1337 dma = sg_dma_address(req->start_sg);
1339 dma = req->request.dma;
1341 trb = &dep->trb_pool[dep->trb_enqueue];
1344 dwc3_gadget_move_started_request(req);
1346 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1351 __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1352 stream_id, short_not_ok, no_interrupt, is_last,
1356 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1358 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1359 unsigned int rem = req->request.length % maxp;
1361 if ((req->request.length && req->request.zero && !rem &&
1362 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1363 (!req->direction && rem))
1370 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1371 * @dep: The endpoint that the request belongs to
1372 * @req: The request to prepare
1373 * @entry_length: The last SG entry size
1374 * @node: Indicates whether this is not the first entry (for isoc only)
1376 * Return the number of TRBs prepared.
1378 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1379 struct dwc3_request *req, unsigned int entry_length,
1382 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1383 unsigned int rem = req->request.length % maxp;
1384 unsigned int num_trbs = 1;
1386 if (dwc3_needs_extra_trb(dep, req))
1389 if (dwc3_calc_trbs_left(dep) < num_trbs)
1392 req->needs_extra_trb = num_trbs > 1;
1394 /* Prepare a normal TRB */
1395 if (req->direction || req->request.length)
1396 dwc3_prepare_one_trb(dep, req, entry_length,
1397 req->needs_extra_trb, node, false, false);
1399 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1400 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1401 dwc3_prepare_one_trb(dep, req,
1402 req->direction ? 0 : maxp - rem,
1403 false, 1, true, false);
1408 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1409 struct dwc3_request *req)
1411 struct scatterlist *sg = req->start_sg;
1412 struct scatterlist *s;
1414 unsigned int length = req->request.length;
1415 unsigned int remaining = req->request.num_mapped_sgs
1416 - req->num_queued_sgs;
1417 unsigned int num_trbs = req->num_trbs;
1418 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1421 * If we resume preparing the request, then get the remaining length of
1422 * the request and resume where we left off.
1424 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1425 length -= sg_dma_len(s);
1427 for_each_sg(sg, s, remaining, i) {
1428 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1429 unsigned int trb_length;
1430 bool must_interrupt = false;
1431 bool last_sg = false;
1433 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1435 length -= trb_length;
1438 * IOMMU driver is coalescing the list of sgs which shares a
1439 * page boundary into one and giving it to USB driver. With
1440 * this the number of sgs mapped is not equal to the number of
1441 * sgs passed. So mark the chain bit to false if it isthe last
1444 if ((i == remaining - 1) || !length)
1451 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1455 * Look ahead to check if we have enough TRBs for the
1456 * next SG entry. If not, set interrupt on this TRB to
1457 * resume preparing the next SG entry when more TRBs are
1460 if (num_trbs_left == 1 || (needs_extra_trb &&
1461 num_trbs_left <= 2 &&
1462 sg_dma_len(sg_next(s)) >= length))
1463 must_interrupt = true;
1465 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1470 * There can be a situation where all sgs in sglist are not
1471 * queued because of insufficient trb number. To handle this
1472 * case, update start_sg to next sg to be queued, so that
1473 * we have free trbs we can continue queuing from where we
1474 * previously stopped
1477 req->start_sg = sg_next(s);
1479 req->num_queued_sgs++;
1480 req->num_pending_sgs--;
1483 * The number of pending SG entries may not correspond to the
1484 * number of mapped SG entries. If all the data are queued, then
1485 * don't include unused SG entries.
1488 req->num_pending_sgs = 0;
1496 return req->num_trbs - num_trbs;
1499 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1500 struct dwc3_request *req)
1502 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1506 * dwc3_prepare_trbs - setup TRBs from requests
1507 * @dep: endpoint for which requests are being prepared
1509 * The function goes through the requests list and sets up TRBs for the
1510 * transfers. The function returns once there are no more TRBs available or
1511 * it runs out of requests.
1513 * Returns the number of TRBs prepared or negative errno.
1515 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1517 struct dwc3_request *req, *n;
1520 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1523 * We can get in a situation where there's a request in the started list
1524 * but there weren't enough TRBs to fully kick it in the first time
1525 * around, so it has been waiting for more TRBs to be freed up.
1527 * In that case, we should check if we have a request with pending_sgs
1528 * in the started list and prepare TRBs for that request first,
1529 * otherwise we will prepare TRBs completely out of order and that will
1532 list_for_each_entry(req, &dep->started_list, list) {
1533 if (req->num_pending_sgs > 0) {
1534 ret = dwc3_prepare_trbs_sg(dep, req);
1535 if (!ret || req->num_pending_sgs)
1539 if (!dwc3_calc_trbs_left(dep))
1543 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1544 * burst capability may try to read and use TRBs beyond the
1545 * active transfer instead of stopping.
1547 if (dep->stream_capable && req->request.is_last &&
1548 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1552 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1553 struct dwc3 *dwc = dep->dwc;
1555 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1560 req->sg = req->request.sg;
1561 req->start_sg = req->sg;
1562 req->num_queued_sgs = 0;
1563 req->num_pending_sgs = req->request.num_mapped_sgs;
1565 if (req->num_pending_sgs > 0) {
1566 ret = dwc3_prepare_trbs_sg(dep, req);
1567 if (req->num_pending_sgs)
1570 ret = dwc3_prepare_trbs_linear(dep, req);
1573 if (!ret || !dwc3_calc_trbs_left(dep))
1577 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1578 * burst capability may try to read and use TRBs beyond the
1579 * active transfer instead of stopping.
1581 if (dep->stream_capable && req->request.is_last &&
1582 !DWC3_MST_CAPABLE(&dwc->hwparams))
1589 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1591 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1593 struct dwc3_gadget_ep_cmd_params params;
1594 struct dwc3_request *req;
1600 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1601 * This happens when we need to stop and restart a transfer such as in
1602 * the case of reinitiating a stream or retrying an isoc transfer.
1604 ret = dwc3_prepare_trbs(dep);
1608 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1611 * If there's no new TRB prepared and we don't need to restart a
1612 * transfer, there's no need to update the transfer.
1614 if (!ret && !starting)
1617 req = next_request(&dep->started_list);
1619 dep->flags |= DWC3_EP_PENDING_REQUEST;
1623 memset(¶ms, 0, sizeof(params));
1626 params.param0 = upper_32_bits(req->trb_dma);
1627 params.param1 = lower_32_bits(req->trb_dma);
1628 cmd = DWC3_DEPCMD_STARTTRANSFER;
1630 if (dep->stream_capable)
1631 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1633 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1634 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1636 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1637 DWC3_DEPCMD_PARAM(dep->resource_index);
1640 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1642 struct dwc3_request *tmp;
1647 dwc3_stop_active_transfer(dep, true, true);
1649 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1650 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1652 /* If ep isn't started, then there's no end transfer pending */
1653 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1654 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1659 if (dep->stream_capable && req->request.is_last &&
1660 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1661 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1666 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1670 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1671 return DWC3_DSTS_SOFFN(reg);
1675 * __dwc3_stop_active_transfer - stop the current active transfer
1676 * @dep: isoc endpoint
1677 * @force: set forcerm bit in the command
1678 * @interrupt: command complete interrupt after End Transfer command
1680 * When setting force, the ForceRM bit will be set. In that case
1681 * the controller won't update the TRB progress on command
1682 * completion. It also won't clear the HWO bit in the TRB.
1683 * The command will also not complete immediately in that case.
1685 static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1687 struct dwc3_gadget_ep_cmd_params params;
1691 cmd = DWC3_DEPCMD_ENDTRANSFER;
1692 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1693 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1694 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1695 memset(¶ms, 0, sizeof(params));
1696 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1698 dep->resource_index = 0;
1701 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1703 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1709 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1710 * @dep: isoc endpoint
1712 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1713 * microframe number reported by the XferNotReady event for the future frame
1714 * number to start the isoc transfer.
1716 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1717 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1718 * XferNotReady event are invalid. The driver uses this number to schedule the
1719 * isochronous transfer and passes it to the START TRANSFER command. Because
1720 * this number is invalid, the command may fail. If BIT[15:14] matches the
1721 * internal 16-bit microframe, the START TRANSFER command will pass and the
1722 * transfer will start at the scheduled time, if it is off by 1, the command
1723 * will still pass, but the transfer will start 2 seconds in the future. For all
1724 * other conditions, the START TRANSFER command will fail with bus-expiry.
1726 * In order to workaround this issue, we can test for the correct combination of
1727 * BIT[15:14] by sending START TRANSFER commands with different values of
1728 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1729 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1730 * As the result, within the 4 possible combinations for BIT[15:14], there will
1731 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1732 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1733 * value is the correct combination.
1735 * Since there are only 4 outcomes and the results are ordered, we can simply
1736 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1737 * deduce the smaller successful combination.
1739 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1740 * of BIT[15:14]. The correct combination is as follow:
1742 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1743 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1744 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1745 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1747 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1750 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1756 while (dep->combo_num < 2) {
1757 struct dwc3_gadget_ep_cmd_params params;
1758 u32 test_frame_number;
1762 * Check if we can start isoc transfer on the next interval or
1763 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1765 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1766 test_frame_number |= dep->combo_num << 14;
1767 test_frame_number += max_t(u32, 4, dep->interval);
1769 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1770 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1772 cmd = DWC3_DEPCMD_STARTTRANSFER;
1773 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1774 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1776 /* Redo if some other failure beside bus-expiry is received */
1777 if (cmd_status && cmd_status != -EAGAIN) {
1778 dep->start_cmd_status = 0;
1783 /* Store the first test status */
1784 if (dep->combo_num == 0)
1785 dep->start_cmd_status = cmd_status;
1790 * End the transfer if the START_TRANSFER command is successful
1791 * to wait for the next XferNotReady to test the command again
1793 if (cmd_status == 0) {
1794 dwc3_stop_active_transfer(dep, true, true);
1799 /* test0 and test1 are both completed at this point */
1800 test0 = (dep->start_cmd_status == 0);
1801 test1 = (cmd_status == 0);
1803 if (!test0 && test1)
1805 else if (!test0 && !test1)
1807 else if (test0 && !test1)
1809 else if (test0 && test1)
1812 dep->frame_number &= DWC3_FRNUMBER_MASK;
1813 dep->frame_number |= dep->combo_num << 14;
1814 dep->frame_number += max_t(u32, 4, dep->interval);
1816 /* Reinitialize test variables */
1817 dep->start_cmd_status = 0;
1820 return __dwc3_gadget_kick_transfer(dep);
1823 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1825 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1826 struct dwc3 *dwc = dep->dwc;
1830 if (list_empty(&dep->pending_list) &&
1831 list_empty(&dep->started_list)) {
1832 dep->flags |= DWC3_EP_PENDING_REQUEST;
1836 if (!dwc->dis_start_transfer_quirk &&
1837 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1838 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1839 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1840 return dwc3_gadget_start_isoc_quirk(dep);
1843 if (desc->bInterval <= 14 &&
1844 dwc->gadget->speed >= USB_SPEED_HIGH) {
1845 u32 frame = __dwc3_gadget_get_frame(dwc);
1846 bool rollover = frame <
1847 (dep->frame_number & DWC3_FRNUMBER_MASK);
1850 * frame_number is set from XferNotReady and may be already
1851 * out of date. DSTS only provides the lower 14 bit of the
1852 * current frame number. So add the upper two bits of
1853 * frame_number and handle a possible rollover.
1854 * This will provide the correct frame_number unless more than
1855 * rollover has happened since XferNotReady.
1858 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1861 dep->frame_number += BIT(14);
1864 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1865 int future_interval = i + 1;
1867 /* Give the controller at least 500us to schedule transfers */
1868 if (desc->bInterval < 3)
1869 future_interval += 3 - desc->bInterval;
1871 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1873 ret = __dwc3_gadget_kick_transfer(dep);
1879 * After a number of unsuccessful start attempts due to bus-expiry
1880 * status, issue END_TRANSFER command and retry on the next XferNotReady
1884 ret = __dwc3_stop_active_transfer(dep, false, true);
1889 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1891 struct dwc3 *dwc = dep->dwc;
1893 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1894 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1899 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1900 &req->request, req->dep->name))
1903 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1904 "%s: request %pK already in flight\n",
1905 dep->name, &req->request))
1908 pm_runtime_get(dwc->dev);
1910 req->request.actual = 0;
1911 req->request.status = -EINPROGRESS;
1913 trace_dwc3_ep_queue(req);
1915 list_add_tail(&req->list, &dep->pending_list);
1916 req->status = DWC3_REQUEST_STATUS_QUEUED;
1918 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1922 * Start the transfer only after the END_TRANSFER is completed
1923 * and endpoint STALL is cleared.
1925 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1926 (dep->flags & DWC3_EP_WEDGE) ||
1927 (dep->flags & DWC3_EP_DELAY_STOP) ||
1928 (dep->flags & DWC3_EP_STALL)) {
1929 dep->flags |= DWC3_EP_DELAY_START;
1934 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1935 * wait for a XferNotReady event so we will know what's the current
1936 * (micro-)frame number.
1938 * Without this trick, we are very, very likely gonna get Bus Expiry
1939 * errors which will force us issue EndTransfer command.
1941 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1942 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1943 if ((dep->flags & DWC3_EP_PENDING_REQUEST))
1944 return __dwc3_gadget_start_isoc(dep);
1950 __dwc3_gadget_kick_transfer(dep);
1955 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1958 struct dwc3_request *req = to_dwc3_request(request);
1959 struct dwc3_ep *dep = to_dwc3_ep(ep);
1960 struct dwc3 *dwc = dep->dwc;
1962 unsigned long flags;
1966 spin_lock_irqsave(&dwc->lock, flags);
1967 ret = __dwc3_gadget_ep_queue(dep, req);
1968 spin_unlock_irqrestore(&dwc->lock, flags);
1973 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1977 /* If req->trb is not set, then the request has not started */
1982 * If request was already started, this means we had to
1983 * stop the transfer. With that we also need to ignore
1984 * all TRBs used by the request, however TRBs can only
1985 * be modified after completion of END_TRANSFER
1986 * command. So what we do here is that we wait for
1987 * END_TRANSFER completion and only after that, we jump
1988 * over TRBs by clearing HWO and incrementing dequeue
1991 for (i = 0; i < req->num_trbs; i++) {
1992 struct dwc3_trb *trb;
1994 trb = &dep->trb_pool[dep->trb_dequeue];
1995 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1996 dwc3_ep_inc_deq(dep);
2002 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2004 struct dwc3_request *req;
2005 struct dwc3 *dwc = dep->dwc;
2007 while (!list_empty(&dep->cancelled_list)) {
2008 req = next_request(&dep->cancelled_list);
2009 dwc3_gadget_ep_skip_trbs(dep, req);
2010 switch (req->status) {
2011 case DWC3_REQUEST_STATUS_DISCONNECTED:
2012 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2014 case DWC3_REQUEST_STATUS_DEQUEUED:
2015 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2017 case DWC3_REQUEST_STATUS_STALLED:
2018 dwc3_gadget_giveback(dep, req, -EPIPE);
2021 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2022 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2026 * The endpoint is disabled, let the dwc3_remove_requests()
2027 * handle the cleanup.
2029 if (!dep->endpoint.desc)
2034 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2035 struct usb_request *request)
2037 struct dwc3_request *req = to_dwc3_request(request);
2038 struct dwc3_request *r = NULL;
2040 struct dwc3_ep *dep = to_dwc3_ep(ep);
2041 struct dwc3 *dwc = dep->dwc;
2043 unsigned long flags;
2046 trace_dwc3_ep_dequeue(req);
2048 spin_lock_irqsave(&dwc->lock, flags);
2050 list_for_each_entry(r, &dep->cancelled_list, list) {
2055 list_for_each_entry(r, &dep->pending_list, list) {
2057 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2062 list_for_each_entry(r, &dep->started_list, list) {
2064 struct dwc3_request *t;
2066 /* wait until it is processed */
2067 dwc3_stop_active_transfer(dep, true, true);
2070 * Remove any started request if the transfer is
2073 list_for_each_entry_safe(r, t, &dep->started_list, list)
2074 dwc3_gadget_move_cancelled_request(r,
2075 DWC3_REQUEST_STATUS_DEQUEUED);
2077 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2083 dev_err(dwc->dev, "request %pK was not queued to %s\n",
2087 spin_unlock_irqrestore(&dwc->lock, flags);
2092 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2094 struct dwc3_gadget_ep_cmd_params params;
2095 struct dwc3 *dwc = dep->dwc;
2096 struct dwc3_request *req;
2097 struct dwc3_request *tmp;
2100 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2101 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2105 memset(¶ms, 0x00, sizeof(params));
2108 struct dwc3_trb *trb;
2110 unsigned int transfer_in_flight;
2111 unsigned int started;
2113 if (dep->number > 1)
2114 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2116 trb = &dwc->ep0_trb[dep->trb_enqueue];
2118 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2119 started = !list_empty(&dep->started_list);
2121 if (!protocol && ((dep->direction && transfer_in_flight) ||
2122 (!dep->direction && started))) {
2126 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2129 dev_err(dwc->dev, "failed to set STALL on %s\n",
2132 dep->flags |= DWC3_EP_STALL;
2135 * Don't issue CLEAR_STALL command to control endpoints. The
2136 * controller automatically clears the STALL when it receives
2139 if (dep->number <= 1) {
2140 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2144 dwc3_stop_active_transfer(dep, true, true);
2146 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2147 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2149 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2150 (dep->flags & DWC3_EP_DELAY_STOP)) {
2151 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2153 dwc->clear_stall_protocol = dep->number;
2158 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2160 ret = dwc3_send_clear_stall_ep_cmd(dep);
2162 dev_err(dwc->dev, "failed to clear STALL on %s\n",
2167 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2169 if ((dep->flags & DWC3_EP_DELAY_START) &&
2170 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2171 __dwc3_gadget_kick_transfer(dep);
2173 dep->flags &= ~DWC3_EP_DELAY_START;
2179 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2181 struct dwc3_ep *dep = to_dwc3_ep(ep);
2182 struct dwc3 *dwc = dep->dwc;
2184 unsigned long flags;
2188 spin_lock_irqsave(&dwc->lock, flags);
2189 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2190 spin_unlock_irqrestore(&dwc->lock, flags);
2195 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2197 struct dwc3_ep *dep = to_dwc3_ep(ep);
2198 struct dwc3 *dwc = dep->dwc;
2199 unsigned long flags;
2202 spin_lock_irqsave(&dwc->lock, flags);
2203 dep->flags |= DWC3_EP_WEDGE;
2205 if (dep->number == 0 || dep->number == 1)
2206 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2208 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2209 spin_unlock_irqrestore(&dwc->lock, flags);
2214 /* -------------------------------------------------------------------------- */
2216 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2217 .bLength = USB_DT_ENDPOINT_SIZE,
2218 .bDescriptorType = USB_DT_ENDPOINT,
2219 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2222 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2223 .enable = dwc3_gadget_ep0_enable,
2224 .disable = dwc3_gadget_ep0_disable,
2225 .alloc_request = dwc3_gadget_ep_alloc_request,
2226 .free_request = dwc3_gadget_ep_free_request,
2227 .queue = dwc3_gadget_ep0_queue,
2228 .dequeue = dwc3_gadget_ep_dequeue,
2229 .set_halt = dwc3_gadget_ep0_set_halt,
2230 .set_wedge = dwc3_gadget_ep_set_wedge,
2233 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2234 .enable = dwc3_gadget_ep_enable,
2235 .disable = dwc3_gadget_ep_disable,
2236 .alloc_request = dwc3_gadget_ep_alloc_request,
2237 .free_request = dwc3_gadget_ep_free_request,
2238 .queue = dwc3_gadget_ep_queue,
2239 .dequeue = dwc3_gadget_ep_dequeue,
2240 .set_halt = dwc3_gadget_ep_set_halt,
2241 .set_wedge = dwc3_gadget_ep_set_wedge,
2244 /* -------------------------------------------------------------------------- */
2246 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2248 struct dwc3 *dwc = gadget_to_dwc(g);
2250 return __dwc3_gadget_get_frame(dwc);
2253 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
2263 * According to the Databook Remote wakeup request should
2264 * be issued only when the device is in early suspend state.
2266 * We can check that via USB Link State bits in DSTS register.
2268 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2270 link_state = DWC3_DSTS_USBLNKST(reg);
2272 switch (link_state) {
2273 case DWC3_LINK_STATE_RESET:
2274 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2275 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2276 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2277 case DWC3_LINK_STATE_U1:
2278 case DWC3_LINK_STATE_RESUME:
2284 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2286 dev_err(dwc->dev, "failed to put link in Recovery\n");
2290 /* Recent versions do this automatically */
2291 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2292 /* write zeroes to Link Change Request */
2293 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2294 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2295 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2298 /* poll until Link State changes to ON */
2302 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2304 /* in HS, means ON */
2305 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2309 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2310 dev_err(dwc->dev, "failed to send remote wakeup\n");
2317 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2319 struct dwc3 *dwc = gadget_to_dwc(g);
2320 unsigned long flags;
2323 spin_lock_irqsave(&dwc->lock, flags);
2324 ret = __dwc3_gadget_wakeup(dwc);
2325 spin_unlock_irqrestore(&dwc->lock, flags);
2330 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2333 struct dwc3 *dwc = gadget_to_dwc(g);
2334 unsigned long flags;
2336 spin_lock_irqsave(&dwc->lock, flags);
2337 g->is_selfpowered = !!is_selfpowered;
2338 spin_unlock_irqrestore(&dwc->lock, flags);
2343 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2347 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2348 struct dwc3_ep *dep;
2350 dep = dwc->eps[epnum];
2354 dwc3_remove_requests(dwc, dep);
2358 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2360 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2363 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2364 ssp_rate = dwc->max_ssp_rate;
2366 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2367 reg &= ~DWC3_DCFG_SPEED_MASK;
2368 reg &= ~DWC3_DCFG_NUMLANES(~0);
2370 if (ssp_rate == USB_SSP_GEN_1x2)
2371 reg |= DWC3_DCFG_SUPERSPEED;
2372 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2373 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2375 if (ssp_rate != USB_SSP_GEN_2x1 &&
2376 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2377 reg |= DWC3_DCFG_NUMLANES(1);
2379 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2382 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2384 enum usb_device_speed speed;
2387 speed = dwc->gadget_max_speed;
2388 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2389 speed = dwc->maximum_speed;
2391 if (speed == USB_SPEED_SUPER_PLUS &&
2392 DWC3_IP_IS(DWC32)) {
2393 __dwc3_gadget_set_ssp_rate(dwc);
2397 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2398 reg &= ~(DWC3_DCFG_SPEED_MASK);
2401 * WORKAROUND: DWC3 revision < 2.20a have an issue
2402 * which would cause metastability state on Run/Stop
2403 * bit if we try to force the IP to USB2-only mode.
2405 * Because of that, we cannot configure the IP to any
2406 * speed other than the SuperSpeed
2410 * STAR#9000525659: Clock Domain Crossing on DCTL in
2413 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2414 !dwc->dis_metastability_quirk) {
2415 reg |= DWC3_DCFG_SUPERSPEED;
2418 case USB_SPEED_FULL:
2419 reg |= DWC3_DCFG_FULLSPEED;
2421 case USB_SPEED_HIGH:
2422 reg |= DWC3_DCFG_HIGHSPEED;
2424 case USB_SPEED_SUPER:
2425 reg |= DWC3_DCFG_SUPERSPEED;
2427 case USB_SPEED_SUPER_PLUS:
2428 if (DWC3_IP_IS(DWC3))
2429 reg |= DWC3_DCFG_SUPERSPEED;
2431 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2434 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2436 if (DWC3_IP_IS(DWC3))
2437 reg |= DWC3_DCFG_SUPERSPEED;
2439 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2443 if (DWC3_IP_IS(DWC32) &&
2444 speed > USB_SPEED_UNKNOWN &&
2445 speed < USB_SPEED_SUPER_PLUS)
2446 reg &= ~DWC3_DCFG_NUMLANES(~0);
2448 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2451 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2456 if (pm_runtime_suspended(dwc->dev))
2459 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2461 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2462 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2463 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2466 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2467 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2468 reg |= DWC3_DCTL_RUN_STOP;
2470 if (dwc->has_hibernation)
2471 reg |= DWC3_DCTL_KEEP_CONNECT;
2473 __dwc3_gadget_set_speed(dwc);
2474 dwc->pullups_connected = true;
2476 reg &= ~DWC3_DCTL_RUN_STOP;
2478 if (dwc->has_hibernation && !suspend)
2479 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2481 dwc->pullups_connected = false;
2484 dwc3_gadget_dctl_write_safe(dwc, reg);
2487 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2488 reg &= DWC3_DSTS_DEVCTRLHLT;
2489 } while (--timeout && !(!is_on ^ !reg));
2497 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2498 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2499 static int __dwc3_gadget_start(struct dwc3 *dwc);
2501 static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2503 unsigned long flags;
2505 spin_lock_irqsave(&dwc->lock, flags);
2506 dwc->connected = false;
2509 * Per databook, when we want to stop the gadget, if a control transfer
2510 * is still in process, complete it and get the core into setup phase.
2512 if (dwc->ep0state != EP0_SETUP_PHASE) {
2515 reinit_completion(&dwc->ep0_in_setup);
2517 spin_unlock_irqrestore(&dwc->lock, flags);
2518 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2519 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2520 spin_lock_irqsave(&dwc->lock, flags);
2522 dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2526 * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2527 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2528 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2529 * command for any active transfers" before clearing the RunStop
2532 dwc3_stop_active_transfers(dwc);
2533 __dwc3_gadget_stop(dwc);
2534 spin_unlock_irqrestore(&dwc->lock, flags);
2537 * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2538 * driver needs to acknowledge them before the controller can halt.
2539 * Simply let the interrupt handler acknowledges and handle the
2540 * remaining event generated by the controller while polling for
2543 return dwc3_gadget_run_stop(dwc, false, false);
2546 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2548 struct dwc3 *dwc = gadget_to_dwc(g);
2553 if (dwc->pullups_connected == is_on)
2556 dwc->softconnect = is_on;
2559 * Avoid issuing a runtime resume if the device is already in the
2560 * suspended state during gadget disconnect. DWC3 gadget was already
2561 * halted/stopped during runtime suspend.
2564 pm_runtime_barrier(dwc->dev);
2565 if (pm_runtime_suspended(dwc->dev))
2570 * Check the return value for successful resume, or error. For a
2571 * successful resume, the DWC3 runtime PM resume routine will handle
2572 * the run stop sequence, so avoid duplicate operations here.
2574 ret = pm_runtime_get_sync(dwc->dev);
2575 if (!ret || ret < 0) {
2576 pm_runtime_put(dwc->dev);
2581 ret = dwc3_gadget_soft_disconnect(dwc);
2584 * In the Synopsys DWC_usb31 1.90a programming guide section
2585 * 4.1.9, it specifies that for a reconnect after a
2586 * device-initiated disconnect requires a core soft reset
2587 * (DCTL.CSftRst) before enabling the run/stop bit.
2589 dwc3_core_soft_reset(dwc);
2591 dwc3_event_buffers_setup(dwc);
2592 __dwc3_gadget_start(dwc);
2593 ret = dwc3_gadget_run_stop(dwc, true, false);
2596 pm_runtime_put(dwc->dev);
2601 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2605 /* Enable all but Start and End of Frame IRQs */
2606 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2607 DWC3_DEVTEN_CMDCMPLTEN |
2608 DWC3_DEVTEN_ERRTICERREN |
2609 DWC3_DEVTEN_WKUPEVTEN |
2610 DWC3_DEVTEN_CONNECTDONEEN |
2611 DWC3_DEVTEN_USBRSTEN |
2612 DWC3_DEVTEN_DISCONNEVTEN);
2614 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2615 reg |= DWC3_DEVTEN_ULSTCNGEN;
2617 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2618 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2619 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2621 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2624 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2626 /* mask all interrupts */
2627 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2630 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2631 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2634 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2635 * @dwc: pointer to our context structure
2637 * The following looks like complex but it's actually very simple. In order to
2638 * calculate the number of packets we can burst at once on OUT transfers, we're
2639 * gonna use RxFIFO size.
2641 * To calculate RxFIFO size we need two numbers:
2642 * MDWIDTH = size, in bits, of the internal memory bus
2643 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2645 * Given these two numbers, the formula is simple:
2647 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2649 * 24 bytes is for 3x SETUP packets
2650 * 16 bytes is a clock domain crossing tolerance
2652 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2654 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2661 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2662 mdwidth = dwc3_mdwidth(dwc);
2664 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2665 nump = min_t(u32, nump, 16);
2668 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2669 reg &= ~DWC3_DCFG_NUMP_MASK;
2670 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2671 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2674 static int __dwc3_gadget_start(struct dwc3 *dwc)
2676 struct dwc3_ep *dep;
2681 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2682 * the core supports IMOD, disable it.
2684 if (dwc->imod_interval) {
2685 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2686 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2687 } else if (dwc3_has_imod(dwc)) {
2688 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2692 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2693 * field instead of letting dwc3 itself calculate that automatically.
2695 * This way, we maximize the chances that we'll be able to get several
2696 * bursts of data without going through any sort of endpoint throttling.
2698 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2699 if (DWC3_IP_IS(DWC3))
2700 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2702 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2704 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2706 dwc3_gadget_setup_nump(dwc);
2709 * Currently the controller handles single stream only. So, Ignore
2710 * Packet Pending bit for stream selection and don't search for another
2711 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2712 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2713 * the stream performance.
2715 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2716 reg |= DWC3_DCFG_IGNSTRMPP;
2717 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2719 /* Enable MST by default if the device is capable of MST */
2720 if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2721 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2722 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2723 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2726 /* Start with SuperSpeed Default */
2727 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2730 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2732 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2737 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2739 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2743 /* begin to receive SETUP packets */
2744 dwc->ep0state = EP0_SETUP_PHASE;
2745 dwc->ep0_bounced = false;
2746 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2747 dwc->delayed_status = false;
2748 dwc3_ep0_out_start(dwc);
2750 dwc3_gadget_enable_irq(dwc);
2755 __dwc3_gadget_ep_disable(dwc->eps[0]);
2761 static int dwc3_gadget_start(struct usb_gadget *g,
2762 struct usb_gadget_driver *driver)
2764 struct dwc3 *dwc = gadget_to_dwc(g);
2765 unsigned long flags;
2769 irq = dwc->irq_gadget;
2770 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2771 IRQF_SHARED, "dwc3", dwc->ev_buf);
2773 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2778 spin_lock_irqsave(&dwc->lock, flags);
2779 dwc->gadget_driver = driver;
2780 spin_unlock_irqrestore(&dwc->lock, flags);
2785 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2787 dwc3_gadget_disable_irq(dwc);
2788 __dwc3_gadget_ep_disable(dwc->eps[0]);
2789 __dwc3_gadget_ep_disable(dwc->eps[1]);
2792 static int dwc3_gadget_stop(struct usb_gadget *g)
2794 struct dwc3 *dwc = gadget_to_dwc(g);
2795 unsigned long flags;
2797 spin_lock_irqsave(&dwc->lock, flags);
2798 dwc->gadget_driver = NULL;
2799 dwc->max_cfg_eps = 0;
2800 spin_unlock_irqrestore(&dwc->lock, flags);
2802 free_irq(dwc->irq_gadget, dwc->ev_buf);
2807 static void dwc3_gadget_config_params(struct usb_gadget *g,
2808 struct usb_dcd_config_params *params)
2810 struct dwc3 *dwc = gadget_to_dwc(g);
2812 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2813 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2815 /* Recommended BESL */
2816 if (!dwc->dis_enblslpm_quirk) {
2818 * If the recommended BESL baseline is 0 or if the BESL deep is
2819 * less than 2, Microsoft's Windows 10 host usb stack will issue
2820 * a usb reset immediately after it receives the extended BOS
2821 * descriptor and the enumeration will fail. To maintain
2822 * compatibility with the Windows' usb stack, let's set the
2823 * recommended BESL baseline to 1 and clamp the BESL deep to be
2826 params->besl_baseline = 1;
2827 if (dwc->is_utmi_l1_suspend)
2829 clamp_t(u8, dwc->hird_threshold, 2, 15);
2832 /* U1 Device exit Latency */
2833 if (dwc->dis_u1_entry_quirk)
2834 params->bU1devExitLat = 0;
2836 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2838 /* U2 Device exit Latency */
2839 if (dwc->dis_u2_entry_quirk)
2840 params->bU2DevExitLat = 0;
2842 params->bU2DevExitLat =
2843 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2846 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2847 enum usb_device_speed speed)
2849 struct dwc3 *dwc = gadget_to_dwc(g);
2850 unsigned long flags;
2852 spin_lock_irqsave(&dwc->lock, flags);
2853 dwc->gadget_max_speed = speed;
2854 spin_unlock_irqrestore(&dwc->lock, flags);
2857 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2858 enum usb_ssp_rate rate)
2860 struct dwc3 *dwc = gadget_to_dwc(g);
2861 unsigned long flags;
2863 spin_lock_irqsave(&dwc->lock, flags);
2864 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2865 dwc->gadget_ssp_rate = rate;
2866 spin_unlock_irqrestore(&dwc->lock, flags);
2869 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2871 struct dwc3 *dwc = gadget_to_dwc(g);
2872 union power_supply_propval val = {0};
2876 return usb_phy_set_power(dwc->usb2_phy, mA);
2881 val.intval = 1000 * mA;
2882 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2888 * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
2889 * @g: pointer to the USB gadget
2891 * Used to record the maximum number of endpoints being used in a USB composite
2892 * device. (across all configurations) This is to be used in the calculation
2893 * of the TXFIFO sizes when resizing internal memory for individual endpoints.
2894 * It will help ensured that the resizing logic reserves enough space for at
2895 * least one max packet.
2897 static int dwc3_gadget_check_config(struct usb_gadget *g)
2899 struct dwc3 *dwc = gadget_to_dwc(g);
2905 if (!dwc->do_fifo_resize)
2908 list_for_each_entry(ep, &g->ep_list, ep_list) {
2909 /* Only interested in the IN endpoints */
2910 if (ep->claimed && (ep->address & USB_DIR_IN))
2914 if (ep_num <= dwc->max_cfg_eps)
2917 /* Update the max number of eps in the composition */
2918 dwc->max_cfg_eps = ep_num;
2920 fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
2921 /* Based on the equation, increment by one for every ep */
2922 fifo_size += dwc->max_cfg_eps;
2924 /* Check if we can fit a single fifo per endpoint */
2925 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
2926 if (fifo_size > ram1_depth)
2932 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2934 struct dwc3 *dwc = gadget_to_dwc(g);
2935 unsigned long flags;
2937 spin_lock_irqsave(&dwc->lock, flags);
2938 dwc->async_callbacks = enable;
2939 spin_unlock_irqrestore(&dwc->lock, flags);
2942 static const struct usb_gadget_ops dwc3_gadget_ops = {
2943 .get_frame = dwc3_gadget_get_frame,
2944 .wakeup = dwc3_gadget_wakeup,
2945 .set_selfpowered = dwc3_gadget_set_selfpowered,
2946 .pullup = dwc3_gadget_pullup,
2947 .udc_start = dwc3_gadget_start,
2948 .udc_stop = dwc3_gadget_stop,
2949 .udc_set_speed = dwc3_gadget_set_speed,
2950 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
2951 .get_config_params = dwc3_gadget_config_params,
2952 .vbus_draw = dwc3_gadget_vbus_draw,
2953 .check_config = dwc3_gadget_check_config,
2954 .udc_async_callbacks = dwc3_gadget_async_callbacks,
2957 /* -------------------------------------------------------------------------- */
2959 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2961 struct dwc3 *dwc = dep->dwc;
2963 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2964 dep->endpoint.maxburst = 1;
2965 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2966 if (!dep->direction)
2967 dwc->gadget->ep0 = &dep->endpoint;
2969 dep->endpoint.caps.type_control = true;
2974 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2976 struct dwc3 *dwc = dep->dwc;
2981 mdwidth = dwc3_mdwidth(dwc);
2983 /* MDWIDTH is represented in bits, we need it in bytes */
2986 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2987 if (DWC3_IP_IS(DWC3))
2988 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2990 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2993 * maxpacket size is determined as part of the following, after assuming
2994 * a mult value of one maxpacket:
2995 * DWC3 revision 280A and prior:
2996 * fifo_size = mult * (max_packet / mdwidth) + 1;
2997 * maxpacket = mdwidth * (fifo_size - 1);
2999 * DWC3 revision 290A and onwards:
3000 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3001 * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3003 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3004 maxpacket = mdwidth * (size - 1);
3006 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3008 /* Functionally, space for one max packet is sufficient */
3009 size = min_t(int, maxpacket, 1024);
3010 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3012 dep->endpoint.max_streams = 16;
3013 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3014 list_add_tail(&dep->endpoint.ep_list,
3015 &dwc->gadget->ep_list);
3016 dep->endpoint.caps.type_iso = true;
3017 dep->endpoint.caps.type_bulk = true;
3018 dep->endpoint.caps.type_int = true;
3020 return dwc3_alloc_trb_pool(dep);
3023 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3025 struct dwc3 *dwc = dep->dwc;
3029 mdwidth = dwc3_mdwidth(dwc);
3031 /* MDWIDTH is represented in bits, convert to bytes */
3034 /* All OUT endpoints share a single RxFIFO space */
3035 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3036 if (DWC3_IP_IS(DWC3))
3037 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3039 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3041 /* FIFO depth is in MDWDITH bytes */
3045 * To meet performance requirement, a minimum recommended RxFIFO size
3046 * is defined as follow:
3047 * RxFIFO size >= (3 x MaxPacketSize) +
3048 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3050 * Then calculate the max packet limit as below.
3052 size -= (3 * 8) + 16;
3058 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3059 dep->endpoint.max_streams = 16;
3060 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3061 list_add_tail(&dep->endpoint.ep_list,
3062 &dwc->gadget->ep_list);
3063 dep->endpoint.caps.type_iso = true;
3064 dep->endpoint.caps.type_bulk = true;
3065 dep->endpoint.caps.type_int = true;
3067 return dwc3_alloc_trb_pool(dep);
3070 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3072 struct dwc3_ep *dep;
3073 bool direction = epnum & 1;
3075 u8 num = epnum >> 1;
3077 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3082 dep->number = epnum;
3083 dep->direction = direction;
3084 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3085 dwc->eps[epnum] = dep;
3087 dep->start_cmd_status = 0;
3089 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3090 direction ? "in" : "out");
3092 dep->endpoint.name = dep->name;
3094 if (!(dep->number > 1)) {
3095 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3096 dep->endpoint.comp_desc = NULL;
3100 ret = dwc3_gadget_init_control_endpoint(dep);
3102 ret = dwc3_gadget_init_in_endpoint(dep);
3104 ret = dwc3_gadget_init_out_endpoint(dep);
3109 dep->endpoint.caps.dir_in = direction;
3110 dep->endpoint.caps.dir_out = !direction;
3112 INIT_LIST_HEAD(&dep->pending_list);
3113 INIT_LIST_HEAD(&dep->started_list);
3114 INIT_LIST_HEAD(&dep->cancelled_list);
3116 dwc3_debugfs_create_endpoint_dir(dep);
3121 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3125 INIT_LIST_HEAD(&dwc->gadget->ep_list);
3127 for (epnum = 0; epnum < total; epnum++) {
3130 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3138 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3140 struct dwc3_ep *dep;
3143 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3144 dep = dwc->eps[epnum];
3148 * Physical endpoints 0 and 1 are special; they form the
3149 * bi-directional USB endpoint 0.
3151 * For those two physical endpoints, we don't allocate a TRB
3152 * pool nor do we add them the endpoints list. Due to that, we
3153 * shouldn't do these two operations otherwise we would end up
3154 * with all sorts of bugs when removing dwc3.ko.
3156 if (epnum != 0 && epnum != 1) {
3157 dwc3_free_trb_pool(dep);
3158 list_del(&dep->endpoint.ep_list);
3161 debugfs_remove_recursive(debugfs_lookup(dep->name,
3162 debugfs_lookup(dev_name(dep->dwc->dev),
3168 /* -------------------------------------------------------------------------- */
3170 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3171 struct dwc3_request *req, struct dwc3_trb *trb,
3172 const struct dwc3_event_depevt *event, int status, int chain)
3176 dwc3_ep_inc_deq(dep);
3178 trace_dwc3_complete_trb(dep, trb);
3182 * If we're in the middle of series of chained TRBs and we
3183 * receive a short transfer along the way, DWC3 will skip
3184 * through all TRBs including the last TRB in the chain (the
3185 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3186 * bit and SW has to do it manually.
3188 * We're going to do that here to avoid problems of HW trying
3189 * to use bogus TRBs for transfers.
3191 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3192 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3195 * For isochronous transfers, the first TRB in a service interval must
3196 * have the Isoc-First type. Track and report its interval frame number.
3198 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3199 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3200 unsigned int frame_number;
3202 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3203 frame_number &= ~(dep->interval - 1);
3204 req->request.frame_number = frame_number;
3208 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3209 * this TRB points to the bounce buffer address, it's a MPS alignment
3210 * TRB. Don't add it to req->remaining calculation.
3212 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3213 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3214 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3218 count = trb->size & DWC3_TRB_SIZE_MASK;
3219 req->remaining += count;
3221 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3224 if (event->status & DEPEVT_STATUS_SHORT && !chain)
3227 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3228 (trb->ctrl & DWC3_TRB_CTRL_LST))
3234 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3235 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3238 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3239 struct scatterlist *sg = req->sg;
3240 struct scatterlist *s;
3241 unsigned int num_queued = req->num_queued_sgs;
3245 for_each_sg(sg, s, num_queued, i) {
3246 trb = &dep->trb_pool[dep->trb_dequeue];
3248 req->sg = sg_next(s);
3249 req->num_queued_sgs--;
3251 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3252 trb, event, status, true);
3260 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3261 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3264 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3266 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3267 event, status, false);
3270 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3272 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3275 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3276 const struct dwc3_event_depevt *event,
3277 struct dwc3_request *req, int status)
3282 if (req->request.num_mapped_sgs)
3283 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3286 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3289 req->request.actual = req->request.length - req->remaining;
3291 if (!dwc3_gadget_ep_request_completed(req))
3294 if (req->needs_extra_trb) {
3295 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3297 req->needs_extra_trb = false;
3301 * The event status only reflects the status of the TRB with IOC set.
3302 * For the requests that don't set interrupt on completion, the driver
3303 * needs to check and return the status of the completed TRBs associated
3304 * with the request. Use the status of the last TRB of the request.
3306 if (req->request.no_interrupt) {
3307 struct dwc3_trb *trb;
3309 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3310 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3311 case DWC3_TRBSTS_MISSED_ISOC:
3312 /* Isoc endpoint only */
3313 request_status = -EXDEV;
3315 case DWC3_TRB_STS_XFER_IN_PROG:
3316 /* Applicable when End Transfer with ForceRM=0 */
3317 case DWC3_TRBSTS_SETUP_PENDING:
3318 /* Control endpoint only */
3319 case DWC3_TRBSTS_OK:
3325 request_status = status;
3328 dwc3_gadget_giveback(dep, req, request_status);
3334 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3335 const struct dwc3_event_depevt *event, int status)
3337 struct dwc3_request *req;
3339 while (!list_empty(&dep->started_list)) {
3342 req = next_request(&dep->started_list);
3343 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3348 * The endpoint is disabled, let the dwc3_remove_requests()
3349 * handle the cleanup.
3351 if (!dep->endpoint.desc)
3356 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3358 struct dwc3_request *req;
3359 struct dwc3 *dwc = dep->dwc;
3361 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3365 if (!list_empty(&dep->pending_list))
3369 * We only need to check the first entry of the started list. We can
3370 * assume the completed requests are removed from the started list.
3372 req = next_request(&dep->started_list);
3376 return !dwc3_gadget_ep_request_completed(req);
3379 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3380 const struct dwc3_event_depevt *event)
3382 dep->frame_number = event->parameters;
3385 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3386 const struct dwc3_event_depevt *event, int status)
3388 struct dwc3 *dwc = dep->dwc;
3389 bool no_started_trb = true;
3391 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3393 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3396 if (!dep->endpoint.desc)
3397 return no_started_trb;
3399 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3400 list_empty(&dep->started_list) &&
3401 (list_empty(&dep->pending_list) || status == -EXDEV))
3402 dwc3_stop_active_transfer(dep, true, true);
3403 else if (dwc3_gadget_ep_should_continue(dep))
3404 if (__dwc3_gadget_kick_transfer(dep) == 0)
3405 no_started_trb = false;
3409 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3410 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3412 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3416 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3419 if (!(dep->flags & DWC3_EP_ENABLED))
3422 if (!list_empty(&dep->started_list))
3423 return no_started_trb;
3426 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3428 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3433 return no_started_trb;
3436 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3437 const struct dwc3_event_depevt *event)
3441 if (!dep->endpoint.desc)
3444 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3445 dwc3_gadget_endpoint_frame_from_event(dep, event);
3447 if (event->status & DEPEVT_STATUS_BUSERR)
3448 status = -ECONNRESET;
3450 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3453 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3456 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3457 const struct dwc3_event_depevt *event)
3461 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3463 if (event->status & DEPEVT_STATUS_BUSERR)
3464 status = -ECONNRESET;
3466 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3467 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3470 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3471 const struct dwc3_event_depevt *event)
3473 dwc3_gadget_endpoint_frame_from_event(dep, event);
3476 * The XferNotReady event is generated only once before the endpoint
3477 * starts. It will be generated again when END_TRANSFER command is
3478 * issued. For some controller versions, the XferNotReady event may be
3479 * generated while the END_TRANSFER command is still in process. Ignore
3480 * it and wait for the next XferNotReady event after the command is
3483 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3486 (void) __dwc3_gadget_start_isoc(dep);
3489 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3490 const struct dwc3_event_depevt *event)
3492 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3494 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3498 * The END_TRANSFER command will cause the controller to generate a
3499 * NoStream Event, and it's not due to the host DP NoStream rejection.
3500 * Ignore the next NoStream event.
3502 if (dep->stream_capable)
3503 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3505 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3506 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3507 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3509 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3510 struct dwc3 *dwc = dep->dwc;
3512 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3513 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3514 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3516 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3517 if (dwc->delayed_status)
3518 __dwc3_gadget_ep0_set_halt(ep0, 1);
3522 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3523 if (dwc->clear_stall_protocol == dep->number)
3524 dwc3_ep0_send_delayed_status(dwc);
3527 if ((dep->flags & DWC3_EP_DELAY_START) &&
3528 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3529 __dwc3_gadget_kick_transfer(dep);
3531 dep->flags &= ~DWC3_EP_DELAY_START;
3534 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3535 const struct dwc3_event_depevt *event)
3537 struct dwc3 *dwc = dep->dwc;
3539 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3540 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3544 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3545 switch (event->parameters) {
3546 case DEPEVT_STREAM_PRIME:
3548 * If the host can properly transition the endpoint state from
3549 * idle to prime after a NoStream rejection, there's no need to
3550 * force restarting the endpoint to reinitiate the stream. To
3551 * simplify the check, assume the host follows the USB spec if
3552 * it primed the endpoint more than once.
3554 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3555 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3556 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3558 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3562 case DEPEVT_STREAM_NOSTREAM:
3563 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3564 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3565 (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3566 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3570 * If the host rejects a stream due to no active stream, by the
3571 * USB and xHCI spec, the endpoint will be put back to idle
3572 * state. When the host is ready (buffer added/updated), it will
3573 * prime the endpoint to inform the usb device controller. This
3574 * triggers the device controller to issue ERDY to restart the
3575 * stream. However, some hosts don't follow this and keep the
3576 * endpoint in the idle state. No prime will come despite host
3577 * streams are updated, and the device controller will not be
3578 * triggered to generate ERDY to move the next stream data. To
3579 * workaround this and maintain compatibility with various
3580 * hosts, force to reinitate the stream until the host is ready
3581 * instead of waiting for the host to prime the endpoint.
3583 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3584 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3586 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3588 dep->flags |= DWC3_EP_DELAY_START;
3589 dwc3_stop_active_transfer(dep, true, true);
3596 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3599 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3600 const struct dwc3_event_depevt *event)
3602 struct dwc3_ep *dep;
3603 u8 epnum = event->endpoint_number;
3605 dep = dwc->eps[epnum];
3607 if (!(dep->flags & DWC3_EP_ENABLED)) {
3608 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3611 /* Handle only EPCMDCMPLT when EP disabled */
3612 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3616 if (epnum == 0 || epnum == 1) {
3617 dwc3_ep0_interrupt(dwc, event);
3621 switch (event->endpoint_event) {
3622 case DWC3_DEPEVT_XFERINPROGRESS:
3623 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3625 case DWC3_DEPEVT_XFERNOTREADY:
3626 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3628 case DWC3_DEPEVT_EPCMDCMPLT:
3629 dwc3_gadget_endpoint_command_complete(dep, event);
3631 case DWC3_DEPEVT_XFERCOMPLETE:
3632 dwc3_gadget_endpoint_transfer_complete(dep, event);
3634 case DWC3_DEPEVT_STREAMEVT:
3635 dwc3_gadget_endpoint_stream_event(dep, event);
3637 case DWC3_DEPEVT_RXTXFIFOEVT:
3642 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3644 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3645 spin_unlock(&dwc->lock);
3646 dwc->gadget_driver->disconnect(dwc->gadget);
3647 spin_lock(&dwc->lock);
3651 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3653 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3654 spin_unlock(&dwc->lock);
3655 dwc->gadget_driver->suspend(dwc->gadget);
3656 spin_lock(&dwc->lock);
3660 static void dwc3_resume_gadget(struct dwc3 *dwc)
3662 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3663 spin_unlock(&dwc->lock);
3664 dwc->gadget_driver->resume(dwc->gadget);
3665 spin_lock(&dwc->lock);
3669 static void dwc3_reset_gadget(struct dwc3 *dwc)
3671 if (!dwc->gadget_driver)
3674 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3675 spin_unlock(&dwc->lock);
3676 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3677 spin_lock(&dwc->lock);
3681 void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3684 struct dwc3 *dwc = dep->dwc;
3687 * Only issue End Transfer command to the control endpoint of a started
3688 * Data Phase. Typically we should only do so in error cases such as
3689 * invalid/unexpected direction as described in the control transfer
3690 * flow of the programming guide.
3692 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3695 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3696 (dep->flags & DWC3_EP_DELAY_STOP) ||
3697 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3701 * If a Setup packet is received but yet to DMA out, the controller will
3702 * not process the End Transfer command of any endpoint. Polling of its
3703 * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3704 * timeout. Delay issuing the End Transfer command until the Setup TRB is
3707 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3708 dep->flags |= DWC3_EP_DELAY_STOP;
3713 * NOTICE: We are violating what the Databook says about the
3714 * EndTransfer command. Ideally we would _always_ wait for the
3715 * EndTransfer Command Completion IRQ, but that's causing too
3716 * much trouble synchronizing between us and gadget driver.
3718 * We have discussed this with the IP Provider and it was
3719 * suggested to giveback all requests here.
3721 * Note also that a similar handling was tested by Synopsys
3722 * (thanks a lot Paul) and nothing bad has come out of it.
3723 * In short, what we're doing is issuing EndTransfer with
3724 * CMDIOC bit set and delay kicking transfer until the
3725 * EndTransfer command had completed.
3727 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3728 * supports a mode to work around the above limitation. The
3729 * software can poll the CMDACT bit in the DEPCMD register
3730 * after issuing a EndTransfer command. This mode is enabled
3731 * by writing GUCTL2[14]. This polling is already done in the
3732 * dwc3_send_gadget_ep_cmd() function so if the mode is
3733 * enabled, the EndTransfer command will have completed upon
3734 * returning from this function.
3736 * This mode is NOT available on the DWC_usb31 IP.
3739 __dwc3_stop_active_transfer(dep, force, interrupt);
3742 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3746 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3747 struct dwc3_ep *dep;
3750 dep = dwc->eps[epnum];
3754 if (!(dep->flags & DWC3_EP_STALL))
3757 dep->flags &= ~DWC3_EP_STALL;
3759 ret = dwc3_send_clear_stall_ep_cmd(dep);
3764 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3768 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3770 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3771 reg &= ~DWC3_DCTL_INITU1ENA;
3772 reg &= ~DWC3_DCTL_INITU2ENA;
3773 dwc3_gadget_dctl_write_safe(dwc, reg);
3775 dwc3_disconnect_gadget(dwc);
3777 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3778 dwc->setup_packet_pending = false;
3779 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3781 dwc->connected = false;
3784 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3789 * Ideally, dwc3_reset_gadget() would trigger the function
3790 * drivers to stop any active transfers through ep disable.
3791 * However, for functions which defer ep disable, such as mass
3792 * storage, we will need to rely on the call to stop active
3793 * transfers here, and avoid allowing of request queuing.
3795 dwc->connected = false;
3798 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3799 * would cause a missing Disconnect Event if there's a
3800 * pending Setup Packet in the FIFO.
3802 * There's no suggested workaround on the official Bug
3803 * report, which states that "unless the driver/application
3804 * is doing any special handling of a disconnect event,
3805 * there is no functional issue".
3807 * Unfortunately, it turns out that we _do_ some special
3808 * handling of a disconnect event, namely complete all
3809 * pending transfers, notify gadget driver of the
3810 * disconnection, and so on.
3812 * Our suggested workaround is to follow the Disconnect
3813 * Event steps here, instead, based on a setup_packet_pending
3814 * flag. Such flag gets set whenever we have a SETUP_PENDING
3815 * status for EP0 TRBs and gets cleared on XferComplete for the
3820 * STAR#9000466709: RTL: Device : Disconnect event not
3821 * generated if setup packet pending in FIFO
3823 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3824 if (dwc->setup_packet_pending)
3825 dwc3_gadget_disconnect_interrupt(dwc);
3828 dwc3_reset_gadget(dwc);
3831 * From SNPS databook section 8.1.2, the EP0 should be in setup
3832 * phase. So ensure that EP0 is in setup phase by issuing a stall
3833 * and restart if EP0 is not in setup phase.
3835 if (dwc->ep0state != EP0_SETUP_PHASE) {
3838 dir = !!dwc->ep0_expect_in;
3839 if (dwc->ep0state == EP0_DATA_PHASE)
3840 dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
3842 dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
3844 dwc->eps[0]->trb_enqueue = 0;
3845 dwc->eps[1]->trb_enqueue = 0;
3847 dwc3_ep0_stall_and_restart(dwc);
3851 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3852 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3853 * needs to ensure that it sends "a DEPENDXFER command for any active
3856 dwc3_stop_active_transfers(dwc);
3857 dwc->connected = true;
3859 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3860 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3861 dwc3_gadget_dctl_write_safe(dwc, reg);
3862 dwc->test_mode = false;
3863 dwc3_clear_stall_all_ep(dwc);
3865 /* Reset device address to zero */
3866 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3867 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3868 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3871 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3873 struct dwc3_ep *dep;
3879 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3880 speed = reg & DWC3_DSTS_CONNECTSPD;
3883 if (DWC3_IP_IS(DWC32))
3884 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3886 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3889 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3890 * each time on Connect Done.
3892 * Currently we always use the reset value. If any platform
3893 * wants to set this to a different value, we need to add a
3894 * setting and update GCTL.RAMCLKSEL here.
3898 case DWC3_DSTS_SUPERSPEED_PLUS:
3899 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3900 dwc->gadget->ep0->maxpacket = 512;
3901 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3904 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3906 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3908 case DWC3_DSTS_SUPERSPEED:
3910 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3911 * would cause a missing USB3 Reset event.
3913 * In such situations, we should force a USB3 Reset
3914 * event by calling our dwc3_gadget_reset_interrupt()
3919 * STAR#9000483510: RTL: SS : USB3 reset event may
3920 * not be generated always when the link enters poll
3922 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3923 dwc3_gadget_reset_interrupt(dwc);
3925 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3926 dwc->gadget->ep0->maxpacket = 512;
3927 dwc->gadget->speed = USB_SPEED_SUPER;
3930 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3931 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3934 case DWC3_DSTS_HIGHSPEED:
3935 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3936 dwc->gadget->ep0->maxpacket = 64;
3937 dwc->gadget->speed = USB_SPEED_HIGH;
3939 case DWC3_DSTS_FULLSPEED:
3940 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3941 dwc->gadget->ep0->maxpacket = 64;
3942 dwc->gadget->speed = USB_SPEED_FULL;
3946 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3948 /* Enable USB2 LPM Capability */
3950 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3951 !dwc->usb2_gadget_lpm_disable &&
3952 (speed != DWC3_DSTS_SUPERSPEED) &&
3953 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3954 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3955 reg |= DWC3_DCFG_LPM_CAP;
3956 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3958 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3959 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3961 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3962 (dwc->is_utmi_l1_suspend << 4));
3965 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3966 * DCFG.LPMCap is set, core responses with an ACK and the
3967 * BESL value in the LPM token is less than or equal to LPM
3970 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3971 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3973 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3974 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3976 dwc3_gadget_dctl_write_safe(dwc, reg);
3978 if (dwc->usb2_gadget_lpm_disable) {
3979 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3980 reg &= ~DWC3_DCFG_LPM_CAP;
3981 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3984 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3985 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3986 dwc3_gadget_dctl_write_safe(dwc, reg);
3990 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3992 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3997 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3999 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4004 * Configure PHY via GUSB3PIPECTLn if required.
4006 * Update GTXFIFOSIZn
4008 * In both cases reset values should be sufficient.
4012 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
4015 * TODO take core out of low power mode when that's
4019 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4020 spin_unlock(&dwc->lock);
4021 dwc->gadget_driver->resume(dwc->gadget);
4022 spin_lock(&dwc->lock);
4026 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4027 unsigned int evtinfo)
4029 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4030 unsigned int pwropt;
4033 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4034 * Hibernation mode enabled which would show up when device detects
4035 * host-initiated U3 exit.
4037 * In that case, device will generate a Link State Change Interrupt
4038 * from U3 to RESUME which is only necessary if Hibernation is
4041 * There are no functional changes due to such spurious event and we
4042 * just need to ignore it.
4046 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4049 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4050 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4051 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4052 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4053 (next == DWC3_LINK_STATE_RESUME)) {
4059 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4060 * on the link partner, the USB session might do multiple entry/exit
4061 * of low power states before a transfer takes place.
4063 * Due to this problem, we might experience lower throughput. The
4064 * suggested workaround is to disable DCTL[12:9] bits if we're
4065 * transitioning from U1/U2 to U0 and enable those bits again
4066 * after a transfer completes and there are no pending transfers
4067 * on any of the enabled endpoints.
4069 * This is the first half of that workaround.
4073 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4074 * core send LGO_Ux entering U0
4076 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4077 if (next == DWC3_LINK_STATE_U0) {
4081 switch (dwc->link_state) {
4082 case DWC3_LINK_STATE_U1:
4083 case DWC3_LINK_STATE_U2:
4084 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4085 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4086 | DWC3_DCTL_ACCEPTU2ENA
4087 | DWC3_DCTL_INITU1ENA
4088 | DWC3_DCTL_ACCEPTU1ENA);
4091 dwc->u1u2 = reg & u1u2;
4095 dwc3_gadget_dctl_write_safe(dwc, reg);
4105 case DWC3_LINK_STATE_U1:
4106 if (dwc->speed == USB_SPEED_SUPER)
4107 dwc3_suspend_gadget(dwc);
4109 case DWC3_LINK_STATE_U2:
4110 case DWC3_LINK_STATE_U3:
4111 dwc3_suspend_gadget(dwc);
4113 case DWC3_LINK_STATE_RESUME:
4114 dwc3_resume_gadget(dwc);
4121 dwc->link_state = next;
4124 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4125 unsigned int evtinfo)
4127 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4129 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
4130 dwc3_suspend_gadget(dwc);
4132 dwc->link_state = next;
4135 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
4136 unsigned int evtinfo)
4138 unsigned int is_ss = evtinfo & BIT(4);
4141 * WORKAROUND: DWC3 revison 2.20a with hibernation support
4142 * have a known issue which can cause USB CV TD.9.23 to fail
4145 * Because of this issue, core could generate bogus hibernation
4146 * events which SW needs to ignore.
4150 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
4151 * Device Fallback from SuperSpeed
4153 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
4156 /* enter hibernation here */
4159 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4160 const struct dwc3_event_devt *event)
4162 switch (event->type) {
4163 case DWC3_DEVICE_EVENT_DISCONNECT:
4164 dwc3_gadget_disconnect_interrupt(dwc);
4166 case DWC3_DEVICE_EVENT_RESET:
4167 dwc3_gadget_reset_interrupt(dwc);
4169 case DWC3_DEVICE_EVENT_CONNECT_DONE:
4170 dwc3_gadget_conndone_interrupt(dwc);
4172 case DWC3_DEVICE_EVENT_WAKEUP:
4173 dwc3_gadget_wakeup_interrupt(dwc);
4175 case DWC3_DEVICE_EVENT_HIBER_REQ:
4176 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
4177 "unexpected hibernation event\n"))
4180 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
4182 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4183 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4185 case DWC3_DEVICE_EVENT_SUSPEND:
4186 /* It changed to be suspend event for version 2.30a and above */
4187 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
4189 * Ignore suspend event until the gadget enters into
4190 * USB_STATE_CONFIGURED state.
4192 if (dwc->gadget->state >= USB_STATE_CONFIGURED)
4193 dwc3_gadget_suspend_interrupt(dwc,
4197 case DWC3_DEVICE_EVENT_SOF:
4198 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4199 case DWC3_DEVICE_EVENT_CMD_CMPL:
4200 case DWC3_DEVICE_EVENT_OVERFLOW:
4203 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4207 static void dwc3_process_event_entry(struct dwc3 *dwc,
4208 const union dwc3_event *event)
4210 trace_dwc3_event(event->raw, dwc);
4212 if (!event->type.is_devspec)
4213 dwc3_endpoint_interrupt(dwc, &event->depevt);
4214 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4215 dwc3_gadget_interrupt(dwc, &event->devt);
4217 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4220 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4222 struct dwc3 *dwc = evt->dwc;
4223 irqreturn_t ret = IRQ_NONE;
4228 if (!(evt->flags & DWC3_EVENT_PENDING))
4232 union dwc3_event event;
4234 event.raw = *(u32 *) (evt->cache + evt->lpos);
4236 dwc3_process_event_entry(dwc, &event);
4239 * FIXME we wrap around correctly to the next entry as
4240 * almost all entries are 4 bytes in size. There is one
4241 * entry which has 12 bytes which is a regular entry
4242 * followed by 8 bytes data. ATM I don't know how
4243 * things are organized if we get next to the a
4244 * boundary so I worry about that once we try to handle
4247 evt->lpos = (evt->lpos + 4) % evt->length;
4252 evt->flags &= ~DWC3_EVENT_PENDING;
4255 /* Unmask interrupt */
4256 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4257 DWC3_GEVNTSIZ_SIZE(evt->length));
4259 if (dwc->imod_interval) {
4260 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4261 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4267 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4269 struct dwc3_event_buffer *evt = _evt;
4270 struct dwc3 *dwc = evt->dwc;
4271 unsigned long flags;
4272 irqreturn_t ret = IRQ_NONE;
4275 spin_lock_irqsave(&dwc->lock, flags);
4276 ret = dwc3_process_event_buf(evt);
4277 spin_unlock_irqrestore(&dwc->lock, flags);
4283 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4285 struct dwc3 *dwc = evt->dwc;
4289 if (pm_runtime_suspended(dwc->dev)) {
4290 pm_runtime_get(dwc->dev);
4291 disable_irq_nosync(dwc->irq_gadget);
4292 dwc->pending_events = true;
4297 * With PCIe legacy interrupt, test shows that top-half irq handler can
4298 * be called again after HW interrupt deassertion. Check if bottom-half
4299 * irq event handler completes before caching new event to prevent
4302 if (evt->flags & DWC3_EVENT_PENDING)
4305 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4306 count &= DWC3_GEVNTCOUNT_MASK;
4311 evt->flags |= DWC3_EVENT_PENDING;
4313 /* Mask interrupt */
4314 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4315 DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4317 amount = min(count, evt->length - evt->lpos);
4318 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4321 memcpy(evt->cache, evt->buf, count - amount);
4323 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4325 return IRQ_WAKE_THREAD;
4328 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4330 struct dwc3_event_buffer *evt = _evt;
4332 return dwc3_check_event_buf(evt);
4335 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4337 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4340 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4344 if (irq == -EPROBE_DEFER)
4347 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4351 if (irq == -EPROBE_DEFER)
4354 irq = platform_get_irq(dwc3_pdev, 0);
4365 static void dwc_gadget_release(struct device *dev)
4367 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4373 * dwc3_gadget_init - initializes gadget related registers
4374 * @dwc: pointer to our controller context structure
4376 * Returns 0 on success otherwise negative errno.
4378 int dwc3_gadget_init(struct dwc3 *dwc)
4384 irq = dwc3_gadget_get_irq(dwc);
4390 dwc->irq_gadget = irq;
4392 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4393 sizeof(*dwc->ep0_trb) * 2,
4394 &dwc->ep0_trb_addr, GFP_KERNEL);
4395 if (!dwc->ep0_trb) {
4396 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4401 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4402 if (!dwc->setup_buf) {
4407 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4408 &dwc->bounce_addr, GFP_KERNEL);
4414 init_completion(&dwc->ep0_in_setup);
4415 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4422 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4423 dev = &dwc->gadget->dev;
4424 dev->platform_data = dwc;
4425 dwc->gadget->ops = &dwc3_gadget_ops;
4426 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4427 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4428 dwc->gadget->sg_supported = true;
4429 dwc->gadget->name = "dwc3-gadget";
4430 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4433 * FIXME We might be setting max_speed to <SUPER, however versions
4434 * <2.20a of dwc3 have an issue with metastability (documented
4435 * elsewhere in this driver) which tells us we can't set max speed to
4436 * anything lower than SUPER.
4438 * Because gadget.max_speed is only used by composite.c and function
4439 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4440 * to happen so we avoid sending SuperSpeed Capability descriptor
4441 * together with our BOS descriptor as that could confuse host into
4442 * thinking we can handle super speed.
4444 * Note that, in fact, we won't even support GetBOS requests when speed
4445 * is less than super speed because we don't have means, yet, to tell
4446 * composite.c that we are USB 2.0 + LPM ECN.
4448 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4449 !dwc->dis_metastability_quirk)
4450 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4453 dwc->gadget->max_speed = dwc->maximum_speed;
4454 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4457 * REVISIT: Here we should clear all pending IRQs to be
4458 * sure we're starting from a well known location.
4461 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4465 ret = usb_add_gadget(dwc->gadget);
4467 dev_err(dwc->dev, "failed to add gadget\n");
4471 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4472 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4474 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4479 dwc3_gadget_free_endpoints(dwc);
4481 usb_put_gadget(dwc->gadget);
4484 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4488 kfree(dwc->setup_buf);
4491 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4492 dwc->ep0_trb, dwc->ep0_trb_addr);
4498 /* -------------------------------------------------------------------------- */
4500 void dwc3_gadget_exit(struct dwc3 *dwc)
4505 usb_del_gadget(dwc->gadget);
4506 dwc3_gadget_free_endpoints(dwc);
4507 usb_put_gadget(dwc->gadget);
4508 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4510 kfree(dwc->setup_buf);
4511 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4512 dwc->ep0_trb, dwc->ep0_trb_addr);
4515 int dwc3_gadget_suspend(struct dwc3 *dwc)
4517 if (!dwc->gadget_driver)
4520 dwc3_gadget_run_stop(dwc, false, false);
4521 dwc3_disconnect_gadget(dwc);
4522 __dwc3_gadget_stop(dwc);
4527 int dwc3_gadget_resume(struct dwc3 *dwc)
4531 if (!dwc->gadget_driver || !dwc->softconnect)
4534 ret = __dwc3_gadget_start(dwc);
4538 ret = dwc3_gadget_run_stop(dwc, true, false);
4545 __dwc3_gadget_stop(dwc);
4551 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4553 if (dwc->pending_events) {
4554 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4555 dwc->pending_events = false;
4556 enable_irq(dwc->irq_gadget);