2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
149 * dwc3_ep_inc_trb() - Increment a TRB index.
150 * @index - Pointer to the TRB index to increment.
152 * The index should never point to the link TRB. After incrementing,
153 * if it is point to the link TRB, wrap around to the beginning. The
154 * link TRB is always at the last TRB entry.
156 static void dwc3_ep_inc_trb(u8 *index)
159 if (*index == (DWC3_TRB_NUM - 1))
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
170 dwc3_ep_inc_trb(&dep->trb_dequeue);
173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
176 struct dwc3 *dwc = dep->dwc;
177 unsigned int unmap_after_complete = false;
179 req->started = false;
180 list_del(&req->list);
183 if (req->request.status == -EINPROGRESS)
184 req->request.status = status;
187 * NOTICE we don't want to unmap before calling ->complete() if we're
188 * dealing with a bounced ep0 request. If we unmap it here, we would end
189 * up overwritting the contents of req->buf and this could confuse the
192 if (dwc->ep0_bounced && dep->number <= 1) {
193 dwc->ep0_bounced = false;
194 unmap_after_complete = true;
196 usb_gadget_unmap_request(&dwc->gadget,
197 &req->request, req->direction);
200 trace_dwc3_gadget_giveback(req);
202 spin_unlock(&dwc->lock);
203 usb_gadget_giveback_request(&dep->endpoint, &req->request);
204 spin_lock(&dwc->lock);
206 if (unmap_after_complete)
207 usb_gadget_unmap_request(&dwc->gadget,
208 &req->request, req->direction);
211 pm_runtime_put(dwc->dev);
214 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
221 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
222 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
225 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
226 if (!(reg & DWC3_DGCMD_CMDACT)) {
227 status = DWC3_DGCMD_STATUS(reg);
239 trace_dwc3_gadget_generic_cmd(cmd, param, status);
244 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
246 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
247 struct dwc3_gadget_ep_cmd_params *params)
249 struct dwc3 *dwc = dep->dwc;
258 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
259 * we're issuing an endpoint command, we must check if
260 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
262 * We will also set SUSPHY bit to what it was before returning as stated
263 * by the same section on Synopsys databook.
265 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
266 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
267 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
269 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
270 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
274 if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
277 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
278 dwc->link_state == DWC3_LINK_STATE_U2 ||
279 dwc->link_state == DWC3_LINK_STATE_U3);
281 if (unlikely(needs_wakeup)) {
282 ret = __dwc3_gadget_wakeup(dwc);
283 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
288 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
289 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
290 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
292 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
294 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
295 if (!(reg & DWC3_DEPCMD_CMDACT)) {
296 cmd_status = DWC3_DEPCMD_STATUS(reg);
298 switch (cmd_status) {
302 case DEPEVT_TRANSFER_NO_RESOURCE:
305 case DEPEVT_TRANSFER_BUS_EXPIRY:
307 * SW issues START TRANSFER command to
308 * isochronous ep with future frame interval. If
309 * future interval time has already passed when
310 * core receives the command, it will respond
311 * with an error status of 'Bus Expiry'.
313 * Instead of always returning -EINVAL, let's
314 * give a hint to the gadget driver that this is
315 * the case by returning -EAGAIN.
320 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
329 cmd_status = -ETIMEDOUT;
332 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
334 if (unlikely(susphy)) {
335 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
336 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
337 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
343 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
345 struct dwc3 *dwc = dep->dwc;
346 struct dwc3_gadget_ep_cmd_params params;
347 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
350 * As of core revision 2.60a the recommended programming model
351 * is to set the ClearPendIN bit when issuing a Clear Stall EP
352 * command for IN endpoints. This is to prevent an issue where
353 * some (non-compliant) hosts may not send ACK TPs for pending
354 * IN transfers due to a mishandled error condition. Synopsys
357 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
358 (dwc->gadget.speed >= USB_SPEED_SUPER))
359 cmd |= DWC3_DEPCMD_CLEARPENDIN;
361 memset(¶ms, 0, sizeof(params));
363 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
366 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
367 struct dwc3_trb *trb)
369 u32 offset = (char *) trb - (char *) dep->trb_pool;
371 return dep->trb_pool_dma + offset;
374 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
376 struct dwc3 *dwc = dep->dwc;
381 dep->trb_pool = dma_alloc_coherent(dwc->dev,
382 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
383 &dep->trb_pool_dma, GFP_KERNEL);
384 if (!dep->trb_pool) {
385 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
393 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
395 struct dwc3 *dwc = dep->dwc;
397 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
398 dep->trb_pool, dep->trb_pool_dma);
400 dep->trb_pool = NULL;
401 dep->trb_pool_dma = 0;
404 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
407 * dwc3_gadget_start_config - Configure EP resources
408 * @dwc: pointer to our controller context structure
409 * @dep: endpoint that is being enabled
411 * The assignment of transfer resources cannot perfectly follow the
412 * data book due to the fact that the controller driver does not have
413 * all knowledge of the configuration in advance. It is given this
414 * information piecemeal by the composite gadget framework after every
415 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
416 * programming model in this scenario can cause errors. For two
419 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
420 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
421 * multiple interfaces.
423 * 2) The databook does not mention doing more DEPXFERCFG for new
424 * endpoint on alt setting (8.1.6).
426 * The following simplified method is used instead:
428 * All hardware endpoints can be assigned a transfer resource and this
429 * setting will stay persistent until either a core reset or
430 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
431 * do DEPXFERCFG for every hardware endpoint as well. We are
432 * guaranteed that there are as many transfer resources as endpoints.
434 * This function is called for each endpoint when it is being enabled
435 * but is triggered only when called for EP0-out, which always happens
436 * first, and which should only happen in one of the above conditions.
438 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
440 struct dwc3_gadget_ep_cmd_params params;
448 memset(¶ms, 0x00, sizeof(params));
449 cmd = DWC3_DEPCMD_DEPSTARTCFG;
451 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
455 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
456 struct dwc3_ep *dep = dwc->eps[i];
461 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
469 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
470 const struct usb_endpoint_descriptor *desc,
471 const struct usb_ss_ep_comp_descriptor *comp_desc,
472 bool modify, bool restore)
474 struct dwc3_gadget_ep_cmd_params params;
476 if (dev_WARN_ONCE(dwc->dev, modify && restore,
477 "Can't modify and restore\n"))
480 memset(¶ms, 0x00, sizeof(params));
482 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
483 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
485 /* Burst size is only needed in SuperSpeed mode */
486 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
487 u32 burst = dep->endpoint.maxburst;
488 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
492 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
493 } else if (restore) {
494 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
495 params.param2 |= dep->saved_state;
497 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
500 if (usb_endpoint_xfer_control(desc))
501 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
503 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
504 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
506 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
507 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
508 | DWC3_DEPCFG_STREAM_EVENT_EN;
509 dep->stream_capable = true;
512 if (!usb_endpoint_xfer_control(desc))
513 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
516 * We are doing 1:1 mapping for endpoints, meaning
517 * Physical Endpoints 2 maps to Logical Endpoint 2 and
518 * so on. We consider the direction bit as part of the physical
519 * endpoint number. So USB endpoint 0x81 is 0x03.
521 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
524 * We must use the lower 16 TX FIFOs even though
528 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
530 if (desc->bInterval) {
534 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13, and it
535 * must be set to 0 when the controller operates in full-speed.
537 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
538 if (dwc->gadget.speed == USB_SPEED_FULL)
541 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
542 dwc->gadget.speed == USB_SPEED_FULL)
543 dep->interval = desc->bInterval;
545 dep->interval = 1 << (desc->bInterval - 1);
547 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
550 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
553 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
555 struct dwc3_gadget_ep_cmd_params params;
557 memset(¶ms, 0x00, sizeof(params));
559 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
561 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
566 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
567 * @dep: endpoint to be initialized
568 * @desc: USB Endpoint Descriptor
570 * Caller should take care of locking
572 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
573 const struct usb_endpoint_descriptor *desc,
574 const struct usb_ss_ep_comp_descriptor *comp_desc,
575 bool modify, bool restore)
577 struct dwc3 *dwc = dep->dwc;
581 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
583 if (!(dep->flags & DWC3_EP_ENABLED)) {
584 ret = dwc3_gadget_start_config(dwc, dep);
589 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify,
594 if (!(dep->flags & DWC3_EP_ENABLED)) {
595 struct dwc3_trb *trb_st_hw;
596 struct dwc3_trb *trb_link;
598 dep->endpoint.desc = desc;
599 dep->comp_desc = comp_desc;
600 dep->type = usb_endpoint_type(desc);
601 dep->flags |= DWC3_EP_ENABLED;
603 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
604 reg |= DWC3_DALEPENA_EP(dep->number);
605 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
607 if (usb_endpoint_xfer_control(desc))
610 /* Initialize the TRB ring */
611 dep->trb_dequeue = 0;
612 dep->trb_enqueue = 0;
613 memset(dep->trb_pool, 0,
614 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
616 /* Link TRB. The HWO bit is never reset */
617 trb_st_hw = &dep->trb_pool[0];
619 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
620 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
621 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
622 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
623 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
629 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
630 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
632 struct dwc3_request *req;
634 dwc3_stop_active_transfer(dwc, dep->number, true);
636 /* - giveback all requests to gadget driver */
637 while (!list_empty(&dep->started_list)) {
638 req = next_request(&dep->started_list);
640 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
643 while (!list_empty(&dep->pending_list)) {
644 req = next_request(&dep->pending_list);
646 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
651 * __dwc3_gadget_ep_disable - Disables a HW endpoint
652 * @dep: the endpoint to disable
654 * This function also removes requests which are currently processed ny the
655 * hardware and those which are not yet scheduled.
656 * Caller should take care of locking.
658 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
660 struct dwc3 *dwc = dep->dwc;
663 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
665 dwc3_remove_requests(dwc, dep);
667 /* make sure HW endpoint isn't stalled */
668 if (dep->flags & DWC3_EP_STALL)
669 __dwc3_gadget_ep_set_halt(dep, 0, false);
671 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
672 reg &= ~DWC3_DALEPENA_EP(dep->number);
673 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
675 dep->stream_capable = false;
676 dep->endpoint.desc = NULL;
677 dep->comp_desc = NULL;
684 /* -------------------------------------------------------------------------- */
686 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
687 const struct usb_endpoint_descriptor *desc)
692 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
697 /* -------------------------------------------------------------------------- */
699 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
700 const struct usb_endpoint_descriptor *desc)
707 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
708 pr_debug("dwc3: invalid parameters\n");
712 if (!desc->wMaxPacketSize) {
713 pr_debug("dwc3: missing wMaxPacketSize\n");
717 dep = to_dwc3_ep(ep);
720 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
721 "%s is already enabled\n",
725 spin_lock_irqsave(&dwc->lock, flags);
726 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
727 spin_unlock_irqrestore(&dwc->lock, flags);
732 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
740 pr_debug("dwc3: invalid parameters\n");
744 dep = to_dwc3_ep(ep);
747 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
748 "%s is already disabled\n",
752 spin_lock_irqsave(&dwc->lock, flags);
753 ret = __dwc3_gadget_ep_disable(dep);
754 spin_unlock_irqrestore(&dwc->lock, flags);
759 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
762 struct dwc3_request *req;
763 struct dwc3_ep *dep = to_dwc3_ep(ep);
765 req = kzalloc(sizeof(*req), gfp_flags);
769 req->epnum = dep->number;
772 dep->allocated_requests++;
774 trace_dwc3_alloc_request(req);
776 return &req->request;
779 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
780 struct usb_request *request)
782 struct dwc3_request *req = to_dwc3_request(request);
783 struct dwc3_ep *dep = to_dwc3_ep(ep);
785 dep->allocated_requests--;
786 trace_dwc3_free_request(req);
790 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
793 * dwc3_prepare_one_trb - setup one TRB from one request
794 * @dep: endpoint for which this request is prepared
795 * @req: dwc3_request pointer
797 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
798 struct dwc3_request *req, dma_addr_t dma,
799 unsigned length, unsigned chain, unsigned node)
801 struct dwc3_trb *trb;
802 struct dwc3 *dwc = dep->dwc;
803 struct usb_gadget *gadget = &dwc->gadget;
804 enum usb_device_speed speed = gadget->speed;
806 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s",
807 dep->name, req, (unsigned long long) dma,
808 length, chain ? " chain" : "");
810 trb = &dep->trb_pool[dep->trb_enqueue];
813 dwc3_gadget_move_started_request(req);
815 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
816 req->first_trb_index = dep->trb_enqueue;
817 dep->queued_requests++;
820 dwc3_ep_inc_enq(dep);
822 trb->size = DWC3_TRB_SIZE_LENGTH(length);
823 trb->bpl = lower_32_bits(dma);
824 trb->bph = upper_32_bits(dma);
826 switch (usb_endpoint_type(dep->endpoint.desc)) {
827 case USB_ENDPOINT_XFER_CONTROL:
828 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
831 case USB_ENDPOINT_XFER_ISOC:
833 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
836 * USB Specification 2.0 Section 5.9.2 states that: "If
837 * there is only a single transaction in the microframe,
838 * only a DATA0 data packet PID is used. If there are
839 * two transactions per microframe, DATA1 is used for
840 * the first transaction data packet and DATA0 is used
841 * for the second transaction data packet. If there are
842 * three transactions per microframe, DATA2 is used for
843 * the first transaction data packet, DATA1 is used for
844 * the second, and DATA0 is used for the third."
846 * IOW, we should satisfy the following cases:
848 * 1) length <= maxpacket
851 * 2) maxpacket < length <= (2 * maxpacket)
854 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
855 * - DATA2, DATA1, DATA0
857 if (speed == USB_SPEED_HIGH) {
858 struct usb_ep *ep = &dep->endpoint;
859 unsigned int mult = ep->mult - 1;
862 maxp = usb_endpoint_maxp(ep->desc) & 0x07ff;
864 if (length <= (2 * maxp))
870 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
873 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
876 /* always enable Interrupt on Missed ISOC */
877 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
880 case USB_ENDPOINT_XFER_BULK:
881 case USB_ENDPOINT_XFER_INT:
882 trb->ctrl = DWC3_TRBCTL_NORMAL;
886 * This is only possible with faulty memory because we
887 * checked it already :)
892 /* always enable Continue on Short Packet */
893 trb->ctrl |= DWC3_TRB_CTRL_CSP;
895 if ((!req->request.no_interrupt && !chain) ||
896 (dwc3_calc_trbs_left(dep) == 0))
897 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
900 trb->ctrl |= DWC3_TRB_CTRL_CHN;
902 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
903 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
906 * As per data book 4.2.3.2TRB Control Bit Rules section
908 * The controller autonomously checks the HWO field of a TRB to determine if the
909 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
910 * is valid before setting the HWO field to '1'. In most systems, this means that
911 * software must update the fourth DWORD of a TRB last.
913 * However there is a possibility of CPU re-ordering here which can cause
914 * controller to observe the HWO bit set prematurely.
915 * Add a write memory barrier to prevent CPU re-ordering.
918 trb->ctrl |= DWC3_TRB_CTRL_HWO;
920 trace_dwc3_prepare_trb(dep, trb);
924 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
925 * @dep: The endpoint with the TRB ring
926 * @index: The index of the current TRB in the ring
928 * Returns the TRB prior to the one pointed to by the index. If the
929 * index is 0, we will wrap backwards, skip the link TRB, and return
930 * the one just before that.
932 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
937 tmp = DWC3_TRB_NUM - 1;
939 return &dep->trb_pool[tmp - 1];
942 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
947 * If the enqueue & dequeue are equal then the TRB ring is either full
948 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
949 * pending to be processed by the driver.
951 if (dep->trb_enqueue == dep->trb_dequeue) {
953 * If there is any request remained in the started_list at
954 * this point, that means there is no TRB available.
956 if (!list_empty(&dep->started_list))
959 return DWC3_TRB_NUM - 1;
962 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
963 trbs_left &= (DWC3_TRB_NUM - 1);
965 if (dep->trb_dequeue < dep->trb_enqueue)
971 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
972 struct dwc3_request *req)
974 struct scatterlist *sg = req->sg;
975 struct scatterlist *s;
980 for_each_sg(sg, s, req->num_pending_sgs, i) {
981 unsigned chain = true;
983 length = sg_dma_len(s);
984 dma = sg_dma_address(s);
989 dwc3_prepare_one_trb(dep, req, dma, length,
992 if (!dwc3_calc_trbs_left(dep))
997 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
998 struct dwc3_request *req)
1000 unsigned int length;
1003 dma = req->request.dma;
1004 length = req->request.length;
1006 dwc3_prepare_one_trb(dep, req, dma, length,
1011 * dwc3_prepare_trbs - setup TRBs from requests
1012 * @dep: endpoint for which requests are being prepared
1014 * The function goes through the requests list and sets up TRBs for the
1015 * transfers. The function returns once there are no more TRBs available or
1016 * it runs out of requests.
1018 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1020 struct dwc3_request *req, *n;
1022 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1024 if (!dwc3_calc_trbs_left(dep))
1027 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1028 if (req->num_pending_sgs > 0)
1029 dwc3_prepare_one_trb_sg(dep, req);
1031 dwc3_prepare_one_trb_linear(dep, req);
1033 if (!dwc3_calc_trbs_left(dep))
1038 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1040 struct dwc3_gadget_ep_cmd_params params;
1041 struct dwc3_request *req;
1042 struct dwc3 *dwc = dep->dwc;
1047 starting = !(dep->flags & DWC3_EP_BUSY);
1049 dwc3_prepare_trbs(dep);
1050 req = next_request(&dep->started_list);
1052 dep->flags |= DWC3_EP_PENDING_REQUEST;
1056 memset(¶ms, 0, sizeof(params));
1059 params.param0 = upper_32_bits(req->trb_dma);
1060 params.param1 = lower_32_bits(req->trb_dma);
1061 cmd = DWC3_DEPCMD_STARTTRANSFER |
1062 DWC3_DEPCMD_PARAM(cmd_param);
1064 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1065 DWC3_DEPCMD_PARAM(dep->resource_index);
1068 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1071 * FIXME we need to iterate over the list of requests
1072 * here and stop, unmap, free and del each of the linked
1073 * requests instead of what we do now.
1075 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1077 list_del(&req->list);
1081 dep->flags |= DWC3_EP_BUSY;
1084 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1085 WARN_ON_ONCE(!dep->resource_index);
1091 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1092 struct dwc3_ep *dep, u32 cur_uf)
1096 if (list_empty(&dep->pending_list)) {
1097 dwc3_trace(trace_dwc3_gadget,
1098 "ISOC ep %s run out for requests",
1100 dep->flags |= DWC3_EP_PENDING_REQUEST;
1104 /* 4 micro frames in the future */
1105 uf = cur_uf + dep->interval * 4;
1107 __dwc3_gadget_kick_transfer(dep, uf);
1110 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1111 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1115 mask = ~(dep->interval - 1);
1116 cur_uf = event->parameters & mask;
1118 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1121 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1123 struct dwc3 *dwc = dep->dwc;
1126 if (!dep->endpoint.desc) {
1127 dwc3_trace(trace_dwc3_gadget,
1128 "trying to queue request %p to disabled %s",
1129 &req->request, dep->endpoint.name);
1133 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1134 &req->request, req->dep->name)) {
1135 dwc3_trace(trace_dwc3_gadget, "request %pK belongs to '%s'",
1136 &req->request, req->dep->name);
1140 pm_runtime_get(dwc->dev);
1142 req->request.actual = 0;
1143 req->request.status = -EINPROGRESS;
1144 req->direction = dep->direction;
1145 req->epnum = dep->number;
1147 trace_dwc3_ep_queue(req);
1149 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1154 req->sg = req->request.sg;
1155 req->num_pending_sgs = req->request.num_mapped_sgs;
1157 list_add_tail(&req->list, &dep->pending_list);
1160 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1161 * wait for a XferNotReady event so we will know what's the current
1162 * (micro-)frame number.
1164 * Without this trick, we are very, very likely gonna get Bus Expiry
1165 * errors which will force us issue EndTransfer command.
1167 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1168 if ((dep->flags & DWC3_EP_PENDING_REQUEST) &&
1169 list_empty(&dep->started_list)) {
1170 dwc3_stop_active_transfer(dwc, dep->number, true);
1171 dep->flags = DWC3_EP_ENABLED;
1176 if (!dwc3_calc_trbs_left(dep))
1179 ret = __dwc3_gadget_kick_transfer(dep, 0);
1180 if (ret && ret != -EBUSY)
1181 dwc3_trace(trace_dwc3_gadget,
1182 "%s: failed to kick transfers",
1190 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1191 struct usb_request *request)
1193 dwc3_gadget_ep_free_request(ep, request);
1196 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1198 struct dwc3_request *req;
1199 struct usb_request *request;
1200 struct usb_ep *ep = &dep->endpoint;
1202 dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1203 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1207 request->length = 0;
1208 request->buf = dwc->zlp_buf;
1209 request->complete = __dwc3_gadget_ep_zlp_complete;
1211 req = to_dwc3_request(request);
1213 return __dwc3_gadget_ep_queue(dep, req);
1216 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1219 struct dwc3_request *req = to_dwc3_request(request);
1220 struct dwc3_ep *dep = to_dwc3_ep(ep);
1221 struct dwc3 *dwc = dep->dwc;
1223 unsigned long flags;
1227 spin_lock_irqsave(&dwc->lock, flags);
1228 ret = __dwc3_gadget_ep_queue(dep, req);
1231 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1232 * setting request->zero, instead of doing magic, we will just queue an
1233 * extra usb_request ourselves so that it gets handled the same way as
1234 * any other request.
1236 if (ret == 0 && request->zero && request->length &&
1237 (request->length % ep->maxpacket == 0))
1238 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1240 spin_unlock_irqrestore(&dwc->lock, flags);
1245 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1246 struct usb_request *request)
1248 struct dwc3_request *req = to_dwc3_request(request);
1249 struct dwc3_request *r = NULL;
1251 struct dwc3_ep *dep = to_dwc3_ep(ep);
1252 struct dwc3 *dwc = dep->dwc;
1254 unsigned long flags;
1257 trace_dwc3_ep_dequeue(req);
1259 spin_lock_irqsave(&dwc->lock, flags);
1261 list_for_each_entry(r, &dep->pending_list, list) {
1267 list_for_each_entry(r, &dep->started_list, list) {
1272 /* wait until it is processed */
1273 dwc3_stop_active_transfer(dwc, dep->number, true);
1276 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1283 /* giveback the request */
1284 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1287 spin_unlock_irqrestore(&dwc->lock, flags);
1292 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1294 struct dwc3_gadget_ep_cmd_params params;
1295 struct dwc3 *dwc = dep->dwc;
1298 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1299 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1303 memset(¶ms, 0x00, sizeof(params));
1306 struct dwc3_trb *trb;
1308 unsigned transfer_in_flight;
1311 if (dep->number > 1)
1312 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1314 trb = &dwc->ep0_trb[dep->trb_enqueue];
1316 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1317 started = !list_empty(&dep->started_list);
1319 if (!protocol && ((dep->direction && transfer_in_flight) ||
1320 (!dep->direction && started))) {
1321 dwc3_trace(trace_dwc3_gadget,
1322 "%s: pending request, cannot halt",
1327 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1330 dev_err(dwc->dev, "failed to set STALL on %s\n",
1333 dep->flags |= DWC3_EP_STALL;
1336 ret = dwc3_send_clear_stall_ep_cmd(dep);
1338 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1341 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1347 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1349 struct dwc3_ep *dep = to_dwc3_ep(ep);
1350 struct dwc3 *dwc = dep->dwc;
1352 unsigned long flags;
1356 spin_lock_irqsave(&dwc->lock, flags);
1357 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1358 spin_unlock_irqrestore(&dwc->lock, flags);
1363 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1365 struct dwc3_ep *dep = to_dwc3_ep(ep);
1366 struct dwc3 *dwc = dep->dwc;
1367 unsigned long flags;
1370 spin_lock_irqsave(&dwc->lock, flags);
1371 dep->flags |= DWC3_EP_WEDGE;
1373 if (dep->number == 0 || dep->number == 1)
1374 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1376 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1377 spin_unlock_irqrestore(&dwc->lock, flags);
1382 /* -------------------------------------------------------------------------- */
1384 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1385 .bLength = USB_DT_ENDPOINT_SIZE,
1386 .bDescriptorType = USB_DT_ENDPOINT,
1387 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1390 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1391 .enable = dwc3_gadget_ep0_enable,
1392 .disable = dwc3_gadget_ep0_disable,
1393 .alloc_request = dwc3_gadget_ep_alloc_request,
1394 .free_request = dwc3_gadget_ep_free_request,
1395 .queue = dwc3_gadget_ep0_queue,
1396 .dequeue = dwc3_gadget_ep_dequeue,
1397 .set_halt = dwc3_gadget_ep0_set_halt,
1398 .set_wedge = dwc3_gadget_ep_set_wedge,
1401 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1402 .enable = dwc3_gadget_ep_enable,
1403 .disable = dwc3_gadget_ep_disable,
1404 .alloc_request = dwc3_gadget_ep_alloc_request,
1405 .free_request = dwc3_gadget_ep_free_request,
1406 .queue = dwc3_gadget_ep_queue,
1407 .dequeue = dwc3_gadget_ep_dequeue,
1408 .set_halt = dwc3_gadget_ep_set_halt,
1409 .set_wedge = dwc3_gadget_ep_set_wedge,
1412 /* -------------------------------------------------------------------------- */
1414 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1416 struct dwc3 *dwc = gadget_to_dwc(g);
1419 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1420 return DWC3_DSTS_SOFFN(reg);
1423 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1434 * According to the Databook Remote wakeup request should
1435 * be issued only when the device is in early suspend state.
1437 * We can check that via USB Link State bits in DSTS register.
1439 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1441 speed = reg & DWC3_DSTS_CONNECTSPD;
1442 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1443 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
1444 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1448 link_state = DWC3_DSTS_USBLNKST(reg);
1450 switch (link_state) {
1451 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1452 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1455 dwc3_trace(trace_dwc3_gadget,
1456 "can't wakeup from '%s'",
1457 dwc3_gadget_link_string(link_state));
1461 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1463 dev_err(dwc->dev, "failed to put link in Recovery\n");
1467 /* Recent versions do this automatically */
1468 if (dwc->revision < DWC3_REVISION_194A) {
1469 /* write zeroes to Link Change Request */
1470 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1471 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1472 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1475 /* poll until Link State changes to ON */
1479 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1481 /* in HS, means ON */
1482 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1486 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1487 dev_err(dwc->dev, "failed to send remote wakeup\n");
1494 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1496 struct dwc3 *dwc = gadget_to_dwc(g);
1497 unsigned long flags;
1500 spin_lock_irqsave(&dwc->lock, flags);
1501 ret = __dwc3_gadget_wakeup(dwc);
1502 spin_unlock_irqrestore(&dwc->lock, flags);
1507 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1510 struct dwc3 *dwc = gadget_to_dwc(g);
1511 unsigned long flags;
1513 spin_lock_irqsave(&dwc->lock, flags);
1514 g->is_selfpowered = !!is_selfpowered;
1515 spin_unlock_irqrestore(&dwc->lock, flags);
1520 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1525 if (pm_runtime_suspended(dwc->dev))
1528 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1530 if (dwc->revision <= DWC3_REVISION_187A) {
1531 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1532 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1535 if (dwc->revision >= DWC3_REVISION_194A)
1536 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1537 reg |= DWC3_DCTL_RUN_STOP;
1539 if (dwc->has_hibernation)
1540 reg |= DWC3_DCTL_KEEP_CONNECT;
1542 dwc->pullups_connected = true;
1544 reg &= ~DWC3_DCTL_RUN_STOP;
1546 if (dwc->has_hibernation && !suspend)
1547 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1549 dwc->pullups_connected = false;
1552 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1555 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1556 reg &= DWC3_DSTS_DEVCTRLHLT;
1557 } while (--timeout && !(!is_on ^ !reg));
1562 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1564 ? dwc->gadget_driver->function : "no-function",
1565 is_on ? "connect" : "disconnect");
1570 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1572 struct dwc3 *dwc = gadget_to_dwc(g);
1573 unsigned long flags;
1578 spin_lock_irqsave(&dwc->lock, flags);
1579 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1580 spin_unlock_irqrestore(&dwc->lock, flags);
1585 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1589 /* Enable all but Start and End of Frame IRQs */
1590 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1591 DWC3_DEVTEN_EVNTOVERFLOWEN |
1592 DWC3_DEVTEN_CMDCMPLTEN |
1593 DWC3_DEVTEN_ERRTICERREN |
1594 DWC3_DEVTEN_WKUPEVTEN |
1595 DWC3_DEVTEN_ULSTCNGEN |
1596 DWC3_DEVTEN_CONNECTDONEEN |
1597 DWC3_DEVTEN_USBRSTEN |
1598 DWC3_DEVTEN_DISCONNEVTEN);
1600 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1603 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1605 /* mask all interrupts */
1606 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1609 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1610 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1613 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1614 * dwc: pointer to our context structure
1616 * The following looks like complex but it's actually very simple. In order to
1617 * calculate the number of packets we can burst at once on OUT transfers, we're
1618 * gonna use RxFIFO size.
1620 * To calculate RxFIFO size we need two numbers:
1621 * MDWIDTH = size, in bits, of the internal memory bus
1622 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1624 * Given these two numbers, the formula is simple:
1626 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1628 * 24 bytes is for 3x SETUP packets
1629 * 16 bytes is a clock domain crossing tolerance
1631 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1633 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1640 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1641 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1643 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1644 nump = min_t(u32, nump, 16);
1647 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1648 reg &= ~DWC3_DCFG_NUMP_MASK;
1649 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1650 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1653 static int __dwc3_gadget_start(struct dwc3 *dwc)
1655 struct dwc3_ep *dep;
1659 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1660 reg &= ~(DWC3_DCFG_SPEED_MASK);
1663 * WORKAROUND: DWC3 revision < 2.20a have an issue
1664 * which would cause metastability state on Run/Stop
1665 * bit if we try to force the IP to USB2-only mode.
1667 * Because of that, we cannot configure the IP to any
1668 * speed other than the SuperSpeed
1672 * STAR#9000525659: Clock Domain Crossing on DCTL in
1675 if (dwc->revision < DWC3_REVISION_220A) {
1676 reg |= DWC3_DCFG_SUPERSPEED;
1678 switch (dwc->maximum_speed) {
1680 reg |= DWC3_DCFG_LOWSPEED;
1682 case USB_SPEED_FULL:
1683 reg |= DWC3_DCFG_FULLSPEED;
1685 case USB_SPEED_HIGH:
1686 reg |= DWC3_DCFG_HIGHSPEED;
1688 case USB_SPEED_SUPER_PLUS:
1689 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
1692 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1693 dwc->maximum_speed);
1695 case USB_SPEED_SUPER:
1696 reg |= DWC3_DCFG_SUPERSPEED;
1700 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1703 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1704 * field instead of letting dwc3 itself calculate that automatically.
1706 * This way, we maximize the chances that we'll be able to get several
1707 * bursts of data without going through any sort of endpoint throttling.
1709 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1710 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1711 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1713 dwc3_gadget_setup_nump(dwc);
1715 /* Start with SuperSpeed Default */
1716 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1719 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1722 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1727 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1730 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1734 /* begin to receive SETUP packets */
1735 dwc->ep0state = EP0_SETUP_PHASE;
1736 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1737 dwc3_ep0_out_start(dwc);
1739 dwc3_gadget_enable_irq(dwc);
1744 __dwc3_gadget_ep_disable(dwc->eps[0]);
1750 static int dwc3_gadget_start(struct usb_gadget *g,
1751 struct usb_gadget_driver *driver)
1753 struct dwc3 *dwc = gadget_to_dwc(g);
1754 unsigned long flags;
1758 irq = dwc->irq_gadget;
1759 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1760 IRQF_SHARED, "dwc3", dwc->ev_buf);
1762 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1767 spin_lock_irqsave(&dwc->lock, flags);
1768 if (dwc->gadget_driver) {
1769 dev_err(dwc->dev, "%s is already bound to %s\n",
1771 dwc->gadget_driver->driver.name);
1776 dwc->gadget_driver = driver;
1778 if (pm_runtime_active(dwc->dev))
1779 __dwc3_gadget_start(dwc);
1781 spin_unlock_irqrestore(&dwc->lock, flags);
1786 spin_unlock_irqrestore(&dwc->lock, flags);
1793 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1795 if (pm_runtime_suspended(dwc->dev))
1798 dwc3_gadget_disable_irq(dwc);
1799 __dwc3_gadget_ep_disable(dwc->eps[0]);
1800 __dwc3_gadget_ep_disable(dwc->eps[1]);
1803 static int dwc3_gadget_stop(struct usb_gadget *g)
1805 struct dwc3 *dwc = gadget_to_dwc(g);
1806 unsigned long flags;
1808 spin_lock_irqsave(&dwc->lock, flags);
1809 __dwc3_gadget_stop(dwc);
1810 dwc->gadget_driver = NULL;
1811 spin_unlock_irqrestore(&dwc->lock, flags);
1813 free_irq(dwc->irq_gadget, dwc->ev_buf);
1818 static const struct usb_gadget_ops dwc3_gadget_ops = {
1819 .get_frame = dwc3_gadget_get_frame,
1820 .wakeup = dwc3_gadget_wakeup,
1821 .set_selfpowered = dwc3_gadget_set_selfpowered,
1822 .pullup = dwc3_gadget_pullup,
1823 .udc_start = dwc3_gadget_start,
1824 .udc_stop = dwc3_gadget_stop,
1827 /* -------------------------------------------------------------------------- */
1829 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1830 u8 num, u32 direction)
1832 struct dwc3_ep *dep;
1835 for (i = 0; i < num; i++) {
1836 u8 epnum = (i << 1) | (direction ? 1 : 0);
1838 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1843 dep->number = epnum;
1844 dep->direction = !!direction;
1845 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1846 dwc->eps[epnum] = dep;
1848 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1849 (epnum & 1) ? "in" : "out");
1851 dep->endpoint.name = dep->name;
1852 spin_lock_init(&dep->lock);
1854 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1856 if (epnum == 0 || epnum == 1) {
1857 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1858 dep->endpoint.maxburst = 1;
1859 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1861 dwc->gadget.ep0 = &dep->endpoint;
1865 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1866 dep->endpoint.max_streams = 15;
1867 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1868 list_add_tail(&dep->endpoint.ep_list,
1869 &dwc->gadget.ep_list);
1871 ret = dwc3_alloc_trb_pool(dep);
1876 if (epnum == 0 || epnum == 1) {
1877 dep->endpoint.caps.type_control = true;
1879 dep->endpoint.caps.type_iso = true;
1880 dep->endpoint.caps.type_bulk = true;
1881 dep->endpoint.caps.type_int = true;
1884 dep->endpoint.caps.dir_in = !!direction;
1885 dep->endpoint.caps.dir_out = !direction;
1887 INIT_LIST_HEAD(&dep->pending_list);
1888 INIT_LIST_HEAD(&dep->started_list);
1894 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1898 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1900 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1902 dwc3_trace(trace_dwc3_gadget,
1903 "failed to allocate OUT endpoints");
1907 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1909 dwc3_trace(trace_dwc3_gadget,
1910 "failed to allocate IN endpoints");
1917 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1919 struct dwc3_ep *dep;
1922 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1923 dep = dwc->eps[epnum];
1927 * Physical endpoints 0 and 1 are special; they form the
1928 * bi-directional USB endpoint 0.
1930 * For those two physical endpoints, we don't allocate a TRB
1931 * pool nor do we add them the endpoints list. Due to that, we
1932 * shouldn't do these two operations otherwise we would end up
1933 * with all sorts of bugs when removing dwc3.ko.
1935 if (epnum != 0 && epnum != 1) {
1936 dwc3_free_trb_pool(dep);
1937 list_del(&dep->endpoint.ep_list);
1944 /* -------------------------------------------------------------------------- */
1946 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1947 struct dwc3_request *req, struct dwc3_trb *trb,
1948 const struct dwc3_event_depevt *event, int status,
1952 unsigned int s_pkt = 0;
1953 unsigned int trb_status;
1955 dwc3_ep_inc_deq(dep);
1957 if (req->trb == trb)
1958 dep->queued_requests--;
1960 trace_dwc3_complete_trb(dep, trb);
1963 * If we're in the middle of series of chained TRBs and we
1964 * receive a short transfer along the way, DWC3 will skip
1965 * through all TRBs including the last TRB in the chain (the
1966 * where CHN bit is zero. DWC3 will also avoid clearing HWO
1967 * bit and SW has to do it manually.
1969 * We're going to do that here to avoid problems of HW trying
1970 * to use bogus TRBs for transfers.
1972 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
1973 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1975 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1978 count = trb->size & DWC3_TRB_SIZE_MASK;
1979 req->request.actual += count;
1981 if (dep->direction) {
1983 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1984 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1985 dwc3_trace(trace_dwc3_gadget,
1986 "%s: incomplete IN transfer",
1989 * If missed isoc occurred and there is
1990 * no request queued then issue END
1991 * TRANSFER, so that core generates
1992 * next xfernotready and we will issue
1993 * a fresh START TRANSFER.
1994 * If there are still queued request
1995 * then wait, do not issue either END
1996 * or UPDATE TRANSFER, just attach next
1997 * request in pending_list during
1998 * giveback.If any future queued request
1999 * is successfully transferred then we
2000 * will issue UPDATE TRANSFER for all
2001 * request in the pending_list.
2003 dep->flags |= DWC3_EP_MISSED_ISOC;
2005 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2007 status = -ECONNRESET;
2010 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2013 if (count && (event->status & DEPEVT_STATUS_SHORT))
2017 if (s_pkt && !chain)
2020 if ((event->status & DEPEVT_STATUS_IOC) &&
2021 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2027 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2028 const struct dwc3_event_depevt *event, int status)
2030 struct dwc3_request *req, *n;
2031 struct dwc3_trb *trb;
2035 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2040 length = req->request.length;
2041 chain = req->num_pending_sgs > 0;
2043 struct scatterlist *sg = req->sg;
2044 struct scatterlist *s;
2045 unsigned int pending = req->num_pending_sgs;
2048 for_each_sg(sg, s, pending, i) {
2049 trb = &dep->trb_pool[dep->trb_dequeue];
2051 req->sg = sg_next(s);
2052 req->num_pending_sgs--;
2054 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2055 event, status, chain);
2060 trb = &dep->trb_pool[dep->trb_dequeue];
2061 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2062 event, status, chain);
2066 * We assume here we will always receive the entire data block
2067 * which we should receive. Meaning, if we program RX to
2068 * receive 4K but we receive only 2K, we assume that's all we
2069 * should receive and we simply bounce the request back to the
2070 * gadget driver for further processing.
2072 actual = length - req->request.actual;
2073 req->request.actual = actual;
2075 if (ret && chain && (actual < length) && req->num_pending_sgs)
2076 return __dwc3_gadget_kick_transfer(dep, 0);
2078 dwc3_gadget_giveback(dep, req, status);
2081 if ((event->status & DEPEVT_STATUS_IOC) &&
2082 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2089 * Our endpoint might get disabled by another thread during
2090 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2091 * early on so DWC3_EP_BUSY flag gets cleared
2093 if (!dep->endpoint.desc)
2096 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2097 list_empty(&dep->started_list)) {
2098 if (list_empty(&dep->pending_list)) {
2100 * If there is no entry in request list then do
2101 * not issue END TRANSFER now. Just set PENDING
2102 * flag, so that END TRANSFER is issued when an
2103 * entry is added into request list.
2105 dep->flags = DWC3_EP_PENDING_REQUEST;
2107 dwc3_stop_active_transfer(dwc, dep->number, true);
2108 dep->flags = DWC3_EP_ENABLED;
2113 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2119 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2120 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2122 unsigned status = 0;
2124 u32 is_xfer_complete;
2126 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2128 if (event->status & DEPEVT_STATUS_BUSERR)
2129 status = -ECONNRESET;
2131 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2132 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2133 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2134 dep->flags &= ~DWC3_EP_BUSY;
2137 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2138 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2140 if (dwc->revision < DWC3_REVISION_183A) {
2144 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2147 if (!(dep->flags & DWC3_EP_ENABLED))
2150 if (!list_empty(&dep->started_list))
2154 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2156 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2162 * Our endpoint might get disabled by another thread during
2163 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2164 * early on so DWC3_EP_BUSY flag gets cleared
2166 if (!dep->endpoint.desc)
2169 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2172 ret = __dwc3_gadget_kick_transfer(dep, 0);
2173 if (!ret || ret == -EBUSY)
2178 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2179 const struct dwc3_event_depevt *event)
2181 struct dwc3_ep *dep;
2182 u8 epnum = event->endpoint_number;
2184 dep = dwc->eps[epnum];
2186 if (!(dep->flags & DWC3_EP_ENABLED))
2189 if (epnum == 0 || epnum == 1) {
2190 dwc3_ep0_interrupt(dwc, event);
2194 switch (event->endpoint_event) {
2195 case DWC3_DEPEVT_XFERCOMPLETE:
2196 dep->resource_index = 0;
2198 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2199 dwc3_trace(trace_dwc3_gadget,
2200 "%s is an Isochronous endpoint",
2205 dwc3_endpoint_transfer_complete(dwc, dep, event);
2207 case DWC3_DEPEVT_XFERINPROGRESS:
2208 dwc3_endpoint_transfer_complete(dwc, dep, event);
2210 case DWC3_DEPEVT_XFERNOTREADY:
2211 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2212 dwc3_gadget_start_isoc(dwc, dep, event);
2217 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2219 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2220 dep->name, active ? "Transfer Active"
2221 : "Transfer Not Active");
2223 ret = __dwc3_gadget_kick_transfer(dep, 0);
2224 if (!ret || ret == -EBUSY)
2227 dwc3_trace(trace_dwc3_gadget,
2228 "%s: failed to kick transfers",
2233 case DWC3_DEPEVT_STREAMEVT:
2234 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2235 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2240 switch (event->status) {
2241 case DEPEVT_STREAMEVT_FOUND:
2242 dwc3_trace(trace_dwc3_gadget,
2243 "Stream %d found and started",
2247 case DEPEVT_STREAMEVT_NOTFOUND:
2250 dwc3_trace(trace_dwc3_gadget,
2251 "unable to find suitable stream");
2254 case DWC3_DEPEVT_RXTXFIFOEVT:
2255 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2257 case DWC3_DEPEVT_EPCMDCMPLT:
2258 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2263 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2265 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2266 spin_unlock(&dwc->lock);
2267 dwc->gadget_driver->disconnect(&dwc->gadget);
2268 spin_lock(&dwc->lock);
2272 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2274 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2275 spin_unlock(&dwc->lock);
2276 dwc->gadget_driver->suspend(&dwc->gadget);
2277 spin_lock(&dwc->lock);
2281 static void dwc3_resume_gadget(struct dwc3 *dwc)
2283 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2284 spin_unlock(&dwc->lock);
2285 dwc->gadget_driver->resume(&dwc->gadget);
2286 spin_lock(&dwc->lock);
2290 static void dwc3_reset_gadget(struct dwc3 *dwc)
2292 if (!dwc->gadget_driver)
2295 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2296 spin_unlock(&dwc->lock);
2297 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2298 spin_lock(&dwc->lock);
2302 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2304 struct dwc3_ep *dep;
2305 struct dwc3_gadget_ep_cmd_params params;
2309 dep = dwc->eps[epnum];
2311 if (!dep->resource_index)
2315 * NOTICE: We are violating what the Databook says about the
2316 * EndTransfer command. Ideally we would _always_ wait for the
2317 * EndTransfer Command Completion IRQ, but that's causing too
2318 * much trouble synchronizing between us and gadget driver.
2320 * We have discussed this with the IP Provider and it was
2321 * suggested to giveback all requests here, but give HW some
2322 * extra time to synchronize with the interconnect. We're using
2323 * an arbitrary 100us delay for that.
2325 * Note also that a similar handling was tested by Synopsys
2326 * (thanks a lot Paul) and nothing bad has come out of it.
2327 * In short, what we're doing is:
2329 * - Issue EndTransfer WITH CMDIOC bit set
2332 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2333 * supports a mode to work around the above limitation. The
2334 * software can poll the CMDACT bit in the DEPCMD register
2335 * after issuing a EndTransfer command. This mode is enabled
2336 * by writing GUCTL2[14]. This polling is already done in the
2337 * dwc3_send_gadget_ep_cmd() function so if the mode is
2338 * enabled, the EndTransfer command will have completed upon
2339 * returning from this function and we don't need to delay for
2342 * This mode is NOT available on the DWC_usb31 IP.
2345 cmd = DWC3_DEPCMD_ENDTRANSFER;
2346 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2347 cmd |= DWC3_DEPCMD_CMDIOC;
2348 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2349 memset(¶ms, 0, sizeof(params));
2350 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2352 dep->resource_index = 0;
2353 dep->flags &= ~DWC3_EP_BUSY;
2355 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2359 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2363 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2364 struct dwc3_ep *dep;
2366 dep = dwc->eps[epnum];
2370 if (!(dep->flags & DWC3_EP_ENABLED))
2373 dwc3_remove_requests(dwc, dep);
2377 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2381 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2382 struct dwc3_ep *dep;
2385 dep = dwc->eps[epnum];
2389 if (!(dep->flags & DWC3_EP_STALL))
2392 dep->flags &= ~DWC3_EP_STALL;
2394 ret = dwc3_send_clear_stall_ep_cmd(dep);
2399 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2403 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2404 reg &= ~DWC3_DCTL_INITU1ENA;
2405 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2407 reg &= ~DWC3_DCTL_INITU2ENA;
2408 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2410 dwc3_disconnect_gadget(dwc);
2412 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2413 dwc->setup_packet_pending = false;
2414 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2416 dwc->connected = false;
2419 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2423 dwc->connected = true;
2426 * Ideally, dwc3_reset_gadget() would trigger the function
2427 * drivers to stop any active transfers through ep disable.
2428 * However, for functions which defer ep disable, such as mass
2429 * storage, we will need to rely on the call to stop active
2430 * transfers here, and avoid allowing of request queuing.
2432 dwc->connected = false;
2435 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2436 * would cause a missing Disconnect Event if there's a
2437 * pending Setup Packet in the FIFO.
2439 * There's no suggested workaround on the official Bug
2440 * report, which states that "unless the driver/application
2441 * is doing any special handling of a disconnect event,
2442 * there is no functional issue".
2444 * Unfortunately, it turns out that we _do_ some special
2445 * handling of a disconnect event, namely complete all
2446 * pending transfers, notify gadget driver of the
2447 * disconnection, and so on.
2449 * Our suggested workaround is to follow the Disconnect
2450 * Event steps here, instead, based on a setup_packet_pending
2451 * flag. Such flag gets set whenever we have a SETUP_PENDING
2452 * status for EP0 TRBs and gets cleared on XferComplete for the
2457 * STAR#9000466709: RTL: Device : Disconnect event not
2458 * generated if setup packet pending in FIFO
2460 if (dwc->revision < DWC3_REVISION_188A) {
2461 if (dwc->setup_packet_pending)
2462 dwc3_gadget_disconnect_interrupt(dwc);
2465 dwc3_reset_gadget(dwc);
2467 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2468 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2469 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2470 dwc->test_mode = false;
2472 dwc3_stop_active_transfers(dwc);
2473 dwc3_clear_stall_all_ep(dwc);
2475 /* Reset device address to zero */
2476 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2477 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2478 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2481 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2484 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2487 * We change the clock only at SS but I dunno why I would want to do
2488 * this. Maybe it becomes part of the power saving plan.
2491 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2492 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
2496 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2497 * each time on Connect Done.
2502 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2503 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2504 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2507 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2509 struct dwc3_ep *dep;
2514 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2515 speed = reg & DWC3_DSTS_CONNECTSPD;
2518 dwc3_update_ram_clk_sel(dwc, speed);
2521 case DWC3_DSTS_SUPERSPEED_PLUS:
2522 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2523 dwc->gadget.ep0->maxpacket = 512;
2524 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2526 case DWC3_DSTS_SUPERSPEED:
2528 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2529 * would cause a missing USB3 Reset event.
2531 * In such situations, we should force a USB3 Reset
2532 * event by calling our dwc3_gadget_reset_interrupt()
2537 * STAR#9000483510: RTL: SS : USB3 reset event may
2538 * not be generated always when the link enters poll
2540 if (dwc->revision < DWC3_REVISION_190A)
2541 dwc3_gadget_reset_interrupt(dwc);
2543 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2544 dwc->gadget.ep0->maxpacket = 512;
2545 dwc->gadget.speed = USB_SPEED_SUPER;
2547 case DWC3_DSTS_HIGHSPEED:
2548 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2549 dwc->gadget.ep0->maxpacket = 64;
2550 dwc->gadget.speed = USB_SPEED_HIGH;
2552 case DWC3_DSTS_FULLSPEED:
2553 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2554 dwc->gadget.ep0->maxpacket = 64;
2555 dwc->gadget.speed = USB_SPEED_FULL;
2557 case DWC3_DSTS_LOWSPEED:
2558 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2559 dwc->gadget.ep0->maxpacket = 8;
2560 dwc->gadget.speed = USB_SPEED_LOW;
2564 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2566 /* Enable USB2 LPM Capability */
2568 if ((dwc->revision > DWC3_REVISION_194A) &&
2569 (speed != DWC3_DSTS_SUPERSPEED) &&
2570 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2571 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2572 reg |= DWC3_DCFG_LPM_CAP;
2573 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2575 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2576 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2578 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2581 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2582 * DCFG.LPMCap is set, core responses with an ACK and the
2583 * BESL value in the LPM token is less than or equal to LPM
2586 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2587 && dwc->has_lpm_erratum,
2588 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2590 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2591 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2593 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2595 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2596 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2597 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2601 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2604 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2609 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2612 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2617 * Configure PHY via GUSB3PIPECTLn if required.
2619 * Update GTXFIFOSIZn
2621 * In both cases reset values should be sufficient.
2625 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2628 * TODO take core out of low power mode when that's
2632 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2633 spin_unlock(&dwc->lock);
2634 dwc->gadget_driver->resume(&dwc->gadget);
2635 spin_lock(&dwc->lock);
2639 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2640 unsigned int evtinfo)
2642 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2643 unsigned int pwropt;
2646 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2647 * Hibernation mode enabled which would show up when device detects
2648 * host-initiated U3 exit.
2650 * In that case, device will generate a Link State Change Interrupt
2651 * from U3 to RESUME which is only necessary if Hibernation is
2654 * There are no functional changes due to such spurious event and we
2655 * just need to ignore it.
2659 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2662 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2663 if ((dwc->revision < DWC3_REVISION_250A) &&
2664 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2665 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2666 (next == DWC3_LINK_STATE_RESUME)) {
2667 dwc3_trace(trace_dwc3_gadget,
2668 "ignoring transition U3 -> Resume");
2674 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2675 * on the link partner, the USB session might do multiple entry/exit
2676 * of low power states before a transfer takes place.
2678 * Due to this problem, we might experience lower throughput. The
2679 * suggested workaround is to disable DCTL[12:9] bits if we're
2680 * transitioning from U1/U2 to U0 and enable those bits again
2681 * after a transfer completes and there are no pending transfers
2682 * on any of the enabled endpoints.
2684 * This is the first half of that workaround.
2688 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2689 * core send LGO_Ux entering U0
2691 if (dwc->revision < DWC3_REVISION_183A) {
2692 if (next == DWC3_LINK_STATE_U0) {
2696 switch (dwc->link_state) {
2697 case DWC3_LINK_STATE_U1:
2698 case DWC3_LINK_STATE_U2:
2699 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2700 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2701 | DWC3_DCTL_ACCEPTU2ENA
2702 | DWC3_DCTL_INITU1ENA
2703 | DWC3_DCTL_ACCEPTU1ENA);
2706 dwc->u1u2 = reg & u1u2;
2710 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2720 case DWC3_LINK_STATE_U1:
2721 if (dwc->speed == USB_SPEED_SUPER)
2722 dwc3_suspend_gadget(dwc);
2724 case DWC3_LINK_STATE_U2:
2725 case DWC3_LINK_STATE_U3:
2726 dwc3_suspend_gadget(dwc);
2728 case DWC3_LINK_STATE_RESUME:
2729 dwc3_resume_gadget(dwc);
2736 dwc->link_state = next;
2739 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2740 unsigned int evtinfo)
2742 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2744 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2745 dwc3_suspend_gadget(dwc);
2747 dwc->link_state = next;
2750 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2751 unsigned int evtinfo)
2753 unsigned int is_ss = evtinfo & BIT(4);
2756 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2757 * have a known issue which can cause USB CV TD.9.23 to fail
2760 * Because of this issue, core could generate bogus hibernation
2761 * events which SW needs to ignore.
2765 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2766 * Device Fallback from SuperSpeed
2768 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2771 /* enter hibernation here */
2774 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2775 const struct dwc3_event_devt *event)
2777 switch (event->type) {
2778 case DWC3_DEVICE_EVENT_DISCONNECT:
2779 dwc3_gadget_disconnect_interrupt(dwc);
2781 case DWC3_DEVICE_EVENT_RESET:
2782 dwc3_gadget_reset_interrupt(dwc);
2784 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2785 dwc3_gadget_conndone_interrupt(dwc);
2787 case DWC3_DEVICE_EVENT_WAKEUP:
2788 dwc3_gadget_wakeup_interrupt(dwc);
2790 case DWC3_DEVICE_EVENT_HIBER_REQ:
2791 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2792 "unexpected hibernation event\n"))
2795 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2797 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2798 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2800 case DWC3_DEVICE_EVENT_EOPF:
2801 /* It changed to be suspend event for version 2.30a and above */
2802 if (dwc->revision < DWC3_REVISION_230A) {
2803 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2805 dwc3_trace(trace_dwc3_gadget, "U3/L1-L2 Suspend Event");
2808 * Ignore suspend event until the gadget enters into
2809 * USB_STATE_CONFIGURED state.
2811 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2812 dwc3_gadget_suspend_interrupt(dwc,
2816 case DWC3_DEVICE_EVENT_SOF:
2817 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2819 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2820 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2822 case DWC3_DEVICE_EVENT_CMD_CMPL:
2823 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2825 case DWC3_DEVICE_EVENT_OVERFLOW:
2826 dwc3_trace(trace_dwc3_gadget, "Overflow");
2829 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2833 static void dwc3_process_event_entry(struct dwc3 *dwc,
2834 const union dwc3_event *event)
2836 trace_dwc3_event(event->raw);
2838 /* Endpoint IRQ, handle it and return early */
2839 if (event->type.is_devspec == 0) {
2841 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2844 switch (event->type.type) {
2845 case DWC3_EVENT_TYPE_DEV:
2846 dwc3_gadget_interrupt(dwc, &event->devt);
2848 /* REVISIT what to do with Carkit and I2C events ? */
2850 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2854 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2856 struct dwc3 *dwc = evt->dwc;
2857 irqreturn_t ret = IRQ_NONE;
2863 if (!(evt->flags & DWC3_EVENT_PENDING))
2867 union dwc3_event event;
2869 event.raw = *(u32 *) (evt->buf + evt->lpos);
2871 dwc3_process_event_entry(dwc, &event);
2874 * FIXME we wrap around correctly to the next entry as
2875 * almost all entries are 4 bytes in size. There is one
2876 * entry which has 12 bytes which is a regular entry
2877 * followed by 8 bytes data. ATM I don't know how
2878 * things are organized if we get next to the a
2879 * boundary so I worry about that once we try to handle
2882 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2885 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2891 /* Unmask interrupt */
2892 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2893 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2894 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2896 /* Keep the clearing of DWC3_EVENT_PENDING at the end */
2897 evt->flags &= ~DWC3_EVENT_PENDING;
2902 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2904 struct dwc3_event_buffer *evt = _evt;
2905 struct dwc3 *dwc = evt->dwc;
2906 unsigned long flags;
2907 irqreturn_t ret = IRQ_NONE;
2910 spin_lock_irqsave(&dwc->lock, flags);
2911 ret = dwc3_process_event_buf(evt);
2912 spin_unlock_irqrestore(&dwc->lock, flags);
2918 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2920 struct dwc3 *dwc = evt->dwc;
2924 if (pm_runtime_suspended(dwc->dev)) {
2925 pm_runtime_get(dwc->dev);
2926 disable_irq_nosync(dwc->irq_gadget);
2927 dwc->pending_events = true;
2932 * With PCIe legacy interrupt, test shows that top-half irq handler can
2933 * be called again after HW interrupt deassertion. Check if bottom-half
2934 * irq event handler completes before caching new event to prevent
2937 if (evt->flags & DWC3_EVENT_PENDING)
2940 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2941 count &= DWC3_GEVNTCOUNT_MASK;
2946 evt->flags |= DWC3_EVENT_PENDING;
2948 /* Mask interrupt */
2949 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2950 reg |= DWC3_GEVNTSIZ_INTMASK;
2951 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2953 return IRQ_WAKE_THREAD;
2956 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2958 struct dwc3_event_buffer *evt = _evt;
2960 return dwc3_check_event_buf(evt);
2964 * dwc3_gadget_init - Initializes gadget related registers
2965 * @dwc: pointer to our controller context structure
2967 * Returns 0 on success otherwise negative errno.
2969 int dwc3_gadget_init(struct dwc3 *dwc)
2972 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
2974 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
2975 if (irq == -EPROBE_DEFER)
2979 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
2980 if (irq == -EPROBE_DEFER)
2984 irq = platform_get_irq(dwc3_pdev, 0);
2986 if (irq != -EPROBE_DEFER) {
2988 "missing peripheral IRQ\n");
2997 dwc->irq_gadget = irq;
2999 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3000 &dwc->ctrl_req_addr, GFP_KERNEL);
3001 if (!dwc->ctrl_req) {
3002 dev_err(dwc->dev, "failed to allocate ctrl request\n");
3007 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3008 &dwc->ep0_trb_addr, GFP_KERNEL);
3009 if (!dwc->ep0_trb) {
3010 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3015 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
3016 if (!dwc->setup_buf) {
3021 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3022 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
3024 if (!dwc->ep0_bounce) {
3025 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
3030 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
3031 if (!dwc->zlp_buf) {
3036 dwc->gadget.ops = &dwc3_gadget_ops;
3037 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3038 dwc->gadget.sg_supported = true;
3039 dwc->gadget.name = "dwc3-gadget";
3042 * FIXME We might be setting max_speed to <SUPER, however versions
3043 * <2.20a of dwc3 have an issue with metastability (documented
3044 * elsewhere in this driver) which tells us we can't set max speed to
3045 * anything lower than SUPER.
3047 * Because gadget.max_speed is only used by composite.c and function
3048 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3049 * to happen so we avoid sending SuperSpeed Capability descriptor
3050 * together with our BOS descriptor as that could confuse host into
3051 * thinking we can handle super speed.
3053 * Note that, in fact, we won't even support GetBOS requests when speed
3054 * is less than super speed because we don't have means, yet, to tell
3055 * composite.c that we are USB 2.0 + LPM ECN.
3057 if (dwc->revision < DWC3_REVISION_220A)
3058 dwc3_trace(trace_dwc3_gadget,
3059 "Changing max_speed on rev %08x",
3062 dwc->gadget.max_speed = dwc->maximum_speed;
3065 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3068 dwc->gadget.quirk_ep_out_aligned_size = true;
3071 * REVISIT: Here we should clear all pending IRQs to be
3072 * sure we're starting from a well known location.
3075 ret = dwc3_gadget_init_endpoints(dwc);
3079 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3081 dev_err(dwc->dev, "failed to register udc\n");
3088 kfree(dwc->zlp_buf);
3091 dwc3_gadget_free_endpoints(dwc);
3092 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3093 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3096 kfree(dwc->setup_buf);
3099 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3100 dwc->ep0_trb, dwc->ep0_trb_addr);
3103 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3104 dwc->ctrl_req, dwc->ctrl_req_addr);
3110 /* -------------------------------------------------------------------------- */
3112 void dwc3_gadget_exit(struct dwc3 *dwc)
3114 usb_del_gadget_udc(&dwc->gadget);
3116 dwc3_gadget_free_endpoints(dwc);
3118 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3119 dwc->ep0_bounce, dwc->ep0_bounce_addr);
3121 kfree(dwc->setup_buf);
3122 kfree(dwc->zlp_buf);
3124 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
3125 dwc->ep0_trb, dwc->ep0_trb_addr);
3127 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3128 dwc->ctrl_req, dwc->ctrl_req_addr);
3131 int dwc3_gadget_suspend(struct dwc3 *dwc)
3133 if (!dwc->gadget_driver)
3136 dwc3_gadget_run_stop(dwc, false, false);
3137 dwc3_disconnect_gadget(dwc);
3138 __dwc3_gadget_stop(dwc);
3140 synchronize_irq(dwc->irq_gadget);
3145 int dwc3_gadget_resume(struct dwc3 *dwc)
3149 if (!dwc->gadget_driver)
3152 ret = __dwc3_gadget_start(dwc);
3156 ret = dwc3_gadget_run_stop(dwc, true, false);
3163 __dwc3_gadget_stop(dwc);
3169 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3171 if (dwc->pending_events) {
3172 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3173 dwc->pending_events = false;
3174 enable_irq(dwc->irq_gadget);