drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/list.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #include <linux/usb/ch9.h>
  23 #include <linux/usb/gadget.h>
  24
  25 #include "debug.h"
  26 #include "core.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 #define DWC3_ALIGN_FRAME(d, n)  (((d)->frame_number + ((d)->interval * (n))) \
  31                                         & ~((d)->interval - 1))
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - enables usb2 test modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will return 0 on
  39  * success or -EINVAL if wrong Test Selector is passed.
  40  */
  41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  42 {
  43         u32             reg;
  44
  45         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  46         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  47
  48         switch (mode) {
  49         case USB_TEST_J:
  50         case USB_TEST_K:
  51         case USB_TEST_SE0_NAK:
  52         case USB_TEST_PACKET:
  53         case USB_TEST_FORCE_ENABLE:
  54                 reg |= mode << 1;
  55                 break;
  56         default:
  57                 return -EINVAL;
  58         }
  59
  60         dwc3_gadget_dctl_write_safe(dwc, reg);
  61
  62         return 0;
  63 }
  64
  65 /**
  66  * dwc3_gadget_get_link_state - gets current state of usb link
  67  * @dwc: pointer to our context structure
  68  *
  69  * Caller should take care of locking. This function will
  70  * return the link state on success (>= 0) or -ETIMEDOUT.
  71  */
  72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  73 {
  74         u32             reg;
  75
  76         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  77
  78         return DWC3_DSTS_USBLNKST(reg);
  79 }
  80
  81 /**
  82  * dwc3_gadget_set_link_state - sets usb link to a particular state
  83  * @dwc: pointer to our context structure
  84  * @state: the state to put link into
  85  *
  86  * Caller should take care of locking. This function will
  87  * return 0 on success or -ETIMEDOUT.
  88  */
  89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  90 {
  91         int             retries = 10000;
  92         u32             reg;
  93
  94         /*
  95          * Wait until device controller is ready. Only applies to 1.94a and
  96          * later RTL.
  97          */
  98         if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
  99                 while (--retries) {
 100                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 101                         if (reg & DWC3_DSTS_DCNRD)
 102                                 udelay(5);
 103                         else
 104                                 break;
 105                 }
 106
 107                 if (retries <= 0)
 108                         return -ETIMEDOUT;
 109         }
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 113
 114         /* set no action before sending new link state change */
 115         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 116
 117         /* set requested state */
 118         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 119         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 120
 121         /*
 122          * The following code is racy when called from dwc3_gadget_wakeup,
 123          * and is not needed, at least on newer versions
 124          */
 125         if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
 126                 return 0;
 127
 128         /* wait for a change in DSTS */
 129         retries = 10000;
 130         while (--retries) {
 131                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 132
 133                 if (DWC3_DSTS_USBLNKST(reg) == state)
 134                         return 0;
 135
 136                 udelay(5);
 137         }
 138
 139         return -ETIMEDOUT;
 140 }
 141
 142 /**
 143  * dwc3_ep_inc_trb - increment a trb index.
 144  * @index: Pointer to the TRB index to increment.
 145  *
 146  * The index should never point to the link TRB. After incrementing,
 147  * if it is point to the link TRB, wrap around to the beginning. The
 148  * link TRB is always at the last TRB entry.
 149  */
 150 static void dwc3_ep_inc_trb(u8 *index)
 151 {
 152         (*index)++;
 153         if (*index == (DWC3_TRB_NUM - 1))
 154                 *index = 0;
 155 }
 156
 157 /**
 158  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
 159  * @dep: The endpoint whose enqueue pointer we're incrementing
 160  */
 161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 162 {
 163         dwc3_ep_inc_trb(&dep->trb_enqueue);
 164 }
 165
 166 /**
 167  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
 168  * @dep: The endpoint whose enqueue pointer we're incrementing
 169  */
 170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 171 {
 172         dwc3_ep_inc_trb(&dep->trb_dequeue);
 173 }
 174
 175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
 176                 struct dwc3_request *req, int status)
 177 {
 178         struct dwc3                     *dwc = dep->dwc;
 179
 180         list_del(&req->list);
 181         req->remaining = 0;
 182         req->needs_extra_trb = false;
 183
 184         if (req->request.status == -EINPROGRESS)
 185                 req->request.status = status;
 186
 187         if (req->trb)
 188                 usb_gadget_unmap_request_by_dev(dwc->sysdev,
 189                                 &req->request, req->direction);
 190
 191         req->trb = NULL;
 192         trace_dwc3_gadget_giveback(req);
 193
 194         if (dep->number > 1)
 195                 pm_runtime_put(dwc->dev);
 196 }
 197
 198 /**
 199  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
 200  * @dep: The endpoint to whom the request belongs to
 201  * @req: The request we're giving back
 202  * @status: completion code for the request
 203  *
 204  * Must be called with controller's lock held and interrupts disabled. This
 205  * function will unmap @req and call its ->complete() callback to notify upper
 206  * layers that it has completed.
 207  */
 208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 209                 int status)
 210 {
 211         struct dwc3                     *dwc = dep->dwc;
 212
 213         dwc3_gadget_del_and_unmap_request(dep, req, status);
 214         req->status = DWC3_REQUEST_STATUS_COMPLETED;
 215
 216         spin_unlock(&dwc->lock);
 217         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 218         spin_lock(&dwc->lock);
 219 }
 220
 221 /**
 222  * dwc3_send_gadget_generic_command - issue a generic command for the controller
 223  * @dwc: pointer to the controller context
 224  * @cmd: the command to be issued
 225  * @param: command parameter
 226  *
 227  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
 228  * and wait for its completion.
 229  */
 230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
 231                 u32 param)
 232 {
 233         u32             timeout = 500;
 234         int             status = 0;
 235         int             ret = 0;
 236         u32             reg;
 237
 238         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 239         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 240
 241         do {
 242                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 243                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 244                         status = DWC3_DGCMD_STATUS(reg);
 245                         if (status)
 246                                 ret = -EINVAL;
 247                         break;
 248                 }
 249         } while (--timeout);
 250
 251         if (!timeout) {
 252                 ret = -ETIMEDOUT;
 253                 status = -ETIMEDOUT;
 254         }
 255
 256         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 257
 258         return ret;
 259 }
 260
 261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 262
 263 /**
 264  * dwc3_send_gadget_ep_cmd - issue an endpoint command
 265  * @dep: the endpoint to which the command is going to be issued
 266  * @cmd: the command to be issued
 267  * @params: parameters to the command
 268  *
 269  * Caller should handle locking. This function will issue @cmd with given
 270  * @params to @dep and wait for its completion.
 271  */
 272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
 273                 struct dwc3_gadget_ep_cmd_params *params)
 274 {
 275         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 276         struct dwc3             *dwc = dep->dwc;
 277         u32                     timeout = 5000;
 278         u32                     saved_config = 0;
 279         u32                     reg;
 280
 281         int                     cmd_status = 0;
 282         int                     ret = -EINVAL;
 283
 284         /*
 285          * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
 286          * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
 287          * endpoint command.
 288          *
 289          * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
 290          * settings. Restore them after the command is completed.
 291          *
 292          * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
 293          */
 294         if (dwc->gadget->speed <= USB_SPEED_HIGH ||
 295             DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
 296                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 297                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 298                         saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
 299                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 300                 }
 301
 302                 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
 303                         saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 304                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 305                 }
 306
 307                 if (saved_config)
 308                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 309         }
 310
 311         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 312                 int link_state;
 313
 314                 /*
 315                  * Initiate remote wakeup if the link state is in U3 when
 316                  * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
 317                  * link state is in U1/U2, no remote wakeup is needed. The Start
 318                  * Transfer command will initiate the link recovery.
 319                  */
 320                 link_state = dwc3_gadget_get_link_state(dwc);
 321                 switch (link_state) {
 322                 case DWC3_LINK_STATE_U2:
 323                         if (dwc->gadget->speed >= USB_SPEED_SUPER)
 324                                 break;
 325
 326                         fallthrough;
 327                 case DWC3_LINK_STATE_U3:
 328                         ret = __dwc3_gadget_wakeup(dwc);
 329                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 330                                         ret);
 331                         break;
 332                 }
 333         }
 334
 335         /*
 336          * For some commands such as Update Transfer command, DEPCMDPARn
 337          * registers are reserved. Since the driver often sends Update Transfer
 338          * command, don't write to DEPCMDPARn to avoid register write delays and
 339          * improve performance.
 340          */
 341         if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
 342                 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 343                 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 344                 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 345         }
 346
 347         /*
 348          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 349          * not relying on XferNotReady, we can make use of a special "No
 350          * Response Update Transfer" command where we should clear both CmdAct
 351          * and CmdIOC bits.
 352          *
 353          * With this, we don't need to wait for command completion and can
 354          * straight away issue further commands to the endpoint.
 355          *
 356          * NOTICE: We're making an assumption that control endpoints will never
 357          * make use of Update Transfer command. This is a safe assumption
 358          * because we can never have more than one request at a time with
 359          * Control Endpoints. If anybody changes that assumption, this chunk
 360          * needs to be updated accordingly.
 361          */
 362         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 363                         !usb_endpoint_xfer_isoc(desc))
 364                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 365         else
 366                 cmd |= DWC3_DEPCMD_CMDACT;
 367
 368         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 369
 370         if (!(cmd & DWC3_DEPCMD_CMDACT) ||
 371                 (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
 372                 !(cmd & DWC3_DEPCMD_CMDIOC))) {
 373                 ret = 0;
 374                 goto skip_status;
 375         }
 376
 377         do {
 378                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 379                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 380                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 381
 382                         switch (cmd_status) {
 383                         case 0:
 384                                 ret = 0;
 385                                 break;
 386                         case DEPEVT_TRANSFER_NO_RESOURCE:
 387                                 dev_WARN(dwc->dev, "No resource for %s\n",
 388                                          dep->name);
 389                                 ret = -EINVAL;
 390                                 break;
 391                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 392                                 /*
 393                                  * SW issues START TRANSFER command to
 394                                  * isochronous ep with future frame interval. If
 395                                  * future interval time has already passed when
 396                                  * core receives the command, it will respond
 397                                  * with an error status of 'Bus Expiry'.
 398                                  *
 399                                  * Instead of always returning -EINVAL, let's
 400                                  * give a hint to the gadget driver that this is
 401                                  * the case by returning -EAGAIN.
 402                                  */
 403                                 ret = -EAGAIN;
 404                                 break;
 405                         default:
 406                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 407                         }
 408
 409                         break;
 410                 }
 411         } while (--timeout);
 412
 413         if (timeout == 0) {
 414                 ret = -ETIMEDOUT;
 415                 cmd_status = -ETIMEDOUT;
 416         }
 417
 418 skip_status:
 419         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 420
 421         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 422                 if (ret == 0)
 423                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 424
 425                 if (ret != -ETIMEDOUT)
 426                         dwc3_gadget_ep_get_transfer_index(dep);
 427         }
 428
 429         if (saved_config) {
 430                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 431                 reg |= saved_config;
 432                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 433         }
 434
 435         return ret;
 436 }
 437
 438 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 439 {
 440         struct dwc3 *dwc = dep->dwc;
 441         struct dwc3_gadget_ep_cmd_params params;
 442         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 443
 444         /*
 445          * As of core revision 2.60a the recommended programming model
 446          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 447          * command for IN endpoints. This is to prevent an issue where
 448          * some (non-compliant) hosts may not send ACK TPs for pending
 449          * IN transfers due to a mishandled error condition. Synopsys
 450          * STAR 9000614252.
 451          */
 452         if (dep->direction &&
 453             !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
 454             (dwc->gadget->speed >= USB_SPEED_SUPER))
 455                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 456
 457         memset(&params, 0, sizeof(params));
 458
 459         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 460 }
 461
 462 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 463                 struct dwc3_trb *trb)
 464 {
 465         u32             offset = (char *) trb - (char *) dep->trb_pool;
 466
 467         return dep->trb_pool_dma + offset;
 468 }
 469
 470 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 471 {
 472         struct dwc3             *dwc = dep->dwc;
 473
 474         if (dep->trb_pool)
 475                 return 0;
 476
 477         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
 478                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 479                         &dep->trb_pool_dma, GFP_KERNEL);
 480         if (!dep->trb_pool) {
 481                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 482                                 dep->name);
 483                 return -ENOMEM;
 484         }
 485
 486         return 0;
 487 }
 488
 489 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 490 {
 491         struct dwc3             *dwc = dep->dwc;
 492
 493         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 494                         dep->trb_pool, dep->trb_pool_dma);
 495
 496         dep->trb_pool = NULL;
 497         dep->trb_pool_dma = 0;
 498 }
 499
 500 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
 501 {
 502         struct dwc3_gadget_ep_cmd_params params;
 503
 504         memset(&params, 0x00, sizeof(params));
 505
 506         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 507
 508         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 509                         &params);
 510 }
 511
 512 /**
 513  * dwc3_gadget_start_config - configure ep resources
 514  * @dep: endpoint that is being enabled
 515  *
 516  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
 517  * completion, it will set Transfer Resource for all available endpoints.
 518  *
 519  * The assignment of transfer resources cannot perfectly follow the data book
 520  * due to the fact that the controller driver does not have all knowledge of the
 521  * configuration in advance. It is given this information piecemeal by the
 522  * composite gadget framework after every SET_CONFIGURATION and
 523  * SET_INTERFACE. Trying to follow the databook programming model in this
 524  * scenario can cause errors. For two reasons:
 525  *
 526  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
 527  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
 528  * incorrect in the scenario of multiple interfaces.
 529  *
 530  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
 531  * endpoint on alt setting (8.1.6).
 532  *
 533  * The following simplified method is used instead:
 534  *
 535  * All hardware endpoints can be assigned a transfer resource and this setting
 536  * will stay persistent until either a core reset or hibernation. So whenever we
 537  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
 538  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
 539  * guaranteed that there are as many transfer resources as endpoints.
 540  *
 541  * This function is called for each endpoint when it is being enabled but is
 542  * triggered only when called for EP0-out, which always happens first, and which
 543  * should only happen in one of the above conditions.
 544  */
 545 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
 546 {
 547         struct dwc3_gadget_ep_cmd_params params;
 548         struct dwc3             *dwc;
 549         u32                     cmd;
 550         int                     i;
 551         int                     ret;
 552
 553         if (dep->number)
 554                 return 0;
 555
 556         memset(&params, 0x00, sizeof(params));
 557         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 558         dwc = dep->dwc;
 559
 560         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 561         if (ret)
 562                 return ret;
 563
 564         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 565                 struct dwc3_ep *dep = dwc->eps[i];
 566
 567                 if (!dep)
 568                         continue;
 569
 570                 ret = dwc3_gadget_set_xfer_resource(dep);
 571                 if (ret)
 572                         return ret;
 573         }
 574
 575         return 0;
 576 }
 577
 578 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 579 {
 580         const struct usb_ss_ep_comp_descriptor *comp_desc;
 581         const struct usb_endpoint_descriptor *desc;
 582         struct dwc3_gadget_ep_cmd_params params;
 583         struct dwc3 *dwc = dep->dwc;
 584
 585         comp_desc = dep->endpoint.comp_desc;
 586         desc = dep->endpoint.desc;
 587
 588         memset(&params, 0x00, sizeof(params));
 589
 590         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 591                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 592
 593         /* Burst size is only needed in SuperSpeed mode */
 594         if (dwc->gadget->speed >= USB_SPEED_SUPER) {
 595                 u32 burst = dep->endpoint.maxburst;
 596
 597                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 598         }
 599
 600         params.param0 |= action;
 601         if (action == DWC3_DEPCFG_ACTION_RESTORE)
 602                 params.param2 |= dep->saved_state;
 603
 604         if (usb_endpoint_xfer_control(desc))
 605                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 606
 607         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 608                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 609
 610         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 611                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 612                         | DWC3_DEPCFG_XFER_COMPLETE_EN
 613                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 614                 dep->stream_capable = true;
 615         }
 616
 617         if (!usb_endpoint_xfer_control(desc))
 618                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 619
 620         /*
 621          * We are doing 1:1 mapping for endpoints, meaning
 622          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 623          * so on. We consider the direction bit as part of the physical
 624          * endpoint number. So USB endpoint 0x81 is 0x03.
 625          */
 626         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 627
 628         /*
 629          * We must use the lower 16 TX FIFOs even though
 630          * HW might have more
 631          */
 632         if (dep->direction)
 633                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 634
 635         if (desc->bInterval) {
 636                 u8 bInterval_m1;
 637
 638                 /*
 639                  * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
 640                  *
 641                  * NOTE: The programming guide incorrectly stated bInterval_m1
 642                  * must be set to 0 when operating in fullspeed. Internally the
 643                  * controller does not have this limitation. See DWC_usb3x
 644                  * programming guide section 3.2.2.1.
 645                  */
 646                 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
 647
 648                 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
 649                     dwc->gadget->speed == USB_SPEED_FULL)
 650                         dep->interval = desc->bInterval;
 651                 else
 652                         dep->interval = 1 << (desc->bInterval - 1);
 653
 654                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
 655         }
 656
 657         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 658 }
 659
 660 /**
 661  * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
 662  * @dwc: pointer to the DWC3 context
 663  * @mult: multiplier to be used when calculating the fifo_size
 664  *
 665  * Calculates the size value based on the equation below:
 666  *
 667  * DWC3 revision 280A and prior:
 668  * fifo_size = mult * (max_packet / mdwidth) + 1;
 669  *
 670  * DWC3 revision 290A and onwards:
 671  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
 672  *
 673  * The max packet size is set to 1024, as the txfifo requirements mainly apply
 674  * to super speed USB use cases.  However, it is safe to overestimate the fifo
 675  * allocations for other scenarios, i.e. high speed USB.
 676  */
 677 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
 678 {
 679         int max_packet = 1024;
 680         int fifo_size;
 681         int mdwidth;
 682
 683         mdwidth = dwc3_mdwidth(dwc);
 684
 685         /* MDWIDTH is represented in bits, we need it in bytes */
 686         mdwidth >>= 3;
 687
 688         if (DWC3_VER_IS_PRIOR(DWC3, 290A))
 689                 fifo_size = mult * (max_packet / mdwidth) + 1;
 690         else
 691                 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
 692         return fifo_size;
 693 }
 694
 695 /**
 696  * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
 697  * @dwc: pointer to the DWC3 context
 698  *
 699  * Iterates through all the endpoint registers and clears the previous txfifo
 700  * allocations.
 701  */
 702 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
 703 {
 704         struct dwc3_ep *dep;
 705         int fifo_depth;
 706         int size;
 707         int num;
 708
 709         if (!dwc->do_fifo_resize)
 710                 return;
 711
 712         /* Read ep0IN related TXFIFO size */
 713         dep = dwc->eps[1];
 714         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
 715         if (DWC3_IP_IS(DWC3))
 716                 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
 717         else
 718                 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
 719
 720         dwc->last_fifo_depth = fifo_depth;
 721         /* Clear existing TXFIFO for all IN eps except ep0 */
 722         for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
 723              num += 2) {
 724                 dep = dwc->eps[num];
 725                 /* Don't change TXFRAMNUM on usb31 version */
 726                 size = DWC3_IP_IS(DWC3) ? 0 :
 727                         dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
 728                                    DWC31_GTXFIFOSIZ_TXFRAMNUM;
 729
 730                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
 731                 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
 732         }
 733         dwc->num_ep_resized = 0;
 734 }
 735
 736 /*
 737  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 738  * @dwc: pointer to our context structure
 739  *
 740  * This function will a best effort FIFO allocation in order
 741  * to improve FIFO usage and throughput, while still allowing
 742  * us to enable as many endpoints as possible.
 743  *
 744  * Keep in mind that this operation will be highly dependent
 745  * on the configured size for RAM1 - which contains TxFifo -,
 746  * the amount of endpoints enabled on coreConsultant tool, and
 747  * the width of the Master Bus.
 748  *
 749  * In general, FIFO depths are represented with the following equation:
 750  *
 751  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
 752  *
 753  * In conjunction with dwc3_gadget_check_config(), this resizing logic will
 754  * ensure that all endpoints will have enough internal memory for one max
 755  * packet per endpoint.
 756  */
 757 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
 758 {
 759         struct dwc3 *dwc = dep->dwc;
 760         int fifo_0_start;
 761         int ram1_depth;
 762         int fifo_size;
 763         int min_depth;
 764         int num_in_ep;
 765         int remaining;
 766         int num_fifos = 1;
 767         int fifo;
 768         int tmp;
 769
 770         if (!dwc->do_fifo_resize)
 771                 return 0;
 772
 773         /* resize IN endpoints except ep0 */
 774         if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
 775                 return 0;
 776
 777         /* bail if already resized */
 778         if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
 779                 return 0;
 780
 781         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 782
 783         if ((dep->endpoint.maxburst > 1 &&
 784              usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
 785             usb_endpoint_xfer_isoc(dep->endpoint.desc))
 786                 num_fifos = 3;
 787
 788         if (dep->endpoint.maxburst > 6 &&
 789             (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
 790              usb_endpoint_xfer_isoc(dep->endpoint.desc)) && DWC3_IP_IS(DWC31))
 791                 num_fifos = dwc->tx_fifo_resize_max_num;
 792
 793         /* FIFO size for a single buffer */
 794         fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
 795
 796         /* Calculate the number of remaining EPs w/o any FIFO */
 797         num_in_ep = dwc->max_cfg_eps;
 798         num_in_ep -= dwc->num_ep_resized;
 799
 800         /* Reserve at least one FIFO for the number of IN EPs */
 801         min_depth = num_in_ep * (fifo + 1);
 802         remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
 803         remaining = max_t(int, 0, remaining);
 804         /*
 805          * We've already reserved 1 FIFO per EP, so check what we can fit in
 806          * addition to it.  If there is not enough remaining space, allocate
 807          * all the remaining space to the EP.
 808          */
 809         fifo_size = (num_fifos - 1) * fifo;
 810         if (remaining < fifo_size)
 811                 fifo_size = remaining;
 812
 813         fifo_size += fifo;
 814         /* Last increment according to the TX FIFO size equation */
 815         fifo_size++;
 816
 817         /* Check if TXFIFOs start at non-zero addr */
 818         tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
 819         fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
 820
 821         fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
 822         if (DWC3_IP_IS(DWC3))
 823                 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
 824         else
 825                 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
 826
 827         /* Check fifo size allocation doesn't exceed available RAM size. */
 828         if (dwc->last_fifo_depth >= ram1_depth) {
 829                 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
 830                         dwc->last_fifo_depth, ram1_depth,
 831                         dep->endpoint.name, fifo_size);
 832                 if (DWC3_IP_IS(DWC3))
 833                         fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
 834                 else
 835                         fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
 836
 837                 dwc->last_fifo_depth -= fifo_size;
 838                 return -ENOMEM;
 839         }
 840
 841         dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
 842         dep->flags |= DWC3_EP_TXFIFO_RESIZED;
 843         dwc->num_ep_resized++;
 844
 845         return 0;
 846 }
 847
 848 /**
 849  * __dwc3_gadget_ep_enable - initializes a hw endpoint
 850  * @dep: endpoint to be initialized
 851  * @action: one of INIT, MODIFY or RESTORE
 852  *
 853  * Caller should take care of locking. Execute all necessary commands to
 854  * initialize a HW endpoint so it can be used by a gadget driver.
 855  */
 856 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 857 {
 858         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 859         struct dwc3             *dwc = dep->dwc;
 860
 861         u32                     reg;
 862         int                     ret;
 863
 864         if (!(dep->flags & DWC3_EP_ENABLED)) {
 865                 ret = dwc3_gadget_resize_tx_fifos(dep);
 866                 if (ret)
 867                         return ret;
 868
 869                 ret = dwc3_gadget_start_config(dep);
 870                 if (ret)
 871                         return ret;
 872         }
 873
 874         ret = dwc3_gadget_set_ep_config(dep, action);
 875         if (ret)
 876                 return ret;
 877
 878         if (!(dep->flags & DWC3_EP_ENABLED)) {
 879                 struct dwc3_trb *trb_st_hw;
 880                 struct dwc3_trb *trb_link;
 881
 882                 dep->type = usb_endpoint_type(desc);
 883                 dep->flags |= DWC3_EP_ENABLED;
 884
 885                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 886                 reg |= DWC3_DALEPENA_EP(dep->number);
 887                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 888
 889                 dep->trb_dequeue = 0;
 890                 dep->trb_enqueue = 0;
 891
 892                 if (usb_endpoint_xfer_control(desc))
 893                         goto out;
 894
 895                 /* Initialize the TRB ring */
 896                 memset(dep->trb_pool, 0,
 897                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 898
 899                 /* Link TRB. The HWO bit is never reset */
 900                 trb_st_hw = &dep->trb_pool[0];
 901
 902                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 903                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 904                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 905                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 906                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 907         }
 908
 909         /*
 910          * Issue StartTransfer here with no-op TRB so we can always rely on No
 911          * Response Update Transfer command.
 912          */
 913         if (usb_endpoint_xfer_bulk(desc) ||
 914                         usb_endpoint_xfer_int(desc)) {
 915                 struct dwc3_gadget_ep_cmd_params params;
 916                 struct dwc3_trb *trb;
 917                 dma_addr_t trb_dma;
 918                 u32 cmd;
 919
 920                 memset(&params, 0, sizeof(params));
 921                 trb = &dep->trb_pool[0];
 922                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 923
 924                 params.param0 = upper_32_bits(trb_dma);
 925                 params.param1 = lower_32_bits(trb_dma);
 926
 927                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 928
 929                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 930                 if (ret < 0)
 931                         return ret;
 932
 933                 if (dep->stream_capable) {
 934                         /*
 935                          * For streams, at start, there maybe a race where the
 936                          * host primes the endpoint before the function driver
 937                          * queues a request to initiate a stream. In that case,
 938                          * the controller will not see the prime to generate the
 939                          * ERDY and start stream. To workaround this, issue a
 940                          * no-op TRB as normal, but end it immediately. As a
 941                          * result, when the function driver queues the request,
 942                          * the next START_TRANSFER command will cause the
 943                          * controller to generate an ERDY to initiate the
 944                          * stream.
 945                          */
 946                         dwc3_stop_active_transfer(dep, true, true);
 947
 948                         /*
 949                          * All stream eps will reinitiate stream on NoStream
 950                          * rejection until we can determine that the host can
 951                          * prime after the first transfer.
 952                          *
 953                          * However, if the controller is capable of
 954                          * TXF_FLUSH_BYPASS, then IN direction endpoints will
 955                          * automatically restart the stream without the driver
 956                          * initiation.
 957                          */
 958                         if (!dep->direction ||
 959                             !(dwc->hwparams.hwparams9 &
 960                               DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
 961                                 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
 962                 }
 963         }
 964
 965 out:
 966         trace_dwc3_gadget_ep_enable(dep);
 967
 968         return 0;
 969 }
 970
 971 void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
 972 {
 973         struct dwc3_request             *req;
 974
 975         dwc3_stop_active_transfer(dep, true, false);
 976
 977         /* If endxfer is delayed, avoid unmapping requests */
 978         if (dep->flags & DWC3_EP_DELAY_STOP)
 979                 return;
 980
 981         /* - giveback all requests to gadget driver */
 982         while (!list_empty(&dep->started_list)) {
 983                 req = next_request(&dep->started_list);
 984
 985                 dwc3_gadget_giveback(dep, req, status);
 986         }
 987
 988         while (!list_empty(&dep->pending_list)) {
 989                 req = next_request(&dep->pending_list);
 990
 991                 dwc3_gadget_giveback(dep, req, status);
 992         }
 993
 994         while (!list_empty(&dep->cancelled_list)) {
 995                 req = next_request(&dep->cancelled_list);
 996
 997                 dwc3_gadget_giveback(dep, req, status);
 998         }
 999 }
1000
1001 /**
1002  * __dwc3_gadget_ep_disable - disables a hw endpoint
1003  * @dep: the endpoint to disable
1004  *
1005  * This function undoes what __dwc3_gadget_ep_enable did and also removes
1006  * requests which are currently being processed by the hardware and those which
1007  * are not yet scheduled.
1008  *
1009  * Caller should take care of locking.
1010  */
1011 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1012 {
1013         struct dwc3             *dwc = dep->dwc;
1014         u32                     reg;
1015         u32                     mask;
1016
1017         trace_dwc3_gadget_ep_disable(dep);
1018
1019         /* make sure HW endpoint isn't stalled */
1020         if (dep->flags & DWC3_EP_STALL)
1021                 __dwc3_gadget_ep_set_halt(dep, 0, false);
1022
1023         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1024         reg &= ~DWC3_DALEPENA_EP(dep->number);
1025         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1026
1027         dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1028
1029         dep->stream_capable = false;
1030         dep->type = 0;
1031         mask = DWC3_EP_TXFIFO_RESIZED;
1032         /*
1033          * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
1034          * set.  Do not clear DEP flags, so that the end transfer command will
1035          * be reattempted during the next SETUP stage.
1036          */
1037         if (dep->flags & DWC3_EP_DELAY_STOP)
1038                 mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
1039         dep->flags &= mask;
1040
1041         /* Clear out the ep descriptors for non-ep0 */
1042         if (dep->number > 1) {
1043                 dep->endpoint.comp_desc = NULL;
1044                 dep->endpoint.desc = NULL;
1045         }
1046
1047         return 0;
1048 }
1049
1050 /* -------------------------------------------------------------------------- */
1051
1052 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1053                 const struct usb_endpoint_descriptor *desc)
1054 {
1055         return -EINVAL;
1056 }
1057
1058 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1059 {
1060         return -EINVAL;
1061 }
1062
1063 /* -------------------------------------------------------------------------- */
1064
1065 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1066                 const struct usb_endpoint_descriptor *desc)
1067 {
1068         struct dwc3_ep                  *dep;
1069         struct dwc3                     *dwc;
1070         unsigned long                   flags;
1071         int                             ret;
1072
1073         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1074                 pr_debug("dwc3: invalid parameters\n");
1075                 return -EINVAL;
1076         }
1077
1078         if (!desc->wMaxPacketSize) {
1079                 pr_debug("dwc3: missing wMaxPacketSize\n");
1080                 return -EINVAL;
1081         }
1082
1083         dep = to_dwc3_ep(ep);
1084         dwc = dep->dwc;
1085
1086         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1087                                         "%s is already enabled\n",
1088                                         dep->name))
1089                 return 0;
1090
1091         spin_lock_irqsave(&dwc->lock, flags);
1092         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1093         spin_unlock_irqrestore(&dwc->lock, flags);
1094
1095         return ret;
1096 }
1097
1098 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1099 {
1100         struct dwc3_ep                  *dep;
1101         struct dwc3                     *dwc;
1102         unsigned long                   flags;
1103         int                             ret;
1104
1105         if (!ep) {
1106                 pr_debug("dwc3: invalid parameters\n");
1107                 return -EINVAL;
1108         }
1109
1110         dep = to_dwc3_ep(ep);
1111         dwc = dep->dwc;
1112
1113         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1114                                         "%s is already disabled\n",
1115                                         dep->name))
1116                 return 0;
1117
1118         spin_lock_irqsave(&dwc->lock, flags);
1119         ret = __dwc3_gadget_ep_disable(dep);
1120         spin_unlock_irqrestore(&dwc->lock, flags);
1121
1122         return ret;
1123 }
1124
1125 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1126                 gfp_t gfp_flags)
1127 {
1128         struct dwc3_request             *req;
1129         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1130
1131         req = kzalloc(sizeof(*req), gfp_flags);
1132         if (!req)
1133                 return NULL;
1134
1135         req->direction  = dep->direction;
1136         req->epnum      = dep->number;
1137         req->dep        = dep;
1138         req->status     = DWC3_REQUEST_STATUS_UNKNOWN;
1139
1140         trace_dwc3_alloc_request(req);
1141
1142         return &req->request;
1143 }
1144
1145 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1146                 struct usb_request *request)
1147 {
1148         struct dwc3_request             *req = to_dwc3_request(request);
1149
1150         trace_dwc3_free_request(req);
1151         kfree(req);
1152 }
1153
1154 /**
1155  * dwc3_ep_prev_trb - returns the previous TRB in the ring
1156  * @dep: The endpoint with the TRB ring
1157  * @index: The index of the current TRB in the ring
1158  *
1159  * Returns the TRB prior to the one pointed to by the index. If the
1160  * index is 0, we will wrap backwards, skip the link TRB, and return
1161  * the one just before that.
1162  */
1163 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1164 {
1165         u8 tmp = index;
1166
1167         if (!tmp)
1168                 tmp = DWC3_TRB_NUM - 1;
1169
1170         return &dep->trb_pool[tmp - 1];
1171 }
1172
1173 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1174 {
1175         u8                      trbs_left;
1176
1177         /*
1178          * If the enqueue & dequeue are equal then the TRB ring is either full
1179          * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1180          * pending to be processed by the driver.
1181          */
1182         if (dep->trb_enqueue == dep->trb_dequeue) {
1183                 /*
1184                  * If there is any request remained in the started_list at
1185                  * this point, that means there is no TRB available.
1186                  */
1187                 if (!list_empty(&dep->started_list))
1188                         return 0;
1189
1190                 return DWC3_TRB_NUM - 1;
1191         }
1192
1193         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1194         trbs_left &= (DWC3_TRB_NUM - 1);
1195
1196         if (dep->trb_dequeue < dep->trb_enqueue)
1197                 trbs_left--;
1198
1199         return trbs_left;
1200 }
1201
1202 /**
1203  * dwc3_prepare_one_trb - setup one TRB from one request
1204  * @dep: endpoint for which this request is prepared
1205  * @req: dwc3_request pointer
1206  * @trb_length: buffer size of the TRB
1207  * @chain: should this TRB be chained to the next?
1208  * @node: only for isochronous endpoints. First TRB needs different type.
1209  * @use_bounce_buffer: set to use bounce buffer
1210  * @must_interrupt: set to interrupt on TRB completion
1211  */
1212 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1213                 struct dwc3_request *req, unsigned int trb_length,
1214                 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1215                 bool must_interrupt)
1216 {
1217         struct dwc3_trb         *trb;
1218         dma_addr_t              dma;
1219         unsigned int            stream_id = req->request.stream_id;
1220         unsigned int            short_not_ok = req->request.short_not_ok;
1221         unsigned int            no_interrupt = req->request.no_interrupt;
1222         unsigned int            is_last = req->request.is_last;
1223         struct dwc3             *dwc = dep->dwc;
1224         struct usb_gadget       *gadget = dwc->gadget;
1225         enum usb_device_speed   speed = gadget->speed;
1226
1227         if (use_bounce_buffer)
1228                 dma = dep->dwc->bounce_addr;
1229         else if (req->request.num_sgs > 0)
1230                 dma = sg_dma_address(req->start_sg);
1231         else
1232                 dma = req->request.dma;
1233
1234         trb = &dep->trb_pool[dep->trb_enqueue];
1235
1236         if (!req->trb) {
1237                 dwc3_gadget_move_started_request(req);
1238                 req->trb = trb;
1239                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1240         }
1241
1242         req->num_trbs++;
1243
1244         trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1245         trb->bpl = lower_32_bits(dma);
1246         trb->bph = upper_32_bits(dma);
1247
1248         switch (usb_endpoint_type(dep->endpoint.desc)) {
1249         case USB_ENDPOINT_XFER_CONTROL:
1250                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1251                 break;
1252
1253         case USB_ENDPOINT_XFER_ISOC:
1254                 if (!node) {
1255                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1256
1257                         /*
1258                          * USB Specification 2.0 Section 5.9.2 states that: "If
1259                          * there is only a single transaction in the microframe,
1260                          * only a DATA0 data packet PID is used.  If there are
1261                          * two transactions per microframe, DATA1 is used for
1262                          * the first transaction data packet and DATA0 is used
1263                          * for the second transaction data packet.  If there are
1264                          * three transactions per microframe, DATA2 is used for
1265                          * the first transaction data packet, DATA1 is used for
1266                          * the second, and DATA0 is used for the third."
1267                          *
1268                          * IOW, we should satisfy the following cases:
1269                          *
1270                          * 1) length <= maxpacket
1271                          *      - DATA0
1272                          *
1273                          * 2) maxpacket < length <= (2 * maxpacket)
1274                          *      - DATA1, DATA0
1275                          *
1276                          * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1277                          *      - DATA2, DATA1, DATA0
1278                          */
1279                         if (speed == USB_SPEED_HIGH) {
1280                                 struct usb_ep *ep = &dep->endpoint;
1281                                 unsigned int mult = 2;
1282                                 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1283
1284                                 if (req->request.length <= (2 * maxp))
1285                                         mult--;
1286
1287                                 if (req->request.length <= maxp)
1288                                         mult--;
1289
1290                                 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1291                         }
1292                 } else {
1293                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1294                 }
1295
1296                 if (!no_interrupt && !chain)
1297                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1298                 break;
1299
1300         case USB_ENDPOINT_XFER_BULK:
1301         case USB_ENDPOINT_XFER_INT:
1302                 trb->ctrl = DWC3_TRBCTL_NORMAL;
1303                 break;
1304         default:
1305                 /*
1306                  * This is only possible with faulty memory because we
1307                  * checked it already :)
1308                  */
1309                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1310                                 usb_endpoint_type(dep->endpoint.desc));
1311         }
1312
1313         /*
1314          * Enable Continue on Short Packet
1315          * when endpoint is not a stream capable
1316          */
1317         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1318                 if (!dep->stream_capable)
1319                         trb->ctrl |= DWC3_TRB_CTRL_CSP;
1320
1321                 if (short_not_ok)
1322                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1323         }
1324
1325         /* All TRBs setup for MST must set CSP=1 when LST=0 */
1326         if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1327                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1328
1329         if ((!no_interrupt && !chain) || must_interrupt)
1330                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1331
1332         if (chain)
1333                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1334         else if (dep->stream_capable && is_last &&
1335                  !DWC3_MST_CAPABLE(&dwc->hwparams))
1336                 trb->ctrl |= DWC3_TRB_CTRL_LST;
1337
1338         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1339                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1340
1341         /*
1342          * As per data book 4.2.3.2TRB Control Bit Rules section
1343          *
1344          * The controller autonomously checks the HWO field of a TRB to determine if the
1345          * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1346          * is valid before setting the HWO field to '1'. In most systems, this means that
1347          * software must update the fourth DWORD of a TRB last.
1348          *
1349          * However there is a possibility of CPU re-ordering here which can cause
1350          * controller to observe the HWO bit set prematurely.
1351          * Add a write memory barrier to prevent CPU re-ordering.
1352          */
1353         wmb();
1354         trb->ctrl |= DWC3_TRB_CTRL_HWO;
1355
1356         dwc3_ep_inc_enq(dep);
1357
1358         trace_dwc3_prepare_trb(dep, trb);
1359 }
1360
1361 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1362 {
1363         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1364         unsigned int rem = req->request.length % maxp;
1365
1366         if ((req->request.length && req->request.zero && !rem &&
1367                         !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1368                         (!req->direction && rem))
1369                 return true;
1370
1371         return false;
1372 }
1373
1374 /**
1375  * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1376  * @dep: The endpoint that the request belongs to
1377  * @req: The request to prepare
1378  * @entry_length: The last SG entry size
1379  * @node: Indicates whether this is not the first entry (for isoc only)
1380  *
1381  * Return the number of TRBs prepared.
1382  */
1383 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1384                 struct dwc3_request *req, unsigned int entry_length,
1385                 unsigned int node)
1386 {
1387         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1388         unsigned int rem = req->request.length % maxp;
1389         unsigned int num_trbs = 1;
1390
1391         if (dwc3_needs_extra_trb(dep, req))
1392                 num_trbs++;
1393
1394         if (dwc3_calc_trbs_left(dep) < num_trbs)
1395                 return 0;
1396
1397         req->needs_extra_trb = num_trbs > 1;
1398
1399         /* Prepare a normal TRB */
1400         if (req->direction || req->request.length)
1401                 dwc3_prepare_one_trb(dep, req, entry_length,
1402                                 req->needs_extra_trb, node, false, false);
1403
1404         /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1405         if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1406                 dwc3_prepare_one_trb(dep, req,
1407                                 req->direction ? 0 : maxp - rem,
1408                                 false, 1, true, false);
1409
1410         return num_trbs;
1411 }
1412
1413 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1414                 struct dwc3_request *req)
1415 {
1416         struct scatterlist *sg = req->start_sg;
1417         struct scatterlist *s;
1418         int             i;
1419         unsigned int length = req->request.length;
1420         unsigned int remaining = req->request.num_mapped_sgs
1421                 - req->num_queued_sgs;
1422         unsigned int num_trbs = req->num_trbs;
1423         bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1424
1425         /*
1426          * If we resume preparing the request, then get the remaining length of
1427          * the request and resume where we left off.
1428          */
1429         for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1430                 length -= sg_dma_len(s);
1431
1432         for_each_sg(sg, s, remaining, i) {
1433                 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1434                 unsigned int trb_length;
1435                 bool must_interrupt = false;
1436                 bool last_sg = false;
1437
1438                 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1439
1440                 length -= trb_length;
1441
1442                 /*
1443                  * IOMMU driver is coalescing the list of sgs which shares a
1444                  * page boundary into one and giving it to USB driver. With
1445                  * this the number of sgs mapped is not equal to the number of
1446                  * sgs passed. So mark the chain bit to false if it isthe last
1447                  * mapped sg.
1448                  */
1449                 if ((i == remaining - 1) || !length)
1450                         last_sg = true;
1451
1452                 if (!num_trbs_left)
1453                         break;
1454
1455                 if (last_sg) {
1456                         if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1457                                 break;
1458                 } else {
1459                         /*
1460                          * Look ahead to check if we have enough TRBs for the
1461                          * next SG entry. If not, set interrupt on this TRB to
1462                          * resume preparing the next SG entry when more TRBs are
1463                          * free.
1464                          */
1465                         if (num_trbs_left == 1 || (needs_extra_trb &&
1466                                         num_trbs_left <= 2 &&
1467                                         sg_dma_len(sg_next(s)) >= length))
1468                                 must_interrupt = true;
1469
1470                         dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1471                                         must_interrupt);
1472                 }
1473
1474                 /*
1475                  * There can be a situation where all sgs in sglist are not
1476                  * queued because of insufficient trb number. To handle this
1477                  * case, update start_sg to next sg to be queued, so that
1478                  * we have free trbs we can continue queuing from where we
1479                  * previously stopped
1480                  */
1481                 if (!last_sg)
1482                         req->start_sg = sg_next(s);
1483
1484                 req->num_queued_sgs++;
1485                 req->num_pending_sgs--;
1486
1487                 /*
1488                  * The number of pending SG entries may not correspond to the
1489                  * number of mapped SG entries. If all the data are queued, then
1490                  * don't include unused SG entries.
1491                  */
1492                 if (length == 0) {
1493                         req->num_pending_sgs = 0;
1494                         break;
1495                 }
1496
1497                 if (must_interrupt)
1498                         break;
1499         }
1500
1501         return req->num_trbs - num_trbs;
1502 }
1503
1504 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1505                 struct dwc3_request *req)
1506 {
1507         return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1508 }
1509
1510 /*
1511  * dwc3_prepare_trbs - setup TRBs from requests
1512  * @dep: endpoint for which requests are being prepared
1513  *
1514  * The function goes through the requests list and sets up TRBs for the
1515  * transfers. The function returns once there are no more TRBs available or
1516  * it runs out of requests.
1517  *
1518  * Returns the number of TRBs prepared or negative errno.
1519  */
1520 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1521 {
1522         struct dwc3_request     *req, *n;
1523         int                     ret = 0;
1524
1525         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1526
1527         /*
1528          * We can get in a situation where there's a request in the started list
1529          * but there weren't enough TRBs to fully kick it in the first time
1530          * around, so it has been waiting for more TRBs to be freed up.
1531          *
1532          * In that case, we should check if we have a request with pending_sgs
1533          * in the started list and prepare TRBs for that request first,
1534          * otherwise we will prepare TRBs completely out of order and that will
1535          * break things.
1536          */
1537         list_for_each_entry(req, &dep->started_list, list) {
1538                 if (req->num_pending_sgs > 0) {
1539                         ret = dwc3_prepare_trbs_sg(dep, req);
1540                         if (!ret || req->num_pending_sgs)
1541                                 return ret;
1542                 }
1543
1544                 if (!dwc3_calc_trbs_left(dep))
1545                         return ret;
1546
1547                 /*
1548                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1549                  * burst capability may try to read and use TRBs beyond the
1550                  * active transfer instead of stopping.
1551                  */
1552                 if (dep->stream_capable && req->request.is_last &&
1553                     !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1554                         return ret;
1555         }
1556
1557         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1558                 struct dwc3     *dwc = dep->dwc;
1559
1560                 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1561                                                     dep->direction);
1562                 if (ret)
1563                         return ret;
1564
1565                 req->sg                 = req->request.sg;
1566                 req->start_sg           = req->sg;
1567                 req->num_queued_sgs     = 0;
1568                 req->num_pending_sgs    = req->request.num_mapped_sgs;
1569
1570                 if (req->num_pending_sgs > 0) {
1571                         ret = dwc3_prepare_trbs_sg(dep, req);
1572                         if (req->num_pending_sgs)
1573                                 return ret;
1574                 } else {
1575                         ret = dwc3_prepare_trbs_linear(dep, req);
1576                 }
1577
1578                 if (!ret || !dwc3_calc_trbs_left(dep))
1579                         return ret;
1580
1581                 /*
1582                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1583                  * burst capability may try to read and use TRBs beyond the
1584                  * active transfer instead of stopping.
1585                  */
1586                 if (dep->stream_capable && req->request.is_last &&
1587                     !DWC3_MST_CAPABLE(&dwc->hwparams))
1588                         return ret;
1589         }
1590
1591         return ret;
1592 }
1593
1594 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1595
1596 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1597 {
1598         struct dwc3_gadget_ep_cmd_params params;
1599         struct dwc3_request             *req;
1600         int                             starting;
1601         int                             ret;
1602         u32                             cmd;
1603
1604         /*
1605          * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1606          * This happens when we need to stop and restart a transfer such as in
1607          * the case of reinitiating a stream or retrying an isoc transfer.
1608          */
1609         ret = dwc3_prepare_trbs(dep);
1610         if (ret < 0)
1611                 return ret;
1612
1613         starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1614
1615         /*
1616          * If there's no new TRB prepared and we don't need to restart a
1617          * transfer, there's no need to update the transfer.
1618          */
1619         if (!ret && !starting)
1620                 return ret;
1621
1622         req = next_request(&dep->started_list);
1623         if (!req) {
1624                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1625                 return 0;
1626         }
1627
1628         memset(&params, 0, sizeof(params));
1629
1630         if (starting) {
1631                 params.param0 = upper_32_bits(req->trb_dma);
1632                 params.param1 = lower_32_bits(req->trb_dma);
1633                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1634
1635                 if (dep->stream_capable)
1636                         cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1637
1638                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1639                         cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1640         } else {
1641                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1642                         DWC3_DEPCMD_PARAM(dep->resource_index);
1643         }
1644
1645         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1646         if (ret < 0) {
1647                 struct dwc3_request *tmp;
1648
1649                 if (ret == -EAGAIN)
1650                         return ret;
1651
1652                 dwc3_stop_active_transfer(dep, true, true);
1653
1654                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1655                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1656
1657                 /* If ep isn't started, then there's no end transfer pending */
1658                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1659                         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1660
1661                 return ret;
1662         }
1663
1664         if (dep->stream_capable && req->request.is_last &&
1665             !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1666                 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1667
1668         return 0;
1669 }
1670
1671 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1672 {
1673         u32                     reg;
1674
1675         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1676         return DWC3_DSTS_SOFFN(reg);
1677 }
1678
1679 /**
1680  * __dwc3_stop_active_transfer - stop the current active transfer
1681  * @dep: isoc endpoint
1682  * @force: set forcerm bit in the command
1683  * @interrupt: command complete interrupt after End Transfer command
1684  *
1685  * When setting force, the ForceRM bit will be set. In that case
1686  * the controller won't update the TRB progress on command
1687  * completion. It also won't clear the HWO bit in the TRB.
1688  * The command will also not complete immediately in that case.
1689  */
1690 static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1691 {
1692         struct dwc3 *dwc = dep->dwc;
1693         struct dwc3_gadget_ep_cmd_params params;
1694         u32 cmd;
1695         int ret;
1696
1697         cmd = DWC3_DEPCMD_ENDTRANSFER;
1698         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1699         cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1700         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1701         memset(&params, 0, sizeof(params));
1702         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1703         /*
1704          * If the End Transfer command was timed out while the device is
1705          * not in SETUP phase, it's possible that an incoming Setup packet
1706          * may prevent the command's completion. Let's retry when the
1707          * ep0state returns to EP0_SETUP_PHASE.
1708          */
1709         if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
1710                 dep->flags |= DWC3_EP_DELAY_STOP;
1711                 return 0;
1712         }
1713         WARN_ON_ONCE(ret);
1714         dep->resource_index = 0;
1715
1716         if (!interrupt) {
1717                 if (!DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC3, 310A))
1718                         mdelay(1);
1719                 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1720         } else if (!ret) {
1721                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1722         }
1723
1724         dep->flags &= ~DWC3_EP_DELAY_STOP;
1725         return ret;
1726 }
1727
1728 /**
1729  * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1730  * @dep: isoc endpoint
1731  *
1732  * This function tests for the correct combination of BIT[15:14] from the 16-bit
1733  * microframe number reported by the XferNotReady event for the future frame
1734  * number to start the isoc transfer.
1735  *
1736  * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1737  * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1738  * XferNotReady event are invalid. The driver uses this number to schedule the
1739  * isochronous transfer and passes it to the START TRANSFER command. Because
1740  * this number is invalid, the command may fail. If BIT[15:14] matches the
1741  * internal 16-bit microframe, the START TRANSFER command will pass and the
1742  * transfer will start at the scheduled time, if it is off by 1, the command
1743  * will still pass, but the transfer will start 2 seconds in the future. For all
1744  * other conditions, the START TRANSFER command will fail with bus-expiry.
1745  *
1746  * In order to workaround this issue, we can test for the correct combination of
1747  * BIT[15:14] by sending START TRANSFER commands with different values of
1748  * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1749  * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1750  * As the result, within the 4 possible combinations for BIT[15:14], there will
1751  * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1752  * command status will result in a 2-second delay start. The smaller BIT[15:14]
1753  * value is the correct combination.
1754  *
1755  * Since there are only 4 outcomes and the results are ordered, we can simply
1756  * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1757  * deduce the smaller successful combination.
1758  *
1759  * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1760  * of BIT[15:14]. The correct combination is as follow:
1761  *
1762  * if test0 fails and test1 passes, BIT[15:14] is 'b01
1763  * if test0 fails and test1 fails, BIT[15:14] is 'b10
1764  * if test0 passes and test1 fails, BIT[15:14] is 'b11
1765  * if test0 passes and test1 passes, BIT[15:14] is 'b00
1766  *
1767  * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1768  * endpoints.
1769  */
1770 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1771 {
1772         int cmd_status = 0;
1773         bool test0;
1774         bool test1;
1775
1776         while (dep->combo_num < 2) {
1777                 struct dwc3_gadget_ep_cmd_params params;
1778                 u32 test_frame_number;
1779                 u32 cmd;
1780
1781                 /*
1782                  * Check if we can start isoc transfer on the next interval or
1783                  * 4 uframes in the future with BIT[15:14] as dep->combo_num
1784                  */
1785                 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1786                 test_frame_number |= dep->combo_num << 14;
1787                 test_frame_number += max_t(u32, 4, dep->interval);
1788
1789                 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1790                 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1791
1792                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1793                 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1794                 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1795
1796                 /* Redo if some other failure beside bus-expiry is received */
1797                 if (cmd_status && cmd_status != -EAGAIN) {
1798                         dep->start_cmd_status = 0;
1799                         dep->combo_num = 0;
1800                         return 0;
1801                 }
1802
1803                 /* Store the first test status */
1804                 if (dep->combo_num == 0)
1805                         dep->start_cmd_status = cmd_status;
1806
1807                 dep->combo_num++;
1808
1809                 /*
1810                  * End the transfer if the START_TRANSFER command is successful
1811                  * to wait for the next XferNotReady to test the command again
1812                  */
1813                 if (cmd_status == 0) {
1814                         dwc3_stop_active_transfer(dep, true, true);
1815                         return 0;
1816                 }
1817         }
1818
1819         /* test0 and test1 are both completed at this point */
1820         test0 = (dep->start_cmd_status == 0);
1821         test1 = (cmd_status == 0);
1822
1823         if (!test0 && test1)
1824                 dep->combo_num = 1;
1825         else if (!test0 && !test1)
1826                 dep->combo_num = 2;
1827         else if (test0 && !test1)
1828                 dep->combo_num = 3;
1829         else if (test0 && test1)
1830                 dep->combo_num = 0;
1831
1832         dep->frame_number &= DWC3_FRNUMBER_MASK;
1833         dep->frame_number |= dep->combo_num << 14;
1834         dep->frame_number += max_t(u32, 4, dep->interval);
1835
1836         /* Reinitialize test variables */
1837         dep->start_cmd_status = 0;
1838         dep->combo_num = 0;
1839
1840         return __dwc3_gadget_kick_transfer(dep);
1841 }
1842
1843 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1844 {
1845         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1846         struct dwc3 *dwc = dep->dwc;
1847         int ret;
1848         int i;
1849
1850         if (list_empty(&dep->pending_list) &&
1851             list_empty(&dep->started_list)) {
1852                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1853                 return -EAGAIN;
1854         }
1855
1856         if (!dwc->dis_start_transfer_quirk &&
1857             (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1858              DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1859                 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1860                         return dwc3_gadget_start_isoc_quirk(dep);
1861         }
1862
1863         if (desc->bInterval <= 14 &&
1864             dwc->gadget->speed >= USB_SPEED_HIGH) {
1865                 u32 frame = __dwc3_gadget_get_frame(dwc);
1866                 bool rollover = frame <
1867                                 (dep->frame_number & DWC3_FRNUMBER_MASK);
1868
1869                 /*
1870                  * frame_number is set from XferNotReady and may be already
1871                  * out of date. DSTS only provides the lower 14 bit of the
1872                  * current frame number. So add the upper two bits of
1873                  * frame_number and handle a possible rollover.
1874                  * This will provide the correct frame_number unless more than
1875                  * rollover has happened since XferNotReady.
1876                  */
1877
1878                 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1879                                      frame;
1880                 if (rollover)
1881                         dep->frame_number += BIT(14);
1882         }
1883
1884         for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1885                 int future_interval = i + 1;
1886
1887                 /* Give the controller at least 500us to schedule transfers */
1888                 if (desc->bInterval < 3)
1889                         future_interval += 3 - desc->bInterval;
1890
1891                 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1892
1893                 ret = __dwc3_gadget_kick_transfer(dep);
1894                 if (ret != -EAGAIN)
1895                         break;
1896         }
1897
1898         /*
1899          * After a number of unsuccessful start attempts due to bus-expiry
1900          * status, issue END_TRANSFER command and retry on the next XferNotReady
1901          * event.
1902          */
1903         if (ret == -EAGAIN)
1904                 ret = __dwc3_stop_active_transfer(dep, false, true);
1905
1906         return ret;
1907 }
1908
1909 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1910 {
1911         struct dwc3             *dwc = dep->dwc;
1912
1913         if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1914                 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1915                                 dep->name);
1916                 return -ESHUTDOWN;
1917         }
1918
1919         if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1920                                 &req->request, req->dep->name))
1921                 return -EINVAL;
1922
1923         if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1924                                 "%s: request %pK already in flight\n",
1925                                 dep->name, &req->request))
1926                 return -EINVAL;
1927
1928         pm_runtime_get(dwc->dev);
1929
1930         req->request.actual     = 0;
1931         req->request.status     = -EINPROGRESS;
1932
1933         trace_dwc3_ep_queue(req);
1934
1935         list_add_tail(&req->list, &dep->pending_list);
1936         req->status = DWC3_REQUEST_STATUS_QUEUED;
1937
1938         if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1939                 return 0;
1940
1941         /*
1942          * Start the transfer only after the END_TRANSFER is completed
1943          * and endpoint STALL is cleared.
1944          */
1945         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1946             (dep->flags & DWC3_EP_WEDGE) ||
1947             (dep->flags & DWC3_EP_DELAY_STOP) ||
1948             (dep->flags & DWC3_EP_STALL)) {
1949                 dep->flags |= DWC3_EP_DELAY_START;
1950                 return 0;
1951         }
1952
1953         /*
1954          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1955          * wait for a XferNotReady event so we will know what's the current
1956          * (micro-)frame number.
1957          *
1958          * Without this trick, we are very, very likely gonna get Bus Expiry
1959          * errors which will force us issue EndTransfer command.
1960          */
1961         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1962                 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1963                         if ((dep->flags & DWC3_EP_PENDING_REQUEST))
1964                                 return __dwc3_gadget_start_isoc(dep);
1965
1966                         return 0;
1967                 }
1968         }
1969
1970         __dwc3_gadget_kick_transfer(dep);
1971
1972         return 0;
1973 }
1974
1975 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1976         gfp_t gfp_flags)
1977 {
1978         struct dwc3_request             *req = to_dwc3_request(request);
1979         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1980         struct dwc3                     *dwc = dep->dwc;
1981
1982         unsigned long                   flags;
1983
1984         int                             ret;
1985
1986         spin_lock_irqsave(&dwc->lock, flags);
1987         ret = __dwc3_gadget_ep_queue(dep, req);
1988         spin_unlock_irqrestore(&dwc->lock, flags);
1989
1990         return ret;
1991 }
1992
1993 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1994 {
1995         int i;
1996
1997         /* If req->trb is not set, then the request has not started */
1998         if (!req->trb)
1999                 return;
2000
2001         /*
2002          * If request was already started, this means we had to
2003          * stop the transfer. With that we also need to ignore
2004          * all TRBs used by the request, however TRBs can only
2005          * be modified after completion of END_TRANSFER
2006          * command. So what we do here is that we wait for
2007          * END_TRANSFER completion and only after that, we jump
2008          * over TRBs by clearing HWO and incrementing dequeue
2009          * pointer.
2010          */
2011         for (i = 0; i < req->num_trbs; i++) {
2012                 struct dwc3_trb *trb;
2013
2014                 trb = &dep->trb_pool[dep->trb_dequeue];
2015                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2016                 dwc3_ep_inc_deq(dep);
2017         }
2018
2019         req->num_trbs = 0;
2020 }
2021
2022 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2023 {
2024         struct dwc3_request             *req;
2025         struct dwc3                     *dwc = dep->dwc;
2026
2027         while (!list_empty(&dep->cancelled_list)) {
2028                 req = next_request(&dep->cancelled_list);
2029                 dwc3_gadget_ep_skip_trbs(dep, req);
2030                 switch (req->status) {
2031                 case DWC3_REQUEST_STATUS_DISCONNECTED:
2032                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2033                         break;
2034                 case DWC3_REQUEST_STATUS_DEQUEUED:
2035                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
2036                         break;
2037                 case DWC3_REQUEST_STATUS_STALLED:
2038                         dwc3_gadget_giveback(dep, req, -EPIPE);
2039                         break;
2040                 default:
2041                         dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2042                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
2043                         break;
2044                 }
2045                 /*
2046                  * The endpoint is disabled, let the dwc3_remove_requests()
2047                  * handle the cleanup.
2048                  */
2049                 if (!dep->endpoint.desc)
2050                         break;
2051         }
2052 }
2053
2054 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2055                 struct usb_request *request)
2056 {
2057         struct dwc3_request             *req = to_dwc3_request(request);
2058         struct dwc3_request             *r = NULL;
2059
2060         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2061         struct dwc3                     *dwc = dep->dwc;
2062
2063         unsigned long                   flags;
2064         int                             ret = 0;
2065
2066         trace_dwc3_ep_dequeue(req);
2067
2068         spin_lock_irqsave(&dwc->lock, flags);
2069
2070         list_for_each_entry(r, &dep->cancelled_list, list) {
2071                 if (r == req)
2072                         goto out;
2073         }
2074
2075         list_for_each_entry(r, &dep->pending_list, list) {
2076                 if (r == req) {
2077                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
2078                         goto out;
2079                 }
2080         }
2081
2082         list_for_each_entry(r, &dep->started_list, list) {
2083                 if (r == req) {
2084                         struct dwc3_request *t;
2085
2086                         /* wait until it is processed */
2087                         dwc3_stop_active_transfer(dep, true, true);
2088
2089                         /*
2090                          * Remove any started request if the transfer is
2091                          * cancelled.
2092                          */
2093                         list_for_each_entry_safe(r, t, &dep->started_list, list)
2094                                 dwc3_gadget_move_cancelled_request(r,
2095                                                 DWC3_REQUEST_STATUS_DEQUEUED);
2096
2097                         dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2098
2099                         goto out;
2100                 }
2101         }
2102
2103         dev_err(dwc->dev, "request %pK was not queued to %s\n",
2104                 request, ep->name);
2105         ret = -EINVAL;
2106 out:
2107         spin_unlock_irqrestore(&dwc->lock, flags);
2108
2109         return ret;
2110 }
2111
2112 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2113 {
2114         struct dwc3_gadget_ep_cmd_params        params;
2115         struct dwc3                             *dwc = dep->dwc;
2116         struct dwc3_request                     *req;
2117         struct dwc3_request                     *tmp;
2118         int                                     ret;
2119
2120         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2121                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2122                 return -EINVAL;
2123         }
2124
2125         memset(&params, 0x00, sizeof(params));
2126
2127         if (value) {
2128                 struct dwc3_trb *trb;
2129
2130                 unsigned int transfer_in_flight;
2131                 unsigned int started;
2132
2133                 if (dep->number > 1)
2134                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2135                 else
2136                         trb = &dwc->ep0_trb[dep->trb_enqueue];
2137
2138                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2139                 started = !list_empty(&dep->started_list);
2140
2141                 if (!protocol && ((dep->direction && transfer_in_flight) ||
2142                                 (!dep->direction && started))) {
2143                         return -EAGAIN;
2144                 }
2145
2146                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2147                                 &params);
2148                 if (ret)
2149                         dev_err(dwc->dev, "failed to set STALL on %s\n",
2150                                         dep->name);
2151                 else
2152                         dep->flags |= DWC3_EP_STALL;
2153         } else {
2154                 /*
2155                  * Don't issue CLEAR_STALL command to control endpoints. The
2156                  * controller automatically clears the STALL when it receives
2157                  * the SETUP token.
2158                  */
2159                 if (dep->number <= 1) {
2160                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2161                         return 0;
2162                 }
2163
2164                 dwc3_stop_active_transfer(dep, true, true);
2165
2166                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2167                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2168
2169                 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2170                     (dep->flags & DWC3_EP_DELAY_STOP)) {
2171                         dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2172                         if (protocol)
2173                                 dwc->clear_stall_protocol = dep->number;
2174
2175                         return 0;
2176                 }
2177
2178                 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2179
2180                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2181                 if (ret) {
2182                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
2183                                         dep->name);
2184                         return ret;
2185                 }
2186
2187                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2188
2189                 if ((dep->flags & DWC3_EP_DELAY_START) &&
2190                     !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2191                         __dwc3_gadget_kick_transfer(dep);
2192
2193                 dep->flags &= ~DWC3_EP_DELAY_START;
2194         }
2195
2196         return ret;
2197 }
2198
2199 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2200 {
2201         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2202         struct dwc3                     *dwc = dep->dwc;
2203
2204         unsigned long                   flags;
2205
2206         int                             ret;
2207
2208         spin_lock_irqsave(&dwc->lock, flags);
2209         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2210         spin_unlock_irqrestore(&dwc->lock, flags);
2211
2212         return ret;
2213 }
2214
2215 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2216 {
2217         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2218         struct dwc3                     *dwc = dep->dwc;
2219         unsigned long                   flags;
2220         int                             ret;
2221
2222         spin_lock_irqsave(&dwc->lock, flags);
2223         dep->flags |= DWC3_EP_WEDGE;
2224
2225         if (dep->number == 0 || dep->number == 1)
2226                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2227         else
2228                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2229         spin_unlock_irqrestore(&dwc->lock, flags);
2230
2231         return ret;
2232 }
2233
2234 /* -------------------------------------------------------------------------- */
2235
2236 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2237         .bLength        = USB_DT_ENDPOINT_SIZE,
2238         .bDescriptorType = USB_DT_ENDPOINT,
2239         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
2240 };
2241
2242 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2243         .enable         = dwc3_gadget_ep0_enable,
2244         .disable        = dwc3_gadget_ep0_disable,
2245         .alloc_request  = dwc3_gadget_ep_alloc_request,
2246         .free_request   = dwc3_gadget_ep_free_request,
2247         .queue          = dwc3_gadget_ep0_queue,
2248         .dequeue        = dwc3_gadget_ep_dequeue,
2249         .set_halt       = dwc3_gadget_ep0_set_halt,
2250         .set_wedge      = dwc3_gadget_ep_set_wedge,
2251 };
2252
2253 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2254         .enable         = dwc3_gadget_ep_enable,
2255         .disable        = dwc3_gadget_ep_disable,
2256         .alloc_request  = dwc3_gadget_ep_alloc_request,
2257         .free_request   = dwc3_gadget_ep_free_request,
2258         .queue          = dwc3_gadget_ep_queue,
2259         .dequeue        = dwc3_gadget_ep_dequeue,
2260         .set_halt       = dwc3_gadget_ep_set_halt,
2261         .set_wedge      = dwc3_gadget_ep_set_wedge,
2262 };
2263
2264 /* -------------------------------------------------------------------------- */
2265
2266 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2267 {
2268         struct dwc3             *dwc = gadget_to_dwc(g);
2269
2270         return __dwc3_gadget_get_frame(dwc);
2271 }
2272
2273 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
2274 {
2275         int                     retries;
2276
2277         int                     ret;
2278         u32                     reg;
2279
2280         u8                      link_state;
2281
2282         /*
2283          * According to the Databook Remote wakeup request should
2284          * be issued only when the device is in early suspend state.
2285          *
2286          * We can check that via USB Link State bits in DSTS register.
2287          */
2288         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2289
2290         link_state = DWC3_DSTS_USBLNKST(reg);
2291
2292         switch (link_state) {
2293         case DWC3_LINK_STATE_RESET:
2294         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
2295         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
2296         case DWC3_LINK_STATE_U2:        /* in HS, means Sleep (L1) */
2297         case DWC3_LINK_STATE_U1:
2298         case DWC3_LINK_STATE_RESUME:
2299                 break;
2300         default:
2301                 return -EINVAL;
2302         }
2303
2304         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2305         if (ret < 0) {
2306                 dev_err(dwc->dev, "failed to put link in Recovery\n");
2307                 return ret;
2308         }
2309
2310         /* Recent versions do this automatically */
2311         if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2312                 /* write zeroes to Link Change Request */
2313                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2314                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2315                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2316         }
2317
2318         /* poll until Link State changes to ON */
2319         retries = 20000;
2320
2321         while (retries--) {
2322                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2323
2324                 /* in HS, means ON */
2325                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2326                         break;
2327         }
2328
2329         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2330                 dev_err(dwc->dev, "failed to send remote wakeup\n");
2331                 return -EINVAL;
2332         }
2333
2334         return 0;
2335 }
2336
2337 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2338 {
2339         struct dwc3             *dwc = gadget_to_dwc(g);
2340         unsigned long           flags;
2341         int                     ret;
2342
2343         spin_lock_irqsave(&dwc->lock, flags);
2344         ret = __dwc3_gadget_wakeup(dwc);
2345         spin_unlock_irqrestore(&dwc->lock, flags);
2346
2347         return ret;
2348 }
2349
2350 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2351                 int is_selfpowered)
2352 {
2353         struct dwc3             *dwc = gadget_to_dwc(g);
2354         unsigned long           flags;
2355
2356         spin_lock_irqsave(&dwc->lock, flags);
2357         g->is_selfpowered = !!is_selfpowered;
2358         spin_unlock_irqrestore(&dwc->lock, flags);
2359
2360         return 0;
2361 }
2362
2363 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2364 {
2365         u32 epnum;
2366
2367         for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2368                 struct dwc3_ep *dep;
2369
2370                 dep = dwc->eps[epnum];
2371                 if (!dep)
2372                         continue;
2373
2374                 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2375         }
2376 }
2377
2378 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2379 {
2380         enum usb_ssp_rate       ssp_rate = dwc->gadget_ssp_rate;
2381         u32                     reg;
2382
2383         if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2384                 ssp_rate = dwc->max_ssp_rate;
2385
2386         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2387         reg &= ~DWC3_DCFG_SPEED_MASK;
2388         reg &= ~DWC3_DCFG_NUMLANES(~0);
2389
2390         if (ssp_rate == USB_SSP_GEN_1x2)
2391                 reg |= DWC3_DCFG_SUPERSPEED;
2392         else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2393                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2394
2395         if (ssp_rate != USB_SSP_GEN_2x1 &&
2396             dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2397                 reg |= DWC3_DCFG_NUMLANES(1);
2398
2399         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2400 }
2401
2402 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2403 {
2404         enum usb_device_speed   speed;
2405         u32                     reg;
2406
2407         speed = dwc->gadget_max_speed;
2408         if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2409                 speed = dwc->maximum_speed;
2410
2411         if (speed == USB_SPEED_SUPER_PLUS &&
2412             DWC3_IP_IS(DWC32)) {
2413                 __dwc3_gadget_set_ssp_rate(dwc);
2414                 return;
2415         }
2416
2417         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2418         reg &= ~(DWC3_DCFG_SPEED_MASK);
2419
2420         /*
2421          * WORKAROUND: DWC3 revision < 2.20a have an issue
2422          * which would cause metastability state on Run/Stop
2423          * bit if we try to force the IP to USB2-only mode.
2424          *
2425          * Because of that, we cannot configure the IP to any
2426          * speed other than the SuperSpeed
2427          *
2428          * Refers to:
2429          *
2430          * STAR#9000525659: Clock Domain Crossing on DCTL in
2431          * USB 2.0 Mode
2432          */
2433         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2434             !dwc->dis_metastability_quirk) {
2435                 reg |= DWC3_DCFG_SUPERSPEED;
2436         } else {
2437                 switch (speed) {
2438                 case USB_SPEED_FULL:
2439                         reg |= DWC3_DCFG_FULLSPEED;
2440                         break;
2441                 case USB_SPEED_HIGH:
2442                         reg |= DWC3_DCFG_HIGHSPEED;
2443                         break;
2444                 case USB_SPEED_SUPER:
2445                         reg |= DWC3_DCFG_SUPERSPEED;
2446                         break;
2447                 case USB_SPEED_SUPER_PLUS:
2448                         if (DWC3_IP_IS(DWC3))
2449                                 reg |= DWC3_DCFG_SUPERSPEED;
2450                         else
2451                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2452                         break;
2453                 default:
2454                         dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2455
2456                         if (DWC3_IP_IS(DWC3))
2457                                 reg |= DWC3_DCFG_SUPERSPEED;
2458                         else
2459                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2460                 }
2461         }
2462
2463         if (DWC3_IP_IS(DWC32) &&
2464             speed > USB_SPEED_UNKNOWN &&
2465             speed < USB_SPEED_SUPER_PLUS)
2466                 reg &= ~DWC3_DCFG_NUMLANES(~0);
2467
2468         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2469 }
2470
2471 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2472 {
2473         u32                     reg;
2474         u32                     timeout = 2000;
2475
2476         if (pm_runtime_suspended(dwc->dev))
2477                 return 0;
2478
2479         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2480         if (is_on) {
2481                 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2482                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
2483                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
2484                 }
2485
2486                 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2487                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2488                 reg |= DWC3_DCTL_RUN_STOP;
2489
2490                 if (dwc->has_hibernation)
2491                         reg |= DWC3_DCTL_KEEP_CONNECT;
2492
2493                 __dwc3_gadget_set_speed(dwc);
2494                 dwc->pullups_connected = true;
2495         } else {
2496                 reg &= ~DWC3_DCTL_RUN_STOP;
2497
2498                 if (dwc->has_hibernation && !suspend)
2499                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2500
2501                 dwc->pullups_connected = false;
2502         }
2503
2504         dwc3_gadget_dctl_write_safe(dwc, reg);
2505
2506         do {
2507                 usleep_range(1000, 2000);
2508                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2509                 reg &= DWC3_DSTS_DEVCTRLHLT;
2510         } while (--timeout && !(!is_on ^ !reg));
2511
2512         if (!timeout)
2513                 return -ETIMEDOUT;
2514
2515         return 0;
2516 }
2517
2518 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2519 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2520 static int __dwc3_gadget_start(struct dwc3 *dwc);
2521
2522 static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2523 {
2524         unsigned long flags;
2525
2526         spin_lock_irqsave(&dwc->lock, flags);
2527         dwc->connected = false;
2528
2529         /*
2530          * Per databook, when we want to stop the gadget, if a control transfer
2531          * is still in process, complete it and get the core into setup phase.
2532          */
2533         if (dwc->ep0state != EP0_SETUP_PHASE) {
2534                 int ret;
2535
2536                 if (dwc->delayed_status)
2537                         dwc3_ep0_send_delayed_status(dwc);
2538
2539                 reinit_completion(&dwc->ep0_in_setup);
2540
2541                 spin_unlock_irqrestore(&dwc->lock, flags);
2542                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2543                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2544                 spin_lock_irqsave(&dwc->lock, flags);
2545                 if (ret == 0)
2546                         dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2547         }
2548
2549         /*
2550          * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2551          * Section 4.1.8 Table 4-7, it states that for a device-initiated
2552          * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2553          * command for any active transfers" before clearing the RunStop
2554          * bit.
2555          */
2556         dwc3_stop_active_transfers(dwc);
2557         __dwc3_gadget_stop(dwc);
2558         spin_unlock_irqrestore(&dwc->lock, flags);
2559
2560         /*
2561          * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2562          * driver needs to acknowledge them before the controller can halt.
2563          * Simply let the interrupt handler acknowledges and handle the
2564          * remaining event generated by the controller while polling for
2565          * DSTS.DEVCTLHLT.
2566          */
2567         return dwc3_gadget_run_stop(dwc, false, false);
2568 }
2569
2570 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2571 {
2572         struct dwc3             *dwc = gadget_to_dwc(g);
2573         int                     ret;
2574
2575         is_on = !!is_on;
2576
2577         dwc->softconnect = is_on;
2578
2579         /*
2580          * Avoid issuing a runtime resume if the device is already in the
2581          * suspended state during gadget disconnect.  DWC3 gadget was already
2582          * halted/stopped during runtime suspend.
2583          */
2584         if (!is_on) {
2585                 pm_runtime_barrier(dwc->dev);
2586                 if (pm_runtime_suspended(dwc->dev))
2587                         return 0;
2588         }
2589
2590         /*
2591          * Check the return value for successful resume, or error.  For a
2592          * successful resume, the DWC3 runtime PM resume routine will handle
2593          * the run stop sequence, so avoid duplicate operations here.
2594          */
2595         ret = pm_runtime_get_sync(dwc->dev);
2596         if (!ret || ret < 0) {
2597                 pm_runtime_put(dwc->dev);
2598                 return 0;
2599         }
2600
2601         if (dwc->pullups_connected == is_on) {
2602                 pm_runtime_put(dwc->dev);
2603                 return 0;
2604         }
2605
2606         synchronize_irq(dwc->irq_gadget);
2607
2608         if (!is_on) {
2609                 ret = dwc3_gadget_soft_disconnect(dwc);
2610         } else {
2611                 /*
2612                  * In the Synopsys DWC_usb31 1.90a programming guide section
2613                  * 4.1.9, it specifies that for a reconnect after a
2614                  * device-initiated disconnect requires a core soft reset
2615                  * (DCTL.CSftRst) before enabling the run/stop bit.
2616                  */
2617                 dwc3_core_soft_reset(dwc);
2618
2619                 dwc3_event_buffers_setup(dwc);
2620                 __dwc3_gadget_start(dwc);
2621                 ret = dwc3_gadget_run_stop(dwc, true, false);
2622         }
2623
2624         pm_runtime_put(dwc->dev);
2625
2626         return ret;
2627 }
2628
2629 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2630 {
2631         u32                     reg;
2632
2633         /* Enable all but Start and End of Frame IRQs */
2634         reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2635                         DWC3_DEVTEN_CMDCMPLTEN |
2636                         DWC3_DEVTEN_ERRTICERREN |
2637                         DWC3_DEVTEN_WKUPEVTEN |
2638                         DWC3_DEVTEN_CONNECTDONEEN |
2639                         DWC3_DEVTEN_USBRSTEN |
2640                         DWC3_DEVTEN_DISCONNEVTEN);
2641
2642         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2643                 reg |= DWC3_DEVTEN_ULSTCNGEN;
2644
2645         /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2646         if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2647                 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2648
2649         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2650 }
2651
2652 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2653 {
2654         /* mask all interrupts */
2655         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2656 }
2657
2658 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2659 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2660
2661 /**
2662  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2663  * @dwc: pointer to our context structure
2664  *
2665  * The following looks like complex but it's actually very simple. In order to
2666  * calculate the number of packets we can burst at once on OUT transfers, we're
2667  * gonna use RxFIFO size.
2668  *
2669  * To calculate RxFIFO size we need two numbers:
2670  * MDWIDTH = size, in bits, of the internal memory bus
2671  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2672  *
2673  * Given these two numbers, the formula is simple:
2674  *
2675  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2676  *
2677  * 24 bytes is for 3x SETUP packets
2678  * 16 bytes is a clock domain crossing tolerance
2679  *
2680  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2681  */
2682 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2683 {
2684         u32 ram2_depth;
2685         u32 mdwidth;
2686         u32 nump;
2687         u32 reg;
2688
2689         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2690         mdwidth = dwc3_mdwidth(dwc);
2691
2692         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2693         nump = min_t(u32, nump, 16);
2694
2695         /* update NumP */
2696         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2697         reg &= ~DWC3_DCFG_NUMP_MASK;
2698         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2699         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2700 }
2701
2702 static int __dwc3_gadget_start(struct dwc3 *dwc)
2703 {
2704         struct dwc3_ep          *dep;
2705         int                     ret = 0;
2706         u32                     reg;
2707
2708         /*
2709          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2710          * the core supports IMOD, disable it.
2711          */
2712         if (dwc->imod_interval) {
2713                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2714                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2715         } else if (dwc3_has_imod(dwc)) {
2716                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2717         }
2718
2719         /*
2720          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2721          * field instead of letting dwc3 itself calculate that automatically.
2722          *
2723          * This way, we maximize the chances that we'll be able to get several
2724          * bursts of data without going through any sort of endpoint throttling.
2725          */
2726         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2727         if (DWC3_IP_IS(DWC3))
2728                 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2729         else
2730                 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2731
2732         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2733
2734         dwc3_gadget_setup_nump(dwc);
2735
2736         /*
2737          * Currently the controller handles single stream only. So, Ignore
2738          * Packet Pending bit for stream selection and don't search for another
2739          * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2740          * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2741          * the stream performance.
2742          */
2743         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2744         reg |= DWC3_DCFG_IGNSTRMPP;
2745         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2746
2747         /* Enable MST by default if the device is capable of MST */
2748         if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2749                 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2750                 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2751                 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2752         }
2753
2754         /* Start with SuperSpeed Default */
2755         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2756
2757         dep = dwc->eps[0];
2758         dep->flags = 0;
2759         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2760         if (ret) {
2761                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2762                 goto err0;
2763         }
2764
2765         dep = dwc->eps[1];
2766         dep->flags = 0;
2767         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2768         if (ret) {
2769                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2770                 goto err1;
2771         }
2772
2773         /* begin to receive SETUP packets */
2774         dwc->ep0state = EP0_SETUP_PHASE;
2775         dwc->ep0_bounced = false;
2776         dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2777         dwc->delayed_status = false;
2778         dwc3_ep0_out_start(dwc);
2779
2780         dwc3_gadget_enable_irq(dwc);
2781
2782         return 0;
2783
2784 err1:
2785         __dwc3_gadget_ep_disable(dwc->eps[0]);
2786
2787 err0:
2788         return ret;
2789 }
2790
2791 static int dwc3_gadget_start(struct usb_gadget *g,
2792                 struct usb_gadget_driver *driver)
2793 {
2794         struct dwc3             *dwc = gadget_to_dwc(g);
2795         unsigned long           flags;
2796         int                     ret;
2797         int                     irq;
2798
2799         irq = dwc->irq_gadget;
2800         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2801                         IRQF_SHARED, "dwc3", dwc->ev_buf);
2802         if (ret) {
2803                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2804                                 irq, ret);
2805                 return ret;
2806         }
2807
2808         spin_lock_irqsave(&dwc->lock, flags);
2809         dwc->gadget_driver      = driver;
2810         spin_unlock_irqrestore(&dwc->lock, flags);
2811
2812         return 0;
2813 }
2814
2815 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2816 {
2817         dwc3_gadget_disable_irq(dwc);
2818         __dwc3_gadget_ep_disable(dwc->eps[0]);
2819         __dwc3_gadget_ep_disable(dwc->eps[1]);
2820 }
2821
2822 static int dwc3_gadget_stop(struct usb_gadget *g)
2823 {
2824         struct dwc3             *dwc = gadget_to_dwc(g);
2825         unsigned long           flags;
2826
2827         spin_lock_irqsave(&dwc->lock, flags);
2828         dwc->gadget_driver      = NULL;
2829         dwc->max_cfg_eps = 0;
2830         spin_unlock_irqrestore(&dwc->lock, flags);
2831
2832         free_irq(dwc->irq_gadget, dwc->ev_buf);
2833
2834         return 0;
2835 }
2836
2837 static void dwc3_gadget_config_params(struct usb_gadget *g,
2838                                       struct usb_dcd_config_params *params)
2839 {
2840         struct dwc3             *dwc = gadget_to_dwc(g);
2841
2842         params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2843         params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2844
2845         /* Recommended BESL */
2846         if (!dwc->dis_enblslpm_quirk) {
2847                 /*
2848                  * If the recommended BESL baseline is 0 or if the BESL deep is
2849                  * less than 2, Microsoft's Windows 10 host usb stack will issue
2850                  * a usb reset immediately after it receives the extended BOS
2851                  * descriptor and the enumeration will fail. To maintain
2852                  * compatibility with the Windows' usb stack, let's set the
2853                  * recommended BESL baseline to 1 and clamp the BESL deep to be
2854                  * within 2 to 15.
2855                  */
2856                 params->besl_baseline = 1;
2857                 if (dwc->is_utmi_l1_suspend)
2858                         params->besl_deep =
2859                                 clamp_t(u8, dwc->hird_threshold, 2, 15);
2860         }
2861
2862         /* U1 Device exit Latency */
2863         if (dwc->dis_u1_entry_quirk)
2864                 params->bU1devExitLat = 0;
2865         else
2866                 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2867
2868         /* U2 Device exit Latency */
2869         if (dwc->dis_u2_entry_quirk)
2870                 params->bU2DevExitLat = 0;
2871         else
2872                 params->bU2DevExitLat =
2873                                 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2874 }
2875
2876 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2877                                   enum usb_device_speed speed)
2878 {
2879         struct dwc3             *dwc = gadget_to_dwc(g);
2880         unsigned long           flags;
2881
2882         spin_lock_irqsave(&dwc->lock, flags);
2883         dwc->gadget_max_speed = speed;
2884         spin_unlock_irqrestore(&dwc->lock, flags);
2885 }
2886
2887 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2888                                      enum usb_ssp_rate rate)
2889 {
2890         struct dwc3             *dwc = gadget_to_dwc(g);
2891         unsigned long           flags;
2892
2893         spin_lock_irqsave(&dwc->lock, flags);
2894         dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2895         dwc->gadget_ssp_rate = rate;
2896         spin_unlock_irqrestore(&dwc->lock, flags);
2897 }
2898
2899 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2900 {
2901         struct dwc3             *dwc = gadget_to_dwc(g);
2902         union power_supply_propval      val = {0};
2903         int                             ret;
2904
2905         if (dwc->usb2_phy)
2906                 return usb_phy_set_power(dwc->usb2_phy, mA);
2907
2908         if (!dwc->usb_psy)
2909                 return -EOPNOTSUPP;
2910
2911         val.intval = 1000 * mA;
2912         ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2913
2914         return ret;
2915 }
2916
2917 /**
2918  * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
2919  * @g: pointer to the USB gadget
2920  *
2921  * Used to record the maximum number of endpoints being used in a USB composite
2922  * device. (across all configurations)  This is to be used in the calculation
2923  * of the TXFIFO sizes when resizing internal memory for individual endpoints.
2924  * It will help ensured that the resizing logic reserves enough space for at
2925  * least one max packet.
2926  */
2927 static int dwc3_gadget_check_config(struct usb_gadget *g)
2928 {
2929         struct dwc3 *dwc = gadget_to_dwc(g);
2930         struct usb_ep *ep;
2931         int fifo_size = 0;
2932         int ram1_depth;
2933         int ep_num = 0;
2934
2935         if (!dwc->do_fifo_resize)
2936                 return 0;
2937
2938         list_for_each_entry(ep, &g->ep_list, ep_list) {
2939                 /* Only interested in the IN endpoints */
2940                 if (ep->claimed && (ep->address & USB_DIR_IN))
2941                         ep_num++;
2942         }
2943
2944         if (ep_num <= dwc->max_cfg_eps)
2945                 return 0;
2946
2947         /* Update the max number of eps in the composition */
2948         dwc->max_cfg_eps = ep_num;
2949
2950         fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
2951         /* Based on the equation, increment by one for every ep */
2952         fifo_size += dwc->max_cfg_eps;
2953
2954         /* Check if we can fit a single fifo per endpoint */
2955         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
2956         if (fifo_size > ram1_depth)
2957                 return -ENOMEM;
2958
2959         return 0;
2960 }
2961
2962 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2963 {
2964         struct dwc3             *dwc = gadget_to_dwc(g);
2965         unsigned long           flags;
2966
2967         spin_lock_irqsave(&dwc->lock, flags);
2968         dwc->async_callbacks = enable;
2969         spin_unlock_irqrestore(&dwc->lock, flags);
2970 }
2971
2972 static const struct usb_gadget_ops dwc3_gadget_ops = {
2973         .get_frame              = dwc3_gadget_get_frame,
2974         .wakeup                 = dwc3_gadget_wakeup,
2975         .set_selfpowered        = dwc3_gadget_set_selfpowered,
2976         .pullup                 = dwc3_gadget_pullup,
2977         .udc_start              = dwc3_gadget_start,
2978         .udc_stop               = dwc3_gadget_stop,
2979         .udc_set_speed          = dwc3_gadget_set_speed,
2980         .udc_set_ssp_rate       = dwc3_gadget_set_ssp_rate,
2981         .get_config_params      = dwc3_gadget_config_params,
2982         .vbus_draw              = dwc3_gadget_vbus_draw,
2983         .check_config           = dwc3_gadget_check_config,
2984         .udc_async_callbacks    = dwc3_gadget_async_callbacks,
2985 };
2986
2987 /* -------------------------------------------------------------------------- */
2988
2989 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2990 {
2991         struct dwc3 *dwc = dep->dwc;
2992
2993         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2994         dep->endpoint.maxburst = 1;
2995         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2996         if (!dep->direction)
2997                 dwc->gadget->ep0 = &dep->endpoint;
2998
2999         dep->endpoint.caps.type_control = true;
3000
3001         return 0;
3002 }
3003
3004 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
3005 {
3006         struct dwc3 *dwc = dep->dwc;
3007         u32 mdwidth;
3008         int size;
3009         int maxpacket;
3010
3011         mdwidth = dwc3_mdwidth(dwc);
3012
3013         /* MDWIDTH is represented in bits, we need it in bytes */
3014         mdwidth /= 8;
3015
3016         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3017         if (DWC3_IP_IS(DWC3))
3018                 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3019         else
3020                 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
3021
3022         /*
3023          * maxpacket size is determined as part of the following, after assuming
3024          * a mult value of one maxpacket:
3025          * DWC3 revision 280A and prior:
3026          * fifo_size = mult * (max_packet / mdwidth) + 1;
3027          * maxpacket = mdwidth * (fifo_size - 1);
3028          *
3029          * DWC3 revision 290A and onwards:
3030          * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3031          * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3032          */
3033         if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3034                 maxpacket = mdwidth * (size - 1);
3035         else
3036                 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3037
3038         /* Functionally, space for one max packet is sufficient */
3039         size = min_t(int, maxpacket, 1024);
3040         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3041
3042         dep->endpoint.max_streams = 16;
3043         dep->endpoint.ops = &dwc3_gadget_ep_ops;
3044         list_add_tail(&dep->endpoint.ep_list,
3045                         &dwc->gadget->ep_list);
3046         dep->endpoint.caps.type_iso = true;
3047         dep->endpoint.caps.type_bulk = true;
3048         dep->endpoint.caps.type_int = true;
3049
3050         return dwc3_alloc_trb_pool(dep);
3051 }
3052
3053 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3054 {
3055         struct dwc3 *dwc = dep->dwc;
3056         u32 mdwidth;
3057         int size;
3058
3059         mdwidth = dwc3_mdwidth(dwc);
3060
3061         /* MDWIDTH is represented in bits, convert to bytes */
3062         mdwidth /= 8;
3063
3064         /* All OUT endpoints share a single RxFIFO space */
3065         size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3066         if (DWC3_IP_IS(DWC3))
3067                 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3068         else
3069                 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3070
3071         /* FIFO depth is in MDWDITH bytes */
3072         size *= mdwidth;
3073
3074         /*
3075          * To meet performance requirement, a minimum recommended RxFIFO size
3076          * is defined as follow:
3077          * RxFIFO size >= (3 x MaxPacketSize) +
3078          * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3079          *
3080          * Then calculate the max packet limit as below.
3081          */
3082         size -= (3 * 8) + 16;
3083         if (size < 0)
3084                 size = 0;
3085         else
3086                 size /= 3;
3087
3088         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3089         dep->endpoint.max_streams = 16;
3090         dep->endpoint.ops = &dwc3_gadget_ep_ops;
3091         list_add_tail(&dep->endpoint.ep_list,
3092                         &dwc->gadget->ep_list);
3093         dep->endpoint.caps.type_iso = true;
3094         dep->endpoint.caps.type_bulk = true;
3095         dep->endpoint.caps.type_int = true;
3096
3097         return dwc3_alloc_trb_pool(dep);
3098 }
3099
3100 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3101 {
3102         struct dwc3_ep                  *dep;
3103         bool                            direction = epnum & 1;
3104         int                             ret;
3105         u8                              num = epnum >> 1;
3106
3107         dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3108         if (!dep)
3109                 return -ENOMEM;
3110
3111         dep->dwc = dwc;
3112         dep->number = epnum;
3113         dep->direction = direction;
3114         dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3115         dwc->eps[epnum] = dep;
3116         dep->combo_num = 0;
3117         dep->start_cmd_status = 0;
3118
3119         snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3120                         direction ? "in" : "out");
3121
3122         dep->endpoint.name = dep->name;
3123
3124         if (!(dep->number > 1)) {
3125                 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3126                 dep->endpoint.comp_desc = NULL;
3127         }
3128
3129         if (num == 0)
3130                 ret = dwc3_gadget_init_control_endpoint(dep);
3131         else if (direction)
3132                 ret = dwc3_gadget_init_in_endpoint(dep);
3133         else
3134                 ret = dwc3_gadget_init_out_endpoint(dep);
3135
3136         if (ret)
3137                 return ret;
3138
3139         dep->endpoint.caps.dir_in = direction;
3140         dep->endpoint.caps.dir_out = !direction;
3141
3142         INIT_LIST_HEAD(&dep->pending_list);
3143         INIT_LIST_HEAD(&dep->started_list);
3144         INIT_LIST_HEAD(&dep->cancelled_list);
3145
3146         dwc3_debugfs_create_endpoint_dir(dep);
3147
3148         return 0;
3149 }
3150
3151 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3152 {
3153         u8                              epnum;
3154
3155         INIT_LIST_HEAD(&dwc->gadget->ep_list);
3156
3157         for (epnum = 0; epnum < total; epnum++) {
3158                 int                     ret;
3159
3160                 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3161                 if (ret)
3162                         return ret;
3163         }
3164
3165         return 0;
3166 }
3167
3168 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3169 {
3170         struct dwc3_ep                  *dep;
3171         u8                              epnum;
3172
3173         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3174                 dep = dwc->eps[epnum];
3175                 if (!dep)
3176                         continue;
3177                 /*
3178                  * Physical endpoints 0 and 1 are special; they form the
3179                  * bi-directional USB endpoint 0.
3180                  *
3181                  * For those two physical endpoints, we don't allocate a TRB
3182                  * pool nor do we add them the endpoints list. Due to that, we
3183                  * shouldn't do these two operations otherwise we would end up
3184                  * with all sorts of bugs when removing dwc3.ko.
3185                  */
3186                 if (epnum != 0 && epnum != 1) {
3187                         dwc3_free_trb_pool(dep);
3188                         list_del(&dep->endpoint.ep_list);
3189                 }
3190
3191                 dwc3_debugfs_remove_endpoint_dir(dep);
3192                 kfree(dep);
3193         }
3194 }
3195
3196 /* -------------------------------------------------------------------------- */
3197
3198 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3199                 struct dwc3_request *req, struct dwc3_trb *trb,
3200                 const struct dwc3_event_depevt *event, int status, int chain)
3201 {
3202         unsigned int            count;
3203
3204         dwc3_ep_inc_deq(dep);
3205
3206         trace_dwc3_complete_trb(dep, trb);
3207         req->num_trbs--;
3208
3209         /*
3210          * If we're in the middle of series of chained TRBs and we
3211          * receive a short transfer along the way, DWC3 will skip
3212          * through all TRBs including the last TRB in the chain (the
3213          * where CHN bit is zero. DWC3 will also avoid clearing HWO
3214          * bit and SW has to do it manually.
3215          *
3216          * We're going to do that here to avoid problems of HW trying
3217          * to use bogus TRBs for transfers.
3218          */
3219         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3220                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3221
3222         /*
3223          * For isochronous transfers, the first TRB in a service interval must
3224          * have the Isoc-First type. Track and report its interval frame number.
3225          */
3226         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3227             (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3228                 unsigned int frame_number;
3229
3230                 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3231                 frame_number &= ~(dep->interval - 1);
3232                 req->request.frame_number = frame_number;
3233         }
3234
3235         /*
3236          * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3237          * this TRB points to the bounce buffer address, it's a MPS alignment
3238          * TRB. Don't add it to req->remaining calculation.
3239          */
3240         if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3241             trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3242                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3243                 return 1;
3244         }
3245
3246         count = trb->size & DWC3_TRB_SIZE_MASK;
3247         req->remaining += count;
3248
3249         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3250                 return 1;
3251
3252         if (event->status & DEPEVT_STATUS_SHORT && !chain)
3253                 return 1;
3254
3255         if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3256             DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3257                 return 1;
3258
3259         if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3260             (trb->ctrl & DWC3_TRB_CTRL_LST))
3261                 return 1;
3262
3263         return 0;
3264 }
3265
3266 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3267                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3268                 int status)
3269 {
3270         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3271         struct scatterlist *sg = req->sg;
3272         struct scatterlist *s;
3273         unsigned int num_queued = req->num_queued_sgs;
3274         unsigned int i;
3275         int ret = 0;
3276
3277         for_each_sg(sg, s, num_queued, i) {
3278                 trb = &dep->trb_pool[dep->trb_dequeue];
3279
3280                 req->sg = sg_next(s);
3281                 req->num_queued_sgs--;
3282
3283                 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3284                                 trb, event, status, true);
3285                 if (ret)
3286                         break;
3287         }
3288
3289         return ret;
3290 }
3291
3292 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3293                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3294                 int status)
3295 {
3296         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3297
3298         return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3299                         event, status, false);
3300 }
3301
3302 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3303 {
3304         return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3305 }
3306
3307 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3308                 const struct dwc3_event_depevt *event,
3309                 struct dwc3_request *req, int status)
3310 {
3311         int request_status;
3312         int ret;
3313
3314         if (req->request.num_mapped_sgs)
3315                 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3316                                 status);
3317         else
3318                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3319                                 status);
3320
3321         req->request.actual = req->request.length - req->remaining;
3322
3323         if (!dwc3_gadget_ep_request_completed(req))
3324                 goto out;
3325
3326         if (req->needs_extra_trb) {
3327                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3328                                 status);
3329                 req->needs_extra_trb = false;
3330         }
3331
3332         /*
3333          * The event status only reflects the status of the TRB with IOC set.
3334          * For the requests that don't set interrupt on completion, the driver
3335          * needs to check and return the status of the completed TRBs associated
3336          * with the request. Use the status of the last TRB of the request.
3337          */
3338         if (req->request.no_interrupt) {
3339                 struct dwc3_trb *trb;
3340
3341                 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3342                 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3343                 case DWC3_TRBSTS_MISSED_ISOC:
3344                         /* Isoc endpoint only */
3345                         request_status = -EXDEV;
3346                         break;
3347                 case DWC3_TRB_STS_XFER_IN_PROG:
3348                         /* Applicable when End Transfer with ForceRM=0 */
3349                 case DWC3_TRBSTS_SETUP_PENDING:
3350                         /* Control endpoint only */
3351                 case DWC3_TRBSTS_OK:
3352                 default:
3353                         request_status = 0;
3354                         break;
3355                 }
3356         } else {
3357                 request_status = status;
3358         }
3359
3360         dwc3_gadget_giveback(dep, req, request_status);
3361
3362 out:
3363         return ret;
3364 }
3365
3366 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3367                 const struct dwc3_event_depevt *event, int status)
3368 {
3369         struct dwc3_request     *req;
3370
3371         while (!list_empty(&dep->started_list)) {
3372                 int ret;
3373
3374                 req = next_request(&dep->started_list);
3375                 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3376                                 req, status);
3377                 if (ret)
3378                         break;
3379                 /*
3380                  * The endpoint is disabled, let the dwc3_remove_requests()
3381                  * handle the cleanup.
3382                  */
3383                 if (!dep->endpoint.desc)
3384                         break;
3385         }
3386 }
3387
3388 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3389 {
3390         struct dwc3_request     *req;
3391         struct dwc3             *dwc = dep->dwc;
3392
3393         if (!dep->endpoint.desc || !dwc->pullups_connected ||
3394             !dwc->connected)
3395                 return false;
3396
3397         if (!list_empty(&dep->pending_list))
3398                 return true;
3399
3400         /*
3401          * We only need to check the first entry of the started list. We can
3402          * assume the completed requests are removed from the started list.
3403          */
3404         req = next_request(&dep->started_list);
3405         if (!req)
3406                 return false;
3407
3408         return !dwc3_gadget_ep_request_completed(req);
3409 }
3410
3411 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3412                 const struct dwc3_event_depevt *event)
3413 {
3414         dep->frame_number = event->parameters;
3415 }
3416
3417 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3418                 const struct dwc3_event_depevt *event, int status)
3419 {
3420         struct dwc3             *dwc = dep->dwc;
3421         bool                    no_started_trb = true;
3422
3423         dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3424
3425         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3426                 goto out;
3427
3428         if (!dep->endpoint.desc)
3429                 return no_started_trb;
3430
3431         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3432                 list_empty(&dep->started_list) &&
3433                 (list_empty(&dep->pending_list) || status == -EXDEV))
3434                 dwc3_stop_active_transfer(dep, true, true);
3435         else if (dwc3_gadget_ep_should_continue(dep))
3436                 if (__dwc3_gadget_kick_transfer(dep) == 0)
3437                         no_started_trb = false;
3438
3439 out:
3440         /*
3441          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3442          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3443          */
3444         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3445                 u32             reg;
3446                 int             i;
3447
3448                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3449                         dep = dwc->eps[i];
3450
3451                         if (!(dep->flags & DWC3_EP_ENABLED))
3452                                 continue;
3453
3454                         if (!list_empty(&dep->started_list))
3455                                 return no_started_trb;
3456                 }
3457
3458                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3459                 reg |= dwc->u1u2;
3460                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3461
3462                 dwc->u1u2 = 0;
3463         }
3464
3465         return no_started_trb;
3466 }
3467
3468 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3469                 const struct dwc3_event_depevt *event)
3470 {
3471         int status = 0;
3472
3473         if (!dep->endpoint.desc)
3474                 return;
3475
3476         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3477                 dwc3_gadget_endpoint_frame_from_event(dep, event);
3478
3479         if (event->status & DEPEVT_STATUS_BUSERR)
3480                 status = -ECONNRESET;
3481
3482         if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3483                 status = -EXDEV;
3484
3485         dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3486 }
3487
3488 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3489                 const struct dwc3_event_depevt *event)
3490 {
3491         int status = 0;
3492
3493         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3494
3495         if (event->status & DEPEVT_STATUS_BUSERR)
3496                 status = -ECONNRESET;
3497
3498         if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3499                 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3500 }
3501
3502 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3503                 const struct dwc3_event_depevt *event)
3504 {
3505         dwc3_gadget_endpoint_frame_from_event(dep, event);
3506
3507         /*
3508          * The XferNotReady event is generated only once before the endpoint
3509          * starts. It will be generated again when END_TRANSFER command is
3510          * issued. For some controller versions, the XferNotReady event may be
3511          * generated while the END_TRANSFER command is still in process. Ignore
3512          * it and wait for the next XferNotReady event after the command is
3513          * completed.
3514          */
3515         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3516                 return;
3517
3518         (void) __dwc3_gadget_start_isoc(dep);
3519 }
3520
3521 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3522                 const struct dwc3_event_depevt *event)
3523 {
3524         u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3525
3526         if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3527                 return;
3528
3529         /*
3530          * The END_TRANSFER command will cause the controller to generate a
3531          * NoStream Event, and it's not due to the host DP NoStream rejection.
3532          * Ignore the next NoStream event.
3533          */
3534         if (dep->stream_capable)
3535                 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3536
3537         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3538         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3539         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3540
3541         if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3542                 struct dwc3 *dwc = dep->dwc;
3543
3544                 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3545                 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3546                         struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3547
3548                         dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3549                         if (dwc->delayed_status)
3550                                 __dwc3_gadget_ep0_set_halt(ep0, 1);
3551                         return;
3552                 }
3553
3554                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3555                 if (dwc->clear_stall_protocol == dep->number)
3556                         dwc3_ep0_send_delayed_status(dwc);
3557         }
3558
3559         if ((dep->flags & DWC3_EP_DELAY_START) &&
3560             !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3561                 __dwc3_gadget_kick_transfer(dep);
3562
3563         dep->flags &= ~DWC3_EP_DELAY_START;
3564 }
3565
3566 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3567                 const struct dwc3_event_depevt *event)
3568 {
3569         struct dwc3 *dwc = dep->dwc;
3570
3571         if (event->status == DEPEVT_STREAMEVT_FOUND) {
3572                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3573                 goto out;
3574         }
3575
3576         /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3577         switch (event->parameters) {
3578         case DEPEVT_STREAM_PRIME:
3579                 /*
3580                  * If the host can properly transition the endpoint state from
3581                  * idle to prime after a NoStream rejection, there's no need to
3582                  * force restarting the endpoint to reinitiate the stream. To
3583                  * simplify the check, assume the host follows the USB spec if
3584                  * it primed the endpoint more than once.
3585                  */
3586                 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3587                         if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3588                                 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3589                         else
3590                                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3591                 }
3592
3593                 break;
3594         case DEPEVT_STREAM_NOSTREAM:
3595                 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3596                     !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3597                     (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3598                      !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3599                         break;
3600
3601                 /*
3602                  * If the host rejects a stream due to no active stream, by the
3603                  * USB and xHCI spec, the endpoint will be put back to idle
3604                  * state. When the host is ready (buffer added/updated), it will
3605                  * prime the endpoint to inform the usb device controller. This
3606                  * triggers the device controller to issue ERDY to restart the
3607                  * stream. However, some hosts don't follow this and keep the
3608                  * endpoint in the idle state. No prime will come despite host
3609                  * streams are updated, and the device controller will not be
3610                  * triggered to generate ERDY to move the next stream data. To
3611                  * workaround this and maintain compatibility with various
3612                  * hosts, force to reinitiate the stream until the host is ready
3613                  * instead of waiting for the host to prime the endpoint.
3614                  */
3615                 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3616                         unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3617
3618                         dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3619                 } else {
3620                         dep->flags |= DWC3_EP_DELAY_START;
3621                         dwc3_stop_active_transfer(dep, true, true);
3622                         return;
3623                 }
3624                 break;
3625         }
3626
3627 out:
3628         dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3629 }
3630
3631 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3632                 const struct dwc3_event_depevt *event)
3633 {
3634         struct dwc3_ep          *dep;
3635         u8                      epnum = event->endpoint_number;
3636
3637         dep = dwc->eps[epnum];
3638
3639         if (!(dep->flags & DWC3_EP_ENABLED)) {
3640                 if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
3641                         return;
3642
3643                 /* Handle only EPCMDCMPLT when EP disabled */
3644                 if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
3645                         !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
3646                         return;
3647         }
3648
3649         if (epnum == 0 || epnum == 1) {
3650                 dwc3_ep0_interrupt(dwc, event);
3651                 return;
3652         }
3653
3654         switch (event->endpoint_event) {
3655         case DWC3_DEPEVT_XFERINPROGRESS:
3656                 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3657                 break;
3658         case DWC3_DEPEVT_XFERNOTREADY:
3659                 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3660                 break;
3661         case DWC3_DEPEVT_EPCMDCMPLT:
3662                 dwc3_gadget_endpoint_command_complete(dep, event);
3663                 break;
3664         case DWC3_DEPEVT_XFERCOMPLETE:
3665                 dwc3_gadget_endpoint_transfer_complete(dep, event);
3666                 break;
3667         case DWC3_DEPEVT_STREAMEVT:
3668                 dwc3_gadget_endpoint_stream_event(dep, event);
3669                 break;
3670         case DWC3_DEPEVT_RXTXFIFOEVT:
3671                 break;
3672         }
3673 }
3674
3675 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3676 {
3677         if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3678                 spin_unlock(&dwc->lock);
3679                 dwc->gadget_driver->disconnect(dwc->gadget);
3680                 spin_lock(&dwc->lock);
3681         }
3682 }
3683
3684 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3685 {
3686         if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3687                 spin_unlock(&dwc->lock);
3688                 dwc->gadget_driver->suspend(dwc->gadget);
3689                 spin_lock(&dwc->lock);
3690         }
3691 }
3692
3693 static void dwc3_resume_gadget(struct dwc3 *dwc)
3694 {
3695         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3696                 spin_unlock(&dwc->lock);
3697                 dwc->gadget_driver->resume(dwc->gadget);
3698                 spin_lock(&dwc->lock);
3699         }
3700 }
3701
3702 static void dwc3_reset_gadget(struct dwc3 *dwc)
3703 {
3704         if (!dwc->gadget_driver)
3705                 return;
3706
3707         if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3708                 spin_unlock(&dwc->lock);
3709                 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3710                 spin_lock(&dwc->lock);
3711         }
3712 }
3713
3714 void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3715         bool interrupt)
3716 {
3717         struct dwc3 *dwc = dep->dwc;
3718
3719         /*
3720          * Only issue End Transfer command to the control endpoint of a started
3721          * Data Phase. Typically we should only do so in error cases such as
3722          * invalid/unexpected direction as described in the control transfer
3723          * flow of the programming guide.
3724          */
3725         if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3726                 return;
3727
3728         if (interrupt && (dep->flags & DWC3_EP_DELAY_STOP))
3729                 return;
3730
3731         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3732             (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3733                 return;
3734
3735         /*
3736          * If a Setup packet is received but yet to DMA out, the controller will
3737          * not process the End Transfer command of any endpoint. Polling of its
3738          * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3739          * timeout. Delay issuing the End Transfer command until the Setup TRB is
3740          * prepared.
3741          */
3742         if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3743                 dep->flags |= DWC3_EP_DELAY_STOP;
3744                 return;
3745         }
3746
3747         /*
3748          * NOTICE: We are violating what the Databook says about the
3749          * EndTransfer command. Ideally we would _always_ wait for the
3750          * EndTransfer Command Completion IRQ, but that's causing too
3751          * much trouble synchronizing between us and gadget driver.
3752          *
3753          * We have discussed this with the IP Provider and it was
3754          * suggested to giveback all requests here.
3755          *
3756          * Note also that a similar handling was tested by Synopsys
3757          * (thanks a lot Paul) and nothing bad has come out of it.
3758          * In short, what we're doing is issuing EndTransfer with
3759          * CMDIOC bit set and delay kicking transfer until the
3760          * EndTransfer command had completed.
3761          *
3762          * As of IP version 3.10a of the DWC_usb3 IP, the controller
3763          * supports a mode to work around the above limitation. The
3764          * software can poll the CMDACT bit in the DEPCMD register
3765          * after issuing a EndTransfer command. This mode is enabled
3766          * by writing GUCTL2[14]. This polling is already done in the
3767          * dwc3_send_gadget_ep_cmd() function so if the mode is
3768          * enabled, the EndTransfer command will have completed upon
3769          * returning from this function.
3770          *
3771          * This mode is NOT available on the DWC_usb31 IP.  In this
3772          * case, if the IOC bit is not set, then delay by 1ms
3773          * after issuing the EndTransfer command.  This allows for the
3774          * controller to handle the command completely before DWC3
3775          * remove requests attempts to unmap USB request buffers.
3776          */
3777
3778         __dwc3_stop_active_transfer(dep, force, interrupt);
3779 }
3780
3781 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3782 {
3783         u32 epnum;
3784
3785         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3786                 struct dwc3_ep *dep;
3787                 int ret;
3788
3789                 dep = dwc->eps[epnum];
3790                 if (!dep)
3791                         continue;
3792
3793                 if (!(dep->flags & DWC3_EP_STALL))
3794                         continue;
3795
3796                 dep->flags &= ~DWC3_EP_STALL;
3797
3798                 ret = dwc3_send_clear_stall_ep_cmd(dep);
3799                 WARN_ON_ONCE(ret);
3800         }
3801 }
3802
3803 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3804 {
3805         int                     reg;
3806
3807         dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3808
3809         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3810         reg &= ~DWC3_DCTL_INITU1ENA;
3811         reg &= ~DWC3_DCTL_INITU2ENA;
3812         dwc3_gadget_dctl_write_safe(dwc, reg);
3813
3814         dwc->connected = false;
3815
3816         dwc3_disconnect_gadget(dwc);
3817
3818         dwc->gadget->speed = USB_SPEED_UNKNOWN;
3819         dwc->setup_packet_pending = false;
3820         usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3821
3822         if (dwc->ep0state != EP0_SETUP_PHASE) {
3823                 unsigned int    dir;
3824
3825                 dir = !!dwc->ep0_expect_in;
3826                 if (dwc->ep0state == EP0_DATA_PHASE)
3827                         dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
3828                 else
3829                         dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
3830                 dwc3_ep0_stall_and_restart(dwc);
3831         }
3832 }
3833
3834 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3835 {
3836         u32                     reg;
3837
3838         /*
3839          * Ideally, dwc3_reset_gadget() would trigger the function
3840          * drivers to stop any active transfers through ep disable.
3841          * However, for functions which defer ep disable, such as mass
3842          * storage, we will need to rely on the call to stop active
3843          * transfers here, and avoid allowing of request queuing.
3844          */
3845         dwc->connected = false;
3846
3847         /*
3848          * WORKAROUND: DWC3 revisions <1.88a have an issue which
3849          * would cause a missing Disconnect Event if there's a
3850          * pending Setup Packet in the FIFO.
3851          *
3852          * There's no suggested workaround on the official Bug
3853          * report, which states that "unless the driver/application
3854          * is doing any special handling of a disconnect event,
3855          * there is no functional issue".
3856          *
3857          * Unfortunately, it turns out that we _do_ some special
3858          * handling of a disconnect event, namely complete all
3859          * pending transfers, notify gadget driver of the
3860          * disconnection, and so on.
3861          *
3862          * Our suggested workaround is to follow the Disconnect
3863          * Event steps here, instead, based on a setup_packet_pending
3864          * flag. Such flag gets set whenever we have a SETUP_PENDING
3865          * status for EP0 TRBs and gets cleared on XferComplete for the
3866          * same endpoint.
3867          *
3868          * Refers to:
3869          *
3870          * STAR#9000466709: RTL: Device : Disconnect event not
3871          * generated if setup packet pending in FIFO
3872          */
3873         if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3874                 if (dwc->setup_packet_pending)
3875                         dwc3_gadget_disconnect_interrupt(dwc);
3876         }
3877
3878         dwc3_reset_gadget(dwc);
3879
3880         /*
3881          * From SNPS databook section 8.1.2, the EP0 should be in setup
3882          * phase. So ensure that EP0 is in setup phase by issuing a stall
3883          * and restart if EP0 is not in setup phase.
3884          */
3885         if (dwc->ep0state != EP0_SETUP_PHASE) {
3886                 unsigned int    dir;
3887
3888                 dir = !!dwc->ep0_expect_in;
3889                 if (dwc->ep0state == EP0_DATA_PHASE)
3890                         dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
3891                 else
3892                         dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
3893
3894                 dwc->eps[0]->trb_enqueue = 0;
3895                 dwc->eps[1]->trb_enqueue = 0;
3896
3897                 dwc3_ep0_stall_and_restart(dwc);
3898         }
3899
3900         /*
3901          * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3902          * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3903          * needs to ensure that it sends "a DEPENDXFER command for any active
3904          * transfers."
3905          */
3906         dwc3_stop_active_transfers(dwc);
3907         dwc->connected = true;
3908
3909         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3910         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3911         dwc3_gadget_dctl_write_safe(dwc, reg);
3912         dwc->test_mode = false;
3913         dwc3_clear_stall_all_ep(dwc);
3914
3915         /* Reset device address to zero */
3916         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3917         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3918         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3919 }
3920
3921 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3922 {
3923         struct dwc3_ep          *dep;
3924         int                     ret;
3925         u32                     reg;
3926         u8                      lanes = 1;
3927         u8                      speed;
3928
3929         if (!dwc->softconnect)
3930                 return;
3931
3932         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3933         speed = reg & DWC3_DSTS_CONNECTSPD;
3934         dwc->speed = speed;
3935
3936         if (DWC3_IP_IS(DWC32))
3937                 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3938
3939         dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3940
3941         /*
3942          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3943          * each time on Connect Done.
3944          *
3945          * Currently we always use the reset value. If any platform
3946          * wants to set this to a different value, we need to add a
3947          * setting and update GCTL.RAMCLKSEL here.
3948          */
3949
3950         switch (speed) {
3951         case DWC3_DSTS_SUPERSPEED_PLUS:
3952                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3953                 dwc->gadget->ep0->maxpacket = 512;
3954                 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3955
3956                 if (lanes > 1)
3957                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3958                 else
3959                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3960                 break;
3961         case DWC3_DSTS_SUPERSPEED:
3962                 /*
3963                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
3964                  * would cause a missing USB3 Reset event.
3965                  *
3966                  * In such situations, we should force a USB3 Reset
3967                  * event by calling our dwc3_gadget_reset_interrupt()
3968                  * routine.
3969                  *
3970                  * Refers to:
3971                  *
3972                  * STAR#9000483510: RTL: SS : USB3 reset event may
3973                  * not be generated always when the link enters poll
3974                  */
3975                 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3976                         dwc3_gadget_reset_interrupt(dwc);
3977
3978                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3979                 dwc->gadget->ep0->maxpacket = 512;
3980                 dwc->gadget->speed = USB_SPEED_SUPER;
3981
3982                 if (lanes > 1) {
3983                         dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3984                         dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3985                 }
3986                 break;
3987         case DWC3_DSTS_HIGHSPEED:
3988                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3989                 dwc->gadget->ep0->maxpacket = 64;
3990                 dwc->gadget->speed = USB_SPEED_HIGH;
3991                 break;
3992         case DWC3_DSTS_FULLSPEED:
3993                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3994                 dwc->gadget->ep0->maxpacket = 64;
3995                 dwc->gadget->speed = USB_SPEED_FULL;
3996                 break;
3997         }
3998
3999         dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
4000
4001         /* Enable USB2 LPM Capability */
4002
4003         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
4004             !dwc->usb2_gadget_lpm_disable &&
4005             (speed != DWC3_DSTS_SUPERSPEED) &&
4006             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4007                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4008                 reg |= DWC3_DCFG_LPM_CAP;
4009                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4010
4011                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4012                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4013
4014                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
4015                                             (dwc->is_utmi_l1_suspend << 4));
4016
4017                 /*
4018                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
4019                  * DCFG.LPMCap is set, core responses with an ACK and the
4020                  * BESL value in the LPM token is less than or equal to LPM
4021                  * NYET threshold.
4022                  */
4023                 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
4024                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
4025
4026                 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
4027                         reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
4028
4029                 dwc3_gadget_dctl_write_safe(dwc, reg);
4030         } else {
4031                 if (dwc->usb2_gadget_lpm_disable) {
4032                         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4033                         reg &= ~DWC3_DCFG_LPM_CAP;
4034                         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4035                 }
4036
4037                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4038                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4039                 dwc3_gadget_dctl_write_safe(dwc, reg);
4040         }
4041
4042         dep = dwc->eps[0];
4043         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4044         if (ret) {
4045                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4046                 return;
4047         }
4048
4049         dep = dwc->eps[1];
4050         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4051         if (ret) {
4052                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4053                 return;
4054         }
4055
4056         /*
4057          * Configure PHY via GUSB3PIPECTLn if required.
4058          *
4059          * Update GTXFIFOSIZn
4060          *
4061          * In both cases reset values should be sufficient.
4062          */
4063 }
4064
4065 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
4066 {
4067         /*
4068          * TODO take core out of low power mode when that's
4069          * implemented.
4070          */
4071
4072         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4073                 spin_unlock(&dwc->lock);
4074                 dwc->gadget_driver->resume(dwc->gadget);
4075                 spin_lock(&dwc->lock);
4076         }
4077 }
4078
4079 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4080                 unsigned int evtinfo)
4081 {
4082         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
4083         unsigned int            pwropt;
4084
4085         /*
4086          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4087          * Hibernation mode enabled which would show up when device detects
4088          * host-initiated U3 exit.
4089          *
4090          * In that case, device will generate a Link State Change Interrupt
4091          * from U3 to RESUME which is only necessary if Hibernation is
4092          * configured in.
4093          *
4094          * There are no functional changes due to such spurious event and we
4095          * just need to ignore it.
4096          *
4097          * Refers to:
4098          *
4099          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4100          * operational mode
4101          */
4102         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4103         if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4104                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4105                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4106                                 (next == DWC3_LINK_STATE_RESUME)) {
4107                         return;
4108                 }
4109         }
4110
4111         /*
4112          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4113          * on the link partner, the USB session might do multiple entry/exit
4114          * of low power states before a transfer takes place.
4115          *
4116          * Due to this problem, we might experience lower throughput. The
4117          * suggested workaround is to disable DCTL[12:9] bits if we're
4118          * transitioning from U1/U2 to U0 and enable those bits again
4119          * after a transfer completes and there are no pending transfers
4120          * on any of the enabled endpoints.
4121          *
4122          * This is the first half of that workaround.
4123          *
4124          * Refers to:
4125          *
4126          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4127          * core send LGO_Ux entering U0
4128          */
4129         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4130                 if (next == DWC3_LINK_STATE_U0) {
4131                         u32     u1u2;
4132                         u32     reg;
4133
4134                         switch (dwc->link_state) {
4135                         case DWC3_LINK_STATE_U1:
4136                         case DWC3_LINK_STATE_U2:
4137                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4138                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4139                                                 | DWC3_DCTL_ACCEPTU2ENA
4140                                                 | DWC3_DCTL_INITU1ENA
4141                                                 | DWC3_DCTL_ACCEPTU1ENA);
4142
4143                                 if (!dwc->u1u2)
4144                                         dwc->u1u2 = reg & u1u2;
4145
4146                                 reg &= ~u1u2;
4147
4148                                 dwc3_gadget_dctl_write_safe(dwc, reg);
4149                                 break;
4150                         default:
4151                                 /* do nothing */
4152                                 break;
4153                         }
4154                 }
4155         }
4156
4157         switch (next) {
4158         case DWC3_LINK_STATE_U1:
4159                 if (dwc->speed == USB_SPEED_SUPER)
4160                         dwc3_suspend_gadget(dwc);
4161                 break;
4162         case DWC3_LINK_STATE_U2:
4163         case DWC3_LINK_STATE_U3:
4164                 dwc3_suspend_gadget(dwc);
4165                 break;
4166         case DWC3_LINK_STATE_RESUME:
4167                 dwc3_resume_gadget(dwc);
4168                 break;
4169         default:
4170                 /* do nothing */
4171                 break;
4172         }
4173
4174         dwc->link_state = next;
4175 }
4176
4177 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4178                                           unsigned int evtinfo)
4179 {
4180         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4181
4182         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
4183                 dwc3_suspend_gadget(dwc);
4184
4185         dwc->link_state = next;
4186 }
4187
4188 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
4189                 unsigned int evtinfo)
4190 {
4191         unsigned int is_ss = evtinfo & BIT(4);
4192
4193         /*
4194          * WORKAROUND: DWC3 revision 2.20a with hibernation support
4195          * have a known issue which can cause USB CV TD.9.23 to fail
4196          * randomly.
4197          *
4198          * Because of this issue, core could generate bogus hibernation
4199          * events which SW needs to ignore.
4200          *
4201          * Refers to:
4202          *
4203          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
4204          * Device Fallback from SuperSpeed
4205          */
4206         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
4207                 return;
4208
4209         /* enter hibernation here */
4210 }
4211
4212 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4213                 const struct dwc3_event_devt *event)
4214 {
4215         switch (event->type) {
4216         case DWC3_DEVICE_EVENT_DISCONNECT:
4217                 dwc3_gadget_disconnect_interrupt(dwc);
4218                 break;
4219         case DWC3_DEVICE_EVENT_RESET:
4220                 dwc3_gadget_reset_interrupt(dwc);
4221                 break;
4222         case DWC3_DEVICE_EVENT_CONNECT_DONE:
4223                 dwc3_gadget_conndone_interrupt(dwc);
4224                 break;
4225         case DWC3_DEVICE_EVENT_WAKEUP:
4226                 dwc3_gadget_wakeup_interrupt(dwc);
4227                 break;
4228         case DWC3_DEVICE_EVENT_HIBER_REQ:
4229                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
4230                                         "unexpected hibernation event\n"))
4231                         break;
4232
4233                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
4234                 break;
4235         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4236                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4237                 break;
4238         case DWC3_DEVICE_EVENT_SUSPEND:
4239                 /* It changed to be suspend event for version 2.30a and above */
4240                 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
4241                         /*
4242                          * Ignore suspend event until the gadget enters into
4243                          * USB_STATE_CONFIGURED state.
4244                          */
4245                         if (dwc->gadget->state >= USB_STATE_CONFIGURED)
4246                                 dwc3_gadget_suspend_interrupt(dwc,
4247                                                 event->event_info);
4248                 }
4249                 break;
4250         case DWC3_DEVICE_EVENT_SOF:
4251         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4252         case DWC3_DEVICE_EVENT_CMD_CMPL:
4253         case DWC3_DEVICE_EVENT_OVERFLOW:
4254                 break;
4255         default:
4256                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4257         }
4258 }
4259
4260 static void dwc3_process_event_entry(struct dwc3 *dwc,
4261                 const union dwc3_event *event)
4262 {
4263         trace_dwc3_event(event->raw, dwc);
4264
4265         if (!event->type.is_devspec)
4266                 dwc3_endpoint_interrupt(dwc, &event->depevt);
4267         else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4268                 dwc3_gadget_interrupt(dwc, &event->devt);
4269         else
4270                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4271 }
4272
4273 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4274 {
4275         struct dwc3 *dwc = evt->dwc;
4276         irqreturn_t ret = IRQ_NONE;
4277         int left;
4278
4279         left = evt->count;
4280
4281         if (!(evt->flags & DWC3_EVENT_PENDING))
4282                 return IRQ_NONE;
4283
4284         while (left > 0) {
4285                 union dwc3_event event;
4286
4287                 event.raw = *(u32 *) (evt->cache + evt->lpos);
4288
4289                 dwc3_process_event_entry(dwc, &event);
4290
4291                 /*
4292                  * FIXME we wrap around correctly to the next entry as
4293                  * almost all entries are 4 bytes in size. There is one
4294                  * entry which has 12 bytes which is a regular entry
4295                  * followed by 8 bytes data. ATM I don't know how
4296                  * things are organized if we get next to the a
4297                  * boundary so I worry about that once we try to handle
4298                  * that.
4299                  */
4300                 evt->lpos = (evt->lpos + 4) % evt->length;
4301                 left -= 4;
4302         }
4303
4304         evt->count = 0;
4305         ret = IRQ_HANDLED;
4306
4307         /* Unmask interrupt */
4308         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4309                     DWC3_GEVNTSIZ_SIZE(evt->length));
4310
4311         if (dwc->imod_interval) {
4312                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4313                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4314         }
4315
4316         /* Keep the clearing of DWC3_EVENT_PENDING at the end */
4317         evt->flags &= ~DWC3_EVENT_PENDING;
4318
4319         return ret;
4320 }
4321
4322 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4323 {
4324         struct dwc3_event_buffer *evt = _evt;
4325         struct dwc3 *dwc = evt->dwc;
4326         unsigned long flags;
4327         irqreturn_t ret = IRQ_NONE;
4328
4329         local_bh_disable();
4330         spin_lock_irqsave(&dwc->lock, flags);
4331         ret = dwc3_process_event_buf(evt);
4332         spin_unlock_irqrestore(&dwc->lock, flags);
4333         local_bh_enable();
4334
4335         return ret;
4336 }
4337
4338 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4339 {
4340         struct dwc3 *dwc = evt->dwc;
4341         u32 amount;
4342         u32 count;
4343
4344         if (pm_runtime_suspended(dwc->dev)) {
4345                 pm_runtime_get(dwc->dev);
4346                 disable_irq_nosync(dwc->irq_gadget);
4347                 dwc->pending_events = true;
4348                 return IRQ_HANDLED;
4349         }
4350
4351         /*
4352          * With PCIe legacy interrupt, test shows that top-half irq handler can
4353          * be called again after HW interrupt deassertion. Check if bottom-half
4354          * irq event handler completes before caching new event to prevent
4355          * losing events.
4356          */
4357         if (evt->flags & DWC3_EVENT_PENDING)
4358                 return IRQ_HANDLED;
4359
4360         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4361         count &= DWC3_GEVNTCOUNT_MASK;
4362         if (!count)
4363                 return IRQ_NONE;
4364
4365         evt->count = count;
4366         evt->flags |= DWC3_EVENT_PENDING;
4367
4368         /* Mask interrupt */
4369         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4370                     DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4371
4372         amount = min(count, evt->length - evt->lpos);
4373         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4374
4375         if (amount < count)
4376                 memcpy(evt->cache, evt->buf, count - amount);
4377
4378         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4379
4380         return IRQ_WAKE_THREAD;
4381 }
4382
4383 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4384 {
4385         struct dwc3_event_buffer        *evt = _evt;
4386
4387         return dwc3_check_event_buf(evt);
4388 }
4389
4390 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4391 {
4392         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4393         int irq;
4394
4395         irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4396         if (irq > 0)
4397                 goto out;
4398
4399         if (irq == -EPROBE_DEFER)
4400                 goto out;
4401
4402         irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4403         if (irq > 0)
4404                 goto out;
4405
4406         if (irq == -EPROBE_DEFER)
4407                 goto out;
4408
4409         irq = platform_get_irq(dwc3_pdev, 0);
4410         if (irq > 0)
4411                 goto out;
4412
4413         if (!irq)
4414                 irq = -EINVAL;
4415
4416 out:
4417         return irq;
4418 }
4419
4420 static void dwc_gadget_release(struct device *dev)
4421 {
4422         struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4423
4424         kfree(gadget);
4425 }
4426
4427 /**
4428  * dwc3_gadget_init - initializes gadget related registers
4429  * @dwc: pointer to our controller context structure
4430  *
4431  * Returns 0 on success otherwise negative errno.
4432  */
4433 int dwc3_gadget_init(struct dwc3 *dwc)
4434 {
4435         int ret;
4436         int irq;
4437         struct device *dev;
4438
4439         irq = dwc3_gadget_get_irq(dwc);
4440         if (irq < 0) {
4441                 ret = irq;
4442                 goto err0;
4443         }
4444
4445         dwc->irq_gadget = irq;
4446
4447         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4448                                           sizeof(*dwc->ep0_trb) * 2,
4449                                           &dwc->ep0_trb_addr, GFP_KERNEL);
4450         if (!dwc->ep0_trb) {
4451                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4452                 ret = -ENOMEM;
4453                 goto err0;
4454         }
4455
4456         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4457         if (!dwc->setup_buf) {
4458                 ret = -ENOMEM;
4459                 goto err1;
4460         }
4461
4462         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4463                         &dwc->bounce_addr, GFP_KERNEL);
4464         if (!dwc->bounce) {
4465                 ret = -ENOMEM;
4466                 goto err2;
4467         }
4468
4469         init_completion(&dwc->ep0_in_setup);
4470         dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4471         if (!dwc->gadget) {
4472                 ret = -ENOMEM;
4473                 goto err3;
4474         }
4475
4476
4477         usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4478         dev                             = &dwc->gadget->dev;
4479         dev->platform_data              = dwc;
4480         dwc->gadget->ops                = &dwc3_gadget_ops;
4481         dwc->gadget->speed              = USB_SPEED_UNKNOWN;
4482         dwc->gadget->ssp_rate           = USB_SSP_GEN_UNKNOWN;
4483         dwc->gadget->sg_supported       = true;
4484         dwc->gadget->name               = "dwc3-gadget";
4485         dwc->gadget->lpm_capable        = !dwc->usb2_gadget_lpm_disable;
4486
4487         /*
4488          * FIXME We might be setting max_speed to <SUPER, however versions
4489          * <2.20a of dwc3 have an issue with metastability (documented
4490          * elsewhere in this driver) which tells us we can't set max speed to
4491          * anything lower than SUPER.
4492          *
4493          * Because gadget.max_speed is only used by composite.c and function
4494          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4495          * to happen so we avoid sending SuperSpeed Capability descriptor
4496          * together with our BOS descriptor as that could confuse host into
4497          * thinking we can handle super speed.
4498          *
4499          * Note that, in fact, we won't even support GetBOS requests when speed
4500          * is less than super speed because we don't have means, yet, to tell
4501          * composite.c that we are USB 2.0 + LPM ECN.
4502          */
4503         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4504             !dwc->dis_metastability_quirk)
4505                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4506                                 dwc->revision);
4507
4508         dwc->gadget->max_speed          = dwc->maximum_speed;
4509         dwc->gadget->max_ssp_rate       = dwc->max_ssp_rate;
4510
4511         /*
4512          * REVISIT: Here we should clear all pending IRQs to be
4513          * sure we're starting from a well known location.
4514          */
4515
4516         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4517         if (ret)
4518                 goto err4;
4519
4520         ret = usb_add_gadget(dwc->gadget);
4521         if (ret) {
4522                 dev_err(dwc->dev, "failed to add gadget\n");
4523                 goto err5;
4524         }
4525
4526         if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4527                 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4528         else
4529                 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4530
4531         return 0;
4532
4533 err5:
4534         dwc3_gadget_free_endpoints(dwc);
4535 err4:
4536         usb_put_gadget(dwc->gadget);
4537         dwc->gadget = NULL;
4538 err3:
4539         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4540                         dwc->bounce_addr);
4541
4542 err2:
4543         kfree(dwc->setup_buf);
4544
4545 err1:
4546         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4547                         dwc->ep0_trb, dwc->ep0_trb_addr);
4548
4549 err0:
4550         return ret;
4551 }
4552
4553 /* -------------------------------------------------------------------------- */
4554
4555 void dwc3_gadget_exit(struct dwc3 *dwc)
4556 {
4557         if (!dwc->gadget)
4558                 return;
4559
4560         usb_del_gadget(dwc->gadget);
4561         dwc3_gadget_free_endpoints(dwc);
4562         usb_put_gadget(dwc->gadget);
4563         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4564                           dwc->bounce_addr);
4565         kfree(dwc->setup_buf);
4566         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4567                           dwc->ep0_trb, dwc->ep0_trb_addr);
4568 }
4569
4570 int dwc3_gadget_suspend(struct dwc3 *dwc)
4571 {
4572         unsigned long flags;
4573
4574         if (!dwc->gadget_driver)
4575                 return 0;
4576
4577         dwc3_gadget_run_stop(dwc, false, false);
4578
4579         spin_lock_irqsave(&dwc->lock, flags);
4580         dwc3_disconnect_gadget(dwc);
4581         __dwc3_gadget_stop(dwc);
4582         spin_unlock_irqrestore(&dwc->lock, flags);
4583
4584         return 0;
4585 }
4586
4587 int dwc3_gadget_resume(struct dwc3 *dwc)
4588 {
4589         int                     ret;
4590
4591         if (!dwc->gadget_driver || !dwc->softconnect)
4592                 return 0;
4593
4594         ret = __dwc3_gadget_start(dwc);
4595         if (ret < 0)
4596                 goto err0;
4597
4598         ret = dwc3_gadget_run_stop(dwc, true, false);
4599         if (ret < 0)
4600                 goto err1;
4601
4602         return 0;
4603
4604 err1:
4605         __dwc3_gadget_stop(dwc);
4606
4607 err0:
4608         return ret;
4609 }
4610
4611 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4612 {
4613         if (dwc->pending_events) {
4614                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4615                 dwc->pending_events = false;
4616                 enable_irq(dwc->irq_gadget);
4617         }
4618 }