1 // SPDX-License-Identifier: GPL-2.0
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/usb/ch9.h>
22 #include <linux/usb/gadget.h>
23 #include <linux/usb/composite.h>
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
60 trace_dwc3_prepare_trb(dep, trb);
63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
65 struct dwc3_gadget_ep_cmd_params params;
69 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
88 struct dwc3_request *req)
90 struct dwc3 *dwc = dep->dwc;
92 req->request.actual = 0;
93 req->request.status = -EINPROGRESS;
94 req->epnum = dep->number;
96 list_add_tail(&req->list, &dep->pending_list);
99 * Gadget driver might not be quick enough to queue a request
100 * before we get a Transfer Not Ready event on this endpoint.
102 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
103 * flag is set, it's telling us that as soon as Gadget queues the
104 * required request, we should kick the transfer here because the
105 * IRQ we were waiting for is long gone.
107 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
108 unsigned int direction;
110 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
112 if (dwc->ep0state != EP0_DATA_PHASE) {
113 dev_WARN(dwc->dev, "Unexpected pending request\n");
117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
126 * In case gadget driver asked us to delay the STATUS phase,
129 if (dwc->delayed_status) {
130 unsigned int direction;
132 direction = !dwc->ep0_expect_in;
133 dwc->delayed_status = false;
134 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
136 if (dwc->ep0state == EP0_STATUS_PHASE)
137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
143 * Unfortunately we have uncovered a limitation wrt the Data Phase.
145 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
146 * come before issueing Start Transfer command, but if we do, we will
147 * miss situations where the host starts another SETUP phase instead of
148 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
149 * Layer Compliance Suite.
151 * The problem surfaces due to the fact that in case of back-to-back
152 * SETUP packets there will be no XferNotReady(DATA) generated and we
153 * will be stuck waiting for XferNotReady(DATA) forever.
155 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
156 * it tells us to start Data Phase right away. It also mentions that if
157 * we receive a SETUP phase instead of the DATA phase, core will issue
158 * XferComplete for the DATA phase, before actually initiating it in
159 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
160 * can only be used to print some debugging logs, as the core expects
161 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
162 * just so it completes right away, without transferring anything and,
163 * only then, we can go back to the SETUP phase.
165 * Because of this scenario, SNPS decided to change the programming
166 * model of control transfers and support on-demand transfers only for
167 * the STATUS phase. To fix the issue we have now, we will always wait
168 * for gadget driver to queue the DATA phase's struct usb_request, then
169 * start it right away.
171 * If we're actually in a 2-stage transfer, we will wait for
172 * XferNotReady(STATUS).
174 if (dwc->three_stage_setup) {
175 unsigned int direction;
177 direction = dwc->ep0_expect_in;
178 dwc->ep0state = EP0_DATA_PHASE;
180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
182 dep->flags &= ~DWC3_EP0_DIR_IN;
188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 struct dwc3_request *req = to_dwc3_request(request);
192 struct dwc3_ep *dep = to_dwc3_ep(ep);
193 struct dwc3 *dwc = dep->dwc;
199 spin_lock_irqsave(&dwc->lock, flags);
200 if (!dep->endpoint.desc || !dwc->pullups_connected) {
201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
207 /* we share one TRB for ep0/1 */
208 if (!list_empty(&dep->pending_list)) {
213 ret = __dwc3_gadget_ep0_queue(dep, req);
216 spin_unlock_irqrestore(&dwc->lock, flags);
221 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
225 /* reinitialize physical ep1 */
227 dep->flags = DWC3_EP_ENABLED;
229 /* stall is always issued on EP0 */
231 __dwc3_gadget_ep_set_halt(dep, 1, false);
232 dep->flags = DWC3_EP_ENABLED;
233 dwc->delayed_status = false;
235 if (!list_empty(&dep->pending_list)) {
236 struct dwc3_request *req;
238 req = next_request(&dep->pending_list);
240 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
242 dwc3_gadget_giveback(dep, req, -ECONNRESET);
245 dwc->ep0state = EP0_SETUP_PHASE;
246 dwc3_ep0_out_start(dwc);
249 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
251 struct dwc3_ep *dep = to_dwc3_ep(ep);
252 struct dwc3 *dwc = dep->dwc;
254 dwc3_ep0_stall_and_restart(dwc);
259 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
261 struct dwc3_ep *dep = to_dwc3_ep(ep);
262 struct dwc3 *dwc = dep->dwc;
266 spin_lock_irqsave(&dwc->lock, flags);
267 ret = __dwc3_gadget_ep0_set_halt(ep, value);
268 spin_unlock_irqrestore(&dwc->lock, flags);
273 void dwc3_ep0_out_start(struct dwc3 *dwc)
278 complete(&dwc->ep0_in_setup);
281 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
282 DWC3_TRBCTL_CONTROL_SETUP, false);
283 ret = dwc3_ep0_start_trans(dep);
287 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
290 u32 windex = le16_to_cpu(wIndex_le);
293 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
294 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
297 dep = dwc->eps[epnum];
301 if (dep->flags & DWC3_EP_ENABLED)
307 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
313 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
314 struct usb_ctrlrequest *ctrl)
321 __le16 *response_pkt;
323 /* We don't support PTM_STATUS */
324 value = le16_to_cpu(ctrl->wValue);
328 recip = ctrl->bRequestType & USB_RECIP_MASK;
330 case USB_RECIP_DEVICE:
332 * LTM will be set once we know how to set this in HW.
334 usb_status |= dwc->gadget->is_selfpowered;
336 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
337 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
338 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
339 if (reg & DWC3_DCTL_INITU1ENA)
340 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
341 if (reg & DWC3_DCTL_INITU2ENA)
342 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
347 case USB_RECIP_INTERFACE:
349 * Function Remote Wake Capable D0
350 * Function Remote Wakeup D1
354 case USB_RECIP_ENDPOINT:
355 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
359 if (dep->flags & DWC3_EP_STALL)
360 usb_status = 1 << USB_ENDPOINT_HALT;
366 response_pkt = (__le16 *) dwc->setup_buf;
367 *response_pkt = cpu_to_le16(usb_status);
370 dwc->ep0_usb_req.dep = dep;
371 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
372 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
373 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
375 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
378 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
383 if (state != USB_STATE_CONFIGURED)
385 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
386 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
388 if (set && dwc->dis_u1_entry_quirk)
391 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
393 reg |= DWC3_DCTL_INITU1ENA;
395 reg &= ~DWC3_DCTL_INITU1ENA;
396 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
401 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
407 if (state != USB_STATE_CONFIGURED)
409 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
410 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
412 if (set && dwc->dis_u2_entry_quirk)
415 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
417 reg |= DWC3_DCTL_INITU2ENA;
419 reg &= ~DWC3_DCTL_INITU2ENA;
420 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
425 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
428 if ((wIndex & 0xff) != 0)
433 switch (wIndex >> 8) {
436 case USB_TEST_SE0_NAK:
437 case USB_TEST_PACKET:
438 case USB_TEST_FORCE_ENABLE:
439 dwc->test_mode_nr = wIndex >> 8;
440 dwc->test_mode = true;
449 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
450 struct usb_ctrlrequest *ctrl, int set)
452 enum usb_device_state state;
457 wValue = le16_to_cpu(ctrl->wValue);
458 wIndex = le16_to_cpu(ctrl->wIndex);
459 state = dwc->gadget->state;
462 case USB_DEVICE_REMOTE_WAKEUP:
465 * 9.4.1 says only only for SS, in AddressState only for
466 * default control pipe
468 case USB_DEVICE_U1_ENABLE:
469 ret = dwc3_ep0_handle_u1(dwc, state, set);
471 case USB_DEVICE_U2_ENABLE:
472 ret = dwc3_ep0_handle_u2(dwc, state, set);
474 case USB_DEVICE_LTM_ENABLE:
477 case USB_DEVICE_TEST_MODE:
478 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
487 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
488 struct usb_ctrlrequest *ctrl, int set)
493 wValue = le16_to_cpu(ctrl->wValue);
496 case USB_INTRF_FUNC_SUSPEND:
498 * REVISIT: Ideally we would enable some low power mode here,
499 * however it's unclear what we should be doing here.
501 * For now, we're not doing anything, just making sure we return
502 * 0 so USB Command Verifier tests pass without any errors.
512 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
513 struct usb_ctrlrequest *ctrl, int set)
519 wValue = le16_to_cpu(ctrl->wValue);
522 case USB_ENDPOINT_HALT:
523 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
527 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
530 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
534 /* ClearFeature(Halt) may need delayed status */
535 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
536 return USB_GADGET_DELAYED_STATUS;
546 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
547 struct usb_ctrlrequest *ctrl, int set)
552 recip = ctrl->bRequestType & USB_RECIP_MASK;
555 case USB_RECIP_DEVICE:
556 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
558 case USB_RECIP_INTERFACE:
559 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
561 case USB_RECIP_ENDPOINT:
562 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
571 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
573 enum usb_device_state state = dwc->gadget->state;
577 addr = le16_to_cpu(ctrl->wValue);
579 dev_err(dwc->dev, "invalid device address %d\n", addr);
583 if (state == USB_STATE_CONFIGURED) {
584 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
588 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
589 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
590 reg |= DWC3_DCFG_DEVADDR(addr);
591 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
594 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
596 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
601 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
605 spin_unlock(&dwc->lock);
606 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
607 spin_lock(&dwc->lock);
611 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
613 enum usb_device_state state = dwc->gadget->state;
618 cfg = le16_to_cpu(ctrl->wValue);
621 case USB_STATE_DEFAULT:
624 case USB_STATE_ADDRESS:
625 ret = dwc3_ep0_delegate_req(dwc, ctrl);
626 /* if the cfg matches and the cfg is non zero */
627 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
630 * only change state if set_config has already
631 * been processed. If gadget driver returns
632 * USB_GADGET_DELAYED_STATUS, we will wait
633 * to change the state on the next usb_ep_queue()
636 usb_gadget_set_state(dwc->gadget,
637 USB_STATE_CONFIGURED);
640 * Enable transition to U1/U2 state when
641 * nothing is pending from application.
643 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
644 if (!dwc->dis_u1_entry_quirk)
645 reg |= DWC3_DCTL_ACCEPTU1ENA;
646 if (!dwc->dis_u2_entry_quirk)
647 reg |= DWC3_DCTL_ACCEPTU2ENA;
648 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
652 case USB_STATE_CONFIGURED:
653 ret = dwc3_ep0_delegate_req(dwc, ctrl);
655 usb_gadget_set_state(dwc->gadget,
664 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
666 struct dwc3_ep *dep = to_dwc3_ep(ep);
667 struct dwc3 *dwc = dep->dwc;
681 memcpy(&timing, req->buf, sizeof(timing));
683 dwc->u1sel = timing.u1sel;
684 dwc->u1pel = timing.u1pel;
685 dwc->u2sel = le16_to_cpu(timing.u2sel);
686 dwc->u2pel = le16_to_cpu(timing.u2pel);
688 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
689 if (reg & DWC3_DCTL_INITU2ENA)
691 if (reg & DWC3_DCTL_INITU1ENA)
695 * According to Synopsys Databook, if parameter is
696 * greater than 125, a value of zero should be
697 * programmed in the register.
702 /* now that we have the time, issue DGCMD Set Sel */
703 ret = dwc3_send_gadget_generic_command(dwc,
704 DWC3_DGCMD_SET_PERIODIC_PAR, param);
708 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
711 enum usb_device_state state = dwc->gadget->state;
714 if (state == USB_STATE_DEFAULT)
717 wLength = le16_to_cpu(ctrl->wLength);
720 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
726 * To handle Set SEL we need to receive 6 bytes from Host. So let's
727 * queue a usb_request for 6 bytes.
729 * Remember, though, this controller can't handle non-wMaxPacketSize
730 * aligned transfers on the OUT direction, so we queue a request for
731 * wMaxPacketSize instead.
734 dwc->ep0_usb_req.dep = dep;
735 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
736 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
737 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
739 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
742 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
748 wValue = le16_to_cpu(ctrl->wValue);
749 wLength = le16_to_cpu(ctrl->wLength);
750 wIndex = le16_to_cpu(ctrl->wIndex);
752 if (wIndex || wLength)
755 dwc->gadget->isoch_delay = wValue;
760 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
764 switch (ctrl->bRequest) {
765 case USB_REQ_GET_STATUS:
766 ret = dwc3_ep0_handle_status(dwc, ctrl);
768 case USB_REQ_CLEAR_FEATURE:
769 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
771 case USB_REQ_SET_FEATURE:
772 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
774 case USB_REQ_SET_ADDRESS:
775 ret = dwc3_ep0_set_address(dwc, ctrl);
777 case USB_REQ_SET_CONFIGURATION:
778 ret = dwc3_ep0_set_config(dwc, ctrl);
780 case USB_REQ_SET_SEL:
781 ret = dwc3_ep0_set_sel(dwc, ctrl);
783 case USB_REQ_SET_ISOCH_DELAY:
784 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
787 ret = dwc3_ep0_delegate_req(dwc, ctrl);
794 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
795 const struct dwc3_event_depevt *event)
797 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
801 if (!dwc->gadget_driver)
804 trace_dwc3_ctrl_req(ctrl);
806 len = le16_to_cpu(ctrl->wLength);
808 dwc->three_stage_setup = false;
809 dwc->ep0_expect_in = false;
810 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
812 dwc->three_stage_setup = true;
813 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
814 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
817 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
818 ret = dwc3_ep0_std_request(dwc, ctrl);
820 ret = dwc3_ep0_delegate_req(dwc, ctrl);
822 if (ret == USB_GADGET_DELAYED_STATUS)
823 dwc->delayed_status = true;
827 dwc3_ep0_stall_and_restart(dwc);
830 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
831 const struct dwc3_event_depevt *event)
833 struct dwc3_request *r;
834 struct usb_request *ur;
835 struct dwc3_trb *trb;
842 epnum = event->endpoint_number;
845 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
847 trace_dwc3_complete_trb(ep0, trb);
849 r = next_request(&ep0->pending_list);
853 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
854 if (status == DWC3_TRBSTS_SETUP_PENDING) {
855 dwc->setup_packet_pending = true;
857 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
864 length = trb->size & DWC3_TRB_SIZE_MASK;
865 transferred = ur->length - length;
866 ur->actual += transferred;
868 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
869 ur->length && ur->zero) || dwc->ep0_bounced) {
871 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
872 trace_dwc3_complete_trb(ep0, trb);
875 dwc->eps[1]->trb_enqueue = 0;
877 dwc->eps[0]->trb_enqueue = 0;
879 dwc->ep0_bounced = false;
882 if ((epnum & 1) && ur->actual < ur->length)
883 dwc3_ep0_stall_and_restart(dwc);
885 dwc3_gadget_giveback(ep0, r, 0);
888 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
889 const struct dwc3_event_depevt *event)
891 struct dwc3_request *r;
893 struct dwc3_trb *trb;
899 trace_dwc3_complete_trb(dep, trb);
901 if (!list_empty(&dep->pending_list)) {
902 r = next_request(&dep->pending_list);
904 dwc3_gadget_giveback(dep, r, 0);
907 if (dwc->test_mode) {
910 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
912 dev_err(dwc->dev, "invalid test #%d\n",
914 dwc3_ep0_stall_and_restart(dwc);
919 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
920 if (status == DWC3_TRBSTS_SETUP_PENDING)
921 dwc->setup_packet_pending = true;
923 dwc->ep0state = EP0_SETUP_PHASE;
924 dwc3_ep0_out_start(dwc);
927 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
928 const struct dwc3_event_depevt *event)
930 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
932 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
933 dep->resource_index = 0;
934 dwc->setup_packet_pending = false;
936 switch (dwc->ep0state) {
937 case EP0_SETUP_PHASE:
938 dwc3_ep0_inspect_setup(dwc, event);
942 dwc3_ep0_complete_data(dwc, event);
945 case EP0_STATUS_PHASE:
946 dwc3_ep0_complete_status(dwc, event);
949 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
953 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
954 struct dwc3_ep *dep, struct dwc3_request *req)
956 unsigned int trb_length = 0;
959 req->direction = !!dep->number;
961 if (req->request.length == 0) {
963 trb_length = dep->endpoint.maxpacket;
965 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
966 DWC3_TRBCTL_CONTROL_DATA, false);
967 ret = dwc3_ep0_start_trans(dep);
968 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
969 && (dep->number == 0)) {
973 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
974 &req->request, dep->number);
978 maxpacket = dep->endpoint.maxpacket;
979 rem = req->request.length % maxpacket;
980 dwc->ep0_bounced = true;
982 /* prepare normal TRB */
983 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
985 DWC3_TRBCTL_CONTROL_DATA,
988 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
990 /* Now prepare one extra TRB to align transfer size */
991 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
993 DWC3_TRBCTL_CONTROL_DATA,
995 ret = dwc3_ep0_start_trans(dep);
996 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
997 req->request.length && req->request.zero) {
999 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1000 &req->request, dep->number);
1004 /* prepare normal TRB */
1005 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1006 req->request.length,
1007 DWC3_TRBCTL_CONTROL_DATA,
1010 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1012 if (!req->direction)
1013 trb_length = dep->endpoint.maxpacket;
1015 /* Now prepare one extra TRB to align transfer size */
1016 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1017 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1019 ret = dwc3_ep0_start_trans(dep);
1021 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1022 &req->request, dep->number);
1026 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1027 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1030 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1032 ret = dwc3_ep0_start_trans(dep);
1038 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1040 struct dwc3 *dwc = dep->dwc;
1043 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1044 : DWC3_TRBCTL_CONTROL_STATUS2;
1046 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1047 return dwc3_ep0_start_trans(dep);
1050 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1052 WARN_ON(dwc3_ep0_start_control_status(dep));
1055 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1056 const struct dwc3_event_depevt *event)
1058 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1060 __dwc3_ep0_do_control_status(dwc, dep);
1063 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1065 unsigned int direction = !dwc->ep0_expect_in;
1067 dwc->delayed_status = false;
1069 if (dwc->ep0state != EP0_STATUS_PHASE)
1072 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1075 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1077 struct dwc3_gadget_ep_cmd_params params;
1081 if (!dep->resource_index)
1084 cmd = DWC3_DEPCMD_ENDTRANSFER;
1085 cmd |= DWC3_DEPCMD_CMDIOC;
1086 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1087 memset(¶ms, 0, sizeof(params));
1088 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1090 dep->resource_index = 0;
1093 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1094 const struct dwc3_event_depevt *event)
1096 switch (event->status) {
1097 case DEPEVT_STATUS_CONTROL_DATA:
1099 * We already have a DATA transfer in the controller's cache,
1100 * if we receive a XferNotReady(DATA) we will ignore it, unless
1101 * it's for the wrong direction.
1103 * In that case, we must issue END_TRANSFER command to the Data
1104 * Phase we already have started and issue SetStall on the
1107 if (dwc->ep0_expect_in != event->endpoint_number) {
1108 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1110 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1111 dwc3_ep0_end_control_data(dwc, dep);
1112 dwc3_ep0_stall_and_restart(dwc);
1118 case DEPEVT_STATUS_CONTROL_STATUS:
1119 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1122 dwc->ep0state = EP0_STATUS_PHASE;
1124 if (dwc->delayed_status) {
1125 struct dwc3_ep *dep = dwc->eps[0];
1127 WARN_ON_ONCE(event->endpoint_number != 1);
1129 * We should handle the delay STATUS phase here if the
1130 * request for handling delay STATUS has been queued
1133 if (!list_empty(&dep->pending_list)) {
1134 dwc->delayed_status = false;
1135 usb_gadget_set_state(dwc->gadget,
1136 USB_STATE_CONFIGURED);
1137 dwc3_ep0_do_control_status(dwc, event);
1143 dwc3_ep0_do_control_status(dwc, event);
1147 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1148 const struct dwc3_event_depevt *event)
1150 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1153 switch (event->endpoint_event) {
1154 case DWC3_DEPEVT_XFERCOMPLETE:
1155 dwc3_ep0_xfer_complete(dwc, event);
1158 case DWC3_DEPEVT_XFERNOTREADY:
1159 dwc3_ep0_xfernotready(dwc, event);
1162 case DWC3_DEPEVT_XFERINPROGRESS:
1163 case DWC3_DEPEVT_RXTXFIFOEVT:
1164 case DWC3_DEPEVT_STREAMEVT:
1166 case DWC3_DEPEVT_EPCMDCMPLT:
1167 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1169 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1170 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1171 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;