1 // SPDX-License-Identifier: GPL-2.0
3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/spinlock.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/interrupt.h>
18 #include <linux/list.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/usb/ch9.h>
22 #include <linux/usb/gadget.h>
23 #include <linux/usb/composite.h>
30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
60 trace_dwc3_prepare_trb(dep, trb);
63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
65 struct dwc3_gadget_ep_cmd_params params;
69 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
88 struct dwc3_request *req)
90 struct dwc3 *dwc = dep->dwc;
92 req->request.actual = 0;
93 req->request.status = -EINPROGRESS;
94 req->epnum = dep->number;
96 list_add_tail(&req->list, &dep->pending_list);
99 * Gadget driver might not be quick enough to queue a request
100 * before we get a Transfer Not Ready event on this endpoint.
102 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
103 * flag is set, it's telling us that as soon as Gadget queues the
104 * required request, we should kick the transfer here because the
105 * IRQ we were waiting for is long gone.
107 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
110 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
112 if (dwc->ep0state != EP0_DATA_PHASE) {
113 dev_WARN(dwc->dev, "Unexpected pending request\n");
117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
126 * In case gadget driver asked us to delay the STATUS phase,
129 if (dwc->delayed_status) {
132 direction = !dwc->ep0_expect_in;
133 dwc->delayed_status = false;
134 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
136 if (dwc->ep0state == EP0_STATUS_PHASE)
137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
143 * Unfortunately we have uncovered a limitation wrt the Data Phase.
145 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
146 * come before issueing Start Transfer command, but if we do, we will
147 * miss situations where the host starts another SETUP phase instead of
148 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
149 * Layer Compliance Suite.
151 * The problem surfaces due to the fact that in case of back-to-back
152 * SETUP packets there will be no XferNotReady(DATA) generated and we
153 * will be stuck waiting for XferNotReady(DATA) forever.
155 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
156 * it tells us to start Data Phase right away. It also mentions that if
157 * we receive a SETUP phase instead of the DATA phase, core will issue
158 * XferComplete for the DATA phase, before actually initiating it in
159 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
160 * can only be used to print some debugging logs, as the core expects
161 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
162 * just so it completes right away, without transferring anything and,
163 * only then, we can go back to the SETUP phase.
165 * Because of this scenario, SNPS decided to change the programming
166 * model of control transfers and support on-demand transfers only for
167 * the STATUS phase. To fix the issue we have now, we will always wait
168 * for gadget driver to queue the DATA phase's struct usb_request, then
169 * start it right away.
171 * If we're actually in a 2-stage transfer, we will wait for
172 * XferNotReady(STATUS).
174 if (dwc->three_stage_setup) {
177 direction = dwc->ep0_expect_in;
178 dwc->ep0state = EP0_DATA_PHASE;
180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
182 dep->flags &= ~DWC3_EP0_DIR_IN;
188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
191 struct dwc3_request *req = to_dwc3_request(request);
192 struct dwc3_ep *dep = to_dwc3_ep(ep);
193 struct dwc3 *dwc = dep->dwc;
199 spin_lock_irqsave(&dwc->lock, flags);
200 if (!dep->endpoint.desc) {
201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
207 /* we share one TRB for ep0/1 */
208 if (!list_empty(&dep->pending_list)) {
213 ret = __dwc3_gadget_ep0_queue(dep, req);
216 spin_unlock_irqrestore(&dwc->lock, flags);
221 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
225 /* reinitialize physical ep1 */
227 dep->flags = DWC3_EP_ENABLED;
229 /* stall is always issued on EP0 */
231 __dwc3_gadget_ep_set_halt(dep, 1, false);
232 dep->flags = DWC3_EP_ENABLED;
233 dwc->delayed_status = false;
235 if (!list_empty(&dep->pending_list)) {
236 struct dwc3_request *req;
238 req = next_request(&dep->pending_list);
239 dwc3_gadget_giveback(dep, req, -ECONNRESET);
242 dwc->ep0state = EP0_SETUP_PHASE;
243 dwc3_ep0_out_start(dwc);
246 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
248 struct dwc3_ep *dep = to_dwc3_ep(ep);
249 struct dwc3 *dwc = dep->dwc;
251 dwc3_ep0_stall_and_restart(dwc);
256 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
258 struct dwc3_ep *dep = to_dwc3_ep(ep);
259 struct dwc3 *dwc = dep->dwc;
263 spin_lock_irqsave(&dwc->lock, flags);
264 ret = __dwc3_gadget_ep0_set_halt(ep, value);
265 spin_unlock_irqrestore(&dwc->lock, flags);
270 void dwc3_ep0_out_start(struct dwc3 *dwc)
275 complete(&dwc->ep0_in_setup);
278 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
279 DWC3_TRBCTL_CONTROL_SETUP, false);
280 ret = dwc3_ep0_start_trans(dep);
284 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
287 u32 windex = le16_to_cpu(wIndex_le);
290 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
291 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
294 dep = dwc->eps[epnum];
298 if (dep->flags & DWC3_EP_ENABLED)
304 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
310 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
311 struct usb_ctrlrequest *ctrl)
318 __le16 *response_pkt;
320 /* We don't support PTM_STATUS */
321 value = le16_to_cpu(ctrl->wValue);
325 recip = ctrl->bRequestType & USB_RECIP_MASK;
327 case USB_RECIP_DEVICE:
329 * LTM will be set once we know how to set this in HW.
331 usb_status |= dwc->gadget.is_selfpowered;
333 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
334 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
335 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
336 if (reg & DWC3_DCTL_INITU1ENA)
337 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
338 if (reg & DWC3_DCTL_INITU2ENA)
339 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
344 case USB_RECIP_INTERFACE:
346 * Function Remote Wake Capable D0
347 * Function Remote Wakeup D1
351 case USB_RECIP_ENDPOINT:
352 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
356 if (dep->flags & DWC3_EP_STALL)
357 usb_status = 1 << USB_ENDPOINT_HALT;
363 response_pkt = (__le16 *) dwc->setup_buf;
364 *response_pkt = cpu_to_le16(usb_status);
367 dwc->ep0_usb_req.dep = dep;
368 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
369 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
370 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
372 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
375 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
380 if (state != USB_STATE_CONFIGURED)
382 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
383 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
386 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
388 reg |= DWC3_DCTL_INITU1ENA;
390 reg &= ~DWC3_DCTL_INITU1ENA;
391 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
396 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
402 if (state != USB_STATE_CONFIGURED)
404 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
405 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
408 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
410 reg |= DWC3_DCTL_INITU2ENA;
412 reg &= ~DWC3_DCTL_INITU2ENA;
413 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
418 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
421 if ((wIndex & 0xff) != 0)
426 switch (wIndex >> 8) {
432 dwc->test_mode_nr = wIndex >> 8;
433 dwc->test_mode = true;
442 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
443 struct usb_ctrlrequest *ctrl, int set)
445 enum usb_device_state state;
450 wValue = le16_to_cpu(ctrl->wValue);
451 wIndex = le16_to_cpu(ctrl->wIndex);
452 state = dwc->gadget.state;
455 case USB_DEVICE_REMOTE_WAKEUP:
458 * 9.4.1 says only only for SS, in AddressState only for
459 * default control pipe
461 case USB_DEVICE_U1_ENABLE:
462 ret = dwc3_ep0_handle_u1(dwc, state, set);
464 case USB_DEVICE_U2_ENABLE:
465 ret = dwc3_ep0_handle_u2(dwc, state, set);
467 case USB_DEVICE_LTM_ENABLE:
470 case USB_DEVICE_TEST_MODE:
471 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
480 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
481 struct usb_ctrlrequest *ctrl, int set)
486 wValue = le16_to_cpu(ctrl->wValue);
489 case USB_INTRF_FUNC_SUSPEND:
491 * REVISIT: Ideally we would enable some low power mode here,
492 * however it's unclear what we should be doing here.
494 * For now, we're not doing anything, just making sure we return
495 * 0 so USB Command Verifier tests pass without any errors.
505 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
506 struct usb_ctrlrequest *ctrl, int set)
512 wValue = le16_to_cpu(ctrl->wValue);
515 case USB_ENDPOINT_HALT:
516 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
520 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
523 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
534 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
535 struct usb_ctrlrequest *ctrl, int set)
540 recip = ctrl->bRequestType & USB_RECIP_MASK;
543 case USB_RECIP_DEVICE:
544 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
546 case USB_RECIP_INTERFACE:
547 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
549 case USB_RECIP_ENDPOINT:
550 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
559 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
561 enum usb_device_state state = dwc->gadget.state;
565 addr = le16_to_cpu(ctrl->wValue);
567 dev_err(dwc->dev, "invalid device address %d\n", addr);
571 if (state == USB_STATE_CONFIGURED) {
572 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
576 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
577 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
578 reg |= DWC3_DCFG_DEVADDR(addr);
579 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
582 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
584 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
589 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
593 spin_unlock(&dwc->lock);
594 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
595 spin_lock(&dwc->lock);
599 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
601 enum usb_device_state state = dwc->gadget.state;
606 cfg = le16_to_cpu(ctrl->wValue);
609 case USB_STATE_DEFAULT:
612 case USB_STATE_ADDRESS:
613 ret = dwc3_ep0_delegate_req(dwc, ctrl);
614 /* if the cfg matches and the cfg is non zero */
615 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
618 * only change state if set_config has already
619 * been processed. If gadget driver returns
620 * USB_GADGET_DELAYED_STATUS, we will wait
621 * to change the state on the next usb_ep_queue()
624 usb_gadget_set_state(&dwc->gadget,
625 USB_STATE_CONFIGURED);
628 * Enable transition to U1/U2 state when
629 * nothing is pending from application.
631 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
632 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
633 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
637 case USB_STATE_CONFIGURED:
638 ret = dwc3_ep0_delegate_req(dwc, ctrl);
640 usb_gadget_set_state(&dwc->gadget,
649 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
651 struct dwc3_ep *dep = to_dwc3_ep(ep);
652 struct dwc3 *dwc = dep->dwc;
666 memcpy(&timing, req->buf, sizeof(timing));
668 dwc->u1sel = timing.u1sel;
669 dwc->u1pel = timing.u1pel;
670 dwc->u2sel = le16_to_cpu(timing.u2sel);
671 dwc->u2pel = le16_to_cpu(timing.u2pel);
673 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
674 if (reg & DWC3_DCTL_INITU2ENA)
676 if (reg & DWC3_DCTL_INITU1ENA)
680 * According to Synopsys Databook, if parameter is
681 * greater than 125, a value of zero should be
682 * programmed in the register.
687 /* now that we have the time, issue DGCMD Set Sel */
688 ret = dwc3_send_gadget_generic_command(dwc,
689 DWC3_DGCMD_SET_PERIODIC_PAR, param);
693 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
696 enum usb_device_state state = dwc->gadget.state;
699 if (state == USB_STATE_DEFAULT)
702 wLength = le16_to_cpu(ctrl->wLength);
705 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
711 * To handle Set SEL we need to receive 6 bytes from Host. So let's
712 * queue a usb_request for 6 bytes.
714 * Remember, though, this controller can't handle non-wMaxPacketSize
715 * aligned transfers on the OUT direction, so we queue a request for
716 * wMaxPacketSize instead.
719 dwc->ep0_usb_req.dep = dep;
720 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
721 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
722 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
724 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
727 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
733 wValue = le16_to_cpu(ctrl->wValue);
734 wLength = le16_to_cpu(ctrl->wLength);
735 wIndex = le16_to_cpu(ctrl->wIndex);
737 if (wIndex || wLength)
740 dwc->gadget.isoch_delay = wValue;
745 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
749 switch (ctrl->bRequest) {
750 case USB_REQ_GET_STATUS:
751 ret = dwc3_ep0_handle_status(dwc, ctrl);
753 case USB_REQ_CLEAR_FEATURE:
754 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
756 case USB_REQ_SET_FEATURE:
757 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
759 case USB_REQ_SET_ADDRESS:
760 ret = dwc3_ep0_set_address(dwc, ctrl);
762 case USB_REQ_SET_CONFIGURATION:
763 ret = dwc3_ep0_set_config(dwc, ctrl);
765 case USB_REQ_SET_SEL:
766 ret = dwc3_ep0_set_sel(dwc, ctrl);
768 case USB_REQ_SET_ISOCH_DELAY:
769 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
772 ret = dwc3_ep0_delegate_req(dwc, ctrl);
779 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
780 const struct dwc3_event_depevt *event)
782 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
786 if (!dwc->gadget_driver)
789 trace_dwc3_ctrl_req(ctrl);
791 len = le16_to_cpu(ctrl->wLength);
793 dwc->three_stage_setup = false;
794 dwc->ep0_expect_in = false;
795 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
797 dwc->three_stage_setup = true;
798 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
799 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
802 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
803 ret = dwc3_ep0_std_request(dwc, ctrl);
805 ret = dwc3_ep0_delegate_req(dwc, ctrl);
807 if (ret == USB_GADGET_DELAYED_STATUS)
808 dwc->delayed_status = true;
812 dwc3_ep0_stall_and_restart(dwc);
815 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
816 const struct dwc3_event_depevt *event)
818 struct dwc3_request *r;
819 struct usb_request *ur;
820 struct dwc3_trb *trb;
827 epnum = event->endpoint_number;
830 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
832 trace_dwc3_complete_trb(ep0, trb);
834 r = next_request(&ep0->pending_list);
838 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
839 if (status == DWC3_TRBSTS_SETUP_PENDING) {
840 dwc->setup_packet_pending = true;
842 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
849 length = trb->size & DWC3_TRB_SIZE_MASK;
850 transferred = ur->length - length;
851 ur->actual += transferred;
853 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
854 ur->length && ur->zero) || dwc->ep0_bounced) {
856 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
857 trace_dwc3_complete_trb(ep0, trb);
860 dwc->eps[1]->trb_enqueue = 0;
862 dwc->eps[0]->trb_enqueue = 0;
864 dwc->ep0_bounced = false;
867 if ((epnum & 1) && ur->actual < ur->length)
868 dwc3_ep0_stall_and_restart(dwc);
870 dwc3_gadget_giveback(ep0, r, 0);
873 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
874 const struct dwc3_event_depevt *event)
876 struct dwc3_request *r;
878 struct dwc3_trb *trb;
884 trace_dwc3_complete_trb(dep, trb);
886 if (!list_empty(&dep->pending_list)) {
887 r = next_request(&dep->pending_list);
889 dwc3_gadget_giveback(dep, r, 0);
892 if (dwc->test_mode) {
895 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
897 dev_err(dwc->dev, "invalid test #%d\n",
899 dwc3_ep0_stall_and_restart(dwc);
904 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
905 if (status == DWC3_TRBSTS_SETUP_PENDING)
906 dwc->setup_packet_pending = true;
908 dwc->ep0state = EP0_SETUP_PHASE;
909 dwc3_ep0_out_start(dwc);
912 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
913 const struct dwc3_event_depevt *event)
915 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
917 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
918 dep->resource_index = 0;
919 dwc->setup_packet_pending = false;
921 switch (dwc->ep0state) {
922 case EP0_SETUP_PHASE:
923 dwc3_ep0_inspect_setup(dwc, event);
927 dwc3_ep0_complete_data(dwc, event);
930 case EP0_STATUS_PHASE:
931 dwc3_ep0_complete_status(dwc, event);
934 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
938 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
939 struct dwc3_ep *dep, struct dwc3_request *req)
941 unsigned int trb_length = 0;
944 req->direction = !!dep->number;
946 if (req->request.length == 0) {
948 trb_length = dep->endpoint.maxpacket;
950 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
951 DWC3_TRBCTL_CONTROL_DATA, false);
952 ret = dwc3_ep0_start_trans(dep);
953 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
954 && (dep->number == 0)) {
958 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
959 &req->request, dep->number);
963 maxpacket = dep->endpoint.maxpacket;
964 rem = req->request.length % maxpacket;
965 dwc->ep0_bounced = true;
967 /* prepare normal TRB */
968 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
970 DWC3_TRBCTL_CONTROL_DATA,
973 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
975 /* Now prepare one extra TRB to align transfer size */
976 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
978 DWC3_TRBCTL_CONTROL_DATA,
980 ret = dwc3_ep0_start_trans(dep);
981 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
982 req->request.length && req->request.zero) {
984 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
985 &req->request, dep->number);
989 /* prepare normal TRB */
990 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
992 DWC3_TRBCTL_CONTROL_DATA,
995 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
998 trb_length = dep->endpoint.maxpacket;
1000 /* Now prepare one extra TRB to align transfer size */
1001 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1002 trb_length, DWC3_TRBCTL_CONTROL_DATA,
1004 ret = dwc3_ep0_start_trans(dep);
1006 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1007 &req->request, dep->number);
1011 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1012 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1015 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1017 ret = dwc3_ep0_start_trans(dep);
1023 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1025 struct dwc3 *dwc = dep->dwc;
1028 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1029 : DWC3_TRBCTL_CONTROL_STATUS2;
1031 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1032 return dwc3_ep0_start_trans(dep);
1035 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1037 WARN_ON(dwc3_ep0_start_control_status(dep));
1040 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1041 const struct dwc3_event_depevt *event)
1043 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1045 __dwc3_ep0_do_control_status(dwc, dep);
1048 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1050 struct dwc3_gadget_ep_cmd_params params;
1054 if (!dep->resource_index)
1057 cmd = DWC3_DEPCMD_ENDTRANSFER;
1058 cmd |= DWC3_DEPCMD_CMDIOC;
1059 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1060 memset(¶ms, 0, sizeof(params));
1061 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1063 dep->resource_index = 0;
1066 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1067 const struct dwc3_event_depevt *event)
1069 switch (event->status) {
1070 case DEPEVT_STATUS_CONTROL_DATA:
1072 * We already have a DATA transfer in the controller's cache,
1073 * if we receive a XferNotReady(DATA) we will ignore it, unless
1074 * it's for the wrong direction.
1076 * In that case, we must issue END_TRANSFER command to the Data
1077 * Phase we already have started and issue SetStall on the
1080 if (dwc->ep0_expect_in != event->endpoint_number) {
1081 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1083 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1084 dwc3_ep0_end_control_data(dwc, dep);
1085 dwc3_ep0_stall_and_restart(dwc);
1091 case DEPEVT_STATUS_CONTROL_STATUS:
1092 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1095 dwc->ep0state = EP0_STATUS_PHASE;
1097 if (dwc->delayed_status) {
1098 struct dwc3_ep *dep = dwc->eps[0];
1100 WARN_ON_ONCE(event->endpoint_number != 1);
1102 * We should handle the delay STATUS phase here if the
1103 * request for handling delay STATUS has been queued
1106 if (!list_empty(&dep->pending_list)) {
1107 dwc->delayed_status = false;
1108 usb_gadget_set_state(&dwc->gadget,
1109 USB_STATE_CONFIGURED);
1110 dwc3_ep0_do_control_status(dwc, event);
1116 dwc3_ep0_do_control_status(dwc, event);
1120 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1121 const struct dwc3_event_depevt *event)
1123 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1126 switch (event->endpoint_event) {
1127 case DWC3_DEPEVT_XFERCOMPLETE:
1128 dwc3_ep0_xfer_complete(dwc, event);
1131 case DWC3_DEPEVT_XFERNOTREADY:
1132 dwc3_ep0_xfernotready(dwc, event);
1135 case DWC3_DEPEVT_XFERINPROGRESS:
1136 case DWC3_DEPEVT_RXTXFIFOEVT:
1137 case DWC3_DEPEVT_STREAMEVT:
1139 case DWC3_DEPEVT_EPCMDCMPLT:
1140 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1142 if (cmd == DWC3_DEPCMD_ENDTRANSFER)
1143 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;