drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
  59                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_trb                 *trb;
  62         struct dwc3_ep                  *dep;
  63
  64         dep = dwc->eps[epnum];
  65
  66         trb = &dwc->ep0_trb[dep->free_slot];
  67
  68         if (chain)
  69                 dep->free_slot++;
  70
  71         trb->bpl = lower_32_bits(buf_dma);
  72         trb->bph = upper_32_bits(buf_dma);
  73         trb->size = len;
  74         trb->ctrl = type;
  75
  76         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  77                         | DWC3_TRB_CTRL_ISP_IMI);
  78
  79         if (chain)
  80                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  81         else
  82                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  83                                 | DWC3_TRB_CTRL_LST);
  84
  85         trace_dwc3_prepare_trb(dep, trb);
  86 }
  87
  88 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
  89 {
  90         struct dwc3_gadget_ep_cmd_params params;
  91         struct dwc3_ep                  *dep;
  92         int                             ret;
  93
  94         dep = dwc->eps[epnum];
  95         if (dep->flags & DWC3_EP_BUSY) {
  96                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  97                 return 0;
  98         }
  99
 100         memset(&params, 0, sizeof(params));
 101         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 102         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 103
 104         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 105                         DWC3_DEPCMD_STARTTRANSFER, &params);
 106         if (ret < 0) {
 107                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 108                                 dep->name);
 109                 return ret;
 110         }
 111
 112         dep->flags |= DWC3_EP_BUSY;
 113         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 114                         dep->number);
 115
 116         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 117
 118         return 0;
 119 }
 120
 121 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 122                 struct dwc3_request *req)
 123 {
 124         struct dwc3             *dwc = dep->dwc;
 125
 126         req->request.actual     = 0;
 127         req->request.status     = -EINPROGRESS;
 128         req->epnum              = dep->number;
 129
 130         list_add_tail(&req->list, &dep->request_list);
 131
 132         /*
 133          * Gadget driver might not be quick enough to queue a request
 134          * before we get a Transfer Not Ready event on this endpoint.
 135          *
 136          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 137          * flag is set, it's telling us that as soon as Gadget queues the
 138          * required request, we should kick the transfer here because the
 139          * IRQ we were waiting for is long gone.
 140          */
 141         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 142                 unsigned        direction;
 143
 144                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 145
 146                 if (dwc->ep0state != EP0_DATA_PHASE) {
 147                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 148                         return 0;
 149                 }
 150
 151                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 152
 153                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 154                                 DWC3_EP0_DIR_IN);
 155
 156                 return 0;
 157         }
 158
 159         /*
 160          * In case gadget driver asked us to delay the STATUS phase,
 161          * handle it here.
 162          */
 163         if (dwc->delayed_status) {
 164                 unsigned        direction;
 165
 166                 direction = !dwc->ep0_expect_in;
 167                 dwc->delayed_status = false;
 168                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 169
 170                 if (dwc->ep0state == EP0_STATUS_PHASE)
 171                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 172                 else
 173                         dwc3_trace(trace_dwc3_ep0,
 174                                         "too early for delayed status");
 175
 176                 return 0;
 177         }
 178
 179         /*
 180          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 181          *
 182          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 183          * come before issueing Start Transfer command, but if we do, we will
 184          * miss situations where the host starts another SETUP phase instead of
 185          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 186          * Layer Compliance Suite.
 187          *
 188          * The problem surfaces due to the fact that in case of back-to-back
 189          * SETUP packets there will be no XferNotReady(DATA) generated and we
 190          * will be stuck waiting for XferNotReady(DATA) forever.
 191          *
 192          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 193          * it tells us to start Data Phase right away. It also mentions that if
 194          * we receive a SETUP phase instead of the DATA phase, core will issue
 195          * XferComplete for the DATA phase, before actually initiating it in
 196          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 197          * can only be used to print some debugging logs, as the core expects
 198          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 199          * just so it completes right away, without transferring anything and,
 200          * only then, we can go back to the SETUP phase.
 201          *
 202          * Because of this scenario, SNPS decided to change the programming
 203          * model of control transfers and support on-demand transfers only for
 204          * the STATUS phase. To fix the issue we have now, we will always wait
 205          * for gadget driver to queue the DATA phase's struct usb_request, then
 206          * start it right away.
 207          *
 208          * If we're actually in a 2-stage transfer, we will wait for
 209          * XferNotReady(STATUS).
 210          */
 211         if (dwc->three_stage_setup) {
 212                 unsigned        direction;
 213
 214                 direction = dwc->ep0_expect_in;
 215                 dwc->ep0state = EP0_DATA_PHASE;
 216
 217                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 218
 219                 dep->flags &= ~DWC3_EP0_DIR_IN;
 220         }
 221
 222         return 0;
 223 }
 224
 225 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 226                 gfp_t gfp_flags)
 227 {
 228         struct dwc3_request             *req = to_dwc3_request(request);
 229         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 230         struct dwc3                     *dwc = dep->dwc;
 231
 232         unsigned long                   flags;
 233
 234         int                             ret;
 235
 236         spin_lock_irqsave(&dwc->lock, flags);
 237         if (!dep->endpoint.desc) {
 238                 dwc3_trace(trace_dwc3_ep0,
 239                                 "trying to queue request %p to disabled %s",
 240                                 request, dep->name);
 241                 ret = -ESHUTDOWN;
 242                 goto out;
 243         }
 244
 245         /* we share one TRB for ep0/1 */
 246         if (!list_empty(&dep->request_list)) {
 247                 ret = -EBUSY;
 248                 goto out;
 249         }
 250
 251         dwc3_trace(trace_dwc3_ep0,
 252                         "queueing request %p to %s length %d state '%s'",
 253                         request, dep->name, request->length,
 254                         dwc3_ep0_state_string(dwc->ep0state));
 255
 256         ret = __dwc3_gadget_ep0_queue(dep, req);
 257
 258 out:
 259         spin_unlock_irqrestore(&dwc->lock, flags);
 260
 261         return ret;
 262 }
 263
 264 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 265 {
 266         struct dwc3_ep          *dep;
 267
 268         /* reinitialize physical ep1 */
 269         dep = dwc->eps[1];
 270         dep->flags = DWC3_EP_ENABLED;
 271
 272         /* stall is always issued on EP0 */
 273         dep = dwc->eps[0];
 274         __dwc3_gadget_ep_set_halt(dep, 1, false);
 275         dep->flags = DWC3_EP_ENABLED;
 276         dwc->delayed_status = false;
 277
 278         if (!list_empty(&dep->request_list)) {
 279                 struct dwc3_request     *req;
 280
 281                 req = next_request(&dep->request_list);
 282                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 283         }
 284
 285         dwc->ep0state = EP0_SETUP_PHASE;
 286         dwc3_ep0_out_start(dwc);
 287 }
 288
 289 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 290 {
 291         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 292         struct dwc3                     *dwc = dep->dwc;
 293
 294         dwc3_ep0_stall_and_restart(dwc);
 295
 296         return 0;
 297 }
 298
 299 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 300 {
 301         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 302         struct dwc3                     *dwc = dep->dwc;
 303         unsigned long                   flags;
 304         int                             ret;
 305
 306         spin_lock_irqsave(&dwc->lock, flags);
 307         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 308         spin_unlock_irqrestore(&dwc->lock, flags);
 309
 310         return ret;
 311 }
 312
 313 void dwc3_ep0_out_start(struct dwc3 *dwc)
 314 {
 315         int                             ret;
 316
 317         dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8,
 318                         DWC3_TRBCTL_CONTROL_SETUP, false);
 319         ret = dwc3_ep0_start_trans(dwc, 0);
 320         WARN_ON(ret < 0);
 321 }
 322
 323 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 324 {
 325         struct dwc3_ep          *dep;
 326         u32                     windex = le16_to_cpu(wIndex_le);
 327         u32                     epnum;
 328
 329         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 330         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 331                 epnum |= 1;
 332
 333         dep = dwc->eps[epnum];
 334         if (dep == NULL)
 335                 return NULL;
 336
 337         if (dep->flags & DWC3_EP_ENABLED)
 338                 return dep;
 339
 340         return NULL;
 341 }
 342
 343 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 344 {
 345 }
 346 /*
 347  * ch 9.4.5
 348  */
 349 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 350                 struct usb_ctrlrequest *ctrl)
 351 {
 352         struct dwc3_ep          *dep;
 353         u32                     recip;
 354         u32                     reg;
 355         u16                     usb_status = 0;
 356         __le16                  *response_pkt;
 357
 358         recip = ctrl->bRequestType & USB_RECIP_MASK;
 359         switch (recip) {
 360         case USB_RECIP_DEVICE:
 361                 /*
 362                  * LTM will be set once we know how to set this in HW.
 363                  */
 364                 usb_status |= dwc->gadget.is_selfpowered;
 365
 366                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 367                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 368                         if (reg & DWC3_DCTL_INITU1ENA)
 369                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 370                         if (reg & DWC3_DCTL_INITU2ENA)
 371                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 372                 }
 373
 374                 break;
 375
 376         case USB_RECIP_INTERFACE:
 377                 /*
 378                  * Function Remote Wake Capable D0
 379                  * Function Remote Wakeup       D1
 380                  */
 381                 break;
 382
 383         case USB_RECIP_ENDPOINT:
 384                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 385                 if (!dep)
 386                         return -EINVAL;
 387
 388                 if (dep->flags & DWC3_EP_STALL)
 389                         usb_status = 1 << USB_ENDPOINT_HALT;
 390                 break;
 391         default:
 392                 return -EINVAL;
 393         }
 394
 395         response_pkt = (__le16 *) dwc->setup_buf;
 396         *response_pkt = cpu_to_le16(usb_status);
 397
 398         dep = dwc->eps[0];
 399         dwc->ep0_usb_req.dep = dep;
 400         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 401         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 402         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 403
 404         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 405 }
 406
 407 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 408                 struct usb_ctrlrequest *ctrl, int set)
 409 {
 410         struct dwc3_ep          *dep;
 411         u32                     recip;
 412         u32                     wValue;
 413         u32                     wIndex;
 414         u32                     reg;
 415         int                     ret;
 416         enum usb_device_state   state;
 417
 418         wValue = le16_to_cpu(ctrl->wValue);
 419         wIndex = le16_to_cpu(ctrl->wIndex);
 420         recip = ctrl->bRequestType & USB_RECIP_MASK;
 421         state = dwc->gadget.state;
 422
 423         switch (recip) {
 424         case USB_RECIP_DEVICE:
 425
 426                 switch (wValue) {
 427                 case USB_DEVICE_REMOTE_WAKEUP:
 428                         break;
 429                 /*
 430                  * 9.4.1 says only only for SS, in AddressState only for
 431                  * default control pipe
 432                  */
 433                 case USB_DEVICE_U1_ENABLE:
 434                         if (state != USB_STATE_CONFIGURED)
 435                                 return -EINVAL;
 436                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 437                                 return -EINVAL;
 438
 439                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 440                         if (set)
 441                                 reg |= DWC3_DCTL_INITU1ENA;
 442                         else
 443                                 reg &= ~DWC3_DCTL_INITU1ENA;
 444                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 445                         break;
 446
 447                 case USB_DEVICE_U2_ENABLE:
 448                         if (state != USB_STATE_CONFIGURED)
 449                                 return -EINVAL;
 450                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 451                                 return -EINVAL;
 452
 453                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 454                         if (set)
 455                                 reg |= DWC3_DCTL_INITU2ENA;
 456                         else
 457                                 reg &= ~DWC3_DCTL_INITU2ENA;
 458                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 459                         break;
 460
 461                 case USB_DEVICE_LTM_ENABLE:
 462                         return -EINVAL;
 463
 464                 case USB_DEVICE_TEST_MODE:
 465                         if ((wIndex & 0xff) != 0)
 466                                 return -EINVAL;
 467                         if (!set)
 468                                 return -EINVAL;
 469
 470                         dwc->test_mode_nr = wIndex >> 8;
 471                         dwc->test_mode = true;
 472                         break;
 473                 default:
 474                         return -EINVAL;
 475                 }
 476                 break;
 477
 478         case USB_RECIP_INTERFACE:
 479                 switch (wValue) {
 480                 case USB_INTRF_FUNC_SUSPEND:
 481                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 482                                 /* XXX enable Low power suspend */
 483                                 ;
 484                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 485                                 /* XXX enable remote wakeup */
 486                                 ;
 487                         break;
 488                 default:
 489                         return -EINVAL;
 490                 }
 491                 break;
 492
 493         case USB_RECIP_ENDPOINT:
 494                 switch (wValue) {
 495                 case USB_ENDPOINT_HALT:
 496                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 497                         if (!dep)
 498                                 return -EINVAL;
 499                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 500                                 break;
 501                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 502                         if (ret)
 503                                 return -EINVAL;
 504                         break;
 505                 default:
 506                         return -EINVAL;
 507                 }
 508                 break;
 509
 510         default:
 511                 return -EINVAL;
 512         }
 513
 514         return 0;
 515 }
 516
 517 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 518 {
 519         enum usb_device_state state = dwc->gadget.state;
 520         u32 addr;
 521         u32 reg;
 522
 523         addr = le16_to_cpu(ctrl->wValue);
 524         if (addr > 127) {
 525                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 526                 return -EINVAL;
 527         }
 528
 529         if (state == USB_STATE_CONFIGURED) {
 530                 dwc3_trace(trace_dwc3_ep0,
 531                                 "trying to set address when configured");
 532                 return -EINVAL;
 533         }
 534
 535         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 536         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 537         reg |= DWC3_DCFG_DEVADDR(addr);
 538         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 539
 540         if (addr)
 541                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 542         else
 543                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 544
 545         return 0;
 546 }
 547
 548 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 549 {
 550         int ret;
 551
 552         spin_unlock(&dwc->lock);
 553         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 554         spin_lock(&dwc->lock);
 555         return ret;
 556 }
 557
 558 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 559 {
 560         enum usb_device_state state = dwc->gadget.state;
 561         u32 cfg;
 562         int ret;
 563         u32 reg;
 564
 565         cfg = le16_to_cpu(ctrl->wValue);
 566
 567         switch (state) {
 568         case USB_STATE_DEFAULT:
 569                 return -EINVAL;
 570
 571         case USB_STATE_ADDRESS:
 572                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 573                 /* if the cfg matches and the cfg is non zero */
 574                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 575
 576                         /*
 577                          * only change state if set_config has already
 578                          * been processed. If gadget driver returns
 579                          * USB_GADGET_DELAYED_STATUS, we will wait
 580                          * to change the state on the next usb_ep_queue()
 581                          */
 582                         if (ret == 0)
 583                                 usb_gadget_set_state(&dwc->gadget,
 584                                                 USB_STATE_CONFIGURED);
 585
 586                         /*
 587                          * Enable transition to U1/U2 state when
 588                          * nothing is pending from application.
 589                          */
 590                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 591                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 592                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 593
 594                         dwc->resize_fifos = true;
 595                         dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
 596                 }
 597                 break;
 598
 599         case USB_STATE_CONFIGURED:
 600                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 601                 if (!cfg && !ret)
 602                         usb_gadget_set_state(&dwc->gadget,
 603                                         USB_STATE_ADDRESS);
 604                 break;
 605         default:
 606                 ret = -EINVAL;
 607         }
 608         return ret;
 609 }
 610
 611 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 612 {
 613         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 614         struct dwc3     *dwc = dep->dwc;
 615
 616         u32             param = 0;
 617         u32             reg;
 618
 619         struct timing {
 620                 u8      u1sel;
 621                 u8      u1pel;
 622                 u16     u2sel;
 623                 u16     u2pel;
 624         } __packed timing;
 625
 626         int             ret;
 627
 628         memcpy(&timing, req->buf, sizeof(timing));
 629
 630         dwc->u1sel = timing.u1sel;
 631         dwc->u1pel = timing.u1pel;
 632         dwc->u2sel = le16_to_cpu(timing.u2sel);
 633         dwc->u2pel = le16_to_cpu(timing.u2pel);
 634
 635         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 636         if (reg & DWC3_DCTL_INITU2ENA)
 637                 param = dwc->u2pel;
 638         if (reg & DWC3_DCTL_INITU1ENA)
 639                 param = dwc->u1pel;
 640
 641         /*
 642          * According to Synopsys Databook, if parameter is
 643          * greater than 125, a value of zero should be
 644          * programmed in the register.
 645          */
 646         if (param > 125)
 647                 param = 0;
 648
 649         /* now that we have the time, issue DGCMD Set Sel */
 650         ret = dwc3_send_gadget_generic_command(dwc,
 651                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 652         WARN_ON(ret < 0);
 653 }
 654
 655 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 656 {
 657         struct dwc3_ep  *dep;
 658         enum usb_device_state state = dwc->gadget.state;
 659         u16             wLength;
 660         u16             wValue;
 661
 662         if (state == USB_STATE_DEFAULT)
 663                 return -EINVAL;
 664
 665         wValue = le16_to_cpu(ctrl->wValue);
 666         wLength = le16_to_cpu(ctrl->wLength);
 667
 668         if (wLength != 6) {
 669                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 670                                 wLength);
 671                 return -EINVAL;
 672         }
 673
 674         /*
 675          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 676          * queue a usb_request for 6 bytes.
 677          *
 678          * Remember, though, this controller can't handle non-wMaxPacketSize
 679          * aligned transfers on the OUT direction, so we queue a request for
 680          * wMaxPacketSize instead.
 681          */
 682         dep = dwc->eps[0];
 683         dwc->ep0_usb_req.dep = dep;
 684         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 685         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 686         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 687
 688         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 689 }
 690
 691 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 692 {
 693         u16             wLength;
 694         u16             wValue;
 695         u16             wIndex;
 696
 697         wValue = le16_to_cpu(ctrl->wValue);
 698         wLength = le16_to_cpu(ctrl->wLength);
 699         wIndex = le16_to_cpu(ctrl->wIndex);
 700
 701         if (wIndex || wLength)
 702                 return -EINVAL;
 703
 704         /*
 705          * REVISIT It's unclear from Databook what to do with this
 706          * value. For now, just cache it.
 707          */
 708         dwc->isoch_delay = wValue;
 709
 710         return 0;
 711 }
 712
 713 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 714 {
 715         int ret;
 716
 717         switch (ctrl->bRequest) {
 718         case USB_REQ_GET_STATUS:
 719                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 720                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 721                 break;
 722         case USB_REQ_CLEAR_FEATURE:
 723                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 724                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 725                 break;
 726         case USB_REQ_SET_FEATURE:
 727                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 728                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 729                 break;
 730         case USB_REQ_SET_ADDRESS:
 731                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 732                 ret = dwc3_ep0_set_address(dwc, ctrl);
 733                 break;
 734         case USB_REQ_SET_CONFIGURATION:
 735                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 736                 ret = dwc3_ep0_set_config(dwc, ctrl);
 737                 break;
 738         case USB_REQ_SET_SEL:
 739                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 740                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 741                 break;
 742         case USB_REQ_SET_ISOCH_DELAY:
 743                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 744                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 745                 break;
 746         default:
 747                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 748                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 749                 break;
 750         }
 751
 752         return ret;
 753 }
 754
 755 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 756                 const struct dwc3_event_depevt *event)
 757 {
 758         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 759         int ret = -EINVAL;
 760         u32 len;
 761
 762         if (!dwc->gadget_driver)
 763                 goto out;
 764
 765         trace_dwc3_ctrl_req(ctrl);
 766
 767         len = le16_to_cpu(ctrl->wLength);
 768         if (!len) {
 769                 dwc->three_stage_setup = false;
 770                 dwc->ep0_expect_in = false;
 771                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 772         } else {
 773                 dwc->three_stage_setup = true;
 774                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 775                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 776         }
 777
 778         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 779                 ret = dwc3_ep0_std_request(dwc, ctrl);
 780         else
 781                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 782
 783         if (ret == USB_GADGET_DELAYED_STATUS)
 784                 dwc->delayed_status = true;
 785
 786 out:
 787         if (ret < 0)
 788                 dwc3_ep0_stall_and_restart(dwc);
 789 }
 790
 791 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 792                 const struct dwc3_event_depevt *event)
 793 {
 794         struct dwc3_request     *r = NULL;
 795         struct usb_request      *ur;
 796         struct dwc3_trb         *trb;
 797         struct dwc3_ep          *ep0;
 798         unsigned                transfer_size = 0;
 799         unsigned                maxp;
 800         unsigned                remaining_ur_length;
 801         void                    *buf;
 802         u32                     transferred = 0;
 803         u32                     status;
 804         u32                     length;
 805         u8                      epnum;
 806
 807         epnum = event->endpoint_number;
 808         ep0 = dwc->eps[0];
 809
 810         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 811
 812         trb = dwc->ep0_trb;
 813
 814         trace_dwc3_complete_trb(ep0, trb);
 815
 816         r = next_request(&ep0->request_list);
 817         if (!r)
 818                 return;
 819
 820         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 821         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 822                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 823
 824                 if (r)
 825                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 826
 827                 return;
 828         }
 829
 830         ur = &r->request;
 831         buf = ur->buf;
 832         remaining_ur_length = ur->length;
 833
 834         length = trb->size & DWC3_TRB_SIZE_MASK;
 835
 836         maxp = ep0->endpoint.maxpacket;
 837
 838         if (dwc->ep0_bounced) {
 839                 /*
 840                  * Handle the first TRB before handling the bounce buffer if
 841                  * the request length is greater than the bounce buffer size
 842                  */
 843                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 844                         transfer_size = ALIGN(ur->length - maxp, maxp);
 845                         transferred = transfer_size - length;
 846                         buf = (u8 *)buf + transferred;
 847                         ur->actual += transferred;
 848                         remaining_ur_length -= transferred;
 849
 850                         trb++;
 851                         length = trb->size & DWC3_TRB_SIZE_MASK;
 852
 853                         ep0->free_slot = 0;
 854                 }
 855
 856                 transfer_size = roundup((ur->length - transfer_size),
 857                                         maxp);
 858
 859                 transferred = min_t(u32, remaining_ur_length,
 860                                     transfer_size - length);
 861                 memcpy(buf, dwc->ep0_bounce, transferred);
 862         } else {
 863                 transferred = ur->length - length;
 864         }
 865
 866         ur->actual += transferred;
 867
 868         if ((epnum & 1) && ur->actual < ur->length) {
 869                 /* for some reason we did not get everything out */
 870
 871                 dwc3_ep0_stall_and_restart(dwc);
 872         } else {
 873                 dwc3_gadget_giveback(ep0, r, 0);
 874
 875                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 876                                 ur->length && ur->zero) {
 877                         int ret;
 878
 879                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 880
 881                         dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr,
 882                                         0, DWC3_TRBCTL_CONTROL_DATA, false);
 883                         ret = dwc3_ep0_start_trans(dwc, epnum);
 884                         WARN_ON(ret < 0);
 885                 }
 886         }
 887 }
 888
 889 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 890                 const struct dwc3_event_depevt *event)
 891 {
 892         struct dwc3_request     *r;
 893         struct dwc3_ep          *dep;
 894         struct dwc3_trb         *trb;
 895         u32                     status;
 896
 897         dep = dwc->eps[0];
 898         trb = dwc->ep0_trb;
 899
 900         trace_dwc3_complete_trb(dep, trb);
 901
 902         if (!list_empty(&dep->request_list)) {
 903                 r = next_request(&dep->request_list);
 904
 905                 dwc3_gadget_giveback(dep, r, 0);
 906         }
 907
 908         if (dwc->test_mode) {
 909                 int ret;
 910
 911                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 912                 if (ret < 0) {
 913                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 914                                         dwc->test_mode_nr);
 915                         dwc3_ep0_stall_and_restart(dwc);
 916                         return;
 917                 }
 918         }
 919
 920         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 921         if (status == DWC3_TRBSTS_SETUP_PENDING)
 922                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 923
 924         dwc->ep0state = EP0_SETUP_PHASE;
 925         dwc3_ep0_out_start(dwc);
 926 }
 927
 928 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 929                         const struct dwc3_event_depevt *event)
 930 {
 931         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 932
 933         dep->flags &= ~DWC3_EP_BUSY;
 934         dep->resource_index = 0;
 935         dwc->setup_packet_pending = false;
 936
 937         switch (dwc->ep0state) {
 938         case EP0_SETUP_PHASE:
 939                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 940                 dwc3_ep0_inspect_setup(dwc, event);
 941                 break;
 942
 943         case EP0_DATA_PHASE:
 944                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 945                 dwc3_ep0_complete_data(dwc, event);
 946                 break;
 947
 948         case EP0_STATUS_PHASE:
 949                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 950                 dwc3_ep0_complete_status(dwc, event);
 951                 break;
 952         default:
 953                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 954         }
 955 }
 956
 957 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 958                 struct dwc3_ep *dep, struct dwc3_request *req)
 959 {
 960         int                     ret;
 961
 962         req->direction = !!dep->number;
 963
 964         if (req->request.length == 0) {
 965                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
 966                                 dwc->ctrl_req_addr, 0,
 967                                 DWC3_TRBCTL_CONTROL_DATA, false);
 968                 ret = dwc3_ep0_start_trans(dwc, dep->number);
 969         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 970                         && (dep->number == 0)) {
 971                 u32     transfer_size = 0;
 972                 u32     maxpacket;
 973
 974                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 975                                 dep->number);
 976                 if (ret) {
 977                         dev_dbg(dwc->dev, "failed to map request\n");
 978                         return;
 979                 }
 980
 981                 maxpacket = dep->endpoint.maxpacket;
 982
 983                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 984                         transfer_size = ALIGN(req->request.length - maxpacket,
 985                                               maxpacket);
 986                         dwc3_ep0_prepare_one_trb(dwc, dep->number,
 987                                                    req->request.dma,
 988                                                    transfer_size,
 989                                                    DWC3_TRBCTL_CONTROL_DATA,
 990                                                    true);
 991                 }
 992
 993                 transfer_size = roundup((req->request.length - transfer_size),
 994                                         maxpacket);
 995
 996                 dwc->ep0_bounced = true;
 997
 998                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
 999                                 dwc->ep0_bounce_addr, transfer_size,
1000                                 DWC3_TRBCTL_CONTROL_DATA, false);
1001                 ret = dwc3_ep0_start_trans(dwc, dep->number);
1002         } else {
1003                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1004                                 dep->number);
1005                 if (ret) {
1006                         dev_dbg(dwc->dev, "failed to map request\n");
1007                         return;
1008                 }
1009
1010                 dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma,
1011                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1012                                 false);
1013                 ret = dwc3_ep0_start_trans(dwc, dep->number);
1014         }
1015
1016         WARN_ON(ret < 0);
1017 }
1018
1019 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1020 {
1021         struct dwc3             *dwc = dep->dwc;
1022         u32                     type;
1023
1024         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1025                 : DWC3_TRBCTL_CONTROL_STATUS2;
1026
1027         dwc3_ep0_prepare_one_trb(dwc, dep->number,
1028                         dwc->ctrl_req_addr, 0, type, false);
1029         return dwc3_ep0_start_trans(dwc, dep->number);
1030 }
1031
1032 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1033 {
1034         if (dwc->resize_fifos) {
1035                 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
1036                 dwc3_gadget_resize_tx_fifos(dwc);
1037                 dwc->resize_fifos = 0;
1038         }
1039
1040         WARN_ON(dwc3_ep0_start_control_status(dep));
1041 }
1042
1043 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1044                 const struct dwc3_event_depevt *event)
1045 {
1046         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1047
1048         __dwc3_ep0_do_control_status(dwc, dep);
1049 }
1050
1051 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1052 {
1053         struct dwc3_gadget_ep_cmd_params params;
1054         u32                     cmd;
1055         int                     ret;
1056
1057         if (!dep->resource_index)
1058                 return;
1059
1060         cmd = DWC3_DEPCMD_ENDTRANSFER;
1061         cmd |= DWC3_DEPCMD_CMDIOC;
1062         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1063         memset(&params, 0, sizeof(params));
1064         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1065         WARN_ON_ONCE(ret);
1066         dep->resource_index = 0;
1067 }
1068
1069 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1070                 const struct dwc3_event_depevt *event)
1071 {
1072         dwc->setup_packet_pending = true;
1073
1074         switch (event->status) {
1075         case DEPEVT_STATUS_CONTROL_DATA:
1076                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1077
1078                 /*
1079                  * We already have a DATA transfer in the controller's cache,
1080                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1081                  * it's for the wrong direction.
1082                  *
1083                  * In that case, we must issue END_TRANSFER command to the Data
1084                  * Phase we already have started and issue SetStall on the
1085                  * control endpoint.
1086                  */
1087                 if (dwc->ep0_expect_in != event->endpoint_number) {
1088                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1089
1090                         dwc3_trace(trace_dwc3_ep0,
1091                                         "Wrong direction for Data phase");
1092                         dwc3_ep0_end_control_data(dwc, dep);
1093                         dwc3_ep0_stall_and_restart(dwc);
1094                         return;
1095                 }
1096
1097                 break;
1098
1099         case DEPEVT_STATUS_CONTROL_STATUS:
1100                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1101                         return;
1102
1103                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1104
1105                 dwc->ep0state = EP0_STATUS_PHASE;
1106
1107                 if (dwc->delayed_status) {
1108                         WARN_ON_ONCE(event->endpoint_number != 1);
1109                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1110                         return;
1111                 }
1112
1113                 dwc3_ep0_do_control_status(dwc, event);
1114         }
1115 }
1116
1117 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1118                 const struct dwc3_event_depevt *event)
1119 {
1120         u8                      epnum = event->endpoint_number;
1121
1122         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1123                         dwc3_ep_event_string(event->endpoint_event),
1124                         epnum >> 1, (epnum & 1) ? "in" : "out",
1125                         dwc3_ep0_state_string(dwc->ep0state));
1126
1127         switch (event->endpoint_event) {
1128         case DWC3_DEPEVT_XFERCOMPLETE:
1129                 dwc3_ep0_xfer_complete(dwc, event);
1130                 break;
1131
1132         case DWC3_DEPEVT_XFERNOTREADY:
1133                 dwc3_ep0_xfernotready(dwc, event);
1134                 break;
1135
1136         case DWC3_DEPEVT_XFERINPROGRESS:
1137         case DWC3_DEPEVT_RXTXFIFOEVT:
1138         case DWC3_DEPEVT_STREAMEVT:
1139         case DWC3_DEPEVT_EPCMDCMPLT:
1140                 break;
1141         }
1142 }