2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
58 static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
59 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
64 dep = dwc->eps[epnum];
66 trb = &dwc->ep0_trb[dep->free_slot];
71 trb->bpl = lower_32_bits(buf_dma);
72 trb->bph = upper_32_bits(buf_dma);
76 trb->ctrl |= (DWC3_TRB_CTRL_HWO
77 | DWC3_TRB_CTRL_ISP_IMI);
80 trb->ctrl |= DWC3_TRB_CTRL_CHN;
82 trb->ctrl |= (DWC3_TRB_CTRL_IOC
85 trace_dwc3_prepare_trb(dep, trb);
88 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
90 struct dwc3_gadget_ep_cmd_params params;
94 dep = dwc->eps[epnum];
95 if (dep->flags & DWC3_EP_BUSY) {
96 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
100 memset(¶ms, 0, sizeof(params));
101 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
102 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
104 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
105 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
107 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
112 dep->flags |= DWC3_EP_BUSY;
113 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
116 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
121 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
122 struct dwc3_request *req)
124 struct dwc3 *dwc = dep->dwc;
126 req->request.actual = 0;
127 req->request.status = -EINPROGRESS;
128 req->epnum = dep->number;
130 list_add_tail(&req->list, &dep->request_list);
133 * Gadget driver might not be quick enough to queue a request
134 * before we get a Transfer Not Ready event on this endpoint.
136 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
137 * flag is set, it's telling us that as soon as Gadget queues the
138 * required request, we should kick the transfer here because the
139 * IRQ we were waiting for is long gone.
141 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
144 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
146 if (dwc->ep0state != EP0_DATA_PHASE) {
147 dev_WARN(dwc->dev, "Unexpected pending request\n");
151 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
153 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
160 * In case gadget driver asked us to delay the STATUS phase,
163 if (dwc->delayed_status) {
166 direction = !dwc->ep0_expect_in;
167 dwc->delayed_status = false;
168 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
170 if (dwc->ep0state == EP0_STATUS_PHASE)
171 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
173 dwc3_trace(trace_dwc3_ep0,
174 "too early for delayed status");
180 * Unfortunately we have uncovered a limitation wrt the Data Phase.
182 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
183 * come before issueing Start Transfer command, but if we do, we will
184 * miss situations where the host starts another SETUP phase instead of
185 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
186 * Layer Compliance Suite.
188 * The problem surfaces due to the fact that in case of back-to-back
189 * SETUP packets there will be no XferNotReady(DATA) generated and we
190 * will be stuck waiting for XferNotReady(DATA) forever.
192 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
193 * it tells us to start Data Phase right away. It also mentions that if
194 * we receive a SETUP phase instead of the DATA phase, core will issue
195 * XferComplete for the DATA phase, before actually initiating it in
196 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
197 * can only be used to print some debugging logs, as the core expects
198 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
199 * just so it completes right away, without transferring anything and,
200 * only then, we can go back to the SETUP phase.
202 * Because of this scenario, SNPS decided to change the programming
203 * model of control transfers and support on-demand transfers only for
204 * the STATUS phase. To fix the issue we have now, we will always wait
205 * for gadget driver to queue the DATA phase's struct usb_request, then
206 * start it right away.
208 * If we're actually in a 2-stage transfer, we will wait for
209 * XferNotReady(STATUS).
211 if (dwc->three_stage_setup) {
214 direction = dwc->ep0_expect_in;
215 dwc->ep0state = EP0_DATA_PHASE;
217 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
219 dep->flags &= ~DWC3_EP0_DIR_IN;
225 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
228 struct dwc3_request *req = to_dwc3_request(request);
229 struct dwc3_ep *dep = to_dwc3_ep(ep);
230 struct dwc3 *dwc = dep->dwc;
236 spin_lock_irqsave(&dwc->lock, flags);
237 if (!dep->endpoint.desc) {
238 dwc3_trace(trace_dwc3_ep0,
239 "trying to queue request %p to disabled %s",
245 /* we share one TRB for ep0/1 */
246 if (!list_empty(&dep->request_list)) {
251 dwc3_trace(trace_dwc3_ep0,
252 "queueing request %p to %s length %d state '%s'",
253 request, dep->name, request->length,
254 dwc3_ep0_state_string(dwc->ep0state));
256 ret = __dwc3_gadget_ep0_queue(dep, req);
259 spin_unlock_irqrestore(&dwc->lock, flags);
264 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
268 /* reinitialize physical ep1 */
270 dep->flags = DWC3_EP_ENABLED;
272 /* stall is always issued on EP0 */
274 __dwc3_gadget_ep_set_halt(dep, 1, false);
275 dep->flags = DWC3_EP_ENABLED;
276 dwc->delayed_status = false;
278 if (!list_empty(&dep->request_list)) {
279 struct dwc3_request *req;
281 req = next_request(&dep->request_list);
282 dwc3_gadget_giveback(dep, req, -ECONNRESET);
285 dwc->ep0state = EP0_SETUP_PHASE;
286 dwc3_ep0_out_start(dwc);
289 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
291 struct dwc3_ep *dep = to_dwc3_ep(ep);
292 struct dwc3 *dwc = dep->dwc;
294 dwc3_ep0_stall_and_restart(dwc);
299 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
301 struct dwc3_ep *dep = to_dwc3_ep(ep);
302 struct dwc3 *dwc = dep->dwc;
306 spin_lock_irqsave(&dwc->lock, flags);
307 ret = __dwc3_gadget_ep0_set_halt(ep, value);
308 spin_unlock_irqrestore(&dwc->lock, flags);
313 void dwc3_ep0_out_start(struct dwc3 *dwc)
317 dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8,
318 DWC3_TRBCTL_CONTROL_SETUP, false);
319 ret = dwc3_ep0_start_trans(dwc, 0);
323 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
326 u32 windex = le16_to_cpu(wIndex_le);
329 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
330 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
333 dep = dwc->eps[epnum];
337 if (dep->flags & DWC3_EP_ENABLED)
343 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
349 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
350 struct usb_ctrlrequest *ctrl)
356 __le16 *response_pkt;
358 recip = ctrl->bRequestType & USB_RECIP_MASK;
360 case USB_RECIP_DEVICE:
362 * LTM will be set once we know how to set this in HW.
364 usb_status |= dwc->gadget.is_selfpowered;
366 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
367 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
368 if (reg & DWC3_DCTL_INITU1ENA)
369 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
370 if (reg & DWC3_DCTL_INITU2ENA)
371 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
376 case USB_RECIP_INTERFACE:
378 * Function Remote Wake Capable D0
379 * Function Remote Wakeup D1
383 case USB_RECIP_ENDPOINT:
384 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
388 if (dep->flags & DWC3_EP_STALL)
389 usb_status = 1 << USB_ENDPOINT_HALT;
395 response_pkt = (__le16 *) dwc->setup_buf;
396 *response_pkt = cpu_to_le16(usb_status);
399 dwc->ep0_usb_req.dep = dep;
400 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
401 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
402 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
404 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
407 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
408 struct usb_ctrlrequest *ctrl, int set)
416 enum usb_device_state state;
418 wValue = le16_to_cpu(ctrl->wValue);
419 wIndex = le16_to_cpu(ctrl->wIndex);
420 recip = ctrl->bRequestType & USB_RECIP_MASK;
421 state = dwc->gadget.state;
424 case USB_RECIP_DEVICE:
427 case USB_DEVICE_REMOTE_WAKEUP:
430 * 9.4.1 says only only for SS, in AddressState only for
431 * default control pipe
433 case USB_DEVICE_U1_ENABLE:
434 if (state != USB_STATE_CONFIGURED)
436 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
439 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
441 reg |= DWC3_DCTL_INITU1ENA;
443 reg &= ~DWC3_DCTL_INITU1ENA;
444 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
447 case USB_DEVICE_U2_ENABLE:
448 if (state != USB_STATE_CONFIGURED)
450 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
453 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
455 reg |= DWC3_DCTL_INITU2ENA;
457 reg &= ~DWC3_DCTL_INITU2ENA;
458 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
461 case USB_DEVICE_LTM_ENABLE:
464 case USB_DEVICE_TEST_MODE:
465 if ((wIndex & 0xff) != 0)
470 dwc->test_mode_nr = wIndex >> 8;
471 dwc->test_mode = true;
478 case USB_RECIP_INTERFACE:
480 case USB_INTRF_FUNC_SUSPEND:
481 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
482 /* XXX enable Low power suspend */
484 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
485 /* XXX enable remote wakeup */
493 case USB_RECIP_ENDPOINT:
495 case USB_ENDPOINT_HALT:
496 dep = dwc3_wIndex_to_dep(dwc, wIndex);
499 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
501 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
517 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
519 enum usb_device_state state = dwc->gadget.state;
523 addr = le16_to_cpu(ctrl->wValue);
525 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
529 if (state == USB_STATE_CONFIGURED) {
530 dwc3_trace(trace_dwc3_ep0,
531 "trying to set address when configured");
535 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
536 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
537 reg |= DWC3_DCFG_DEVADDR(addr);
538 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
541 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
543 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
548 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
552 spin_unlock(&dwc->lock);
553 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
554 spin_lock(&dwc->lock);
558 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
560 enum usb_device_state state = dwc->gadget.state;
565 cfg = le16_to_cpu(ctrl->wValue);
568 case USB_STATE_DEFAULT:
571 case USB_STATE_ADDRESS:
572 ret = dwc3_ep0_delegate_req(dwc, ctrl);
573 /* if the cfg matches and the cfg is non zero */
574 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
577 * only change state if set_config has already
578 * been processed. If gadget driver returns
579 * USB_GADGET_DELAYED_STATUS, we will wait
580 * to change the state on the next usb_ep_queue()
583 usb_gadget_set_state(&dwc->gadget,
584 USB_STATE_CONFIGURED);
587 * Enable transition to U1/U2 state when
588 * nothing is pending from application.
590 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
591 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
592 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
594 dwc->resize_fifos = true;
595 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
599 case USB_STATE_CONFIGURED:
600 ret = dwc3_ep0_delegate_req(dwc, ctrl);
602 usb_gadget_set_state(&dwc->gadget,
611 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
613 struct dwc3_ep *dep = to_dwc3_ep(ep);
614 struct dwc3 *dwc = dep->dwc;
628 memcpy(&timing, req->buf, sizeof(timing));
630 dwc->u1sel = timing.u1sel;
631 dwc->u1pel = timing.u1pel;
632 dwc->u2sel = le16_to_cpu(timing.u2sel);
633 dwc->u2pel = le16_to_cpu(timing.u2pel);
635 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
636 if (reg & DWC3_DCTL_INITU2ENA)
638 if (reg & DWC3_DCTL_INITU1ENA)
642 * According to Synopsys Databook, if parameter is
643 * greater than 125, a value of zero should be
644 * programmed in the register.
649 /* now that we have the time, issue DGCMD Set Sel */
650 ret = dwc3_send_gadget_generic_command(dwc,
651 DWC3_DGCMD_SET_PERIODIC_PAR, param);
655 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
658 enum usb_device_state state = dwc->gadget.state;
662 if (state == USB_STATE_DEFAULT)
665 wValue = le16_to_cpu(ctrl->wValue);
666 wLength = le16_to_cpu(ctrl->wLength);
669 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
675 * To handle Set SEL we need to receive 6 bytes from Host. So let's
676 * queue a usb_request for 6 bytes.
678 * Remember, though, this controller can't handle non-wMaxPacketSize
679 * aligned transfers on the OUT direction, so we queue a request for
680 * wMaxPacketSize instead.
683 dwc->ep0_usb_req.dep = dep;
684 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
685 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
686 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
688 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
691 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
697 wValue = le16_to_cpu(ctrl->wValue);
698 wLength = le16_to_cpu(ctrl->wLength);
699 wIndex = le16_to_cpu(ctrl->wIndex);
701 if (wIndex || wLength)
705 * REVISIT It's unclear from Databook what to do with this
706 * value. For now, just cache it.
708 dwc->isoch_delay = wValue;
713 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
717 switch (ctrl->bRequest) {
718 case USB_REQ_GET_STATUS:
719 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
720 ret = dwc3_ep0_handle_status(dwc, ctrl);
722 case USB_REQ_CLEAR_FEATURE:
723 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
724 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
726 case USB_REQ_SET_FEATURE:
727 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
728 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
730 case USB_REQ_SET_ADDRESS:
731 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
732 ret = dwc3_ep0_set_address(dwc, ctrl);
734 case USB_REQ_SET_CONFIGURATION:
735 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
736 ret = dwc3_ep0_set_config(dwc, ctrl);
738 case USB_REQ_SET_SEL:
739 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
740 ret = dwc3_ep0_set_sel(dwc, ctrl);
742 case USB_REQ_SET_ISOCH_DELAY:
743 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
744 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
747 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
748 ret = dwc3_ep0_delegate_req(dwc, ctrl);
755 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
756 const struct dwc3_event_depevt *event)
758 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
762 if (!dwc->gadget_driver)
765 trace_dwc3_ctrl_req(ctrl);
767 len = le16_to_cpu(ctrl->wLength);
769 dwc->three_stage_setup = false;
770 dwc->ep0_expect_in = false;
771 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
773 dwc->three_stage_setup = true;
774 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
775 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
778 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
779 ret = dwc3_ep0_std_request(dwc, ctrl);
781 ret = dwc3_ep0_delegate_req(dwc, ctrl);
783 if (ret == USB_GADGET_DELAYED_STATUS)
784 dwc->delayed_status = true;
788 dwc3_ep0_stall_and_restart(dwc);
791 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
792 const struct dwc3_event_depevt *event)
794 struct dwc3_request *r = NULL;
795 struct usb_request *ur;
796 struct dwc3_trb *trb;
798 unsigned transfer_size = 0;
800 unsigned remaining_ur_length;
807 epnum = event->endpoint_number;
810 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
814 trace_dwc3_complete_trb(ep0, trb);
816 r = next_request(&ep0->request_list);
820 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
821 if (status == DWC3_TRBSTS_SETUP_PENDING) {
822 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
825 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
832 remaining_ur_length = ur->length;
834 length = trb->size & DWC3_TRB_SIZE_MASK;
836 maxp = ep0->endpoint.maxpacket;
838 if (dwc->ep0_bounced) {
840 * Handle the first TRB before handling the bounce buffer if
841 * the request length is greater than the bounce buffer size
843 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
844 transfer_size = ALIGN(ur->length - maxp, maxp);
845 transferred = transfer_size - length;
846 buf = (u8 *)buf + transferred;
847 ur->actual += transferred;
848 remaining_ur_length -= transferred;
851 length = trb->size & DWC3_TRB_SIZE_MASK;
856 transfer_size = roundup((ur->length - transfer_size),
859 transferred = min_t(u32, remaining_ur_length,
860 transfer_size - length);
861 memcpy(buf, dwc->ep0_bounce, transferred);
863 transferred = ur->length - length;
866 ur->actual += transferred;
868 if ((epnum & 1) && ur->actual < ur->length) {
869 /* for some reason we did not get everything out */
871 dwc3_ep0_stall_and_restart(dwc);
873 dwc3_gadget_giveback(ep0, r, 0);
875 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
876 ur->length && ur->zero) {
879 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
881 dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr,
882 0, DWC3_TRBCTL_CONTROL_DATA, false);
883 ret = dwc3_ep0_start_trans(dwc, epnum);
889 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
890 const struct dwc3_event_depevt *event)
892 struct dwc3_request *r;
894 struct dwc3_trb *trb;
900 trace_dwc3_complete_trb(dep, trb);
902 if (!list_empty(&dep->request_list)) {
903 r = next_request(&dep->request_list);
905 dwc3_gadget_giveback(dep, r, 0);
908 if (dwc->test_mode) {
911 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
913 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
915 dwc3_ep0_stall_and_restart(dwc);
920 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
921 if (status == DWC3_TRBSTS_SETUP_PENDING)
922 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
924 dwc->ep0state = EP0_SETUP_PHASE;
925 dwc3_ep0_out_start(dwc);
928 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
929 const struct dwc3_event_depevt *event)
931 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
933 dep->flags &= ~DWC3_EP_BUSY;
934 dep->resource_index = 0;
935 dwc->setup_packet_pending = false;
937 switch (dwc->ep0state) {
938 case EP0_SETUP_PHASE:
939 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
940 dwc3_ep0_inspect_setup(dwc, event);
944 dwc3_trace(trace_dwc3_ep0, "Data Phase");
945 dwc3_ep0_complete_data(dwc, event);
948 case EP0_STATUS_PHASE:
949 dwc3_trace(trace_dwc3_ep0, "Status Phase");
950 dwc3_ep0_complete_status(dwc, event);
953 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
957 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
958 struct dwc3_ep *dep, struct dwc3_request *req)
962 req->direction = !!dep->number;
964 if (req->request.length == 0) {
965 dwc3_ep0_prepare_one_trb(dwc, dep->number,
966 dwc->ctrl_req_addr, 0,
967 DWC3_TRBCTL_CONTROL_DATA, false);
968 ret = dwc3_ep0_start_trans(dwc, dep->number);
969 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
970 && (dep->number == 0)) {
971 u32 transfer_size = 0;
974 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
977 dev_dbg(dwc->dev, "failed to map request\n");
981 maxpacket = dep->endpoint.maxpacket;
983 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
984 transfer_size = ALIGN(req->request.length - maxpacket,
986 dwc3_ep0_prepare_one_trb(dwc, dep->number,
989 DWC3_TRBCTL_CONTROL_DATA,
993 transfer_size = roundup((req->request.length - transfer_size),
996 dwc->ep0_bounced = true;
998 dwc3_ep0_prepare_one_trb(dwc, dep->number,
999 dwc->ep0_bounce_addr, transfer_size,
1000 DWC3_TRBCTL_CONTROL_DATA, false);
1001 ret = dwc3_ep0_start_trans(dwc, dep->number);
1003 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1006 dev_dbg(dwc->dev, "failed to map request\n");
1010 dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma,
1011 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1013 ret = dwc3_ep0_start_trans(dwc, dep->number);
1019 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1021 struct dwc3 *dwc = dep->dwc;
1024 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1025 : DWC3_TRBCTL_CONTROL_STATUS2;
1027 dwc3_ep0_prepare_one_trb(dwc, dep->number,
1028 dwc->ctrl_req_addr, 0, type, false);
1029 return dwc3_ep0_start_trans(dwc, dep->number);
1032 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1034 if (dwc->resize_fifos) {
1035 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
1036 dwc3_gadget_resize_tx_fifos(dwc);
1037 dwc->resize_fifos = 0;
1040 WARN_ON(dwc3_ep0_start_control_status(dep));
1043 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1044 const struct dwc3_event_depevt *event)
1046 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1048 __dwc3_ep0_do_control_status(dwc, dep);
1051 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1053 struct dwc3_gadget_ep_cmd_params params;
1057 if (!dep->resource_index)
1060 cmd = DWC3_DEPCMD_ENDTRANSFER;
1061 cmd |= DWC3_DEPCMD_CMDIOC;
1062 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1063 memset(¶ms, 0, sizeof(params));
1064 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1066 dep->resource_index = 0;
1069 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1070 const struct dwc3_event_depevt *event)
1072 dwc->setup_packet_pending = true;
1074 switch (event->status) {
1075 case DEPEVT_STATUS_CONTROL_DATA:
1076 dwc3_trace(trace_dwc3_ep0, "Control Data");
1079 * We already have a DATA transfer in the controller's cache,
1080 * if we receive a XferNotReady(DATA) we will ignore it, unless
1081 * it's for the wrong direction.
1083 * In that case, we must issue END_TRANSFER command to the Data
1084 * Phase we already have started and issue SetStall on the
1087 if (dwc->ep0_expect_in != event->endpoint_number) {
1088 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1090 dwc3_trace(trace_dwc3_ep0,
1091 "Wrong direction for Data phase");
1092 dwc3_ep0_end_control_data(dwc, dep);
1093 dwc3_ep0_stall_and_restart(dwc);
1099 case DEPEVT_STATUS_CONTROL_STATUS:
1100 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1103 dwc3_trace(trace_dwc3_ep0, "Control Status");
1105 dwc->ep0state = EP0_STATUS_PHASE;
1107 if (dwc->delayed_status) {
1108 WARN_ON_ONCE(event->endpoint_number != 1);
1109 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1113 dwc3_ep0_do_control_status(dwc, event);
1117 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1118 const struct dwc3_event_depevt *event)
1120 u8 epnum = event->endpoint_number;
1122 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1123 dwc3_ep_event_string(event->endpoint_event),
1124 epnum >> 1, (epnum & 1) ? "in" : "out",
1125 dwc3_ep0_state_string(dwc->ep0state));
1127 switch (event->endpoint_event) {
1128 case DWC3_DEPEVT_XFERCOMPLETE:
1129 dwc3_ep0_xfer_complete(dwc, event);
1132 case DWC3_DEPEVT_XFERNOTREADY:
1133 dwc3_ep0_xfernotready(dwc, event);
1136 case DWC3_DEPEVT_XFERINPROGRESS:
1137 case DWC3_DEPEVT_RXTXFIFOEVT:
1138 case DWC3_DEPEVT_STREAMEVT:
1139 case DWC3_DEPEVT_EPCMDCMPLT: