2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
58 static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
59 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
64 dep = dwc->eps[epnum];
66 trb = &dwc->ep0_trb[dep->trb_enqueue];
71 trb->bpl = lower_32_bits(buf_dma);
72 trb->bph = upper_32_bits(buf_dma);
76 trb->ctrl |= (DWC3_TRB_CTRL_HWO
77 | DWC3_TRB_CTRL_ISP_IMI);
80 trb->ctrl |= DWC3_TRB_CTRL_CHN;
82 trb->ctrl |= (DWC3_TRB_CTRL_IOC
85 trace_dwc3_prepare_trb(dep, trb);
88 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
90 struct dwc3_gadget_ep_cmd_params params;
94 dep = dwc->eps[epnum];
95 if (dep->flags & DWC3_EP_BUSY) {
96 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
100 memset(¶ms, 0, sizeof(params));
101 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
102 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
104 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
106 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
111 dep->flags |= DWC3_EP_BUSY;
112 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
113 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
119 struct dwc3_request *req)
121 struct dwc3 *dwc = dep->dwc;
123 req->request.actual = 0;
124 req->request.status = -EINPROGRESS;
125 req->epnum = dep->number;
127 list_add_tail(&req->list, &dep->pending_list);
130 * Gadget driver might not be quick enough to queue a request
131 * before we get a Transfer Not Ready event on this endpoint.
133 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
134 * flag is set, it's telling us that as soon as Gadget queues the
135 * required request, we should kick the transfer here because the
136 * IRQ we were waiting for is long gone.
138 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
141 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
143 if (dwc->ep0state != EP0_DATA_PHASE) {
144 dev_WARN(dwc->dev, "Unexpected pending request\n");
148 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
150 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
157 * In case gadget driver asked us to delay the STATUS phase,
160 if (dwc->delayed_status) {
163 direction = !dwc->ep0_expect_in;
164 dwc->delayed_status = false;
165 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
167 if (dwc->ep0state == EP0_STATUS_PHASE)
168 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
170 dwc3_trace(trace_dwc3_ep0,
171 "too early for delayed status");
177 * Unfortunately we have uncovered a limitation wrt the Data Phase.
179 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
180 * come before issueing Start Transfer command, but if we do, we will
181 * miss situations where the host starts another SETUP phase instead of
182 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
183 * Layer Compliance Suite.
185 * The problem surfaces due to the fact that in case of back-to-back
186 * SETUP packets there will be no XferNotReady(DATA) generated and we
187 * will be stuck waiting for XferNotReady(DATA) forever.
189 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
190 * it tells us to start Data Phase right away. It also mentions that if
191 * we receive a SETUP phase instead of the DATA phase, core will issue
192 * XferComplete for the DATA phase, before actually initiating it in
193 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
194 * can only be used to print some debugging logs, as the core expects
195 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
196 * just so it completes right away, without transferring anything and,
197 * only then, we can go back to the SETUP phase.
199 * Because of this scenario, SNPS decided to change the programming
200 * model of control transfers and support on-demand transfers only for
201 * the STATUS phase. To fix the issue we have now, we will always wait
202 * for gadget driver to queue the DATA phase's struct usb_request, then
203 * start it right away.
205 * If we're actually in a 2-stage transfer, we will wait for
206 * XferNotReady(STATUS).
208 if (dwc->three_stage_setup) {
211 direction = dwc->ep0_expect_in;
212 dwc->ep0state = EP0_DATA_PHASE;
214 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
216 dep->flags &= ~DWC3_EP0_DIR_IN;
222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
225 struct dwc3_request *req = to_dwc3_request(request);
226 struct dwc3_ep *dep = to_dwc3_ep(ep);
227 struct dwc3 *dwc = dep->dwc;
233 spin_lock_irqsave(&dwc->lock, flags);
234 if (!dep->endpoint.desc) {
235 dwc3_trace(trace_dwc3_ep0,
236 "trying to queue request %p to disabled %s",
242 /* we share one TRB for ep0/1 */
243 if (!list_empty(&dep->pending_list)) {
248 dwc3_trace(trace_dwc3_ep0,
249 "queueing request %p to %s length %d state '%s'",
250 request, dep->name, request->length,
251 dwc3_ep0_state_string(dwc->ep0state));
253 ret = __dwc3_gadget_ep0_queue(dep, req);
256 spin_unlock_irqrestore(&dwc->lock, flags);
261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
265 /* reinitialize physical ep1 */
267 dep->flags = DWC3_EP_ENABLED;
269 /* stall is always issued on EP0 */
271 __dwc3_gadget_ep_set_halt(dep, 1, false);
272 dep->flags = DWC3_EP_ENABLED;
273 dwc->delayed_status = false;
275 if (!list_empty(&dep->pending_list)) {
276 struct dwc3_request *req;
278 req = next_request(&dep->pending_list);
279 dwc3_gadget_giveback(dep, req, -ECONNRESET);
282 dwc->ep0state = EP0_SETUP_PHASE;
283 dwc3_ep0_out_start(dwc);
286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
288 struct dwc3_ep *dep = to_dwc3_ep(ep);
289 struct dwc3 *dwc = dep->dwc;
291 dwc3_ep0_stall_and_restart(dwc);
296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
298 struct dwc3_ep *dep = to_dwc3_ep(ep);
299 struct dwc3 *dwc = dep->dwc;
303 spin_lock_irqsave(&dwc->lock, flags);
304 ret = __dwc3_gadget_ep0_set_halt(ep, value);
305 spin_unlock_irqrestore(&dwc->lock, flags);
310 void dwc3_ep0_out_start(struct dwc3 *dwc)
314 dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8,
315 DWC3_TRBCTL_CONTROL_SETUP, false);
316 ret = dwc3_ep0_start_trans(dwc, 0);
320 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
323 u32 windex = le16_to_cpu(wIndex_le);
326 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
327 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
330 dep = dwc->eps[epnum];
334 if (dep->flags & DWC3_EP_ENABLED)
340 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
346 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
347 struct usb_ctrlrequest *ctrl)
353 __le16 *response_pkt;
355 recip = ctrl->bRequestType & USB_RECIP_MASK;
357 case USB_RECIP_DEVICE:
359 * LTM will be set once we know how to set this in HW.
361 usb_status |= dwc->gadget.is_selfpowered;
363 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
364 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
365 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
366 if (reg & DWC3_DCTL_INITU1ENA)
367 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
368 if (reg & DWC3_DCTL_INITU2ENA)
369 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
374 case USB_RECIP_INTERFACE:
376 * Function Remote Wake Capable D0
377 * Function Remote Wakeup D1
381 case USB_RECIP_ENDPOINT:
382 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
386 if (dep->flags & DWC3_EP_STALL)
387 usb_status = 1 << USB_ENDPOINT_HALT;
393 response_pkt = (__le16 *) dwc->setup_buf;
394 *response_pkt = cpu_to_le16(usb_status);
397 dwc->ep0_usb_req.dep = dep;
398 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
399 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
400 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
402 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
405 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
406 struct usb_ctrlrequest *ctrl, int set)
414 enum usb_device_state state;
416 wValue = le16_to_cpu(ctrl->wValue);
417 wIndex = le16_to_cpu(ctrl->wIndex);
418 recip = ctrl->bRequestType & USB_RECIP_MASK;
419 state = dwc->gadget.state;
422 case USB_RECIP_DEVICE:
425 case USB_DEVICE_REMOTE_WAKEUP:
428 * 9.4.1 says only only for SS, in AddressState only for
429 * default control pipe
431 case USB_DEVICE_U1_ENABLE:
432 if (state != USB_STATE_CONFIGURED)
434 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
435 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
438 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
440 reg |= DWC3_DCTL_INITU1ENA;
442 reg &= ~DWC3_DCTL_INITU1ENA;
443 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
446 case USB_DEVICE_U2_ENABLE:
447 if (state != USB_STATE_CONFIGURED)
449 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
450 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
453 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
455 reg |= DWC3_DCTL_INITU2ENA;
457 reg &= ~DWC3_DCTL_INITU2ENA;
458 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
461 case USB_DEVICE_LTM_ENABLE:
464 case USB_DEVICE_TEST_MODE:
465 if ((wIndex & 0xff) != 0)
470 switch (wIndex >> 8) {
476 dwc->test_mode_nr = wIndex >> 8;
477 dwc->test_mode = true;
488 case USB_RECIP_INTERFACE:
490 case USB_INTRF_FUNC_SUSPEND:
491 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
492 /* XXX enable Low power suspend */
494 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
495 /* XXX enable remote wakeup */
503 case USB_RECIP_ENDPOINT:
505 case USB_ENDPOINT_HALT:
506 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
509 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
511 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
527 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
529 enum usb_device_state state = dwc->gadget.state;
533 addr = le16_to_cpu(ctrl->wValue);
535 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
539 if (state == USB_STATE_CONFIGURED) {
540 dwc3_trace(trace_dwc3_ep0,
541 "trying to set address when configured");
545 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
546 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
547 reg |= DWC3_DCFG_DEVADDR(addr);
548 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
551 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
553 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
558 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
562 spin_unlock(&dwc->lock);
563 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
564 spin_lock(&dwc->lock);
568 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
570 enum usb_device_state state = dwc->gadget.state;
575 cfg = le16_to_cpu(ctrl->wValue);
578 case USB_STATE_DEFAULT:
581 case USB_STATE_ADDRESS:
582 ret = dwc3_ep0_delegate_req(dwc, ctrl);
583 /* if the cfg matches and the cfg is non zero */
584 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
587 * only change state if set_config has already
588 * been processed. If gadget driver returns
589 * USB_GADGET_DELAYED_STATUS, we will wait
590 * to change the state on the next usb_ep_queue()
593 usb_gadget_set_state(&dwc->gadget,
594 USB_STATE_CONFIGURED);
597 * Enable transition to U1/U2 state when
598 * nothing is pending from application.
600 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
601 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
602 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
606 case USB_STATE_CONFIGURED:
607 ret = dwc3_ep0_delegate_req(dwc, ctrl);
609 usb_gadget_set_state(&dwc->gadget,
618 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
620 struct dwc3_ep *dep = to_dwc3_ep(ep);
621 struct dwc3 *dwc = dep->dwc;
635 memcpy(&timing, req->buf, sizeof(timing));
637 dwc->u1sel = timing.u1sel;
638 dwc->u1pel = timing.u1pel;
639 dwc->u2sel = le16_to_cpu(timing.u2sel);
640 dwc->u2pel = le16_to_cpu(timing.u2pel);
642 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
643 if (reg & DWC3_DCTL_INITU2ENA)
645 if (reg & DWC3_DCTL_INITU1ENA)
649 * According to Synopsys Databook, if parameter is
650 * greater than 125, a value of zero should be
651 * programmed in the register.
656 /* now that we have the time, issue DGCMD Set Sel */
657 ret = dwc3_send_gadget_generic_command(dwc,
658 DWC3_DGCMD_SET_PERIODIC_PAR, param);
662 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
665 enum usb_device_state state = dwc->gadget.state;
669 if (state == USB_STATE_DEFAULT)
672 wValue = le16_to_cpu(ctrl->wValue);
673 wLength = le16_to_cpu(ctrl->wLength);
676 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
682 * To handle Set SEL we need to receive 6 bytes from Host. So let's
683 * queue a usb_request for 6 bytes.
685 * Remember, though, this controller can't handle non-wMaxPacketSize
686 * aligned transfers on the OUT direction, so we queue a request for
687 * wMaxPacketSize instead.
690 dwc->ep0_usb_req.dep = dep;
691 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
692 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
693 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
695 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
698 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
704 wValue = le16_to_cpu(ctrl->wValue);
705 wLength = le16_to_cpu(ctrl->wLength);
706 wIndex = le16_to_cpu(ctrl->wIndex);
708 if (wIndex || wLength)
712 * REVISIT It's unclear from Databook what to do with this
713 * value. For now, just cache it.
715 dwc->isoch_delay = wValue;
720 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
724 switch (ctrl->bRequest) {
725 case USB_REQ_GET_STATUS:
726 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
727 ret = dwc3_ep0_handle_status(dwc, ctrl);
729 case USB_REQ_CLEAR_FEATURE:
730 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
731 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
733 case USB_REQ_SET_FEATURE:
734 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
735 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
737 case USB_REQ_SET_ADDRESS:
738 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
739 ret = dwc3_ep0_set_address(dwc, ctrl);
741 case USB_REQ_SET_CONFIGURATION:
742 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
743 ret = dwc3_ep0_set_config(dwc, ctrl);
745 case USB_REQ_SET_SEL:
746 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
747 ret = dwc3_ep0_set_sel(dwc, ctrl);
749 case USB_REQ_SET_ISOCH_DELAY:
750 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
751 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
754 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
755 ret = dwc3_ep0_delegate_req(dwc, ctrl);
762 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
763 const struct dwc3_event_depevt *event)
765 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
769 if (!dwc->gadget_driver)
772 trace_dwc3_ctrl_req(ctrl);
774 len = le16_to_cpu(ctrl->wLength);
776 dwc->three_stage_setup = false;
777 dwc->ep0_expect_in = false;
778 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
780 dwc->three_stage_setup = true;
781 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
782 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
785 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
786 ret = dwc3_ep0_std_request(dwc, ctrl);
788 ret = dwc3_ep0_delegate_req(dwc, ctrl);
790 if (ret == USB_GADGET_DELAYED_STATUS)
791 dwc->delayed_status = true;
795 dwc3_ep0_stall_and_restart(dwc);
798 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
799 const struct dwc3_event_depevt *event)
801 struct dwc3_request *r = NULL;
802 struct usb_request *ur;
803 struct dwc3_trb *trb;
805 unsigned transfer_size = 0;
807 unsigned remaining_ur_length;
814 epnum = event->endpoint_number;
817 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
821 trace_dwc3_complete_trb(ep0, trb);
823 r = next_request(&ep0->pending_list);
827 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
828 if (status == DWC3_TRBSTS_SETUP_PENDING) {
829 dwc->setup_packet_pending = true;
831 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
834 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
841 remaining_ur_length = ur->length;
843 length = trb->size & DWC3_TRB_SIZE_MASK;
845 maxp = ep0->endpoint.maxpacket;
847 if (dwc->ep0_bounced) {
849 * Handle the first TRB before handling the bounce buffer if
850 * the request length is greater than the bounce buffer size
852 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
853 transfer_size = ALIGN(ur->length - maxp, maxp);
854 transferred = transfer_size - length;
855 buf = (u8 *)buf + transferred;
856 ur->actual += transferred;
857 remaining_ur_length -= transferred;
860 length = trb->size & DWC3_TRB_SIZE_MASK;
862 ep0->trb_enqueue = 0;
865 transfer_size = roundup((ur->length - transfer_size),
868 transferred = min_t(u32, remaining_ur_length,
869 transfer_size - length);
870 memcpy(buf, dwc->ep0_bounce, transferred);
872 transferred = ur->length - length;
875 ur->actual += transferred;
877 if ((epnum & 1) && ur->actual < ur->length) {
878 /* for some reason we did not get everything out */
880 dwc3_ep0_stall_and_restart(dwc);
882 dwc3_gadget_giveback(ep0, r, 0);
884 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
885 ur->length && ur->zero) {
888 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
890 dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr,
891 0, DWC3_TRBCTL_CONTROL_DATA, false);
892 ret = dwc3_ep0_start_trans(dwc, epnum);
898 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
899 const struct dwc3_event_depevt *event)
901 struct dwc3_request *r;
903 struct dwc3_trb *trb;
909 trace_dwc3_complete_trb(dep, trb);
911 if (!list_empty(&dep->pending_list)) {
912 r = next_request(&dep->pending_list);
914 dwc3_gadget_giveback(dep, r, 0);
917 if (dwc->test_mode) {
920 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
922 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
924 dwc3_ep0_stall_and_restart(dwc);
929 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
930 if (status == DWC3_TRBSTS_SETUP_PENDING) {
931 dwc->setup_packet_pending = true;
932 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
935 dwc->ep0state = EP0_SETUP_PHASE;
936 dwc3_ep0_out_start(dwc);
939 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
940 const struct dwc3_event_depevt *event)
942 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
944 dep->flags &= ~DWC3_EP_BUSY;
945 dep->resource_index = 0;
946 dwc->setup_packet_pending = false;
948 switch (dwc->ep0state) {
949 case EP0_SETUP_PHASE:
950 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
951 dwc3_ep0_inspect_setup(dwc, event);
955 dwc3_trace(trace_dwc3_ep0, "Data Phase");
956 dwc3_ep0_complete_data(dwc, event);
959 case EP0_STATUS_PHASE:
960 dwc3_trace(trace_dwc3_ep0, "Status Phase");
961 dwc3_ep0_complete_status(dwc, event);
964 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
968 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
969 struct dwc3_ep *dep, struct dwc3_request *req)
973 req->direction = !!dep->number;
975 if (req->request.length == 0) {
976 dwc3_ep0_prepare_one_trb(dwc, dep->number,
977 dwc->ctrl_req_addr, 0,
978 DWC3_TRBCTL_CONTROL_DATA, false);
979 ret = dwc3_ep0_start_trans(dwc, dep->number);
980 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
981 && (dep->number == 0)) {
982 u32 transfer_size = 0;
985 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
988 dwc3_trace(trace_dwc3_ep0, "failed to map request");
992 maxpacket = dep->endpoint.maxpacket;
994 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
995 transfer_size = ALIGN(req->request.length - maxpacket,
997 dwc3_ep0_prepare_one_trb(dwc, dep->number,
1000 DWC3_TRBCTL_CONTROL_DATA,
1004 transfer_size = roundup((req->request.length - transfer_size),
1007 dwc->ep0_bounced = true;
1009 dwc3_ep0_prepare_one_trb(dwc, dep->number,
1010 dwc->ep0_bounce_addr, transfer_size,
1011 DWC3_TRBCTL_CONTROL_DATA, false);
1012 ret = dwc3_ep0_start_trans(dwc, dep->number);
1014 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1017 dwc3_trace(trace_dwc3_ep0, "failed to map request");
1021 dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma,
1022 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1024 ret = dwc3_ep0_start_trans(dwc, dep->number);
1030 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1032 struct dwc3 *dwc = dep->dwc;
1035 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1036 : DWC3_TRBCTL_CONTROL_STATUS2;
1038 dwc3_ep0_prepare_one_trb(dwc, dep->number,
1039 dwc->ctrl_req_addr, 0, type, false);
1040 return dwc3_ep0_start_trans(dwc, dep->number);
1043 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1045 WARN_ON(dwc3_ep0_start_control_status(dep));
1048 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1049 const struct dwc3_event_depevt *event)
1051 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1053 __dwc3_ep0_do_control_status(dwc, dep);
1056 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1058 struct dwc3_gadget_ep_cmd_params params;
1062 if (!dep->resource_index)
1065 cmd = DWC3_DEPCMD_ENDTRANSFER;
1066 cmd |= DWC3_DEPCMD_CMDIOC;
1067 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1068 memset(¶ms, 0, sizeof(params));
1069 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1071 dep->resource_index = 0;
1074 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1075 const struct dwc3_event_depevt *event)
1077 switch (event->status) {
1078 case DEPEVT_STATUS_CONTROL_DATA:
1079 dwc3_trace(trace_dwc3_ep0, "Control Data");
1082 * We already have a DATA transfer in the controller's cache,
1083 * if we receive a XferNotReady(DATA) we will ignore it, unless
1084 * it's for the wrong direction.
1086 * In that case, we must issue END_TRANSFER command to the Data
1087 * Phase we already have started and issue SetStall on the
1090 if (dwc->ep0_expect_in != event->endpoint_number) {
1091 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1093 dwc3_trace(trace_dwc3_ep0,
1094 "Wrong direction for Data phase");
1095 dwc3_ep0_end_control_data(dwc, dep);
1096 dwc3_ep0_stall_and_restart(dwc);
1102 case DEPEVT_STATUS_CONTROL_STATUS:
1103 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1106 dwc3_trace(trace_dwc3_ep0, "Control Status");
1108 dwc->ep0state = EP0_STATUS_PHASE;
1110 if (dwc->delayed_status) {
1111 WARN_ON_ONCE(event->endpoint_number != 1);
1112 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1116 dwc3_ep0_do_control_status(dwc, event);
1120 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1121 const struct dwc3_event_depevt *event)
1123 dwc3_trace(trace_dwc3_ep0, "%s: state '%s'",
1124 dwc3_ep_event_string(event),
1125 dwc3_ep0_state_string(dwc->ep0state));
1127 switch (event->endpoint_event) {
1128 case DWC3_DEPEVT_XFERCOMPLETE:
1129 dwc3_ep0_xfer_complete(dwc, event);
1132 case DWC3_DEPEVT_XFERNOTREADY:
1133 dwc3_ep0_xfernotready(dwc, event);
1136 case DWC3_DEPEVT_XFERINPROGRESS:
1137 case DWC3_DEPEVT_RXTXFIFOEVT:
1138 case DWC3_DEPEVT_STREAMEVT:
1139 case DWC3_DEPEVT_EPCMDCMPLT: