drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum,
  59                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_trb                 *trb;
  62         struct dwc3_ep                  *dep;
  63
  64         dep = dwc->eps[epnum];
  65
  66         trb = &dwc->ep0_trb[dep->trb_enqueue];
  67
  68         if (chain)
  69                 dep->trb_enqueue++;
  70
  71         trb->bpl = lower_32_bits(buf_dma);
  72         trb->bph = upper_32_bits(buf_dma);
  73         trb->size = len;
  74         trb->ctrl = type;
  75
  76         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  77                         | DWC3_TRB_CTRL_ISP_IMI);
  78
  79         if (chain)
  80                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  81         else
  82                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  83                                 | DWC3_TRB_CTRL_LST);
  84
  85         trace_dwc3_prepare_trb(dep, trb);
  86 }
  87
  88 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum)
  89 {
  90         struct dwc3_gadget_ep_cmd_params params;
  91         struct dwc3_ep                  *dep;
  92         int                             ret;
  93
  94         dep = dwc->eps[epnum];
  95         if (dep->flags & DWC3_EP_BUSY) {
  96                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  97                 return 0;
  98         }
  99
 100         memset(&params, 0, sizeof(params));
 101         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
 102         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
 103
 104         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
 105         if (ret < 0) {
 106                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 107                                 dep->name);
 108                 return ret;
 109         }
 110
 111         dep->flags |= DWC3_EP_BUSY;
 112         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
 113         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 114
 115         return 0;
 116 }
 117
 118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 119                 struct dwc3_request *req)
 120 {
 121         struct dwc3             *dwc = dep->dwc;
 122
 123         req->request.actual     = 0;
 124         req->request.status     = -EINPROGRESS;
 125         req->epnum              = dep->number;
 126
 127         list_add_tail(&req->list, &dep->pending_list);
 128
 129         /*
 130          * Gadget driver might not be quick enough to queue a request
 131          * before we get a Transfer Not Ready event on this endpoint.
 132          *
 133          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 134          * flag is set, it's telling us that as soon as Gadget queues the
 135          * required request, we should kick the transfer here because the
 136          * IRQ we were waiting for is long gone.
 137          */
 138         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 139                 unsigned        direction;
 140
 141                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 142
 143                 if (dwc->ep0state != EP0_DATA_PHASE) {
 144                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 145                         return 0;
 146                 }
 147
 148                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 149
 150                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 151                                 DWC3_EP0_DIR_IN);
 152
 153                 return 0;
 154         }
 155
 156         /*
 157          * In case gadget driver asked us to delay the STATUS phase,
 158          * handle it here.
 159          */
 160         if (dwc->delayed_status) {
 161                 unsigned        direction;
 162
 163                 direction = !dwc->ep0_expect_in;
 164                 dwc->delayed_status = false;
 165                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 166
 167                 if (dwc->ep0state == EP0_STATUS_PHASE)
 168                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 169                 else
 170                         dwc3_trace(trace_dwc3_ep0,
 171                                         "too early for delayed status");
 172
 173                 return 0;
 174         }
 175
 176         /*
 177          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 178          *
 179          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 180          * come before issueing Start Transfer command, but if we do, we will
 181          * miss situations where the host starts another SETUP phase instead of
 182          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 183          * Layer Compliance Suite.
 184          *
 185          * The problem surfaces due to the fact that in case of back-to-back
 186          * SETUP packets there will be no XferNotReady(DATA) generated and we
 187          * will be stuck waiting for XferNotReady(DATA) forever.
 188          *
 189          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 190          * it tells us to start Data Phase right away. It also mentions that if
 191          * we receive a SETUP phase instead of the DATA phase, core will issue
 192          * XferComplete for the DATA phase, before actually initiating it in
 193          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 194          * can only be used to print some debugging logs, as the core expects
 195          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 196          * just so it completes right away, without transferring anything and,
 197          * only then, we can go back to the SETUP phase.
 198          *
 199          * Because of this scenario, SNPS decided to change the programming
 200          * model of control transfers and support on-demand transfers only for
 201          * the STATUS phase. To fix the issue we have now, we will always wait
 202          * for gadget driver to queue the DATA phase's struct usb_request, then
 203          * start it right away.
 204          *
 205          * If we're actually in a 2-stage transfer, we will wait for
 206          * XferNotReady(STATUS).
 207          */
 208         if (dwc->three_stage_setup) {
 209                 unsigned        direction;
 210
 211                 direction = dwc->ep0_expect_in;
 212                 dwc->ep0state = EP0_DATA_PHASE;
 213
 214                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 215
 216                 dep->flags &= ~DWC3_EP0_DIR_IN;
 217         }
 218
 219         return 0;
 220 }
 221
 222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 223                 gfp_t gfp_flags)
 224 {
 225         struct dwc3_request             *req = to_dwc3_request(request);
 226         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 227         struct dwc3                     *dwc = dep->dwc;
 228
 229         unsigned long                   flags;
 230
 231         int                             ret;
 232
 233         spin_lock_irqsave(&dwc->lock, flags);
 234         if (!dep->endpoint.desc) {
 235                 dwc3_trace(trace_dwc3_ep0,
 236                                 "trying to queue request %p to disabled %s",
 237                                 request, dep->name);
 238                 ret = -ESHUTDOWN;
 239                 goto out;
 240         }
 241
 242         /* we share one TRB for ep0/1 */
 243         if (!list_empty(&dep->pending_list)) {
 244                 ret = -EBUSY;
 245                 goto out;
 246         }
 247
 248         dwc3_trace(trace_dwc3_ep0,
 249                         "queueing request %p to %s length %d state '%s'",
 250                         request, dep->name, request->length,
 251                         dwc3_ep0_state_string(dwc->ep0state));
 252
 253         ret = __dwc3_gadget_ep0_queue(dep, req);
 254
 255 out:
 256         spin_unlock_irqrestore(&dwc->lock, flags);
 257
 258         return ret;
 259 }
 260
 261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 262 {
 263         struct dwc3_ep          *dep;
 264
 265         /* reinitialize physical ep1 */
 266         dep = dwc->eps[1];
 267         dep->flags = DWC3_EP_ENABLED;
 268
 269         /* stall is always issued on EP0 */
 270         dep = dwc->eps[0];
 271         __dwc3_gadget_ep_set_halt(dep, 1, false);
 272         dep->flags = DWC3_EP_ENABLED;
 273         dwc->delayed_status = false;
 274
 275         if (!list_empty(&dep->pending_list)) {
 276                 struct dwc3_request     *req;
 277
 278                 req = next_request(&dep->pending_list);
 279                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 280         }
 281
 282         dwc->ep0state = EP0_SETUP_PHASE;
 283         dwc3_ep0_out_start(dwc);
 284 }
 285
 286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 287 {
 288         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 289         struct dwc3                     *dwc = dep->dwc;
 290
 291         dwc3_ep0_stall_and_restart(dwc);
 292
 293         return 0;
 294 }
 295
 296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 297 {
 298         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 299         struct dwc3                     *dwc = dep->dwc;
 300         unsigned long                   flags;
 301         int                             ret;
 302
 303         spin_lock_irqsave(&dwc->lock, flags);
 304         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 305         spin_unlock_irqrestore(&dwc->lock, flags);
 306
 307         return ret;
 308 }
 309
 310 void dwc3_ep0_out_start(struct dwc3 *dwc)
 311 {
 312         int                             ret;
 313
 314         dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8,
 315                         DWC3_TRBCTL_CONTROL_SETUP, false);
 316         ret = dwc3_ep0_start_trans(dwc, 0);
 317         WARN_ON(ret < 0);
 318 }
 319
 320 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 321 {
 322         struct dwc3_ep          *dep;
 323         u32                     windex = le16_to_cpu(wIndex_le);
 324         u32                     epnum;
 325
 326         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 327         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 328                 epnum |= 1;
 329
 330         dep = dwc->eps[epnum];
 331         if (dep == NULL)
 332                 return NULL;
 333
 334         if (dep->flags & DWC3_EP_ENABLED)
 335                 return dep;
 336
 337         return NULL;
 338 }
 339
 340 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 341 {
 342 }
 343 /*
 344  * ch 9.4.5
 345  */
 346 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 347                 struct usb_ctrlrequest *ctrl)
 348 {
 349         struct dwc3_ep          *dep;
 350         u32                     recip;
 351         u32                     reg;
 352         u16                     usb_status = 0;
 353         __le16                  *response_pkt;
 354
 355         recip = ctrl->bRequestType & USB_RECIP_MASK;
 356         switch (recip) {
 357         case USB_RECIP_DEVICE:
 358                 /*
 359                  * LTM will be set once we know how to set this in HW.
 360                  */
 361                 usb_status |= dwc->gadget.is_selfpowered;
 362
 363                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 364                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 365                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 366                         if (reg & DWC3_DCTL_INITU1ENA)
 367                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 368                         if (reg & DWC3_DCTL_INITU2ENA)
 369                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 370                 }
 371
 372                 break;
 373
 374         case USB_RECIP_INTERFACE:
 375                 /*
 376                  * Function Remote Wake Capable D0
 377                  * Function Remote Wakeup       D1
 378                  */
 379                 break;
 380
 381         case USB_RECIP_ENDPOINT:
 382                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 383                 if (!dep)
 384                         return -EINVAL;
 385
 386                 if (dep->flags & DWC3_EP_STALL)
 387                         usb_status = 1 << USB_ENDPOINT_HALT;
 388                 break;
 389         default:
 390                 return -EINVAL;
 391         }
 392
 393         response_pkt = (__le16 *) dwc->setup_buf;
 394         *response_pkt = cpu_to_le16(usb_status);
 395
 396         dep = dwc->eps[0];
 397         dwc->ep0_usb_req.dep = dep;
 398         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 399         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 400         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 401
 402         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 403 }
 404
 405 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 406                 struct usb_ctrlrequest *ctrl, int set)
 407 {
 408         struct dwc3_ep          *dep;
 409         u32                     recip;
 410         u32                     wValue;
 411         u32                     wIndex;
 412         u32                     reg;
 413         int                     ret;
 414         enum usb_device_state   state;
 415
 416         wValue = le16_to_cpu(ctrl->wValue);
 417         wIndex = le16_to_cpu(ctrl->wIndex);
 418         recip = ctrl->bRequestType & USB_RECIP_MASK;
 419         state = dwc->gadget.state;
 420
 421         switch (recip) {
 422         case USB_RECIP_DEVICE:
 423
 424                 switch (wValue) {
 425                 case USB_DEVICE_REMOTE_WAKEUP:
 426                         break;
 427                 /*
 428                  * 9.4.1 says only only for SS, in AddressState only for
 429                  * default control pipe
 430                  */
 431                 case USB_DEVICE_U1_ENABLE:
 432                         if (state != USB_STATE_CONFIGURED)
 433                                 return -EINVAL;
 434                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 435                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 436                                 return -EINVAL;
 437
 438                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 439                         if (set)
 440                                 reg |= DWC3_DCTL_INITU1ENA;
 441                         else
 442                                 reg &= ~DWC3_DCTL_INITU1ENA;
 443                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 444                         break;
 445
 446                 case USB_DEVICE_U2_ENABLE:
 447                         if (state != USB_STATE_CONFIGURED)
 448                                 return -EINVAL;
 449                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 450                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 451                                 return -EINVAL;
 452
 453                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 454                         if (set)
 455                                 reg |= DWC3_DCTL_INITU2ENA;
 456                         else
 457                                 reg &= ~DWC3_DCTL_INITU2ENA;
 458                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 459                         break;
 460
 461                 case USB_DEVICE_LTM_ENABLE:
 462                         return -EINVAL;
 463
 464                 case USB_DEVICE_TEST_MODE:
 465                         if ((wIndex & 0xff) != 0)
 466                                 return -EINVAL;
 467                         if (!set)
 468                                 return -EINVAL;
 469
 470                         switch (wIndex >> 8) {
 471                         case TEST_J:
 472                         case TEST_K:
 473                         case TEST_SE0_NAK:
 474                         case TEST_PACKET:
 475                         case TEST_FORCE_EN:
 476                                 dwc->test_mode_nr = wIndex >> 8;
 477                                 dwc->test_mode = true;
 478                                 break;
 479                         default:
 480                                 return -EINVAL;
 481                         }
 482                         break;
 483                 default:
 484                         return -EINVAL;
 485                 }
 486                 break;
 487
 488         case USB_RECIP_INTERFACE:
 489                 switch (wValue) {
 490                 case USB_INTRF_FUNC_SUSPEND:
 491                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 492                                 /* XXX enable Low power suspend */
 493                                 ;
 494                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 495                                 /* XXX enable remote wakeup */
 496                                 ;
 497                         break;
 498                 default:
 499                         return -EINVAL;
 500                 }
 501                 break;
 502
 503         case USB_RECIP_ENDPOINT:
 504                 switch (wValue) {
 505                 case USB_ENDPOINT_HALT:
 506                         dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 507                         if (!dep)
 508                                 return -EINVAL;
 509                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 510                                 break;
 511                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 512                         if (ret)
 513                                 return -EINVAL;
 514                         break;
 515                 default:
 516                         return -EINVAL;
 517                 }
 518                 break;
 519
 520         default:
 521                 return -EINVAL;
 522         }
 523
 524         return 0;
 525 }
 526
 527 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 528 {
 529         enum usb_device_state state = dwc->gadget.state;
 530         u32 addr;
 531         u32 reg;
 532
 533         addr = le16_to_cpu(ctrl->wValue);
 534         if (addr > 127) {
 535                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 536                 return -EINVAL;
 537         }
 538
 539         if (state == USB_STATE_CONFIGURED) {
 540                 dwc3_trace(trace_dwc3_ep0,
 541                                 "trying to set address when configured");
 542                 return -EINVAL;
 543         }
 544
 545         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 546         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 547         reg |= DWC3_DCFG_DEVADDR(addr);
 548         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 549
 550         if (addr)
 551                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 552         else
 553                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 554
 555         return 0;
 556 }
 557
 558 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 559 {
 560         int ret;
 561
 562         spin_unlock(&dwc->lock);
 563         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 564         spin_lock(&dwc->lock);
 565         return ret;
 566 }
 567
 568 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 569 {
 570         enum usb_device_state state = dwc->gadget.state;
 571         u32 cfg;
 572         int ret;
 573         u32 reg;
 574
 575         cfg = le16_to_cpu(ctrl->wValue);
 576
 577         switch (state) {
 578         case USB_STATE_DEFAULT:
 579                 return -EINVAL;
 580
 581         case USB_STATE_ADDRESS:
 582                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 583                 /* if the cfg matches and the cfg is non zero */
 584                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 585
 586                         /*
 587                          * only change state if set_config has already
 588                          * been processed. If gadget driver returns
 589                          * USB_GADGET_DELAYED_STATUS, we will wait
 590                          * to change the state on the next usb_ep_queue()
 591                          */
 592                         if (ret == 0)
 593                                 usb_gadget_set_state(&dwc->gadget,
 594                                                 USB_STATE_CONFIGURED);
 595
 596                         /*
 597                          * Enable transition to U1/U2 state when
 598                          * nothing is pending from application.
 599                          */
 600                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 601                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 602                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 603                 }
 604                 break;
 605
 606         case USB_STATE_CONFIGURED:
 607                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 608                 if (!cfg && !ret)
 609                         usb_gadget_set_state(&dwc->gadget,
 610                                         USB_STATE_ADDRESS);
 611                 break;
 612         default:
 613                 ret = -EINVAL;
 614         }
 615         return ret;
 616 }
 617
 618 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 619 {
 620         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 621         struct dwc3     *dwc = dep->dwc;
 622
 623         u32             param = 0;
 624         u32             reg;
 625
 626         struct timing {
 627                 u8      u1sel;
 628                 u8      u1pel;
 629                 __le16  u2sel;
 630                 __le16  u2pel;
 631         } __packed timing;
 632
 633         int             ret;
 634
 635         memcpy(&timing, req->buf, sizeof(timing));
 636
 637         dwc->u1sel = timing.u1sel;
 638         dwc->u1pel = timing.u1pel;
 639         dwc->u2sel = le16_to_cpu(timing.u2sel);
 640         dwc->u2pel = le16_to_cpu(timing.u2pel);
 641
 642         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 643         if (reg & DWC3_DCTL_INITU2ENA)
 644                 param = dwc->u2pel;
 645         if (reg & DWC3_DCTL_INITU1ENA)
 646                 param = dwc->u1pel;
 647
 648         /*
 649          * According to Synopsys Databook, if parameter is
 650          * greater than 125, a value of zero should be
 651          * programmed in the register.
 652          */
 653         if (param > 125)
 654                 param = 0;
 655
 656         /* now that we have the time, issue DGCMD Set Sel */
 657         ret = dwc3_send_gadget_generic_command(dwc,
 658                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 659         WARN_ON(ret < 0);
 660 }
 661
 662 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 663 {
 664         struct dwc3_ep  *dep;
 665         enum usb_device_state state = dwc->gadget.state;
 666         u16             wLength;
 667         u16             wValue;
 668
 669         if (state == USB_STATE_DEFAULT)
 670                 return -EINVAL;
 671
 672         wValue = le16_to_cpu(ctrl->wValue);
 673         wLength = le16_to_cpu(ctrl->wLength);
 674
 675         if (wLength != 6) {
 676                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 677                                 wLength);
 678                 return -EINVAL;
 679         }
 680
 681         /*
 682          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 683          * queue a usb_request for 6 bytes.
 684          *
 685          * Remember, though, this controller can't handle non-wMaxPacketSize
 686          * aligned transfers on the OUT direction, so we queue a request for
 687          * wMaxPacketSize instead.
 688          */
 689         dep = dwc->eps[0];
 690         dwc->ep0_usb_req.dep = dep;
 691         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 692         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 693         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 694
 695         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 696 }
 697
 698 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 699 {
 700         u16             wLength;
 701         u16             wValue;
 702         u16             wIndex;
 703
 704         wValue = le16_to_cpu(ctrl->wValue);
 705         wLength = le16_to_cpu(ctrl->wLength);
 706         wIndex = le16_to_cpu(ctrl->wIndex);
 707
 708         if (wIndex || wLength)
 709                 return -EINVAL;
 710
 711         /*
 712          * REVISIT It's unclear from Databook what to do with this
 713          * value. For now, just cache it.
 714          */
 715         dwc->isoch_delay = wValue;
 716
 717         return 0;
 718 }
 719
 720 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 721 {
 722         int ret;
 723
 724         switch (ctrl->bRequest) {
 725         case USB_REQ_GET_STATUS:
 726                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 727                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 728                 break;
 729         case USB_REQ_CLEAR_FEATURE:
 730                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 731                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 732                 break;
 733         case USB_REQ_SET_FEATURE:
 734                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 735                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 736                 break;
 737         case USB_REQ_SET_ADDRESS:
 738                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 739                 ret = dwc3_ep0_set_address(dwc, ctrl);
 740                 break;
 741         case USB_REQ_SET_CONFIGURATION:
 742                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 743                 ret = dwc3_ep0_set_config(dwc, ctrl);
 744                 break;
 745         case USB_REQ_SET_SEL:
 746                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 747                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 748                 break;
 749         case USB_REQ_SET_ISOCH_DELAY:
 750                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 751                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 752                 break;
 753         default:
 754                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 755                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 756                 break;
 757         }
 758
 759         return ret;
 760 }
 761
 762 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 763                 const struct dwc3_event_depevt *event)
 764 {
 765         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 766         int ret = -EINVAL;
 767         u32 len;
 768
 769         if (!dwc->gadget_driver)
 770                 goto out;
 771
 772         trace_dwc3_ctrl_req(ctrl);
 773
 774         len = le16_to_cpu(ctrl->wLength);
 775         if (!len) {
 776                 dwc->three_stage_setup = false;
 777                 dwc->ep0_expect_in = false;
 778                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 779         } else {
 780                 dwc->three_stage_setup = true;
 781                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 782                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 783         }
 784
 785         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 786                 ret = dwc3_ep0_std_request(dwc, ctrl);
 787         else
 788                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 789
 790         if (ret == USB_GADGET_DELAYED_STATUS)
 791                 dwc->delayed_status = true;
 792
 793 out:
 794         if (ret < 0)
 795                 dwc3_ep0_stall_and_restart(dwc);
 796 }
 797
 798 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 799                 const struct dwc3_event_depevt *event)
 800 {
 801         struct dwc3_request     *r = NULL;
 802         struct usb_request      *ur;
 803         struct dwc3_trb         *trb;
 804         struct dwc3_ep          *ep0;
 805         unsigned                transfer_size = 0;
 806         unsigned                maxp;
 807         unsigned                remaining_ur_length;
 808         void                    *buf;
 809         u32                     transferred = 0;
 810         u32                     status;
 811         u32                     length;
 812         u8                      epnum;
 813
 814         epnum = event->endpoint_number;
 815         ep0 = dwc->eps[0];
 816
 817         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 818
 819         trb = dwc->ep0_trb;
 820
 821         trace_dwc3_complete_trb(ep0, trb);
 822
 823         r = next_request(&ep0->pending_list);
 824         if (!r)
 825                 return;
 826
 827         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 828         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 829                 dwc->setup_packet_pending = true;
 830
 831                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 832
 833                 if (r)
 834                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 835
 836                 return;
 837         }
 838
 839         ur = &r->request;
 840         buf = ur->buf;
 841         remaining_ur_length = ur->length;
 842
 843         length = trb->size & DWC3_TRB_SIZE_MASK;
 844
 845         maxp = ep0->endpoint.maxpacket;
 846
 847         if (dwc->ep0_bounced) {
 848                 /*
 849                  * Handle the first TRB before handling the bounce buffer if
 850                  * the request length is greater than the bounce buffer size
 851                  */
 852                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 853                         transfer_size = ALIGN(ur->length - maxp, maxp);
 854                         transferred = transfer_size - length;
 855                         buf = (u8 *)buf + transferred;
 856                         ur->actual += transferred;
 857                         remaining_ur_length -= transferred;
 858
 859                         trb++;
 860                         length = trb->size & DWC3_TRB_SIZE_MASK;
 861
 862                         ep0->trb_enqueue = 0;
 863                 }
 864
 865                 transfer_size = roundup((ur->length - transfer_size),
 866                                         maxp);
 867
 868                 transferred = min_t(u32, remaining_ur_length,
 869                                     transfer_size - length);
 870                 memcpy(buf, dwc->ep0_bounce, transferred);
 871         } else {
 872                 transferred = ur->length - length;
 873         }
 874
 875         ur->actual += transferred;
 876
 877         if ((epnum & 1) && ur->actual < ur->length) {
 878                 /* for some reason we did not get everything out */
 879
 880                 dwc3_ep0_stall_and_restart(dwc);
 881         } else {
 882                 dwc3_gadget_giveback(ep0, r, 0);
 883
 884                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 885                                 ur->length && ur->zero) {
 886                         int ret;
 887
 888                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 889
 890                         dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr,
 891                                         0, DWC3_TRBCTL_CONTROL_DATA, false);
 892                         ret = dwc3_ep0_start_trans(dwc, epnum);
 893                         WARN_ON(ret < 0);
 894                 }
 895         }
 896 }
 897
 898 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 899                 const struct dwc3_event_depevt *event)
 900 {
 901         struct dwc3_request     *r;
 902         struct dwc3_ep          *dep;
 903         struct dwc3_trb         *trb;
 904         u32                     status;
 905
 906         dep = dwc->eps[0];
 907         trb = dwc->ep0_trb;
 908
 909         trace_dwc3_complete_trb(dep, trb);
 910
 911         if (!list_empty(&dep->pending_list)) {
 912                 r = next_request(&dep->pending_list);
 913
 914                 dwc3_gadget_giveback(dep, r, 0);
 915         }
 916
 917         if (dwc->test_mode) {
 918                 int ret;
 919
 920                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 921                 if (ret < 0) {
 922                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 923                                         dwc->test_mode_nr);
 924                         dwc3_ep0_stall_and_restart(dwc);
 925                         return;
 926                 }
 927         }
 928
 929         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 930         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 931                 dwc->setup_packet_pending = true;
 932                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 933         }
 934
 935         dwc->ep0state = EP0_SETUP_PHASE;
 936         dwc3_ep0_out_start(dwc);
 937 }
 938
 939 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 940                         const struct dwc3_event_depevt *event)
 941 {
 942         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 943
 944         dep->flags &= ~DWC3_EP_BUSY;
 945         dep->resource_index = 0;
 946         dwc->setup_packet_pending = false;
 947
 948         switch (dwc->ep0state) {
 949         case EP0_SETUP_PHASE:
 950                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 951                 dwc3_ep0_inspect_setup(dwc, event);
 952                 break;
 953
 954         case EP0_DATA_PHASE:
 955                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 956                 dwc3_ep0_complete_data(dwc, event);
 957                 break;
 958
 959         case EP0_STATUS_PHASE:
 960                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 961                 dwc3_ep0_complete_status(dwc, event);
 962                 break;
 963         default:
 964                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 965         }
 966 }
 967
 968 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 969                 struct dwc3_ep *dep, struct dwc3_request *req)
 970 {
 971         int                     ret;
 972
 973         req->direction = !!dep->number;
 974
 975         if (req->request.length == 0) {
 976                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
 977                                 dwc->ctrl_req_addr, 0,
 978                                 DWC3_TRBCTL_CONTROL_DATA, false);
 979                 ret = dwc3_ep0_start_trans(dwc, dep->number);
 980         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 981                         && (dep->number == 0)) {
 982                 u32     transfer_size = 0;
 983                 u32     maxpacket;
 984
 985                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 986                                 dep->number);
 987                 if (ret) {
 988                         dwc3_trace(trace_dwc3_ep0, "failed to map request");
 989                         return;
 990                 }
 991
 992                 maxpacket = dep->endpoint.maxpacket;
 993
 994                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 995                         transfer_size = ALIGN(req->request.length - maxpacket,
 996                                               maxpacket);
 997                         dwc3_ep0_prepare_one_trb(dwc, dep->number,
 998                                                    req->request.dma,
 999                                                    transfer_size,
1000                                                    DWC3_TRBCTL_CONTROL_DATA,
1001                                                    true);
1002                 }
1003
1004                 transfer_size = roundup((req->request.length - transfer_size),
1005                                         maxpacket);
1006
1007                 dwc->ep0_bounced = true;
1008
1009                 dwc3_ep0_prepare_one_trb(dwc, dep->number,
1010                                 dwc->ep0_bounce_addr, transfer_size,
1011                                 DWC3_TRBCTL_CONTROL_DATA, false);
1012                 ret = dwc3_ep0_start_trans(dwc, dep->number);
1013         } else {
1014                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1015                                 dep->number);
1016                 if (ret) {
1017                         dwc3_trace(trace_dwc3_ep0, "failed to map request");
1018                         return;
1019                 }
1020
1021                 dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma,
1022                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1023                                 false);
1024                 ret = dwc3_ep0_start_trans(dwc, dep->number);
1025         }
1026
1027         WARN_ON(ret < 0);
1028 }
1029
1030 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1031 {
1032         struct dwc3             *dwc = dep->dwc;
1033         u32                     type;
1034
1035         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1036                 : DWC3_TRBCTL_CONTROL_STATUS2;
1037
1038         dwc3_ep0_prepare_one_trb(dwc, dep->number,
1039                         dwc->ctrl_req_addr, 0, type, false);
1040         return dwc3_ep0_start_trans(dwc, dep->number);
1041 }
1042
1043 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1044 {
1045         WARN_ON(dwc3_ep0_start_control_status(dep));
1046 }
1047
1048 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1049                 const struct dwc3_event_depevt *event)
1050 {
1051         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1052
1053         __dwc3_ep0_do_control_status(dwc, dep);
1054 }
1055
1056 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1057 {
1058         struct dwc3_gadget_ep_cmd_params params;
1059         u32                     cmd;
1060         int                     ret;
1061
1062         if (!dep->resource_index)
1063                 return;
1064
1065         cmd = DWC3_DEPCMD_ENDTRANSFER;
1066         cmd |= DWC3_DEPCMD_CMDIOC;
1067         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1068         memset(&params, 0, sizeof(params));
1069         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1070         WARN_ON_ONCE(ret);
1071         dep->resource_index = 0;
1072 }
1073
1074 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1075                 const struct dwc3_event_depevt *event)
1076 {
1077         switch (event->status) {
1078         case DEPEVT_STATUS_CONTROL_DATA:
1079                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1080
1081                 /*
1082                  * We already have a DATA transfer in the controller's cache,
1083                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1084                  * it's for the wrong direction.
1085                  *
1086                  * In that case, we must issue END_TRANSFER command to the Data
1087                  * Phase we already have started and issue SetStall on the
1088                  * control endpoint.
1089                  */
1090                 if (dwc->ep0_expect_in != event->endpoint_number) {
1091                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1092
1093                         dwc3_trace(trace_dwc3_ep0,
1094                                         "Wrong direction for Data phase");
1095                         dwc3_ep0_end_control_data(dwc, dep);
1096                         dwc3_ep0_stall_and_restart(dwc);
1097                         return;
1098                 }
1099
1100                 break;
1101
1102         case DEPEVT_STATUS_CONTROL_STATUS:
1103                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1104                         return;
1105
1106                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1107
1108                 dwc->ep0state = EP0_STATUS_PHASE;
1109
1110                 if (dwc->delayed_status) {
1111                         WARN_ON_ONCE(event->endpoint_number != 1);
1112                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1113                         return;
1114                 }
1115
1116                 dwc3_ep0_do_control_status(dwc, event);
1117         }
1118 }
1119
1120 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1121                 const struct dwc3_event_depevt *event)
1122 {
1123         dwc3_trace(trace_dwc3_ep0, "%s: state '%s'",
1124                         dwc3_ep_event_string(event),
1125                         dwc3_ep0_state_string(dwc->ep0state));
1126
1127         switch (event->endpoint_event) {
1128         case DWC3_DEPEVT_XFERCOMPLETE:
1129                 dwc3_ep0_xfer_complete(dwc, event);
1130                 break;
1131
1132         case DWC3_DEPEVT_XFERNOTREADY:
1133                 dwc3_ep0_xfernotready(dwc, event);
1134                 break;
1135
1136         case DWC3_DEPEVT_XFERINPROGRESS:
1137         case DWC3_DEPEVT_RXTXFIFOEVT:
1138         case DWC3_DEPEVT_STREAMEVT:
1139         case DWC3_DEPEVT_EPCMDCMPLT:
1140                 break;
1141         }
1142 }