drivers/usb/dwc3/ep0.c

   1 /*
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  43                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  44 {
  45         struct dwc3_trb                 *trb;
  46         struct dwc3                     *dwc;
  47
  48         dwc = dep->dwc;
  49         trb = &dwc->ep0_trb[dep->trb_enqueue];
  50
  51         if (chain)
  52                 dep->trb_enqueue++;
  53
  54         trb->bpl = lower_32_bits(buf_dma);
  55         trb->bph = upper_32_bits(buf_dma);
  56         trb->size = len;
  57         trb->ctrl = type;
  58
  59         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  60                         | DWC3_TRB_CTRL_ISP_IMI);
  61
  62         if (chain)
  63                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  64         else
  65                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  66                                 | DWC3_TRB_CTRL_LST);
  67
  68         trace_dwc3_prepare_trb(dep, trb);
  69 }
  70
  71 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  72 {
  73         struct dwc3_gadget_ep_cmd_params params;
  74         struct dwc3                     *dwc;
  75         int                             ret;
  76
  77         if (dep->flags & DWC3_EP_BUSY)
  78                 return 0;
  79
  80         dwc = dep->dwc;
  81
  82         memset(&params, 0, sizeof(params));
  83         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  84         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  85
  86         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  87         if (ret < 0)
  88                 return ret;
  89
  90         dep->flags |= DWC3_EP_BUSY;
  91         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
  92         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  93
  94         return 0;
  95 }
  96
  97 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  98                 struct dwc3_request *req)
  99 {
 100         struct dwc3             *dwc = dep->dwc;
 101
 102         req->request.actual     = 0;
 103         req->request.status     = -EINPROGRESS;
 104         req->epnum              = dep->number;
 105
 106         list_add_tail(&req->list, &dep->pending_list);
 107
 108         /*
 109          * Gadget driver might not be quick enough to queue a request
 110          * before we get a Transfer Not Ready event on this endpoint.
 111          *
 112          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 113          * flag is set, it's telling us that as soon as Gadget queues the
 114          * required request, we should kick the transfer here because the
 115          * IRQ we were waiting for is long gone.
 116          */
 117         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 118                 unsigned        direction;
 119
 120                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 121
 122                 if (dwc->ep0state != EP0_DATA_PHASE) {
 123                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 124                         return 0;
 125                 }
 126
 127                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 128
 129                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 130                                 DWC3_EP0_DIR_IN);
 131
 132                 return 0;
 133         }
 134
 135         /*
 136          * In case gadget driver asked us to delay the STATUS phase,
 137          * handle it here.
 138          */
 139         if (dwc->delayed_status) {
 140                 unsigned        direction;
 141
 142                 direction = !dwc->ep0_expect_in;
 143                 dwc->delayed_status = false;
 144                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 145
 146                 if (dwc->ep0state == EP0_STATUS_PHASE)
 147                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 148
 149                 return 0;
 150         }
 151
 152         /*
 153          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 154          *
 155          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 156          * come before issueing Start Transfer command, but if we do, we will
 157          * miss situations where the host starts another SETUP phase instead of
 158          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 159          * Layer Compliance Suite.
 160          *
 161          * The problem surfaces due to the fact that in case of back-to-back
 162          * SETUP packets there will be no XferNotReady(DATA) generated and we
 163          * will be stuck waiting for XferNotReady(DATA) forever.
 164          *
 165          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 166          * it tells us to start Data Phase right away. It also mentions that if
 167          * we receive a SETUP phase instead of the DATA phase, core will issue
 168          * XferComplete for the DATA phase, before actually initiating it in
 169          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 170          * can only be used to print some debugging logs, as the core expects
 171          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 172          * just so it completes right away, without transferring anything and,
 173          * only then, we can go back to the SETUP phase.
 174          *
 175          * Because of this scenario, SNPS decided to change the programming
 176          * model of control transfers and support on-demand transfers only for
 177          * the STATUS phase. To fix the issue we have now, we will always wait
 178          * for gadget driver to queue the DATA phase's struct usb_request, then
 179          * start it right away.
 180          *
 181          * If we're actually in a 2-stage transfer, we will wait for
 182          * XferNotReady(STATUS).
 183          */
 184         if (dwc->three_stage_setup) {
 185                 unsigned        direction;
 186
 187                 direction = dwc->ep0_expect_in;
 188                 dwc->ep0state = EP0_DATA_PHASE;
 189
 190                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 191
 192                 dep->flags &= ~DWC3_EP0_DIR_IN;
 193         }
 194
 195         return 0;
 196 }
 197
 198 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 199                 gfp_t gfp_flags)
 200 {
 201         struct dwc3_request             *req = to_dwc3_request(request);
 202         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 203         struct dwc3                     *dwc = dep->dwc;
 204
 205         unsigned long                   flags;
 206
 207         int                             ret;
 208
 209         spin_lock_irqsave(&dwc->lock, flags);
 210         if (!dep->endpoint.desc) {
 211                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 212                                 dep->name);
 213                 ret = -ESHUTDOWN;
 214                 goto out;
 215         }
 216
 217         /* we share one TRB for ep0/1 */
 218         if (!list_empty(&dep->pending_list)) {
 219                 ret = -EBUSY;
 220                 goto out;
 221         }
 222
 223         ret = __dwc3_gadget_ep0_queue(dep, req);
 224
 225 out:
 226         spin_unlock_irqrestore(&dwc->lock, flags);
 227
 228         return ret;
 229 }
 230
 231 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 232 {
 233         struct dwc3_ep          *dep;
 234
 235         /* reinitialize physical ep1 */
 236         dep = dwc->eps[1];
 237         dep->flags = DWC3_EP_ENABLED;
 238
 239         /* stall is always issued on EP0 */
 240         dep = dwc->eps[0];
 241         __dwc3_gadget_ep_set_halt(dep, 1, false);
 242         dep->flags = DWC3_EP_ENABLED;
 243         dwc->delayed_status = false;
 244
 245         if (!list_empty(&dep->pending_list)) {
 246                 struct dwc3_request     *req;
 247
 248                 req = next_request(&dep->pending_list);
 249                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 250         }
 251
 252         dwc->ep0state = EP0_SETUP_PHASE;
 253         dwc3_ep0_out_start(dwc);
 254 }
 255
 256 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 257 {
 258         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 259         struct dwc3                     *dwc = dep->dwc;
 260
 261         dwc3_ep0_stall_and_restart(dwc);
 262
 263         return 0;
 264 }
 265
 266 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 267 {
 268         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 269         struct dwc3                     *dwc = dep->dwc;
 270         unsigned long                   flags;
 271         int                             ret;
 272
 273         spin_lock_irqsave(&dwc->lock, flags);
 274         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 275         spin_unlock_irqrestore(&dwc->lock, flags);
 276
 277         return ret;
 278 }
 279
 280 void dwc3_ep0_out_start(struct dwc3 *dwc)
 281 {
 282         struct dwc3_ep                  *dep;
 283         int                             ret;
 284
 285         complete(&dwc->ep0_in_setup);
 286
 287         dep = dwc->eps[0];
 288         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 289                         DWC3_TRBCTL_CONTROL_SETUP, false);
 290         ret = dwc3_ep0_start_trans(dep);
 291         WARN_ON(ret < 0);
 292 }
 293
 294 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 295 {
 296         struct dwc3_ep          *dep;
 297         u32                     windex = le16_to_cpu(wIndex_le);
 298         u32                     epnum;
 299
 300         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 301         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 302                 epnum |= 1;
 303
 304         dep = dwc->eps[epnum];
 305         if (dep == NULL)
 306                 return NULL;
 307
 308         if (dep->flags & DWC3_EP_ENABLED)
 309                 return dep;
 310
 311         return NULL;
 312 }
 313
 314 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 315 {
 316 }
 317 /*
 318  * ch 9.4.5
 319  */
 320 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 321                 struct usb_ctrlrequest *ctrl)
 322 {
 323         struct dwc3_ep          *dep;
 324         u32                     recip;
 325         u32                     value;
 326         u32                     reg;
 327         u16                     usb_status = 0;
 328         __le16                  *response_pkt;
 329
 330         /* We don't support PTM_STATUS */
 331         value = le16_to_cpu(ctrl->wValue);
 332         if (value != 0)
 333                 return -EINVAL;
 334
 335         recip = ctrl->bRequestType & USB_RECIP_MASK;
 336         switch (recip) {
 337         case USB_RECIP_DEVICE:
 338                 /*
 339                  * LTM will be set once we know how to set this in HW.
 340                  */
 341                 usb_status |= dwc->gadget.is_selfpowered;
 342
 343                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 344                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 345                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 346                         if (reg & DWC3_DCTL_INITU1ENA)
 347                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 348                         if (reg & DWC3_DCTL_INITU2ENA)
 349                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 350                 }
 351
 352                 break;
 353
 354         case USB_RECIP_INTERFACE:
 355                 /*
 356                  * Function Remote Wake Capable D0
 357                  * Function Remote Wakeup       D1
 358                  */
 359                 break;
 360
 361         case USB_RECIP_ENDPOINT:
 362                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 363                 if (!dep)
 364                         return -EINVAL;
 365
 366                 if (dep->flags & DWC3_EP_STALL)
 367                         usb_status = 1 << USB_ENDPOINT_HALT;
 368                 break;
 369         default:
 370                 return -EINVAL;
 371         }
 372
 373         response_pkt = (__le16 *) dwc->setup_buf;
 374         *response_pkt = cpu_to_le16(usb_status);
 375
 376         dep = dwc->eps[0];
 377         dwc->ep0_usb_req.dep = dep;
 378         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 379         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 380         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 381
 382         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 383 }
 384
 385 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 386                 int set)
 387 {
 388         u32 reg;
 389
 390         if (state != USB_STATE_CONFIGURED)
 391                 return -EINVAL;
 392         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 393                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 394                 return -EINVAL;
 395
 396         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 397         if (set)
 398                 reg |= DWC3_DCTL_INITU1ENA;
 399         else
 400                 reg &= ~DWC3_DCTL_INITU1ENA;
 401         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 402
 403         return 0;
 404 }
 405
 406 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 407                 int set)
 408 {
 409         u32 reg;
 410
 411
 412         if (state != USB_STATE_CONFIGURED)
 413                 return -EINVAL;
 414         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 415                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 416                 return -EINVAL;
 417
 418         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 419         if (set)
 420                 reg |= DWC3_DCTL_INITU2ENA;
 421         else
 422                 reg &= ~DWC3_DCTL_INITU2ENA;
 423         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 424
 425         return 0;
 426 }
 427
 428 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 429                 u32 wIndex, int set)
 430 {
 431         if ((wIndex & 0xff) != 0)
 432                 return -EINVAL;
 433         if (!set)
 434                 return -EINVAL;
 435
 436         switch (wIndex >> 8) {
 437         case TEST_J:
 438         case TEST_K:
 439         case TEST_SE0_NAK:
 440         case TEST_PACKET:
 441         case TEST_FORCE_EN:
 442                 dwc->test_mode_nr = wIndex >> 8;
 443                 dwc->test_mode = true;
 444                 break;
 445         default:
 446                 return -EINVAL;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 453                 struct usb_ctrlrequest *ctrl, int set)
 454 {
 455         enum usb_device_state   state;
 456         u32                     wValue;
 457         u32                     wIndex;
 458         int                     ret = 0;
 459
 460         wValue = le16_to_cpu(ctrl->wValue);
 461         wIndex = le16_to_cpu(ctrl->wIndex);
 462         state = dwc->gadget.state;
 463
 464         switch (wValue) {
 465         case USB_DEVICE_REMOTE_WAKEUP:
 466                 break;
 467         /*
 468          * 9.4.1 says only only for SS, in AddressState only for
 469          * default control pipe
 470          */
 471         case USB_DEVICE_U1_ENABLE:
 472                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 473                 break;
 474         case USB_DEVICE_U2_ENABLE:
 475                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 476                 break;
 477         case USB_DEVICE_LTM_ENABLE:
 478                 ret = -EINVAL;
 479                 break;
 480         case USB_DEVICE_TEST_MODE:
 481                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 482                 break;
 483         default:
 484                 ret = -EINVAL;
 485         }
 486
 487         return ret;
 488 }
 489
 490 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 491                 struct usb_ctrlrequest *ctrl, int set)
 492 {
 493         enum usb_device_state   state;
 494         u32                     wValue;
 495         u32                     wIndex;
 496         int                     ret = 0;
 497
 498         wValue = le16_to_cpu(ctrl->wValue);
 499         wIndex = le16_to_cpu(ctrl->wIndex);
 500         state = dwc->gadget.state;
 501
 502         switch (wValue) {
 503         case USB_INTRF_FUNC_SUSPEND:
 504                 /*
 505                  * REVISIT: Ideally we would enable some low power mode here,
 506                  * however it's unclear what we should be doing here.
 507                  *
 508                  * For now, we're not doing anything, just making sure we return
 509                  * 0 so USB Command Verifier tests pass without any errors.
 510                  */
 511                 break;
 512         default:
 513                 ret = -EINVAL;
 514         }
 515
 516         return ret;
 517 }
 518
 519 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 520                 struct usb_ctrlrequest *ctrl, int set)
 521 {
 522         struct dwc3_ep          *dep;
 523         enum usb_device_state   state;
 524         u32                     wValue;
 525         u32                     wIndex;
 526         int                     ret;
 527
 528         wValue = le16_to_cpu(ctrl->wValue);
 529         wIndex = le16_to_cpu(ctrl->wIndex);
 530         state = dwc->gadget.state;
 531
 532         switch (wValue) {
 533         case USB_ENDPOINT_HALT:
 534                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 535                 if (!dep)
 536                         return -EINVAL;
 537
 538                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 539                         break;
 540
 541                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 542                 if (ret)
 543                         return -EINVAL;
 544                 break;
 545         default:
 546                 return -EINVAL;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 553                 struct usb_ctrlrequest *ctrl, int set)
 554 {
 555         u32                     recip;
 556         int                     ret;
 557         enum usb_device_state   state;
 558
 559         recip = ctrl->bRequestType & USB_RECIP_MASK;
 560         state = dwc->gadget.state;
 561
 562         switch (recip) {
 563         case USB_RECIP_DEVICE:
 564                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 565                 break;
 566         case USB_RECIP_INTERFACE:
 567                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 568                 break;
 569         case USB_RECIP_ENDPOINT:
 570                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 571                 break;
 572         default:
 573                 ret = -EINVAL;
 574         }
 575
 576         return ret;
 577 }
 578
 579 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 580 {
 581         enum usb_device_state state = dwc->gadget.state;
 582         u32 addr;
 583         u32 reg;
 584
 585         addr = le16_to_cpu(ctrl->wValue);
 586         if (addr > 127) {
 587                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 588                 return -EINVAL;
 589         }
 590
 591         if (state == USB_STATE_CONFIGURED) {
 592                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 593                 return -EINVAL;
 594         }
 595
 596         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 597         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 598         reg |= DWC3_DCFG_DEVADDR(addr);
 599         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 600
 601         if (addr)
 602                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 603         else
 604                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 605
 606         return 0;
 607 }
 608
 609 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 610 {
 611         int ret;
 612
 613         spin_unlock(&dwc->lock);
 614         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 615         spin_lock(&dwc->lock);
 616         return ret;
 617 }
 618
 619 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 620 {
 621         enum usb_device_state state = dwc->gadget.state;
 622         u32 cfg;
 623         int ret;
 624         u32 reg;
 625
 626         cfg = le16_to_cpu(ctrl->wValue);
 627
 628         switch (state) {
 629         case USB_STATE_DEFAULT:
 630                 return -EINVAL;
 631
 632         case USB_STATE_ADDRESS:
 633                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 634                 /* if the cfg matches and the cfg is non zero */
 635                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 636
 637                         /*
 638                          * only change state if set_config has already
 639                          * been processed. If gadget driver returns
 640                          * USB_GADGET_DELAYED_STATUS, we will wait
 641                          * to change the state on the next usb_ep_queue()
 642                          */
 643                         if (ret == 0)
 644                                 usb_gadget_set_state(&dwc->gadget,
 645                                                 USB_STATE_CONFIGURED);
 646
 647                         /*
 648                          * Enable transition to U1/U2 state when
 649                          * nothing is pending from application.
 650                          */
 651                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 652                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 653                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 654                 }
 655                 break;
 656
 657         case USB_STATE_CONFIGURED:
 658                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 659                 if (!cfg && !ret)
 660                         usb_gadget_set_state(&dwc->gadget,
 661                                         USB_STATE_ADDRESS);
 662                 break;
 663         default:
 664                 ret = -EINVAL;
 665         }
 666         return ret;
 667 }
 668
 669 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 670 {
 671         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 672         struct dwc3     *dwc = dep->dwc;
 673
 674         u32             param = 0;
 675         u32             reg;
 676
 677         struct timing {
 678                 u8      u1sel;
 679                 u8      u1pel;
 680                 __le16  u2sel;
 681                 __le16  u2pel;
 682         } __packed timing;
 683
 684         int             ret;
 685
 686         memcpy(&timing, req->buf, sizeof(timing));
 687
 688         dwc->u1sel = timing.u1sel;
 689         dwc->u1pel = timing.u1pel;
 690         dwc->u2sel = le16_to_cpu(timing.u2sel);
 691         dwc->u2pel = le16_to_cpu(timing.u2pel);
 692
 693         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 694         if (reg & DWC3_DCTL_INITU2ENA)
 695                 param = dwc->u2pel;
 696         if (reg & DWC3_DCTL_INITU1ENA)
 697                 param = dwc->u1pel;
 698
 699         /*
 700          * According to Synopsys Databook, if parameter is
 701          * greater than 125, a value of zero should be
 702          * programmed in the register.
 703          */
 704         if (param > 125)
 705                 param = 0;
 706
 707         /* now that we have the time, issue DGCMD Set Sel */
 708         ret = dwc3_send_gadget_generic_command(dwc,
 709                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 710         WARN_ON(ret < 0);
 711 }
 712
 713 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 714 {
 715         struct dwc3_ep  *dep;
 716         enum usb_device_state state = dwc->gadget.state;
 717         u16             wLength;
 718         u16             wValue;
 719
 720         if (state == USB_STATE_DEFAULT)
 721                 return -EINVAL;
 722
 723         wValue = le16_to_cpu(ctrl->wValue);
 724         wLength = le16_to_cpu(ctrl->wLength);
 725
 726         if (wLength != 6) {
 727                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 728                                 wLength);
 729                 return -EINVAL;
 730         }
 731
 732         /*
 733          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 734          * queue a usb_request for 6 bytes.
 735          *
 736          * Remember, though, this controller can't handle non-wMaxPacketSize
 737          * aligned transfers on the OUT direction, so we queue a request for
 738          * wMaxPacketSize instead.
 739          */
 740         dep = dwc->eps[0];
 741         dwc->ep0_usb_req.dep = dep;
 742         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 743         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 744         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 745
 746         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 747 }
 748
 749 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 750 {
 751         u16             wLength;
 752         u16             wValue;
 753         u16             wIndex;
 754
 755         wValue = le16_to_cpu(ctrl->wValue);
 756         wLength = le16_to_cpu(ctrl->wLength);
 757         wIndex = le16_to_cpu(ctrl->wIndex);
 758
 759         if (wIndex || wLength)
 760                 return -EINVAL;
 761
 762         /*
 763          * REVISIT It's unclear from Databook what to do with this
 764          * value. For now, just cache it.
 765          */
 766         dwc->isoch_delay = wValue;
 767
 768         return 0;
 769 }
 770
 771 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 772 {
 773         int ret;
 774
 775         switch (ctrl->bRequest) {
 776         case USB_REQ_GET_STATUS:
 777                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 778                 break;
 779         case USB_REQ_CLEAR_FEATURE:
 780                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 781                 break;
 782         case USB_REQ_SET_FEATURE:
 783                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 784                 break;
 785         case USB_REQ_SET_ADDRESS:
 786                 ret = dwc3_ep0_set_address(dwc, ctrl);
 787                 break;
 788         case USB_REQ_SET_CONFIGURATION:
 789                 ret = dwc3_ep0_set_config(dwc, ctrl);
 790                 break;
 791         case USB_REQ_SET_SEL:
 792                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 793                 break;
 794         case USB_REQ_SET_ISOCH_DELAY:
 795                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 796                 break;
 797         default:
 798                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 799                 break;
 800         }
 801
 802         return ret;
 803 }
 804
 805 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 806                 const struct dwc3_event_depevt *event)
 807 {
 808         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 809         int ret = -EINVAL;
 810         u32 len;
 811
 812         if (!dwc->gadget_driver)
 813                 goto out;
 814
 815         trace_dwc3_ctrl_req(ctrl);
 816
 817         len = le16_to_cpu(ctrl->wLength);
 818         if (!len) {
 819                 dwc->three_stage_setup = false;
 820                 dwc->ep0_expect_in = false;
 821                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 822         } else {
 823                 dwc->three_stage_setup = true;
 824                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 825                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 826         }
 827
 828         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 829                 ret = dwc3_ep0_std_request(dwc, ctrl);
 830         else
 831                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 832
 833         if (ret == USB_GADGET_DELAYED_STATUS)
 834                 dwc->delayed_status = true;
 835
 836 out:
 837         if (ret < 0)
 838                 dwc3_ep0_stall_and_restart(dwc);
 839 }
 840
 841 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 842                 const struct dwc3_event_depevt *event)
 843 {
 844         struct dwc3_request     *r = NULL;
 845         struct usb_request      *ur;
 846         struct dwc3_trb         *trb;
 847         struct dwc3_ep          *ep0;
 848         unsigned                maxp;
 849         unsigned                remaining_ur_length;
 850         void                    *buf;
 851         u32                     transferred = 0;
 852         u32                     status;
 853         u32                     length;
 854         u8                      epnum;
 855
 856         epnum = event->endpoint_number;
 857         ep0 = dwc->eps[0];
 858
 859         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 860         trb = dwc->ep0_trb;
 861         trace_dwc3_complete_trb(ep0, trb);
 862
 863         r = next_request(&ep0->pending_list);
 864         if (!r)
 865                 return;
 866
 867         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 868         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 869                 dwc->setup_packet_pending = true;
 870                 if (r)
 871                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 872
 873                 return;
 874         }
 875
 876         ur = &r->request;
 877         buf = ur->buf;
 878         remaining_ur_length = ur->length;
 879
 880         length = trb->size & DWC3_TRB_SIZE_MASK;
 881         maxp = ep0->endpoint.maxpacket;
 882         transferred = ur->length - length;
 883         ur->actual += transferred;
 884
 885         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 886              ur->length && ur->zero) || dwc->ep0_bounced) {
 887                 trb++;
 888                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 889                 trace_dwc3_complete_trb(ep0, trb);
 890
 891                 if (r->direction)
 892                         dwc->eps[1]->trb_enqueue = 0;
 893                 else
 894                         dwc->eps[0]->trb_enqueue = 0;
 895
 896                 dwc->ep0_bounced = false;
 897         }
 898
 899         if ((epnum & 1) && ur->actual < ur->length)
 900                 dwc3_ep0_stall_and_restart(dwc);
 901         else
 902                 dwc3_gadget_giveback(ep0, r, 0);
 903 }
 904
 905 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 906                 const struct dwc3_event_depevt *event)
 907 {
 908         struct dwc3_request     *r;
 909         struct dwc3_ep          *dep;
 910         struct dwc3_trb         *trb;
 911         u32                     status;
 912
 913         dep = dwc->eps[0];
 914         trb = dwc->ep0_trb;
 915
 916         trace_dwc3_complete_trb(dep, trb);
 917
 918         if (!list_empty(&dep->pending_list)) {
 919                 r = next_request(&dep->pending_list);
 920
 921                 dwc3_gadget_giveback(dep, r, 0);
 922         }
 923
 924         if (dwc->test_mode) {
 925                 int ret;
 926
 927                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 928                 if (ret < 0) {
 929                         dev_err(dwc->dev, "invalid test #%d\n",
 930                                         dwc->test_mode_nr);
 931                         dwc3_ep0_stall_and_restart(dwc);
 932                         return;
 933                 }
 934         }
 935
 936         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 937         if (status == DWC3_TRBSTS_SETUP_PENDING)
 938                 dwc->setup_packet_pending = true;
 939
 940         dwc->ep0state = EP0_SETUP_PHASE;
 941         dwc3_ep0_out_start(dwc);
 942 }
 943
 944 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 945                         const struct dwc3_event_depevt *event)
 946 {
 947         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 948
 949         dep->flags &= ~DWC3_EP_BUSY;
 950         dep->resource_index = 0;
 951         dwc->setup_packet_pending = false;
 952
 953         switch (dwc->ep0state) {
 954         case EP0_SETUP_PHASE:
 955                 dwc3_ep0_inspect_setup(dwc, event);
 956                 break;
 957
 958         case EP0_DATA_PHASE:
 959                 dwc3_ep0_complete_data(dwc, event);
 960                 break;
 961
 962         case EP0_STATUS_PHASE:
 963                 dwc3_ep0_complete_status(dwc, event);
 964                 break;
 965         default:
 966                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 967         }
 968 }
 969
 970 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 971                 struct dwc3_ep *dep, struct dwc3_request *req)
 972 {
 973         unsigned int            trb_length = 0;
 974         int                     ret;
 975
 976         req->direction = !!dep->number;
 977
 978         if (req->request.length == 0) {
 979                 if (!req->direction)
 980                         trb_length = dep->endpoint.maxpacket;
 981
 982                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 983                                 DWC3_TRBCTL_CONTROL_DATA, false);
 984                 ret = dwc3_ep0_start_trans(dep);
 985         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 986                         && (dep->number == 0)) {
 987                 u32     maxpacket;
 988                 u32     rem;
 989
 990                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 991                                 &req->request, dep->number);
 992                 if (ret)
 993                         return;
 994
 995                 maxpacket = dep->endpoint.maxpacket;
 996                 rem = req->request.length % maxpacket;
 997                 dwc->ep0_bounced = true;
 998
 999                 /* prepare normal TRB */
1000                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1001                                          req->request.length,
1002                                          DWC3_TRBCTL_CONTROL_DATA,
1003                                          true);
1004
1005                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1006
1007                 /* Now prepare one extra TRB to align transfer size */
1008                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1009                                          maxpacket - rem,
1010                                          DWC3_TRBCTL_CONTROL_DATA,
1011                                          false);
1012                 ret = dwc3_ep0_start_trans(dep);
1013         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1014                    req->request.length && req->request.zero) {
1015                 u32     maxpacket;
1016                 u32     rem;
1017
1018                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1019                                 &req->request, dep->number);
1020                 if (ret)
1021                         return;
1022
1023                 maxpacket = dep->endpoint.maxpacket;
1024                 rem = req->request.length % maxpacket;
1025
1026                 /* prepare normal TRB */
1027                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1028                                          req->request.length,
1029                                          DWC3_TRBCTL_CONTROL_DATA,
1030                                          true);
1031
1032                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1033
1034                 if (!req->direction)
1035                         trb_length = dep->endpoint.maxpacket;
1036
1037                 /* Now prepare one extra TRB to align transfer size */
1038                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1039                                          trb_length, DWC3_TRBCTL_CONTROL_DATA,
1040                                          false);
1041                 ret = dwc3_ep0_start_trans(dep);
1042         } else {
1043                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1044                                 &req->request, dep->number);
1045                 if (ret)
1046                         return;
1047
1048                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1049                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1050                                 false);
1051
1052                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1053
1054                 ret = dwc3_ep0_start_trans(dep);
1055         }
1056
1057         WARN_ON(ret < 0);
1058 }
1059
1060 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1061 {
1062         struct dwc3             *dwc = dep->dwc;
1063         u32                     type;
1064
1065         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1066                 : DWC3_TRBCTL_CONTROL_STATUS2;
1067
1068         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1069         return dwc3_ep0_start_trans(dep);
1070 }
1071
1072 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1073 {
1074         WARN_ON(dwc3_ep0_start_control_status(dep));
1075 }
1076
1077 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1078                 const struct dwc3_event_depevt *event)
1079 {
1080         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1081
1082         __dwc3_ep0_do_control_status(dwc, dep);
1083 }
1084
1085 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1086 {
1087         struct dwc3_gadget_ep_cmd_params params;
1088         u32                     cmd;
1089         int                     ret;
1090
1091         if (!dep->resource_index)
1092                 return;
1093
1094         cmd = DWC3_DEPCMD_ENDTRANSFER;
1095         cmd |= DWC3_DEPCMD_CMDIOC;
1096         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1097         memset(&params, 0, sizeof(params));
1098         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1099         WARN_ON_ONCE(ret);
1100         dep->resource_index = 0;
1101 }
1102
1103 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1104                 const struct dwc3_event_depevt *event)
1105 {
1106         switch (event->status) {
1107         case DEPEVT_STATUS_CONTROL_DATA:
1108                 /*
1109                  * We already have a DATA transfer in the controller's cache,
1110                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1111                  * it's for the wrong direction.
1112                  *
1113                  * In that case, we must issue END_TRANSFER command to the Data
1114                  * Phase we already have started and issue SetStall on the
1115                  * control endpoint.
1116                  */
1117                 if (dwc->ep0_expect_in != event->endpoint_number) {
1118                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1119
1120                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1121                         dwc3_ep0_end_control_data(dwc, dep);
1122                         dwc3_ep0_stall_and_restart(dwc);
1123                         return;
1124                 }
1125
1126                 break;
1127
1128         case DEPEVT_STATUS_CONTROL_STATUS:
1129                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1130                         return;
1131
1132                 dwc->ep0state = EP0_STATUS_PHASE;
1133
1134                 if (dwc->delayed_status) {
1135                         struct dwc3_ep *dep = dwc->eps[0];
1136
1137                         WARN_ON_ONCE(event->endpoint_number != 1);
1138                         /*
1139                          * We should handle the delay STATUS phase here if the
1140                          * request for handling delay STATUS has been queued
1141                          * into the list.
1142                          */
1143                         if (!list_empty(&dep->pending_list)) {
1144                                 dwc->delayed_status = false;
1145                                 usb_gadget_set_state(&dwc->gadget,
1146                                                      USB_STATE_CONFIGURED);
1147                                 dwc3_ep0_do_control_status(dwc, event);
1148                         }
1149
1150                         return;
1151                 }
1152
1153                 dwc3_ep0_do_control_status(dwc, event);
1154         }
1155 }
1156
1157 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1158                 const struct dwc3_event_depevt *event)
1159 {
1160         struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1161         u8              cmd;
1162
1163         switch (event->endpoint_event) {
1164         case DWC3_DEPEVT_XFERCOMPLETE:
1165                 dwc3_ep0_xfer_complete(dwc, event);
1166                 break;
1167
1168         case DWC3_DEPEVT_XFERNOTREADY:
1169                 dwc3_ep0_xfernotready(dwc, event);
1170                 break;
1171
1172         case DWC3_DEPEVT_XFERINPROGRESS:
1173         case DWC3_DEPEVT_RXTXFIFOEVT:
1174         case DWC3_DEPEVT_STREAMEVT:
1175                 break;
1176         case DWC3_DEPEVT_EPCMDCMPLT:
1177                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1178
1179                 if (cmd == DWC3_DEPCMD_ENDTRANSFER)
1180                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1181                 break;
1182         }
1183 }