1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver
5 * Authors: Manish Narani <manish.narani@xilinx.com>
6 * Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/clk.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/of_address.h>
21 #include <linux/delay.h>
22 #include <linux/firmware/xlnx-zynqmp.h>
25 #include <linux/phy/phy.h>
27 /* USB phy reset mask register */
28 #define XLNX_USB_PHY_RST_EN 0x001C
29 #define XLNX_PHY_RST_MASK 0x1
31 /* Xilinx USB 3.0 IP Register */
32 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C
33 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1
35 #define XLNX_USB_FPD_PIPE_CLK 0x7c
36 #define PIPE_CLK_DESELECT 1
37 #define PIPE_CLK_SELECT 0
38 #define XLNX_USB_FPD_POWER_PRSNT 0x80
39 #define FPD_POWER_PRSNT_OPTION BIT(0)
43 struct clk_bulk_data *clks;
46 int (*pltfm_init)(struct dwc3_xlnx *data);
50 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask)
55 * Enable or disable ULPI PHY reset from USB Controller.
56 * This does not actually reset the phy, but just controls
57 * whether USB controller can or cannot reset ULPI PHY.
59 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN);
62 reg &= ~XLNX_PHY_RST_MASK;
64 reg |= XLNX_PHY_RST_MASK;
66 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN);
69 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
71 struct device *dev = priv_data->dev;
72 struct reset_control *crst;
75 crst = devm_reset_control_get_exclusive(dev, NULL);
77 return dev_err_probe(dev, PTR_ERR(crst), "failed to get reset signal\n");
79 dwc3_xlnx_mask_phy_rst(priv_data, false);
81 /* Assert and De-assert reset */
82 ret = reset_control_assert(crst);
84 dev_err_probe(dev, ret, "failed to assert Reset\n");
88 ret = reset_control_deassert(crst);
90 dev_err_probe(dev, ret, "failed to De-assert Reset\n");
94 dwc3_xlnx_mask_phy_rst(priv_data, true);
99 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
101 struct device *dev = priv_data->dev;
102 struct reset_control *crst, *hibrst, *apbrst;
103 struct gpio_desc *reset_gpio;
107 priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
108 if (IS_ERR(priv_data->usb3_phy)) {
109 ret = PTR_ERR(priv_data->usb3_phy);
110 dev_err_probe(dev, ret,
111 "failed to get USB3 PHY\n");
116 * The following core resets are not required unless a USB3 PHY
117 * is used, and the subsequent register settings are not required
118 * unless a core reset is performed (they should be set properly
119 * by the first-stage boot loader, but may be reverted by a core
120 * reset). They may also break the configuration if USB3 is actually
121 * in use but the usb3-phy entry is missing from the device tree.
122 * Therefore, skip these operations in this case.
124 if (!priv_data->usb3_phy)
127 crst = devm_reset_control_get_exclusive(dev, "usb_crst");
130 dev_err_probe(dev, ret,
131 "failed to get core reset signal\n");
135 hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst");
136 if (IS_ERR(hibrst)) {
137 ret = PTR_ERR(hibrst);
138 dev_err_probe(dev, ret,
139 "failed to get hibernation reset signal\n");
143 apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst");
144 if (IS_ERR(apbrst)) {
145 ret = PTR_ERR(apbrst);
146 dev_err_probe(dev, ret,
147 "failed to get APB reset signal\n");
151 ret = reset_control_assert(crst);
153 dev_err(dev, "Failed to assert core reset\n");
157 ret = reset_control_assert(hibrst);
159 dev_err(dev, "Failed to assert hibernation reset\n");
163 ret = reset_control_assert(apbrst);
165 dev_err(dev, "Failed to assert APB reset\n");
169 ret = phy_init(priv_data->usb3_phy);
171 phy_exit(priv_data->usb3_phy);
175 ret = reset_control_deassert(apbrst);
177 dev_err(dev, "Failed to release APB reset\n");
181 /* Set PIPE Power Present signal in FPD Power Present Register*/
182 writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT);
184 /* Set the PIPE Clock Select bit in FPD PIPE Clock register */
185 writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK);
187 ret = reset_control_deassert(crst);
189 dev_err(dev, "Failed to release core reset\n");
193 ret = reset_control_deassert(hibrst);
195 dev_err(dev, "Failed to release hibernation reset\n");
199 ret = phy_power_on(priv_data->usb3_phy);
201 phy_exit(priv_data->usb3_phy);
206 /* ulpi reset via gpio-modepin or gpio-framework driver */
207 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
208 if (IS_ERR(reset_gpio)) {
209 return dev_err_probe(dev, PTR_ERR(reset_gpio),
210 "Failed to request reset GPIO\n");
214 /* Toggle ulpi to reset the phy. */
215 gpiod_set_value_cansleep(reset_gpio, 1);
216 usleep_range(5000, 10000);
217 gpiod_set_value_cansleep(reset_gpio, 0);
218 usleep_range(5000, 10000);
222 * This routes the USB DMA traffic to go through FPD path instead
223 * of reaching DDR directly. This traffic routing is needed to
224 * make SMMU and CCI work with USB DMA.
226 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) {
227 reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
228 reg |= XLNX_USB_TRAFFIC_ROUTE_FPD;
229 writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG);
236 static const struct of_device_id dwc3_xlnx_of_match[] = {
238 .compatible = "xlnx,zynqmp-dwc3",
239 .data = &dwc3_xlnx_init_zynqmp,
242 .compatible = "xlnx,versal-dwc3",
243 .data = &dwc3_xlnx_init_versal,
247 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
249 static int dwc3_xlnx_probe(struct platform_device *pdev)
251 struct dwc3_xlnx *priv_data;
252 struct device *dev = &pdev->dev;
253 struct device_node *np = dev->of_node;
254 const struct of_device_id *match;
258 priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
262 regs = devm_platform_ioremap_resource(pdev, 0);
265 dev_err_probe(dev, ret, "failed to map registers\n");
269 match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
271 priv_data->pltfm_init = match->data;
272 priv_data->regs = regs;
273 priv_data->dev = dev;
275 platform_set_drvdata(pdev, priv_data);
277 ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks);
281 priv_data->num_clocks = ret;
283 ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks);
287 ret = priv_data->pltfm_init(priv_data);
291 ret = of_platform_populate(np, NULL, NULL, dev);
295 pm_runtime_set_active(dev);
296 pm_runtime_enable(dev);
297 pm_suspend_ignore_children(dev, false);
298 pm_runtime_get_sync(dev);
303 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
308 static void dwc3_xlnx_remove(struct platform_device *pdev)
310 struct dwc3_xlnx *priv_data = platform_get_drvdata(pdev);
311 struct device *dev = &pdev->dev;
313 of_platform_depopulate(dev);
315 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks);
316 priv_data->num_clocks = 0;
318 pm_runtime_disable(dev);
319 pm_runtime_put_noidle(dev);
320 pm_runtime_set_suspended(dev);
323 static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev)
325 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
327 clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
332 static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev)
334 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
336 return clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
339 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev)
341 pm_runtime_mark_last_busy(dev);
342 pm_runtime_autosuspend(dev);
347 static int __maybe_unused dwc3_xlnx_suspend(struct device *dev)
349 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
351 phy_exit(priv_data->usb3_phy);
353 /* Disable the clocks */
354 clk_bulk_disable(priv_data->num_clocks, priv_data->clks);
359 static int __maybe_unused dwc3_xlnx_resume(struct device *dev)
361 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev);
364 ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks);
368 ret = phy_init(priv_data->usb3_phy);
372 ret = phy_power_on(priv_data->usb3_phy);
374 phy_exit(priv_data->usb3_phy);
381 static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = {
382 SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume)
383 SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend,
384 dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle)
387 static struct platform_driver dwc3_xlnx_driver = {
388 .probe = dwc3_xlnx_probe,
389 .remove_new = dwc3_xlnx_remove,
391 .name = "dwc3-xilinx",
392 .of_match_table = dwc3_xlnx_of_match,
393 .pm = &dwc3_xlnx_dev_pm_ops,
397 module_platform_driver(dwc3_xlnx_driver);
399 MODULE_LICENSE("GPL v2");
400 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver");
401 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>");
402 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>");