drivers/usb/dwc3/dwc3-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
   3  *
   4  * Inspired by dwc3-of-simple.c
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/io.h>
   9 #include <linux/of.h>
  10 #include <linux/clk.h>
  11 #include <linux/irq.h>
  12 #include <linux/of_clk.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/extcon.h>
  16 #include <linux/interconnect.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/usb/of.h>
  21 #include <linux/reset.h>
  22 #include <linux/iopoll.h>
  23
  24 #include "core.h"
  25
  26 /* USB QSCRATCH Hardware registers */
  27 #define QSCRATCH_HS_PHY_CTRL                    0x10
  28 #define UTMI_OTG_VBUS_VALID                     BIT(20)
  29 #define SW_SESSVLD_SEL                          BIT(28)
  30
  31 #define QSCRATCH_SS_PHY_CTRL                    0x30
  32 #define LANE0_PWR_PRESENT                       BIT(24)
  33
  34 #define QSCRATCH_GENERAL_CFG                    0x08
  35 #define PIPE_UTMI_CLK_SEL                       BIT(0)
  36 #define PIPE3_PHYSTATUS_SW                      BIT(3)
  37 #define PIPE_UTMI_CLK_DIS                       BIT(8)
  38
  39 #define PWR_EVNT_IRQ_STAT_REG                   0x58
  40 #define PWR_EVNT_LPM_IN_L2_MASK                 BIT(4)
  41 #define PWR_EVNT_LPM_OUT_L2_MASK                BIT(5)
  42
  43 #define SDM845_QSCRATCH_BASE_OFFSET             0xf8800
  44 #define SDM845_QSCRATCH_SIZE                    0x400
  45 #define SDM845_DWC3_CORE_SIZE                   0xcd00
  46
  47 /* Interconnect path bandwidths in MBps */
  48 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
  49 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
  50 #define USB_MEMORY_AVG_SS_BW  MBps_to_icc(1000)
  51 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
  52 #define APPS_USB_AVG_BW 0
  53 #define APPS_USB_PEAK_BW MBps_to_icc(40)
  54
  55 struct dwc3_acpi_pdata {
  56         u32                     qscratch_base_offset;
  57         u32                     qscratch_base_size;
  58         u32                     dwc3_core_base_size;
  59         int                     hs_phy_irq_index;
  60         int                     dp_hs_phy_irq_index;
  61         int                     dm_hs_phy_irq_index;
  62         int                     ss_phy_irq_index;
  63         bool                    is_urs;
  64 };
  65
  66 struct dwc3_qcom {
  67         struct device           *dev;
  68         void __iomem            *qscratch_base;
  69         struct platform_device  *dwc3;
  70         struct platform_device  *urs_usb;
  71         struct clk              **clks;
  72         int                     num_clocks;
  73         struct reset_control    *resets;
  74
  75         int                     hs_phy_irq;
  76         int                     dp_hs_phy_irq;
  77         int                     dm_hs_phy_irq;
  78         int                     ss_phy_irq;
  79
  80         struct extcon_dev       *edev;
  81         struct extcon_dev       *host_edev;
  82         struct notifier_block   vbus_nb;
  83         struct notifier_block   host_nb;
  84
  85         const struct dwc3_acpi_pdata *acpi_pdata;
  86
  87         enum usb_dr_mode        mode;
  88         bool                    is_suspended;
  89         bool                    pm_suspended;
  90         struct icc_path         *icc_path_ddr;
  91         struct icc_path         *icc_path_apps;
  92 };
  93
  94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
  95 {
  96         u32 reg;
  97
  98         reg = readl(base + offset);
  99         reg |= val;
 100         writel(reg, base + offset);
 101
 102         /* ensure that above write is through */
 103         readl(base + offset);
 104 }
 105
 106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
 107 {
 108         u32 reg;
 109
 110         reg = readl(base + offset);
 111         reg &= ~val;
 112         writel(reg, base + offset);
 113
 114         /* ensure that above write is through */
 115         readl(base + offset);
 116 }
 117
 118 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
 119 {
 120         if (enable) {
 121                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
 122                                   LANE0_PWR_PRESENT);
 123                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
 124                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
 125         } else {
 126                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
 127                                   LANE0_PWR_PRESENT);
 128                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
 129                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
 130         }
 131 }
 132
 133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
 134                                    unsigned long event, void *ptr)
 135 {
 136         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
 137
 138         /* enable vbus override for device mode */
 139         dwc3_qcom_vbus_override_enable(qcom, event);
 140         qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
 141
 142         return NOTIFY_DONE;
 143 }
 144
 145 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
 146                                    unsigned long event, void *ptr)
 147 {
 148         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
 149
 150         /* disable vbus override in host mode */
 151         dwc3_qcom_vbus_override_enable(qcom, !event);
 152         qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
 153
 154         return NOTIFY_DONE;
 155 }
 156
 157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
 158 {
 159         struct device           *dev = qcom->dev;
 160         struct extcon_dev       *host_edev;
 161         int                     ret;
 162
 163         if (!of_property_read_bool(dev->of_node, "extcon"))
 164                 return 0;
 165
 166         qcom->edev = extcon_get_edev_by_phandle(dev, 0);
 167         if (IS_ERR(qcom->edev))
 168                 return PTR_ERR(qcom->edev);
 169
 170         qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
 171
 172         qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
 173         if (IS_ERR(qcom->host_edev))
 174                 qcom->host_edev = NULL;
 175
 176         ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
 177                                             &qcom->vbus_nb);
 178         if (ret < 0) {
 179                 dev_err(dev, "VBUS notifier register failed\n");
 180                 return ret;
 181         }
 182
 183         if (qcom->host_edev)
 184                 host_edev = qcom->host_edev;
 185         else
 186                 host_edev = qcom->edev;
 187
 188         qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
 189         ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
 190                                             &qcom->host_nb);
 191         if (ret < 0) {
 192                 dev_err(dev, "Host notifier register failed\n");
 193                 return ret;
 194         }
 195
 196         /* Update initial VBUS override based on extcon state */
 197         if (extcon_get_state(qcom->edev, EXTCON_USB) ||
 198             !extcon_get_state(host_edev, EXTCON_USB_HOST))
 199                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
 200         else
 201                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
 202
 203         return 0;
 204 }
 205
 206 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
 207 {
 208         int ret;
 209
 210         ret = icc_enable(qcom->icc_path_ddr);
 211         if (ret)
 212                 return ret;
 213
 214         ret = icc_enable(qcom->icc_path_apps);
 215         if (ret)
 216                 icc_disable(qcom->icc_path_ddr);
 217
 218         return ret;
 219 }
 220
 221 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
 222 {
 223         int ret;
 224
 225         ret = icc_disable(qcom->icc_path_ddr);
 226         if (ret)
 227                 return ret;
 228
 229         ret = icc_disable(qcom->icc_path_apps);
 230         if (ret)
 231                 icc_enable(qcom->icc_path_ddr);
 232
 233         return ret;
 234 }
 235
 236 /**
 237  * dwc3_qcom_interconnect_init() - Get interconnect path handles
 238  * and set bandwidhth.
 239  * @qcom:                       Pointer to the concerned usb core.
 240  *
 241  */
 242 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
 243 {
 244         struct device *dev = qcom->dev;
 245         int ret;
 246
 247         if (has_acpi_companion(dev))
 248                 return 0;
 249
 250         qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
 251         if (IS_ERR(qcom->icc_path_ddr)) {
 252                 dev_err(dev, "failed to get usb-ddr path: %ld\n",
 253                         PTR_ERR(qcom->icc_path_ddr));
 254                 return PTR_ERR(qcom->icc_path_ddr);
 255         }
 256
 257         qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
 258         if (IS_ERR(qcom->icc_path_apps)) {
 259                 dev_err(dev, "failed to get apps-usb path: %ld\n",
 260                                 PTR_ERR(qcom->icc_path_apps));
 261                 ret = PTR_ERR(qcom->icc_path_apps);
 262                 goto put_path_ddr;
 263         }
 264
 265         if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
 266                         usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
 267                 ret = icc_set_bw(qcom->icc_path_ddr,
 268                         USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
 269         else
 270                 ret = icc_set_bw(qcom->icc_path_ddr,
 271                         USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
 272
 273         if (ret) {
 274                 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
 275                 goto put_path_apps;
 276         }
 277
 278         ret = icc_set_bw(qcom->icc_path_apps,
 279                 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
 280         if (ret) {
 281                 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
 282                 goto put_path_apps;
 283         }
 284
 285         return 0;
 286
 287 put_path_apps:
 288         icc_put(qcom->icc_path_apps);
 289 put_path_ddr:
 290         icc_put(qcom->icc_path_ddr);
 291         return ret;
 292 }
 293
 294 /**
 295  * dwc3_qcom_interconnect_exit() - Release interconnect path handles
 296  * @qcom:                       Pointer to the concerned usb core.
 297  *
 298  * This function is used to release interconnect path handle.
 299  */
 300 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
 301 {
 302         icc_put(qcom->icc_path_ddr);
 303         icc_put(qcom->icc_path_apps);
 304 }
 305
 306 /* Only usable in contexts where the role can not change. */
 307 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
 308 {
 309         struct dwc3 *dwc;
 310
 311         /*
 312          * FIXME: Fix this layering violation.
 313          */
 314         dwc = platform_get_drvdata(qcom->dwc3);
 315
 316         /* Core driver may not have probed yet. */
 317         if (!dwc)
 318                 return false;
 319
 320         return dwc->xhci;
 321 }
 322
 323 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 324 {
 325         if (qcom->hs_phy_irq) {
 326                 disable_irq_wake(qcom->hs_phy_irq);
 327                 disable_irq_nosync(qcom->hs_phy_irq);
 328         }
 329
 330         if (qcom->dp_hs_phy_irq) {
 331                 disable_irq_wake(qcom->dp_hs_phy_irq);
 332                 disable_irq_nosync(qcom->dp_hs_phy_irq);
 333         }
 334
 335         if (qcom->dm_hs_phy_irq) {
 336                 disable_irq_wake(qcom->dm_hs_phy_irq);
 337                 disable_irq_nosync(qcom->dm_hs_phy_irq);
 338         }
 339
 340         if (qcom->ss_phy_irq) {
 341                 disable_irq_wake(qcom->ss_phy_irq);
 342                 disable_irq_nosync(qcom->ss_phy_irq);
 343         }
 344 }
 345
 346 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 347 {
 348         if (qcom->hs_phy_irq) {
 349                 enable_irq(qcom->hs_phy_irq);
 350                 enable_irq_wake(qcom->hs_phy_irq);
 351         }
 352
 353         if (qcom->dp_hs_phy_irq) {
 354                 enable_irq(qcom->dp_hs_phy_irq);
 355                 enable_irq_wake(qcom->dp_hs_phy_irq);
 356         }
 357
 358         if (qcom->dm_hs_phy_irq) {
 359                 enable_irq(qcom->dm_hs_phy_irq);
 360                 enable_irq_wake(qcom->dm_hs_phy_irq);
 361         }
 362
 363         if (qcom->ss_phy_irq) {
 364                 enable_irq(qcom->ss_phy_irq);
 365                 enable_irq_wake(qcom->ss_phy_irq);
 366         }
 367 }
 368
 369 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
 370 {
 371         u32 val;
 372         int i, ret;
 373
 374         if (qcom->is_suspended)
 375                 return 0;
 376
 377         val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
 378         if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
 379                 dev_err(qcom->dev, "HS-PHY not in L2\n");
 380
 381         for (i = qcom->num_clocks - 1; i >= 0; i--)
 382                 clk_disable_unprepare(qcom->clks[i]);
 383
 384         ret = dwc3_qcom_interconnect_disable(qcom);
 385         if (ret)
 386                 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
 387
 388         if (device_may_wakeup(qcom->dev))
 389                 dwc3_qcom_enable_interrupts(qcom);
 390
 391         qcom->is_suspended = true;
 392
 393         return 0;
 394 }
 395
 396 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
 397 {
 398         int ret;
 399         int i;
 400
 401         if (!qcom->is_suspended)
 402                 return 0;
 403
 404         if (device_may_wakeup(qcom->dev))
 405                 dwc3_qcom_disable_interrupts(qcom);
 406
 407         for (i = 0; i < qcom->num_clocks; i++) {
 408                 ret = clk_prepare_enable(qcom->clks[i]);
 409                 if (ret < 0) {
 410                         while (--i >= 0)
 411                                 clk_disable_unprepare(qcom->clks[i]);
 412                         return ret;
 413                 }
 414         }
 415
 416         ret = dwc3_qcom_interconnect_enable(qcom);
 417         if (ret)
 418                 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
 419
 420         /* Clear existing events from PHY related to L2 in/out */
 421         dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
 422                           PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
 423
 424         qcom->is_suspended = false;
 425
 426         return 0;
 427 }
 428
 429 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
 430 {
 431         struct dwc3_qcom *qcom = data;
 432         struct dwc3     *dwc = platform_get_drvdata(qcom->dwc3);
 433
 434         /* If pm_suspended then let pm_resume take care of resuming h/w */
 435         if (qcom->pm_suspended)
 436                 return IRQ_HANDLED;
 437
 438         /*
 439          * This is safe as role switching is done from a freezable workqueue
 440          * and the wakeup interrupts are disabled as part of resume.
 441          */
 442         if (dwc3_qcom_is_host(qcom))
 443                 pm_runtime_resume(&dwc->xhci->dev);
 444
 445         return IRQ_HANDLED;
 446 }
 447
 448 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
 449 {
 450         /* Configure dwc3 to use UTMI clock as PIPE clock not present */
 451         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 452                           PIPE_UTMI_CLK_DIS);
 453
 454         usleep_range(100, 1000);
 455
 456         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 457                           PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 458
 459         usleep_range(100, 1000);
 460
 461         dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 462                           PIPE_UTMI_CLK_DIS);
 463 }
 464
 465 static int dwc3_qcom_get_irq(struct platform_device *pdev,
 466                              const char *name, int num)
 467 {
 468         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 469         struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
 470         struct device_node *np = pdev->dev.of_node;
 471         int ret;
 472
 473         if (np)
 474                 ret = platform_get_irq_byname_optional(pdev_irq, name);
 475         else
 476                 ret = platform_get_irq_optional(pdev_irq, num);
 477
 478         return ret;
 479 }
 480
 481 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
 482 {
 483         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 484         const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
 485         int irq;
 486         int ret;
 487
 488         irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
 489                                 pdata ? pdata->hs_phy_irq_index : -1);
 490         if (irq > 0) {
 491                 /* Keep wakeup interrupts disabled until suspend */
 492                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 493                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 494                                         qcom_dwc3_resume_irq,
 495                                         IRQF_ONESHOT,
 496                                         "qcom_dwc3 HS", qcom);
 497                 if (ret) {
 498                         dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
 499                         return ret;
 500                 }
 501                 qcom->hs_phy_irq = irq;
 502         }
 503
 504         irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
 505                                 pdata ? pdata->dp_hs_phy_irq_index : -1);
 506         if (irq > 0) {
 507                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 508                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 509                                         qcom_dwc3_resume_irq,
 510                                         IRQF_ONESHOT,
 511                                         "qcom_dwc3 DP_HS", qcom);
 512                 if (ret) {
 513                         dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
 514                         return ret;
 515                 }
 516                 qcom->dp_hs_phy_irq = irq;
 517         }
 518
 519         irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
 520                                 pdata ? pdata->dm_hs_phy_irq_index : -1);
 521         if (irq > 0) {
 522                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 523                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 524                                         qcom_dwc3_resume_irq,
 525                                         IRQF_ONESHOT,
 526                                         "qcom_dwc3 DM_HS", qcom);
 527                 if (ret) {
 528                         dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
 529                         return ret;
 530                 }
 531                 qcom->dm_hs_phy_irq = irq;
 532         }
 533
 534         irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
 535                                 pdata ? pdata->ss_phy_irq_index : -1);
 536         if (irq > 0) {
 537                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 538                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 539                                         qcom_dwc3_resume_irq,
 540                                         IRQF_ONESHOT,
 541                                         "qcom_dwc3 SS", qcom);
 542                 if (ret) {
 543                         dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
 544                         return ret;
 545                 }
 546                 qcom->ss_phy_irq = irq;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
 553 {
 554         struct device           *dev = qcom->dev;
 555         struct device_node      *np = dev->of_node;
 556         int                     i;
 557
 558         if (!np || !count)
 559                 return 0;
 560
 561         if (count < 0)
 562                 return count;
 563
 564         qcom->num_clocks = count;
 565
 566         qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
 567                                   sizeof(struct clk *), GFP_KERNEL);
 568         if (!qcom->clks)
 569                 return -ENOMEM;
 570
 571         for (i = 0; i < qcom->num_clocks; i++) {
 572                 struct clk      *clk;
 573                 int             ret;
 574
 575                 clk = of_clk_get(np, i);
 576                 if (IS_ERR(clk)) {
 577                         while (--i >= 0)
 578                                 clk_put(qcom->clks[i]);
 579                         return PTR_ERR(clk);
 580                 }
 581
 582                 ret = clk_prepare_enable(clk);
 583                 if (ret < 0) {
 584                         while (--i >= 0) {
 585                                 clk_disable_unprepare(qcom->clks[i]);
 586                                 clk_put(qcom->clks[i]);
 587                         }
 588                         clk_put(clk);
 589
 590                         return ret;
 591                 }
 592
 593                 qcom->clks[i] = clk;
 594         }
 595
 596         return 0;
 597 }
 598
 599 static const struct property_entry dwc3_qcom_acpi_properties[] = {
 600         PROPERTY_ENTRY_STRING("dr_mode", "host"),
 601         {}
 602 };
 603
 604 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
 605 {
 606         struct dwc3_qcom        *qcom = platform_get_drvdata(pdev);
 607         struct device           *dev = &pdev->dev;
 608         struct resource         *res, *child_res = NULL;
 609         struct platform_device  *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
 610                                                             pdev;
 611         int                     irq;
 612         int                     ret;
 613
 614         qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 615         if (!qcom->dwc3)
 616                 return -ENOMEM;
 617
 618         qcom->dwc3->dev.parent = dev;
 619         qcom->dwc3->dev.type = dev->type;
 620         qcom->dwc3->dev.dma_mask = dev->dma_mask;
 621         qcom->dwc3->dev.dma_parms = dev->dma_parms;
 622         qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
 623
 624         child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
 625         if (!child_res)
 626                 return -ENOMEM;
 627
 628         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 629         if (!res) {
 630                 dev_err(&pdev->dev, "failed to get memory resource\n");
 631                 ret = -ENODEV;
 632                 goto out;
 633         }
 634
 635         child_res[0].flags = res->flags;
 636         child_res[0].start = res->start;
 637         child_res[0].end = child_res[0].start +
 638                 qcom->acpi_pdata->dwc3_core_base_size;
 639
 640         irq = platform_get_irq(pdev_irq, 0);
 641         if (irq < 0) {
 642                 ret = irq;
 643                 goto out;
 644         }
 645         child_res[1].flags = IORESOURCE_IRQ;
 646         child_res[1].start = child_res[1].end = irq;
 647
 648         ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
 649         if (ret) {
 650                 dev_err(&pdev->dev, "failed to add resources\n");
 651                 goto out;
 652         }
 653
 654         ret = platform_device_add_properties(qcom->dwc3,
 655                                              dwc3_qcom_acpi_properties);
 656         if (ret < 0) {
 657                 dev_err(&pdev->dev, "failed to add properties\n");
 658                 goto out;
 659         }
 660
 661         ret = platform_device_add(qcom->dwc3);
 662         if (ret)
 663                 dev_err(&pdev->dev, "failed to add device\n");
 664
 665 out:
 666         kfree(child_res);
 667         return ret;
 668 }
 669
 670 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
 671 {
 672         struct dwc3_qcom        *qcom = platform_get_drvdata(pdev);
 673         struct device_node      *np = pdev->dev.of_node, *dwc3_np;
 674         struct device           *dev = &pdev->dev;
 675         int                     ret;
 676
 677         dwc3_np = of_get_child_by_name(np, "dwc3");
 678         if (!dwc3_np) {
 679                 dev_err(dev, "failed to find dwc3 core child\n");
 680                 return -ENODEV;
 681         }
 682
 683         ret = of_platform_populate(np, NULL, NULL, dev);
 684         if (ret) {
 685                 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
 686                 goto node_put;
 687         }
 688
 689         qcom->dwc3 = of_find_device_by_node(dwc3_np);
 690         if (!qcom->dwc3) {
 691                 ret = -ENODEV;
 692                 dev_err(dev, "failed to get dwc3 platform device\n");
 693                 of_platform_depopulate(dev);
 694         }
 695
 696 node_put:
 697         of_node_put(dwc3_np);
 698
 699         return ret;
 700 }
 701
 702 static struct platform_device *dwc3_qcom_create_urs_usb_platdev(struct device *dev)
 703 {
 704         struct platform_device *urs_usb = NULL;
 705         struct fwnode_handle *fwh;
 706         struct acpi_device *adev;
 707         char name[8];
 708         int ret;
 709         int id;
 710
 711         /* Figure out device id */
 712         ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
 713         if (!ret)
 714                 return NULL;
 715
 716         /* Find the child using name */
 717         snprintf(name, sizeof(name), "USB%d", id);
 718         fwh = fwnode_get_named_child_node(dev->fwnode, name);
 719         if (!fwh)
 720                 return NULL;
 721
 722         adev = to_acpi_device_node(fwh);
 723         if (!adev)
 724                 goto err_put_handle;
 725
 726         urs_usb = acpi_create_platform_device(adev, NULL);
 727         if (IS_ERR_OR_NULL(urs_usb))
 728                 goto err_put_handle;
 729
 730         return urs_usb;
 731
 732 err_put_handle:
 733         fwnode_handle_put(fwh);
 734
 735         return urs_usb;
 736 }
 737
 738 static void dwc3_qcom_destroy_urs_usb_platdev(struct platform_device *urs_usb)
 739 {
 740         struct fwnode_handle *fwh = urs_usb->dev.fwnode;
 741
 742         platform_device_unregister(urs_usb);
 743         fwnode_handle_put(fwh);
 744 }
 745
 746 static int dwc3_qcom_probe(struct platform_device *pdev)
 747 {
 748         struct device_node      *np = pdev->dev.of_node;
 749         struct device           *dev = &pdev->dev;
 750         struct dwc3_qcom        *qcom;
 751         struct resource         *res, *parent_res = NULL;
 752         struct resource         local_res;
 753         int                     ret, i;
 754         bool                    ignore_pipe_clk;
 755
 756         qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
 757         if (!qcom)
 758                 return -ENOMEM;
 759
 760         platform_set_drvdata(pdev, qcom);
 761         qcom->dev = &pdev->dev;
 762
 763         if (has_acpi_companion(dev)) {
 764                 qcom->acpi_pdata = acpi_device_get_match_data(dev);
 765                 if (!qcom->acpi_pdata) {
 766                         dev_err(&pdev->dev, "no supporting ACPI device data\n");
 767                         return -EINVAL;
 768                 }
 769         }
 770
 771         qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
 772         if (IS_ERR(qcom->resets)) {
 773                 ret = PTR_ERR(qcom->resets);
 774                 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
 775                 return ret;
 776         }
 777
 778         ret = reset_control_assert(qcom->resets);
 779         if (ret) {
 780                 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
 781                 return ret;
 782         }
 783
 784         usleep_range(10, 1000);
 785
 786         ret = reset_control_deassert(qcom->resets);
 787         if (ret) {
 788                 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
 789                 goto reset_assert;
 790         }
 791
 792         ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
 793         if (ret) {
 794                 dev_err(dev, "failed to get clocks\n");
 795                 goto reset_assert;
 796         }
 797
 798         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 799
 800         if (np) {
 801                 parent_res = res;
 802         } else {
 803                 memcpy(&local_res, res, sizeof(struct resource));
 804                 parent_res = &local_res;
 805
 806                 parent_res->start = res->start +
 807                         qcom->acpi_pdata->qscratch_base_offset;
 808                 parent_res->end = parent_res->start +
 809                         qcom->acpi_pdata->qscratch_base_size;
 810
 811                 if (qcom->acpi_pdata->is_urs) {
 812                         qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
 813                         if (IS_ERR_OR_NULL(qcom->urs_usb)) {
 814                                 dev_err(dev, "failed to create URS USB platdev\n");
 815                                 if (!qcom->urs_usb)
 816                                         ret = -ENODEV;
 817                                 else
 818                                         ret = PTR_ERR(qcom->urs_usb);
 819                                 goto clk_disable;
 820                         }
 821                 }
 822         }
 823
 824         qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
 825         if (IS_ERR(qcom->qscratch_base)) {
 826                 dev_err(dev, "failed to map qscratch, err=%d\n", ret);
 827                 ret = PTR_ERR(qcom->qscratch_base);
 828                 goto free_urs;
 829         }
 830
 831         ret = dwc3_qcom_setup_irq(pdev);
 832         if (ret) {
 833                 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
 834                 goto free_urs;
 835         }
 836
 837         /*
 838          * Disable pipe_clk requirement if specified. Used when dwc3
 839          * operates without SSPHY and only HS/FS/LS modes are supported.
 840          */
 841         ignore_pipe_clk = device_property_read_bool(dev,
 842                                 "qcom,select-utmi-as-pipe-clk");
 843         if (ignore_pipe_clk)
 844                 dwc3_qcom_select_utmi_clk(qcom);
 845
 846         if (np)
 847                 ret = dwc3_qcom_of_register_core(pdev);
 848         else
 849                 ret = dwc3_qcom_acpi_register_core(pdev);
 850
 851         if (ret) {
 852                 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
 853                 goto free_urs;
 854         }
 855
 856         ret = dwc3_qcom_interconnect_init(qcom);
 857         if (ret)
 858                 goto depopulate;
 859
 860         qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
 861
 862         /* enable vbus override for device mode */
 863         if (qcom->mode != USB_DR_MODE_HOST)
 864                 dwc3_qcom_vbus_override_enable(qcom, true);
 865
 866         /* register extcon to override sw_vbus on Vbus change later */
 867         ret = dwc3_qcom_register_extcon(qcom);
 868         if (ret)
 869                 goto interconnect_exit;
 870
 871         device_init_wakeup(&pdev->dev, 1);
 872         qcom->is_suspended = false;
 873         pm_runtime_set_active(dev);
 874         pm_runtime_enable(dev);
 875         pm_runtime_forbid(dev);
 876
 877         return 0;
 878
 879 interconnect_exit:
 880         dwc3_qcom_interconnect_exit(qcom);
 881 depopulate:
 882         if (np)
 883                 of_platform_depopulate(&pdev->dev);
 884         else
 885                 platform_device_del(qcom->dwc3);
 886         platform_device_put(qcom->dwc3);
 887 free_urs:
 888         if (qcom->urs_usb)
 889                 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
 890 clk_disable:
 891         for (i = qcom->num_clocks - 1; i >= 0; i--) {
 892                 clk_disable_unprepare(qcom->clks[i]);
 893                 clk_put(qcom->clks[i]);
 894         }
 895 reset_assert:
 896         reset_control_assert(qcom->resets);
 897
 898         return ret;
 899 }
 900
 901 static int dwc3_qcom_remove(struct platform_device *pdev)
 902 {
 903         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 904         struct device_node *np = pdev->dev.of_node;
 905         struct device *dev = &pdev->dev;
 906         int i;
 907
 908         if (np)
 909                 of_platform_depopulate(&pdev->dev);
 910         else
 911                 platform_device_del(qcom->dwc3);
 912         platform_device_put(qcom->dwc3);
 913
 914         if (qcom->urs_usb)
 915                 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
 916
 917         for (i = qcom->num_clocks - 1; i >= 0; i--) {
 918                 clk_disable_unprepare(qcom->clks[i]);
 919                 clk_put(qcom->clks[i]);
 920         }
 921         qcom->num_clocks = 0;
 922
 923         dwc3_qcom_interconnect_exit(qcom);
 924         reset_control_assert(qcom->resets);
 925
 926         pm_runtime_allow(dev);
 927         pm_runtime_disable(dev);
 928
 929         return 0;
 930 }
 931
 932 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
 933 {
 934         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 935         int ret = 0;
 936
 937         ret = dwc3_qcom_suspend(qcom);
 938         if (!ret)
 939                 qcom->pm_suspended = true;
 940
 941         return ret;
 942 }
 943
 944 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
 945 {
 946         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 947         int ret;
 948
 949         ret = dwc3_qcom_resume(qcom);
 950         if (!ret)
 951                 qcom->pm_suspended = false;
 952
 953         return ret;
 954 }
 955
 956 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
 957 {
 958         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 959
 960         return dwc3_qcom_suspend(qcom);
 961 }
 962
 963 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
 964 {
 965         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 966
 967         return dwc3_qcom_resume(qcom);
 968 }
 969
 970 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
 971         SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
 972         SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
 973                            NULL)
 974 };
 975
 976 static const struct of_device_id dwc3_qcom_of_match[] = {
 977         { .compatible = "qcom,dwc3" },
 978         { .compatible = "qcom,msm8996-dwc3" },
 979         { .compatible = "qcom,msm8998-dwc3" },
 980         { .compatible = "qcom,sdm845-dwc3" },
 981         { }
 982 };
 983 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
 984
 985 #ifdef CONFIG_ACPI
 986 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
 987         .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
 988         .qscratch_base_size = SDM845_QSCRATCH_SIZE,
 989         .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
 990         .hs_phy_irq_index = 1,
 991         .dp_hs_phy_irq_index = 4,
 992         .dm_hs_phy_irq_index = 3,
 993         .ss_phy_irq_index = 2
 994 };
 995
 996 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
 997         .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
 998         .qscratch_base_size = SDM845_QSCRATCH_SIZE,
 999         .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1000         .hs_phy_irq_index = 1,
1001         .dp_hs_phy_irq_index = 4,
1002         .dm_hs_phy_irq_index = 3,
1003         .ss_phy_irq_index = 2,
1004         .is_urs = true,
1005 };
1006
1007 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1008         { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1009         { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1010         { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1011         { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1012         { },
1013 };
1014 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1015 #endif
1016
1017 static struct platform_driver dwc3_qcom_driver = {
1018         .probe          = dwc3_qcom_probe,
1019         .remove         = dwc3_qcom_remove,
1020         .driver         = {
1021                 .name   = "dwc3-qcom",
1022                 .pm     = &dwc3_qcom_dev_pm_ops,
1023                 .of_match_table = dwc3_qcom_of_match,
1024                 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1025         },
1026 };
1027
1028 module_platform_driver(dwc3_qcom_driver);
1029
1030 MODULE_LICENSE("GPL v2");
1031 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");