drivers/usb/dwc3/dwc3-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
   3  *
   4  * Inspired by dwc3-of-simple.c
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/io.h>
   9 #include <linux/of.h>
  10 #include <linux/clk.h>
  11 #include <linux/irq.h>
  12 #include <linux/of_clk.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/extcon.h>
  16 #include <linux/interconnect.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/usb/of.h>
  21 #include <linux/reset.h>
  22 #include <linux/iopoll.h>
  23
  24 #include "core.h"
  25
  26 /* USB QSCRATCH Hardware registers */
  27 #define QSCRATCH_HS_PHY_CTRL                    0x10
  28 #define UTMI_OTG_VBUS_VALID                     BIT(20)
  29 #define SW_SESSVLD_SEL                          BIT(28)
  30
  31 #define QSCRATCH_SS_PHY_CTRL                    0x30
  32 #define LANE0_PWR_PRESENT                       BIT(24)
  33
  34 #define QSCRATCH_GENERAL_CFG                    0x08
  35 #define PIPE_UTMI_CLK_SEL                       BIT(0)
  36 #define PIPE3_PHYSTATUS_SW                      BIT(3)
  37 #define PIPE_UTMI_CLK_DIS                       BIT(8)
  38
  39 #define PWR_EVNT_IRQ_STAT_REG                   0x58
  40 #define PWR_EVNT_LPM_IN_L2_MASK                 BIT(4)
  41 #define PWR_EVNT_LPM_OUT_L2_MASK                BIT(5)
  42
  43 #define SDM845_QSCRATCH_BASE_OFFSET             0xf8800
  44 #define SDM845_QSCRATCH_SIZE                    0x400
  45 #define SDM845_DWC3_CORE_SIZE                   0xcd00
  46
  47 /* Interconnect path bandwidths in MBps */
  48 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
  49 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
  50 #define USB_MEMORY_AVG_SS_BW  MBps_to_icc(1000)
  51 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
  52 #define APPS_USB_AVG_BW 0
  53 #define APPS_USB_PEAK_BW MBps_to_icc(40)
  54
  55 struct dwc3_acpi_pdata {
  56         u32                     qscratch_base_offset;
  57         u32                     qscratch_base_size;
  58         u32                     dwc3_core_base_size;
  59         int                     hs_phy_irq_index;
  60         int                     dp_hs_phy_irq_index;
  61         int                     dm_hs_phy_irq_index;
  62         int                     ss_phy_irq_index;
  63         bool                    is_urs;
  64 };
  65
  66 struct dwc3_qcom {
  67         struct device           *dev;
  68         void __iomem            *qscratch_base;
  69         struct platform_device  *dwc3;
  70         struct platform_device  *urs_usb;
  71         struct clk              **clks;
  72         int                     num_clocks;
  73         struct reset_control    *resets;
  74
  75         int                     hs_phy_irq;
  76         int                     dp_hs_phy_irq;
  77         int                     dm_hs_phy_irq;
  78         int                     ss_phy_irq;
  79
  80         struct extcon_dev       *edev;
  81         struct extcon_dev       *host_edev;
  82         struct notifier_block   vbus_nb;
  83         struct notifier_block   host_nb;
  84
  85         const struct dwc3_acpi_pdata *acpi_pdata;
  86
  87         enum usb_dr_mode        mode;
  88         bool                    is_suspended;
  89         bool                    pm_suspended;
  90         struct icc_path         *icc_path_ddr;
  91         struct icc_path         *icc_path_apps;
  92 };
  93
  94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
  95 {
  96         u32 reg;
  97
  98         reg = readl(base + offset);
  99         reg |= val;
 100         writel(reg, base + offset);
 101
 102         /* ensure that above write is through */
 103         readl(base + offset);
 104 }
 105
 106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
 107 {
 108         u32 reg;
 109
 110         reg = readl(base + offset);
 111         reg &= ~val;
 112         writel(reg, base + offset);
 113
 114         /* ensure that above write is through */
 115         readl(base + offset);
 116 }
 117
 118 static void dwc3_qcom_vbus_overrride_enable(struct dwc3_qcom *qcom, bool enable)
 119 {
 120         if (enable) {
 121                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
 122                                   LANE0_PWR_PRESENT);
 123                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
 124                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
 125         } else {
 126                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
 127                                   LANE0_PWR_PRESENT);
 128                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
 129                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
 130         }
 131 }
 132
 133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
 134                                    unsigned long event, void *ptr)
 135 {
 136         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
 137
 138         /* enable vbus override for device mode */
 139         dwc3_qcom_vbus_overrride_enable(qcom, event);
 140         qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
 141
 142         return NOTIFY_DONE;
 143 }
 144
 145 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
 146                                    unsigned long event, void *ptr)
 147 {
 148         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
 149
 150         /* disable vbus override in host mode */
 151         dwc3_qcom_vbus_overrride_enable(qcom, !event);
 152         qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
 153
 154         return NOTIFY_DONE;
 155 }
 156
 157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
 158 {
 159         struct device           *dev = qcom->dev;
 160         struct extcon_dev       *host_edev;
 161         int                     ret;
 162
 163         if (!of_property_read_bool(dev->of_node, "extcon"))
 164                 return 0;
 165
 166         qcom->edev = extcon_get_edev_by_phandle(dev, 0);
 167         if (IS_ERR(qcom->edev))
 168                 return PTR_ERR(qcom->edev);
 169
 170         qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
 171
 172         qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
 173         if (IS_ERR(qcom->host_edev))
 174                 qcom->host_edev = NULL;
 175
 176         ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
 177                                             &qcom->vbus_nb);
 178         if (ret < 0) {
 179                 dev_err(dev, "VBUS notifier register failed\n");
 180                 return ret;
 181         }
 182
 183         if (qcom->host_edev)
 184                 host_edev = qcom->host_edev;
 185         else
 186                 host_edev = qcom->edev;
 187
 188         qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
 189         ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
 190                                             &qcom->host_nb);
 191         if (ret < 0) {
 192                 dev_err(dev, "Host notifier register failed\n");
 193                 return ret;
 194         }
 195
 196         /* Update initial VBUS override based on extcon state */
 197         if (extcon_get_state(qcom->edev, EXTCON_USB) ||
 198             !extcon_get_state(host_edev, EXTCON_USB_HOST))
 199                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
 200         else
 201                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
 202
 203         return 0;
 204 }
 205
 206 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
 207 {
 208         int ret;
 209
 210         ret = icc_enable(qcom->icc_path_ddr);
 211         if (ret)
 212                 return ret;
 213
 214         ret = icc_enable(qcom->icc_path_apps);
 215         if (ret)
 216                 icc_disable(qcom->icc_path_ddr);
 217
 218         return ret;
 219 }
 220
 221 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
 222 {
 223         int ret;
 224
 225         ret = icc_disable(qcom->icc_path_ddr);
 226         if (ret)
 227                 return ret;
 228
 229         ret = icc_disable(qcom->icc_path_apps);
 230         if (ret)
 231                 icc_enable(qcom->icc_path_ddr);
 232
 233         return ret;
 234 }
 235
 236 /**
 237  * dwc3_qcom_interconnect_init() - Get interconnect path handles
 238  * and set bandwidhth.
 239  * @qcom:                       Pointer to the concerned usb core.
 240  *
 241  */
 242 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
 243 {
 244         struct device *dev = qcom->dev;
 245         int ret;
 246
 247         if (has_acpi_companion(dev))
 248                 return 0;
 249
 250         qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
 251         if (IS_ERR(qcom->icc_path_ddr)) {
 252                 dev_err(dev, "failed to get usb-ddr path: %ld\n",
 253                         PTR_ERR(qcom->icc_path_ddr));
 254                 return PTR_ERR(qcom->icc_path_ddr);
 255         }
 256
 257         qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
 258         if (IS_ERR(qcom->icc_path_apps)) {
 259                 dev_err(dev, "failed to get apps-usb path: %ld\n",
 260                                 PTR_ERR(qcom->icc_path_apps));
 261                 return PTR_ERR(qcom->icc_path_apps);
 262         }
 263
 264         if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
 265                         usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
 266                 ret = icc_set_bw(qcom->icc_path_ddr,
 267                         USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
 268         else
 269                 ret = icc_set_bw(qcom->icc_path_ddr,
 270                         USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
 271
 272         if (ret) {
 273                 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
 274                 return ret;
 275         }
 276
 277         ret = icc_set_bw(qcom->icc_path_apps,
 278                 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
 279         if (ret) {
 280                 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
 281                 return ret;
 282         }
 283
 284         return 0;
 285 }
 286
 287 /**
 288  * dwc3_qcom_interconnect_exit() - Release interconnect path handles
 289  * @qcom:                       Pointer to the concerned usb core.
 290  *
 291  * This function is used to release interconnect path handle.
 292  */
 293 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
 294 {
 295         icc_put(qcom->icc_path_ddr);
 296         icc_put(qcom->icc_path_apps);
 297 }
 298
 299 /* Only usable in contexts where the role can not change. */
 300 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
 301 {
 302         struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
 303
 304         return dwc->xhci;
 305 }
 306
 307 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 308 {
 309         if (qcom->hs_phy_irq) {
 310                 disable_irq_wake(qcom->hs_phy_irq);
 311                 disable_irq_nosync(qcom->hs_phy_irq);
 312         }
 313
 314         if (qcom->dp_hs_phy_irq) {
 315                 disable_irq_wake(qcom->dp_hs_phy_irq);
 316                 disable_irq_nosync(qcom->dp_hs_phy_irq);
 317         }
 318
 319         if (qcom->dm_hs_phy_irq) {
 320                 disable_irq_wake(qcom->dm_hs_phy_irq);
 321                 disable_irq_nosync(qcom->dm_hs_phy_irq);
 322         }
 323
 324         if (qcom->ss_phy_irq) {
 325                 disable_irq_wake(qcom->ss_phy_irq);
 326                 disable_irq_nosync(qcom->ss_phy_irq);
 327         }
 328 }
 329
 330 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 331 {
 332         if (qcom->hs_phy_irq) {
 333                 enable_irq(qcom->hs_phy_irq);
 334                 enable_irq_wake(qcom->hs_phy_irq);
 335         }
 336
 337         if (qcom->dp_hs_phy_irq) {
 338                 enable_irq(qcom->dp_hs_phy_irq);
 339                 enable_irq_wake(qcom->dp_hs_phy_irq);
 340         }
 341
 342         if (qcom->dm_hs_phy_irq) {
 343                 enable_irq(qcom->dm_hs_phy_irq);
 344                 enable_irq_wake(qcom->dm_hs_phy_irq);
 345         }
 346
 347         if (qcom->ss_phy_irq) {
 348                 enable_irq(qcom->ss_phy_irq);
 349                 enable_irq_wake(qcom->ss_phy_irq);
 350         }
 351 }
 352
 353 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
 354 {
 355         u32 val;
 356         int i, ret;
 357
 358         if (qcom->is_suspended)
 359                 return 0;
 360
 361         val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
 362         if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
 363                 dev_err(qcom->dev, "HS-PHY not in L2\n");
 364
 365         for (i = qcom->num_clocks - 1; i >= 0; i--)
 366                 clk_disable_unprepare(qcom->clks[i]);
 367
 368         ret = dwc3_qcom_interconnect_disable(qcom);
 369         if (ret)
 370                 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
 371
 372         if (device_may_wakeup(qcom->dev))
 373                 dwc3_qcom_enable_interrupts(qcom);
 374
 375         qcom->is_suspended = true;
 376
 377         return 0;
 378 }
 379
 380 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
 381 {
 382         int ret;
 383         int i;
 384
 385         if (!qcom->is_suspended)
 386                 return 0;
 387
 388         if (device_may_wakeup(qcom->dev))
 389                 dwc3_qcom_disable_interrupts(qcom);
 390
 391         for (i = 0; i < qcom->num_clocks; i++) {
 392                 ret = clk_prepare_enable(qcom->clks[i]);
 393                 if (ret < 0) {
 394                         while (--i >= 0)
 395                                 clk_disable_unprepare(qcom->clks[i]);
 396                         return ret;
 397                 }
 398         }
 399
 400         ret = dwc3_qcom_interconnect_enable(qcom);
 401         if (ret)
 402                 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
 403
 404         /* Clear existing events from PHY related to L2 in/out */
 405         dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
 406                           PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
 407
 408         qcom->is_suspended = false;
 409
 410         return 0;
 411 }
 412
 413 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
 414 {
 415         struct dwc3_qcom *qcom = data;
 416         struct dwc3     *dwc = platform_get_drvdata(qcom->dwc3);
 417
 418         /* If pm_suspended then let pm_resume take care of resuming h/w */
 419         if (qcom->pm_suspended)
 420                 return IRQ_HANDLED;
 421
 422         /*
 423          * This is safe as role switching is done from a freezable workqueue
 424          * and the wakeup interrupts are disabled as part of resume.
 425          */
 426         if (dwc3_qcom_is_host(qcom))
 427                 pm_runtime_resume(&dwc->xhci->dev);
 428
 429         return IRQ_HANDLED;
 430 }
 431
 432 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
 433 {
 434         /* Configure dwc3 to use UTMI clock as PIPE clock not present */
 435         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 436                           PIPE_UTMI_CLK_DIS);
 437
 438         usleep_range(100, 1000);
 439
 440         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 441                           PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 442
 443         usleep_range(100, 1000);
 444
 445         dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 446                           PIPE_UTMI_CLK_DIS);
 447 }
 448
 449 static int dwc3_qcom_get_irq(struct platform_device *pdev,
 450                              const char *name, int num)
 451 {
 452         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 453         struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
 454         struct device_node *np = pdev->dev.of_node;
 455         int ret;
 456
 457         if (np)
 458                 ret = platform_get_irq_byname_optional(pdev_irq, name);
 459         else
 460                 ret = platform_get_irq_optional(pdev_irq, num);
 461
 462         return ret;
 463 }
 464
 465 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
 466 {
 467         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 468         const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
 469         int irq;
 470         int ret;
 471
 472         irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
 473                                 pdata ? pdata->hs_phy_irq_index : -1);
 474         if (irq > 0) {
 475                 /* Keep wakeup interrupts disabled until suspend */
 476                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 477                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 478                                         qcom_dwc3_resume_irq,
 479                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 480                                         "qcom_dwc3 HS", qcom);
 481                 if (ret) {
 482                         dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
 483                         return ret;
 484                 }
 485                 qcom->hs_phy_irq = irq;
 486         }
 487
 488         irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
 489                                 pdata ? pdata->dp_hs_phy_irq_index : -1);
 490         if (irq > 0) {
 491                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 492                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 493                                         qcom_dwc3_resume_irq,
 494                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 495                                         "qcom_dwc3 DP_HS", qcom);
 496                 if (ret) {
 497                         dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
 498                         return ret;
 499                 }
 500                 qcom->dp_hs_phy_irq = irq;
 501         }
 502
 503         irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
 504                                 pdata ? pdata->dm_hs_phy_irq_index : -1);
 505         if (irq > 0) {
 506                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 507                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 508                                         qcom_dwc3_resume_irq,
 509                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 510                                         "qcom_dwc3 DM_HS", qcom);
 511                 if (ret) {
 512                         dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
 513                         return ret;
 514                 }
 515                 qcom->dm_hs_phy_irq = irq;
 516         }
 517
 518         irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
 519                                 pdata ? pdata->ss_phy_irq_index : -1);
 520         if (irq > 0) {
 521                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 522                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 523                                         qcom_dwc3_resume_irq,
 524                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 525                                         "qcom_dwc3 SS", qcom);
 526                 if (ret) {
 527                         dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
 528                         return ret;
 529                 }
 530                 qcom->ss_phy_irq = irq;
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
 537 {
 538         struct device           *dev = qcom->dev;
 539         struct device_node      *np = dev->of_node;
 540         int                     i;
 541
 542         if (!np || !count)
 543                 return 0;
 544
 545         if (count < 0)
 546                 return count;
 547
 548         qcom->num_clocks = count;
 549
 550         qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
 551                                   sizeof(struct clk *), GFP_KERNEL);
 552         if (!qcom->clks)
 553                 return -ENOMEM;
 554
 555         for (i = 0; i < qcom->num_clocks; i++) {
 556                 struct clk      *clk;
 557                 int             ret;
 558
 559                 clk = of_clk_get(np, i);
 560                 if (IS_ERR(clk)) {
 561                         while (--i >= 0)
 562                                 clk_put(qcom->clks[i]);
 563                         return PTR_ERR(clk);
 564                 }
 565
 566                 ret = clk_prepare_enable(clk);
 567                 if (ret < 0) {
 568                         while (--i >= 0) {
 569                                 clk_disable_unprepare(qcom->clks[i]);
 570                                 clk_put(qcom->clks[i]);
 571                         }
 572                         clk_put(clk);
 573
 574                         return ret;
 575                 }
 576
 577                 qcom->clks[i] = clk;
 578         }
 579
 580         return 0;
 581 }
 582
 583 static const struct property_entry dwc3_qcom_acpi_properties[] = {
 584         PROPERTY_ENTRY_STRING("dr_mode", "host"),
 585         {}
 586 };
 587
 588 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
 589 {
 590         struct dwc3_qcom        *qcom = platform_get_drvdata(pdev);
 591         struct device           *dev = &pdev->dev;
 592         struct resource         *res, *child_res = NULL;
 593         struct platform_device  *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
 594                                                             pdev;
 595         int                     irq;
 596         int                     ret;
 597
 598         qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 599         if (!qcom->dwc3)
 600                 return -ENOMEM;
 601
 602         qcom->dwc3->dev.parent = dev;
 603         qcom->dwc3->dev.type = dev->type;
 604         qcom->dwc3->dev.dma_mask = dev->dma_mask;
 605         qcom->dwc3->dev.dma_parms = dev->dma_parms;
 606         qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
 607
 608         child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
 609         if (!child_res)
 610                 return -ENOMEM;
 611
 612         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 613         if (!res) {
 614                 dev_err(&pdev->dev, "failed to get memory resource\n");
 615                 ret = -ENODEV;
 616                 goto out;
 617         }
 618
 619         child_res[0].flags = res->flags;
 620         child_res[0].start = res->start;
 621         child_res[0].end = child_res[0].start +
 622                 qcom->acpi_pdata->dwc3_core_base_size;
 623
 624         irq = platform_get_irq(pdev_irq, 0);
 625         if (irq < 0) {
 626                 ret = irq;
 627                 goto out;
 628         }
 629         child_res[1].flags = IORESOURCE_IRQ;
 630         child_res[1].start = child_res[1].end = irq;
 631
 632         ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
 633         if (ret) {
 634                 dev_err(&pdev->dev, "failed to add resources\n");
 635                 goto out;
 636         }
 637
 638         ret = platform_device_add_properties(qcom->dwc3,
 639                                              dwc3_qcom_acpi_properties);
 640         if (ret < 0) {
 641                 dev_err(&pdev->dev, "failed to add properties\n");
 642                 goto out;
 643         }
 644
 645         ret = platform_device_add(qcom->dwc3);
 646         if (ret)
 647                 dev_err(&pdev->dev, "failed to add device\n");
 648
 649 out:
 650         kfree(child_res);
 651         return ret;
 652 }
 653
 654 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
 655 {
 656         struct dwc3_qcom        *qcom = platform_get_drvdata(pdev);
 657         struct device_node      *np = pdev->dev.of_node, *dwc3_np;
 658         struct device           *dev = &pdev->dev;
 659         int                     ret;
 660
 661         dwc3_np = of_get_child_by_name(np, "dwc3");
 662         if (!dwc3_np) {
 663                 dev_err(dev, "failed to find dwc3 core child\n");
 664                 return -ENODEV;
 665         }
 666
 667         ret = of_platform_populate(np, NULL, NULL, dev);
 668         if (ret) {
 669                 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
 670                 goto node_put;
 671         }
 672
 673         qcom->dwc3 = of_find_device_by_node(dwc3_np);
 674         if (!qcom->dwc3) {
 675                 ret = -ENODEV;
 676                 dev_err(dev, "failed to get dwc3 platform device\n");
 677         }
 678
 679 node_put:
 680         of_node_put(dwc3_np);
 681
 682         return ret;
 683 }
 684
 685 static struct platform_device *
 686 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
 687 {
 688         struct fwnode_handle *fwh;
 689         struct acpi_device *adev;
 690         char name[8];
 691         int ret;
 692         int id;
 693
 694         /* Figure out device id */
 695         ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
 696         if (!ret)
 697                 return NULL;
 698
 699         /* Find the child using name */
 700         snprintf(name, sizeof(name), "USB%d", id);
 701         fwh = fwnode_get_named_child_node(dev->fwnode, name);
 702         if (!fwh)
 703                 return NULL;
 704
 705         adev = to_acpi_device_node(fwh);
 706         if (!adev)
 707                 return NULL;
 708
 709         return acpi_create_platform_device(adev, NULL);
 710 }
 711
 712 static int dwc3_qcom_probe(struct platform_device *pdev)
 713 {
 714         struct device_node      *np = pdev->dev.of_node;
 715         struct device           *dev = &pdev->dev;
 716         struct dwc3_qcom        *qcom;
 717         struct resource         *res, *parent_res = NULL;
 718         int                     ret, i;
 719         bool                    ignore_pipe_clk;
 720
 721         qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
 722         if (!qcom)
 723                 return -ENOMEM;
 724
 725         platform_set_drvdata(pdev, qcom);
 726         qcom->dev = &pdev->dev;
 727
 728         if (has_acpi_companion(dev)) {
 729                 qcom->acpi_pdata = acpi_device_get_match_data(dev);
 730                 if (!qcom->acpi_pdata) {
 731                         dev_err(&pdev->dev, "no supporting ACPI device data\n");
 732                         return -EINVAL;
 733                 }
 734         }
 735
 736         qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
 737         if (IS_ERR(qcom->resets)) {
 738                 ret = PTR_ERR(qcom->resets);
 739                 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
 740                 return ret;
 741         }
 742
 743         ret = reset_control_assert(qcom->resets);
 744         if (ret) {
 745                 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
 746                 return ret;
 747         }
 748
 749         usleep_range(10, 1000);
 750
 751         ret = reset_control_deassert(qcom->resets);
 752         if (ret) {
 753                 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
 754                 goto reset_assert;
 755         }
 756
 757         ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
 758         if (ret) {
 759                 dev_err(dev, "failed to get clocks\n");
 760                 goto reset_assert;
 761         }
 762
 763         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 764
 765         if (np) {
 766                 parent_res = res;
 767         } else {
 768                 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
 769                 if (!parent_res)
 770                         return -ENOMEM;
 771
 772                 parent_res->start = res->start +
 773                         qcom->acpi_pdata->qscratch_base_offset;
 774                 parent_res->end = parent_res->start +
 775                         qcom->acpi_pdata->qscratch_base_size;
 776
 777                 if (qcom->acpi_pdata->is_urs) {
 778                         qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
 779                         if (IS_ERR_OR_NULL(qcom->urs_usb)) {
 780                                 dev_err(dev, "failed to create URS USB platdev\n");
 781                                 if (!qcom->urs_usb)
 782                                         return -ENODEV;
 783                                 else
 784                                         return PTR_ERR(qcom->urs_usb);
 785                         }
 786                 }
 787         }
 788
 789         qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
 790         if (IS_ERR(qcom->qscratch_base)) {
 791                 dev_err(dev, "failed to map qscratch, err=%d\n", ret);
 792                 ret = PTR_ERR(qcom->qscratch_base);
 793                 goto clk_disable;
 794         }
 795
 796         ret = dwc3_qcom_setup_irq(pdev);
 797         if (ret) {
 798                 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
 799                 goto clk_disable;
 800         }
 801
 802         /*
 803          * Disable pipe_clk requirement if specified. Used when dwc3
 804          * operates without SSPHY and only HS/FS/LS modes are supported.
 805          */
 806         ignore_pipe_clk = device_property_read_bool(dev,
 807                                 "qcom,select-utmi-as-pipe-clk");
 808         if (ignore_pipe_clk)
 809                 dwc3_qcom_select_utmi_clk(qcom);
 810
 811         if (np)
 812                 ret = dwc3_qcom_of_register_core(pdev);
 813         else
 814                 ret = dwc3_qcom_acpi_register_core(pdev);
 815
 816         if (ret) {
 817                 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
 818                 goto depopulate;
 819         }
 820
 821         ret = dwc3_qcom_interconnect_init(qcom);
 822         if (ret)
 823                 goto depopulate;
 824
 825         qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
 826
 827         /* enable vbus override for device mode */
 828         if (qcom->mode == USB_DR_MODE_PERIPHERAL)
 829                 dwc3_qcom_vbus_overrride_enable(qcom, true);
 830
 831         /* register extcon to override sw_vbus on Vbus change later */
 832         ret = dwc3_qcom_register_extcon(qcom);
 833         if (ret)
 834                 goto interconnect_exit;
 835
 836         device_init_wakeup(&pdev->dev, 1);
 837         qcom->is_suspended = false;
 838         pm_runtime_set_active(dev);
 839         pm_runtime_enable(dev);
 840         pm_runtime_forbid(dev);
 841
 842         return 0;
 843
 844 interconnect_exit:
 845         dwc3_qcom_interconnect_exit(qcom);
 846 depopulate:
 847         if (np)
 848                 of_platform_depopulate(&pdev->dev);
 849         else
 850                 platform_device_put(pdev);
 851 clk_disable:
 852         for (i = qcom->num_clocks - 1; i >= 0; i--) {
 853                 clk_disable_unprepare(qcom->clks[i]);
 854                 clk_put(qcom->clks[i]);
 855         }
 856 reset_assert:
 857         reset_control_assert(qcom->resets);
 858
 859         return ret;
 860 }
 861
 862 static int dwc3_qcom_remove(struct platform_device *pdev)
 863 {
 864         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 865         struct device *dev = &pdev->dev;
 866         int i;
 867
 868         of_platform_depopulate(dev);
 869
 870         for (i = qcom->num_clocks - 1; i >= 0; i--) {
 871                 clk_disable_unprepare(qcom->clks[i]);
 872                 clk_put(qcom->clks[i]);
 873         }
 874         qcom->num_clocks = 0;
 875
 876         dwc3_qcom_interconnect_exit(qcom);
 877         reset_control_assert(qcom->resets);
 878
 879         pm_runtime_allow(dev);
 880         pm_runtime_disable(dev);
 881
 882         return 0;
 883 }
 884
 885 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
 886 {
 887         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 888         int ret = 0;
 889
 890         ret = dwc3_qcom_suspend(qcom);
 891         if (!ret)
 892                 qcom->pm_suspended = true;
 893
 894         return ret;
 895 }
 896
 897 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
 898 {
 899         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 900         int ret;
 901
 902         ret = dwc3_qcom_resume(qcom);
 903         if (!ret)
 904                 qcom->pm_suspended = false;
 905
 906         return ret;
 907 }
 908
 909 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
 910 {
 911         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 912
 913         return dwc3_qcom_suspend(qcom);
 914 }
 915
 916 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
 917 {
 918         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 919
 920         return dwc3_qcom_resume(qcom);
 921 }
 922
 923 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
 924         SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
 925         SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
 926                            NULL)
 927 };
 928
 929 static const struct of_device_id dwc3_qcom_of_match[] = {
 930         { .compatible = "qcom,dwc3" },
 931         { .compatible = "qcom,msm8996-dwc3" },
 932         { .compatible = "qcom,msm8998-dwc3" },
 933         { .compatible = "qcom,sdm845-dwc3" },
 934         { }
 935 };
 936 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
 937
 938 #ifdef CONFIG_ACPI
 939 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
 940         .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
 941         .qscratch_base_size = SDM845_QSCRATCH_SIZE,
 942         .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
 943         .hs_phy_irq_index = 1,
 944         .dp_hs_phy_irq_index = 4,
 945         .dm_hs_phy_irq_index = 3,
 946         .ss_phy_irq_index = 2
 947 };
 948
 949 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
 950         .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
 951         .qscratch_base_size = SDM845_QSCRATCH_SIZE,
 952         .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
 953         .hs_phy_irq_index = 1,
 954         .dp_hs_phy_irq_index = 4,
 955         .dm_hs_phy_irq_index = 3,
 956         .ss_phy_irq_index = 2,
 957         .is_urs = true,
 958 };
 959
 960 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
 961         { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
 962         { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
 963         { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
 964         { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
 965         { },
 966 };
 967 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
 968 #endif
 969
 970 static struct platform_driver dwc3_qcom_driver = {
 971         .probe          = dwc3_qcom_probe,
 972         .remove         = dwc3_qcom_remove,
 973         .driver         = {
 974                 .name   = "dwc3-qcom",
 975                 .pm     = &dwc3_qcom_dev_pm_ops,
 976                 .of_match_table = dwc3_qcom_of_match,
 977                 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
 978         },
 979 };
 980
 981 module_platform_driver(dwc3_qcom_driver);
 982
 983 MODULE_LICENSE("GPL v2");
 984 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");