drivers/usb/dwc3/dwc3-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * dwc3-pci.c - PCI Specific glue layer
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/slab.h>
  14 #include <linux/pci.h>
  15 #include <linux/workqueue.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/gpio/consumer.h>
  19 #include <linux/gpio/machine.h>
  20 #include <linux/acpi.h>
  21 #include <linux/delay.h>
  22
  23 #define PCI_DEVICE_ID_INTEL_BYT                 0x0f37
  24 #define PCI_DEVICE_ID_INTEL_MRFLD               0x119e
  25 #define PCI_DEVICE_ID_INTEL_BSW                 0x22b7
  26 #define PCI_DEVICE_ID_INTEL_SPTLP               0x9d30
  27 #define PCI_DEVICE_ID_INTEL_SPTH                0xa130
  28 #define PCI_DEVICE_ID_INTEL_BXT                 0x0aaa
  29 #define PCI_DEVICE_ID_INTEL_BXT_M               0x1aaa
  30 #define PCI_DEVICE_ID_INTEL_APL                 0x5aaa
  31 #define PCI_DEVICE_ID_INTEL_KBP                 0xa2b0
  32 #define PCI_DEVICE_ID_INTEL_CMLLP               0x02ee
  33 #define PCI_DEVICE_ID_INTEL_CMLH                0x06ee
  34 #define PCI_DEVICE_ID_INTEL_GLK                 0x31aa
  35 #define PCI_DEVICE_ID_INTEL_CNPLP               0x9dee
  36 #define PCI_DEVICE_ID_INTEL_CNPH                0xa36e
  37 #define PCI_DEVICE_ID_INTEL_CNPV                0xa3b0
  38 #define PCI_DEVICE_ID_INTEL_ICLLP               0x34ee
  39
  40 #define PCI_INTEL_BXT_DSM_GUID          "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
  41 #define PCI_INTEL_BXT_FUNC_PMU_PWR      4
  42 #define PCI_INTEL_BXT_STATE_D0          0
  43 #define PCI_INTEL_BXT_STATE_D3          3
  44
  45 #define GP_RWBAR                        1
  46 #define GP_RWREG1                       0xa0
  47 #define GP_RWREG1_ULPI_REFCLK_DISABLE   (1 << 17)
  48
  49 /**
  50  * struct dwc3_pci - Driver private structure
  51  * @dwc3: child dwc3 platform_device
  52  * @pci: our link to PCI bus
  53  * @guid: _DSM GUID
  54  * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
  55  * @wakeup_work: work for asynchronous resume
  56  */
  57 struct dwc3_pci {
  58         struct platform_device *dwc3;
  59         struct pci_dev *pci;
  60
  61         guid_t guid;
  62
  63         unsigned int has_dsm_for_pm:1;
  64         struct work_struct wakeup_work;
  65 };
  66
  67 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  68 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  69
  70 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  71         { "reset-gpios", &reset_gpios, 1 },
  72         { "cs-gpios", &cs_gpios, 1 },
  73         { },
  74 };
  75
  76 static struct gpiod_lookup_table platform_bytcr_gpios = {
  77         .dev_id         = "0000:00:16.0",
  78         .table          = {
  79                 GPIO_LOOKUP("INT33FC:00", 54, "cs", GPIO_ACTIVE_HIGH),
  80                 GPIO_LOOKUP("INT33FC:02", 14, "reset", GPIO_ACTIVE_HIGH),
  81                 {}
  82         },
  83 };
  84
  85 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
  86 {
  87         void __iomem    *reg;
  88         u32             value;
  89
  90         reg = pcim_iomap(pci, GP_RWBAR, 0);
  91         if (!reg)
  92                 return -ENOMEM;
  93
  94         value = readl(reg + GP_RWREG1);
  95         if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
  96                 goto unmap; /* ULPI refclk already enabled */
  97
  98         value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
  99         writel(value, reg + GP_RWREG1);
 100         /* This comes from the Intel Android x86 tree w/o any explanation */
 101         msleep(100);
 102 unmap:
 103         pcim_iounmap(pci, reg);
 104         return 0;
 105 }
 106
 107 static const struct property_entry dwc3_pci_intel_properties[] = {
 108         PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
 109         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 110         {}
 111 };
 112
 113 static const struct property_entry dwc3_pci_mrfld_properties[] = {
 114         PROPERTY_ENTRY_STRING("dr_mode", "otg"),
 115         PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
 116         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 117         {}
 118 };
 119
 120 static const struct property_entry dwc3_pci_amd_properties[] = {
 121         PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
 122         PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
 123         PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
 124         PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
 125         PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
 126         PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
 127         PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
 128         PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
 129         PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
 130         PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
 131         PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
 132         /* FIXME these quirks should be removed when AMD NL tapes out */
 133         PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
 134         PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
 135         PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
 136         PROPERTY_ENTRY_BOOL("snps,usb2-gadget-lpm-disable"),
 137         PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
 138         {}
 139 };
 140
 141 static int dwc3_pci_quirks(struct dwc3_pci *dwc)
 142 {
 143         struct pci_dev                  *pdev = dwc->pci;
 144
 145         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 146                 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
 147                                 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
 148                         guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
 149                         dwc->has_dsm_for_pm = true;
 150                 }
 151
 152                 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
 153                         struct gpio_desc *gpio;
 154                         int ret;
 155
 156                         /* On BYT the FW does not always enable the refclock */
 157                         ret = dwc3_byt_enable_ulpi_refclock(pdev);
 158                         if (ret)
 159                                 return ret;
 160
 161                         ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
 162                                         acpi_dwc3_byt_gpios);
 163                         if (ret)
 164                                 dev_dbg(&pdev->dev, "failed to add mapping table\n");
 165
 166                         /*
 167                          * A lot of BYT devices lack ACPI resource entries for
 168                          * the GPIOs, add a fallback mapping to the reference
 169                          * design GPIOs which all boards seem to use.
 170                          */
 171                         gpiod_add_lookup_table(&platform_bytcr_gpios);
 172
 173                         /*
 174                          * These GPIOs will turn on the USB2 PHY. Note that we have to
 175                          * put the gpio descriptors again here because the phy driver
 176                          * might want to grab them, too.
 177                          */
 178                         gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
 179                         if (IS_ERR(gpio))
 180                                 return PTR_ERR(gpio);
 181
 182                         gpiod_set_value_cansleep(gpio, 1);
 183                         gpiod_put(gpio);
 184
 185                         gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
 186                         if (IS_ERR(gpio))
 187                                 return PTR_ERR(gpio);
 188
 189                         if (gpio) {
 190                                 gpiod_set_value_cansleep(gpio, 1);
 191                                 gpiod_put(gpio);
 192                                 usleep_range(10000, 11000);
 193                         }
 194                 }
 195         }
 196
 197         return 0;
 198 }
 199
 200 #ifdef CONFIG_PM
 201 static void dwc3_pci_resume_work(struct work_struct *work)
 202 {
 203         struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
 204         struct platform_device *dwc3 = dwc->dwc3;
 205         int ret;
 206
 207         ret = pm_runtime_get_sync(&dwc3->dev);
 208         if (ret) {
 209                 pm_runtime_put_sync_autosuspend(&dwc3->dev);
 210                 return;
 211         }
 212
 213         pm_runtime_mark_last_busy(&dwc3->dev);
 214         pm_runtime_put_sync_autosuspend(&dwc3->dev);
 215 }
 216 #endif
 217
 218 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
 219 {
 220         struct property_entry *p = (struct property_entry *)id->driver_data;
 221         struct dwc3_pci         *dwc;
 222         struct resource         res[2];
 223         int                     ret;
 224         struct device           *dev = &pci->dev;
 225
 226         ret = pcim_enable_device(pci);
 227         if (ret) {
 228                 dev_err(dev, "failed to enable pci device\n");
 229                 return -ENODEV;
 230         }
 231
 232         pci_set_master(pci);
 233
 234         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
 235         if (!dwc)
 236                 return -ENOMEM;
 237
 238         dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
 239         if (!dwc->dwc3)
 240                 return -ENOMEM;
 241
 242         memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
 243
 244         res[0].start    = pci_resource_start(pci, 0);
 245         res[0].end      = pci_resource_end(pci, 0);
 246         res[0].name     = "dwc_usb3";
 247         res[0].flags    = IORESOURCE_MEM;
 248
 249         res[1].start    = pci->irq;
 250         res[1].name     = "dwc_usb3";
 251         res[1].flags    = IORESOURCE_IRQ;
 252
 253         ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
 254         if (ret) {
 255                 dev_err(dev, "couldn't add resources to dwc3 device\n");
 256                 goto err;
 257         }
 258
 259         dwc->pci = pci;
 260         dwc->dwc3->dev.parent = dev;
 261         ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
 262
 263         ret = platform_device_add_properties(dwc->dwc3, p);
 264         if (ret < 0)
 265                 goto err;
 266
 267         ret = dwc3_pci_quirks(dwc);
 268         if (ret)
 269                 goto err;
 270
 271         ret = platform_device_add(dwc->dwc3);
 272         if (ret) {
 273                 dev_err(dev, "failed to register dwc3 device\n");
 274                 goto err;
 275         }
 276
 277         device_init_wakeup(dev, true);
 278         pci_set_drvdata(pci, dwc);
 279         pm_runtime_put(dev);
 280 #ifdef CONFIG_PM
 281         INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
 282 #endif
 283
 284         return 0;
 285 err:
 286         platform_device_put(dwc->dwc3);
 287         return ret;
 288 }
 289
 290 static void dwc3_pci_remove(struct pci_dev *pci)
 291 {
 292         struct dwc3_pci         *dwc = pci_get_drvdata(pci);
 293         struct pci_dev          *pdev = dwc->pci;
 294
 295         if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
 296                 gpiod_remove_lookup_table(&platform_bytcr_gpios);
 297 #ifdef CONFIG_PM
 298         cancel_work_sync(&dwc->wakeup_work);
 299 #endif
 300         device_init_wakeup(&pci->dev, false);
 301         pm_runtime_get(&pci->dev);
 302         platform_device_unregister(dwc->dwc3);
 303 }
 304
 305 static const struct pci_device_id dwc3_pci_id_table[] = {
 306         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
 307           (kernel_ulong_t) &dwc3_pci_intel_properties },
 308
 309         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
 310           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 311
 312         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
 313           (kernel_ulong_t) &dwc3_pci_mrfld_properties, },
 314
 315         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
 316           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 317
 318         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
 319           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 320
 321         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
 322           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 323
 324         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
 325           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 326
 327         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
 328           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 329
 330         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
 331           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 332
 333         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
 334           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 335
 336         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
 337           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 338
 339         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
 340           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 341
 342         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
 343           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 344
 345         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
 346           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 347
 348         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
 349           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 350
 351         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
 352           (kernel_ulong_t) &dwc3_pci_intel_properties, },
 353
 354         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
 355           (kernel_ulong_t) &dwc3_pci_amd_properties, },
 356         {  }    /* Terminating Entry */
 357 };
 358 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
 359
 360 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
 361 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
 362 {
 363         union acpi_object *obj;
 364         union acpi_object tmp;
 365         union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
 366
 367         if (!dwc->has_dsm_for_pm)
 368                 return 0;
 369
 370         tmp.type = ACPI_TYPE_INTEGER;
 371         tmp.integer.value = param;
 372
 373         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
 374                         1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
 375         if (!obj) {
 376                 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
 377                 return -EIO;
 378         }
 379
 380         ACPI_FREE(obj);
 381
 382         return 0;
 383 }
 384 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
 385
 386 #ifdef CONFIG_PM
 387 static int dwc3_pci_runtime_suspend(struct device *dev)
 388 {
 389         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 390
 391         if (device_can_wakeup(dev))
 392                 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 393
 394         return -EBUSY;
 395 }
 396
 397 static int dwc3_pci_runtime_resume(struct device *dev)
 398 {
 399         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 400         int                     ret;
 401
 402         ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 403         if (ret)
 404                 return ret;
 405
 406         queue_work(pm_wq, &dwc->wakeup_work);
 407
 408         return 0;
 409 }
 410 #endif /* CONFIG_PM */
 411
 412 #ifdef CONFIG_PM_SLEEP
 413 static int dwc3_pci_suspend(struct device *dev)
 414 {
 415         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 416
 417         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
 418 }
 419
 420 static int dwc3_pci_resume(struct device *dev)
 421 {
 422         struct dwc3_pci         *dwc = dev_get_drvdata(dev);
 423
 424         return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
 425 }
 426 #endif /* CONFIG_PM_SLEEP */
 427
 428 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
 429         SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
 430         SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
 431                 NULL)
 432 };
 433
 434 static struct pci_driver dwc3_pci_driver = {
 435         .name           = "dwc3-pci",
 436         .id_table       = dwc3_pci_id_table,
 437         .probe          = dwc3_pci_probe,
 438         .remove         = dwc3_pci_remove,
 439         .driver         = {
 440                 .pm     = &dwc3_pci_dev_pm_ops,
 441         }
 442 };
 443
 444 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
 445 MODULE_LICENSE("GPL v2");
 446 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
 447
 448 module_pci_driver(dwc3_pci_driver);