1 // SPDX-License-Identifier: GPL-2.0
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/ioport.h>
17 #include <linux/list.h>
18 #include <linux/bitops.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/wait.h>
23 #include <linux/workqueue.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27 #include <linux/usb/otg.h>
28 #include <linux/ulpi/interface.h>
30 #include <linux/phy/phy.h>
32 #define DWC3_MSG_MAX 500
34 /* Global constants */
35 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
36 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
37 #define DWC3_EP0_SETUP_SIZE 512
38 #define DWC3_ENDPOINTS_NUM 32
39 #define DWC3_XHCI_RESOURCES_NUM 2
41 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
42 #define DWC3_EVENT_BUFFERS_SIZE 4096
43 #define DWC3_EVENT_TYPE_MASK 0xfe
45 #define DWC3_EVENT_TYPE_DEV 0
46 #define DWC3_EVENT_TYPE_CARKIT 3
47 #define DWC3_EVENT_TYPE_I2C 4
49 #define DWC3_DEVICE_EVENT_DISCONNECT 0
50 #define DWC3_DEVICE_EVENT_RESET 1
51 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
52 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
53 #define DWC3_DEVICE_EVENT_WAKEUP 4
54 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
55 #define DWC3_DEVICE_EVENT_EOPF 6
56 #define DWC3_DEVICE_EVENT_SOF 7
57 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
58 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
59 #define DWC3_DEVICE_EVENT_OVERFLOW 11
61 /* Controller's role while using the OTG block */
62 #define DWC3_OTG_ROLE_IDLE 0
63 #define DWC3_OTG_ROLE_HOST 1
64 #define DWC3_OTG_ROLE_DEVICE 2
66 #define DWC3_GEVNTCOUNT_MASK 0xfffc
67 #define DWC3_GEVNTCOUNT_EHB BIT(31)
68 #define DWC3_GSNPSID_MASK 0xffff0000
69 #define DWC3_GSNPSREV_MASK 0xffff
71 /* DWC3 registers memory space boundries */
72 #define DWC3_XHCI_REGS_START 0x0
73 #define DWC3_XHCI_REGS_END 0x7fff
74 #define DWC3_GLOBALS_REGS_START 0xc100
75 #define DWC3_GLOBALS_REGS_END 0xc6ff
76 #define DWC3_DEVICE_REGS_START 0xc700
77 #define DWC3_DEVICE_REGS_END 0xcbff
78 #define DWC3_OTG_REGS_START 0xcc00
79 #define DWC3_OTG_REGS_END 0xccff
81 /* Global Registers */
82 #define DWC3_GSBUSCFG0 0xc100
83 #define DWC3_GSBUSCFG1 0xc104
84 #define DWC3_GTXTHRCFG 0xc108
85 #define DWC3_GRXTHRCFG 0xc10c
86 #define DWC3_GCTL 0xc110
87 #define DWC3_GEVTEN 0xc114
88 #define DWC3_GSTS 0xc118
89 #define DWC3_GUCTL1 0xc11c
90 #define DWC3_GSNPSID 0xc120
91 #define DWC3_GGPIO 0xc124
92 #define DWC3_GUID 0xc128
93 #define DWC3_GUCTL 0xc12c
94 #define DWC3_GBUSERRADDR0 0xc130
95 #define DWC3_GBUSERRADDR1 0xc134
96 #define DWC3_GPRTBIMAP0 0xc138
97 #define DWC3_GPRTBIMAP1 0xc13c
98 #define DWC3_GHWPARAMS0 0xc140
99 #define DWC3_GHWPARAMS1 0xc144
100 #define DWC3_GHWPARAMS2 0xc148
101 #define DWC3_GHWPARAMS3 0xc14c
102 #define DWC3_GHWPARAMS4 0xc150
103 #define DWC3_GHWPARAMS5 0xc154
104 #define DWC3_GHWPARAMS6 0xc158
105 #define DWC3_GHWPARAMS7 0xc15c
106 #define DWC3_GDBGFIFOSPACE 0xc160
107 #define DWC3_GDBGLTSSM 0xc164
108 #define DWC3_GDBGBMU 0xc16c
109 #define DWC3_GDBGLSPMUX 0xc170
110 #define DWC3_GDBGLSP 0xc174
111 #define DWC3_GDBGEPINFO0 0xc178
112 #define DWC3_GDBGEPINFO1 0xc17c
113 #define DWC3_GPRTBIMAP_HS0 0xc180
114 #define DWC3_GPRTBIMAP_HS1 0xc184
115 #define DWC3_GPRTBIMAP_FS0 0xc188
116 #define DWC3_GPRTBIMAP_FS1 0xc18c
117 #define DWC3_GUCTL2 0xc19c
119 #define DWC3_VER_NUMBER 0xc1a0
120 #define DWC3_VER_TYPE 0xc1a4
122 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
123 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
125 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
127 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
129 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
130 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
132 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
133 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
134 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
135 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
137 #define DWC3_GHWPARAMS8 0xc600
138 #define DWC3_GFLADJ 0xc630
140 /* Device Registers */
141 #define DWC3_DCFG 0xc700
142 #define DWC3_DCTL 0xc704
143 #define DWC3_DEVTEN 0xc708
144 #define DWC3_DSTS 0xc70c
145 #define DWC3_DGCMDPAR 0xc710
146 #define DWC3_DGCMD 0xc714
147 #define DWC3_DALEPENA 0xc720
149 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
150 #define DWC3_DEPCMDPAR2 0x00
151 #define DWC3_DEPCMDPAR1 0x04
152 #define DWC3_DEPCMDPAR0 0x08
153 #define DWC3_DEPCMD 0x0c
155 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
158 #define DWC3_OCFG 0xcc00
159 #define DWC3_OCTL 0xcc04
160 #define DWC3_OEVT 0xcc08
161 #define DWC3_OEVTEN 0xcc0C
162 #define DWC3_OSTS 0xcc10
166 /* Global SoC Bus Configuration INCRx Register 0 */
167 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
168 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
169 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
170 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
171 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
172 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
173 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
174 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
175 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
177 /* Global Debug Queue/FIFO Space Available Register */
178 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
179 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
180 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
182 #define DWC3_TXFIFOQ 0
183 #define DWC3_RXFIFOQ 1
184 #define DWC3_TXREQQ 2
185 #define DWC3_RXREQQ 3
186 #define DWC3_RXINFOQ 4
187 #define DWC3_PSTATQ 5
188 #define DWC3_DESCFETCHQ 6
189 #define DWC3_EVENTQ 7
190 #define DWC3_AUXEVENTQ 8
192 /* Global RX Threshold Configuration Register */
193 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
194 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
195 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
197 /* Global RX Threshold Configuration Register for DWC_usb31 only */
198 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
199 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
200 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
201 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
202 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
203 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
204 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
205 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
207 /* Global TX Threshold Configuration Register for DWC_usb31 only */
208 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
209 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
210 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
211 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
212 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
213 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
214 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
215 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
217 /* Global Configuration Register */
218 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
219 #define DWC3_GCTL_U2RSTECN BIT(16)
220 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
221 #define DWC3_GCTL_CLK_BUS (0)
222 #define DWC3_GCTL_CLK_PIPE (1)
223 #define DWC3_GCTL_CLK_PIPEHALF (2)
224 #define DWC3_GCTL_CLK_MASK (3)
226 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
227 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
228 #define DWC3_GCTL_PRTCAP_HOST 1
229 #define DWC3_GCTL_PRTCAP_DEVICE 2
230 #define DWC3_GCTL_PRTCAP_OTG 3
232 #define DWC3_GCTL_CORESOFTRESET BIT(11)
233 #define DWC3_GCTL_SOFITPSYNC BIT(10)
234 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
235 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
236 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
237 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
238 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
239 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
241 /* Global User Control 1 Register */
242 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
243 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
244 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
246 /* Global Status Register */
247 #define DWC3_GSTS_OTG_IP BIT(10)
248 #define DWC3_GSTS_BC_IP BIT(9)
249 #define DWC3_GSTS_ADP_IP BIT(8)
250 #define DWC3_GSTS_HOST_IP BIT(7)
251 #define DWC3_GSTS_DEVICE_IP BIT(6)
252 #define DWC3_GSTS_CSR_TIMEOUT BIT(5)
253 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
255 /* Global USB2 PHY Configuration Register */
256 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
257 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
258 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
259 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
260 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
261 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
262 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
263 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
264 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
265 #define USBTRDTIM_UTMI_8_BIT 9
266 #define USBTRDTIM_UTMI_16_BIT 5
267 #define UTMI_PHYIF_16_BIT 1
268 #define UTMI_PHYIF_8_BIT 0
270 /* Global USB2 PHY Vendor Control Register */
271 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
272 #define DWC3_GUSB2PHYACC_DONE BIT(24)
273 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
274 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
275 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
276 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
277 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
279 /* Global USB3 PIPE Control Register */
280 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
281 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
282 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
283 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
284 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
285 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
286 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
287 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
288 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
289 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
290 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
291 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
292 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
293 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
295 /* Global TX Fifo Size Register */
296 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
297 #define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */
298 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
299 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
301 /* Global RX Fifo Size Register */
302 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
303 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
305 /* Global Event Size Registers */
306 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
307 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
309 /* Global HWPARAMS0 Register */
310 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
311 #define DWC3_GHWPARAMS0_MODE_GADGET 0
312 #define DWC3_GHWPARAMS0_MODE_HOST 1
313 #define DWC3_GHWPARAMS0_MODE_DRD 2
314 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
315 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
316 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
317 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
318 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
320 /* Global HWPARAMS1 Register */
321 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
322 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
323 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
324 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
325 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
326 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
328 /* Global HWPARAMS3 Register */
329 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
330 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
331 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
332 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
333 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
334 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
335 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
336 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
337 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
338 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
339 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
340 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
342 /* Global HWPARAMS4 Register */
343 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
344 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
346 /* Global HWPARAMS6 Register */
347 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
348 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
349 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
350 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
351 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
352 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
354 /* Global HWPARAMS7 Register */
355 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
356 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
358 /* Global Frame Length Adjustment Register */
359 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
360 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
362 /* Global User Control Register 2 */
363 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
365 /* Device Configuration Register */
366 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
367 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
369 #define DWC3_DCFG_SPEED_MASK (7 << 0)
370 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
371 #define DWC3_DCFG_SUPERSPEED (4 << 0)
372 #define DWC3_DCFG_HIGHSPEED (0 << 0)
373 #define DWC3_DCFG_FULLSPEED BIT(0)
374 #define DWC3_DCFG_LOWSPEED (2 << 0)
376 #define DWC3_DCFG_NUMP_SHIFT 17
377 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
378 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
379 #define DWC3_DCFG_LPM_CAP BIT(22)
381 /* Device Control Register */
382 #define DWC3_DCTL_RUN_STOP BIT(31)
383 #define DWC3_DCTL_CSFTRST BIT(30)
384 #define DWC3_DCTL_LSFTRST BIT(29)
386 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
387 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
389 #define DWC3_DCTL_APPL1RES BIT(23)
391 /* These apply for core versions 1.87a and earlier */
392 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
393 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
394 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
395 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
396 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
397 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
398 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
400 /* These apply for core versions 1.94a and later */
401 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
402 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
404 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
405 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
406 #define DWC3_DCTL_CRS BIT(17)
407 #define DWC3_DCTL_CSS BIT(16)
409 #define DWC3_DCTL_INITU2ENA BIT(12)
410 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
411 #define DWC3_DCTL_INITU1ENA BIT(10)
412 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
413 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
415 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
416 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
418 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
419 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
420 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
421 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
422 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
423 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
424 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
426 /* Device Event Enable Register */
427 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
428 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
429 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
430 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
431 #define DWC3_DEVTEN_SOFEN BIT(7)
432 #define DWC3_DEVTEN_EOPFEN BIT(6)
433 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
434 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
435 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
436 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
437 #define DWC3_DEVTEN_USBRSTEN BIT(1)
438 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
440 /* Device Status Register */
441 #define DWC3_DSTS_DCNRD BIT(29)
443 /* This applies for core versions 1.87a and earlier */
444 #define DWC3_DSTS_PWRUPREQ BIT(24)
446 /* These apply for core versions 1.94a and later */
447 #define DWC3_DSTS_RSS BIT(25)
448 #define DWC3_DSTS_SSS BIT(24)
450 #define DWC3_DSTS_COREIDLE BIT(23)
451 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
453 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
454 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
456 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
458 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
459 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
461 #define DWC3_DSTS_CONNECTSPD (7 << 0)
463 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
464 #define DWC3_DSTS_SUPERSPEED (4 << 0)
465 #define DWC3_DSTS_HIGHSPEED (0 << 0)
466 #define DWC3_DSTS_FULLSPEED BIT(0)
467 #define DWC3_DSTS_LOWSPEED (2 << 0)
469 /* Device Generic Command Register */
470 #define DWC3_DGCMD_SET_LMP 0x01
471 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
472 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
474 /* These apply for core versions 1.94a and later */
475 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
476 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
478 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
479 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
480 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
481 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
483 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
484 #define DWC3_DGCMD_CMDACT BIT(10)
485 #define DWC3_DGCMD_CMDIOC BIT(8)
487 /* Device Generic Command Parameter Register */
488 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
489 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
490 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
491 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
492 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
493 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
495 /* Device Endpoint Command Register */
496 #define DWC3_DEPCMD_PARAM_SHIFT 16
497 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
498 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
499 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
500 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
501 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
502 #define DWC3_DEPCMD_CMDACT BIT(10)
503 #define DWC3_DEPCMD_CMDIOC BIT(8)
505 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
506 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
507 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
508 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
509 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
510 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
511 /* This applies for core versions 1.90a and earlier */
512 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
513 /* This applies for core versions 1.94a and later */
514 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
515 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
516 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
518 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
520 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
521 #define DWC3_DALEPENA_EP(n) BIT(n)
523 #define DWC3_DEPCMD_TYPE_CONTROL 0
524 #define DWC3_DEPCMD_TYPE_ISOC 1
525 #define DWC3_DEPCMD_TYPE_BULK 2
526 #define DWC3_DEPCMD_TYPE_INTR 3
528 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
529 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
530 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
531 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
533 /* OTG Configuration Register */
534 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
535 #define DWC3_OCFG_HIBDISMASK BIT(4)
536 #define DWC3_OCFG_SFTRSTMASK BIT(3)
537 #define DWC3_OCFG_OTGVERSION BIT(2)
538 #define DWC3_OCFG_HNPCAP BIT(1)
539 #define DWC3_OCFG_SRPCAP BIT(0)
541 /* OTG CTL Register */
542 #define DWC3_OCTL_OTG3GOERR BIT(7)
543 #define DWC3_OCTL_PERIMODE BIT(6)
544 #define DWC3_OCTL_PRTPWRCTL BIT(5)
545 #define DWC3_OCTL_HNPREQ BIT(4)
546 #define DWC3_OCTL_SESREQ BIT(3)
547 #define DWC3_OCTL_TERMSELIDPULSE BIT(2)
548 #define DWC3_OCTL_DEVSETHNPEN BIT(1)
549 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
551 /* OTG Event Register */
552 #define DWC3_OEVT_DEVICEMODE BIT(31)
553 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
554 #define DWC3_OEVT_DEVRUNSTPSET BIT(26)
555 #define DWC3_OEVT_HIBENTRY BIT(25)
556 #define DWC3_OEVT_CONIDSTSCHNG BIT(24)
557 #define DWC3_OEVT_HRRCONFNOTIF BIT(23)
558 #define DWC3_OEVT_HRRINITNOTIF BIT(22)
559 #define DWC3_OEVT_ADEVIDLE BIT(21)
560 #define DWC3_OEVT_ADEVBHOSTEND BIT(20)
561 #define DWC3_OEVT_ADEVHOST BIT(19)
562 #define DWC3_OEVT_ADEVHNPCHNG BIT(18)
563 #define DWC3_OEVT_ADEVSRPDET BIT(17)
564 #define DWC3_OEVT_ADEVSESSENDDET BIT(16)
565 #define DWC3_OEVT_BDEVBHOSTEND BIT(11)
566 #define DWC3_OEVT_BDEVHNPCHNG BIT(10)
567 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
568 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
569 #define DWC3_OEVT_BSESSVLD BIT(3)
570 #define DWC3_OEVT_HSTNEGSTS BIT(2)
571 #define DWC3_OEVT_SESREQSTS BIT(1)
572 #define DWC3_OEVT_ERROR BIT(0)
574 /* OTG Event Enable Register */
575 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
576 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
577 #define DWC3_OEVTEN_HIBENTRYEN BIT(25)
578 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
579 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
580 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
581 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
582 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
583 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
584 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
585 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
586 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
587 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
588 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
589 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
590 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
592 /* OTG Status Register */
593 #define DWC3_OSTS_DEVRUNSTP BIT(13)
594 #define DWC3_OSTS_XHCIRUNSTP BIT(12)
595 #define DWC3_OSTS_PERIPHERALSTATE BIT(4)
596 #define DWC3_OSTS_XHCIPRTPOWER BIT(3)
597 #define DWC3_OSTS_BSESVLD BIT(2)
598 #define DWC3_OSTS_VBUSVLD BIT(1)
599 #define DWC3_OSTS_CONIDSTS BIT(0)
606 * struct dwc3_event_buffer - Software event buffer representation
608 * @cache: The buffer cache used in the threaded interrupt
609 * @length: size of this buffer
610 * @lpos: event offset
611 * @count: cache of last read event count register
612 * @flags: flags related to this event buffer
614 * @dwc: pointer to DWC controller
616 struct dwc3_event_buffer {
624 #define DWC3_EVENT_PENDING BIT(0)
631 #define DWC3_EP_FLAG_STALLED BIT(0)
632 #define DWC3_EP_FLAG_WEDGED BIT(1)
634 #define DWC3_EP_DIRECTION_TX true
635 #define DWC3_EP_DIRECTION_RX false
637 #define DWC3_TRB_NUM 256
640 * struct dwc3_ep - device side endpoint representation
641 * @endpoint: usb endpoint
642 * @cancelled_list: list of cancelled requests for this endpoint
643 * @pending_list: list of pending requests for this endpoint
644 * @started_list: list of started requests on this endpoint
645 * @lock: spinlock for endpoint request queue traversal
646 * @regs: pointer to first endpoint register
647 * @trb_pool: array of transaction buffers
648 * @trb_pool_dma: dma address of @trb_pool
649 * @trb_enqueue: enqueue 'pointer' into TRB array
650 * @trb_dequeue: dequeue 'pointer' into TRB array
651 * @dwc: pointer to DWC controller
652 * @saved_state: ep state saved during hibernation
653 * @flags: endpoint flags (wedged, stalled, ...)
654 * @number: endpoint number (1 - 15)
655 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
656 * @resource_index: Resource transfer index
657 * @frame_number: set to the frame number we want this transfer to start (ISOC)
658 * @interval: the interval on which the ISOC transfer is started
659 * @name: a human readable name e.g. ep1out-bulk
660 * @direction: true for TX, false for RX
661 * @stream_capable: true when streams are enabled
664 struct usb_ep endpoint;
665 struct list_head cancelled_list;
666 struct list_head pending_list;
667 struct list_head started_list;
672 struct dwc3_trb *trb_pool;
673 dma_addr_t trb_pool_dma;
678 #define DWC3_EP_ENABLED BIT(0)
679 #define DWC3_EP_STALL BIT(1)
680 #define DWC3_EP_WEDGE BIT(2)
681 #define DWC3_EP_TRANSFER_STARTED BIT(3)
682 #define DWC3_EP_PENDING_REQUEST BIT(5)
683 #define DWC3_EP_END_TRANSFER_PENDING BIT(7)
685 /* This last one is specific to EP0 */
686 #define DWC3_EP0_DIR_IN BIT(31)
689 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
690 * use a u8 type here. If anybody decides to increase number of TRBs to
691 * anything larger than 256 - I can't see why people would want to do
692 * this though - then this type needs to be changed.
694 * By using u8 types we ensure that our % operator when incrementing
695 * enqueue and dequeue get optimized away by the compiler.
708 unsigned direction:1;
709 unsigned stream_capable:1;
713 DWC3_PHY_UNKNOWN = 0,
719 DWC3_EP0_UNKNOWN = 0,
722 DWC3_EP0_NRDY_STATUS,
725 enum dwc3_ep0_state {
732 enum dwc3_link_state {
734 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
735 DWC3_LINK_STATE_U1 = 0x01,
736 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
737 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
738 DWC3_LINK_STATE_SS_DIS = 0x04,
739 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
740 DWC3_LINK_STATE_SS_INACT = 0x06,
741 DWC3_LINK_STATE_POLL = 0x07,
742 DWC3_LINK_STATE_RECOV = 0x08,
743 DWC3_LINK_STATE_HRESET = 0x09,
744 DWC3_LINK_STATE_CMPLY = 0x0a,
745 DWC3_LINK_STATE_LPBK = 0x0b,
746 DWC3_LINK_STATE_RESET = 0x0e,
747 DWC3_LINK_STATE_RESUME = 0x0f,
748 DWC3_LINK_STATE_MASK = 0x0f,
751 /* TRB Length, PCM and Status */
752 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
753 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
754 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
755 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
757 #define DWC3_TRBSTS_OK 0
758 #define DWC3_TRBSTS_MISSED_ISOC 1
759 #define DWC3_TRBSTS_SETUP_PENDING 2
760 #define DWC3_TRB_STS_XFER_IN_PROG 4
763 #define DWC3_TRB_CTRL_HWO BIT(0)
764 #define DWC3_TRB_CTRL_LST BIT(1)
765 #define DWC3_TRB_CTRL_CHN BIT(2)
766 #define DWC3_TRB_CTRL_CSP BIT(3)
767 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
768 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
769 #define DWC3_TRB_CTRL_IOC BIT(11)
770 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
772 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
773 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
774 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
775 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
776 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
777 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
778 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
779 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
780 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
783 * struct dwc3_trb - transfer request block (hw format)
797 * struct dwc3_hwparams - copy of HWPARAMS registers
798 * @hwparams0: GHWPARAMS0
799 * @hwparams1: GHWPARAMS1
800 * @hwparams2: GHWPARAMS2
801 * @hwparams3: GHWPARAMS3
802 * @hwparams4: GHWPARAMS4
803 * @hwparams5: GHWPARAMS5
804 * @hwparams6: GHWPARAMS6
805 * @hwparams7: GHWPARAMS7
806 * @hwparams8: GHWPARAMS8
808 struct dwc3_hwparams {
821 #define DWC3_MODE(n) ((n) & 0x7)
823 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
826 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
829 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
830 #define DWC3_NUM_EPS_MASK (0x3f << 12)
831 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
832 (DWC3_NUM_EPS_MASK)) >> 12)
833 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
834 (DWC3_NUM_IN_EPS_MASK)) >> 18)
837 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
840 * struct dwc3_request - representation of a transfer request
841 * @request: struct usb_request to be transferred
842 * @list: a list_head used for request queueing
843 * @dep: struct dwc3_ep owning this request
844 * @sg: pointer to first incomplete sg
845 * @start_sg: pointer to the sg which should be queued next
846 * @num_pending_sgs: counter to pending sgs
847 * @num_queued_sgs: counter to the number of sgs which already got queued
848 * @remaining: amount of data remaining
849 * @epnum: endpoint number to which this request refers
850 * @trb: pointer to struct dwc3_trb
851 * @trb_dma: DMA address of @trb
852 * @num_trbs: number of TRBs used by this request
853 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
855 * @direction: IN or OUT direction flag
856 * @mapped: true when request has been dma-mapped
857 * @started: request is started
859 struct dwc3_request {
860 struct usb_request request;
861 struct list_head list;
863 struct scatterlist *sg;
864 struct scatterlist *start_sg;
866 unsigned num_pending_sgs;
867 unsigned int num_queued_sgs;
870 struct dwc3_trb *trb;
875 unsigned needs_extra_trb:1;
876 unsigned direction:1;
882 * struct dwc3_scratchpad_array - hibernation scratchpad array
883 * (format defined by hw)
885 struct dwc3_scratchpad_array {
886 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
890 * struct dwc3 - representation of our controller
891 * @drd_work: workqueue used for role swapping
892 * @ep0_trb: trb which is used for the ctrl_req
893 * @bounce: address of bounce buffer
894 * @scratchbuf: address of scratch buffer
895 * @setup_buf: used while precessing STD USB requests
896 * @ep0_trb_addr: dma address of @ep0_trb
897 * @bounce_addr: dma address of @bounce
898 * @ep0_usb_req: dummy req used while handling STD USB requests
899 * @scratch_addr: dma address of scratchbuf
900 * @ep0_in_setup: one control transfer is completed and enter setup phase
901 * @lock: for synchronizing
902 * @dev: pointer to our struct device
903 * @sysdev: pointer to the DMA-capable device
904 * @xhci: pointer to our xHCI child
905 * @xhci_resources: struct resources for our @xhci child
906 * @ev_buf: struct dwc3_event_buffer pointer
907 * @eps: endpoint array
908 * @gadget: device side representation of the peripheral controller
909 * @gadget_driver: pointer to the gadget driver
910 * @clks: array of clocks
911 * @num_clks: number of clocks
912 * @reset: reset control
913 * @regs: base address for our registers
914 * @regs_size: address space size
915 * @fladj: frame length adjustment
916 * @irq_gadget: peripheral controller's IRQ number
917 * @otg_irq: IRQ number for OTG IRQs
918 * @current_otg_role: current role of operation while using the OTG block
919 * @desired_otg_role: desired role of operation while using the OTG block
920 * @otg_restart_host: flag that OTG controller needs to restart host
921 * @nr_scratch: number of scratch buffers
922 * @u1u2: only used on revisions <1.83a for workaround
923 * @maximum_speed: maximum speed requested (mainly for testing purposes)
924 * @revision: revision register contents
925 * @dr_mode: requested mode of operation
926 * @current_dr_role: current role of operation when in dual-role mode
927 * @desired_dr_role: desired role of operation when in dual-role mode
928 * @edev: extcon handle
929 * @edev_nb: extcon notifier
930 * @hsphy_mode: UTMI phy mode, one of following:
931 * - USBPHY_INTERFACE_MODE_UTMI
932 * - USBPHY_INTERFACE_MODE_UTMIW
933 * @usb2_phy: pointer to USB2 PHY
934 * @usb3_phy: pointer to USB3 PHY
935 * @usb2_generic_phy: pointer to USB2 PHY
936 * @usb3_generic_phy: pointer to USB3 PHY
937 * @phys_ready: flag to indicate that PHYs are ready
938 * @ulpi: pointer to ulpi interface
939 * @ulpi_ready: flag to indicate that ULPI is initialized
940 * @u2sel: parameter from Set SEL request.
941 * @u2pel: parameter from Set SEL request.
942 * @u1sel: parameter from Set SEL request.
943 * @u1pel: parameter from Set SEL request.
944 * @num_eps: number of endpoints
945 * @ep0_next_event: hold the next expected event
946 * @ep0state: state of endpoint zero
947 * @link_state: link state
948 * @speed: device speed (super, high, full, low)
949 * @hwparams: copy of hwparams registers
950 * @root: debugfs root folder pointer
951 * @regset: debugfs pointer to regdump file
952 * @test_mode: true when we're entering a USB test mode
953 * @test_mode_nr: test feature selector
954 * @lpm_nyet_threshold: LPM NYET response threshold
955 * @hird_threshold: HIRD threshold
956 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
957 * @rx_max_burst_prd: max periodic ESS receive burst size
958 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
959 * @tx_max_burst_prd: max periodic ESS transmit burst size
960 * @hsphy_interface: "utmi" or "ulpi"
961 * @connected: true when we're connected to a host, false otherwise
962 * @delayed_status: true when gadget driver asks for delayed status
963 * @ep0_bounced: true when we used bounce buffer
964 * @ep0_expect_in: true when we expect a DATA IN transfer
965 * @has_hibernation: true when dwc3 was configured with Hibernation
966 * @sysdev_is_parent: true when dwc3 device has a parent driver
967 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
968 * there's now way for software to detect this in runtime.
969 * @is_utmi_l1_suspend: the core asserts output signal
971 * 1 - utmi_l1_suspend_n
972 * @is_fpga: true when we are using the FPGA board
973 * @pending_events: true when we have pending IRQs to be handled
974 * @pullups_connected: true when Run/Stop bit is set
975 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
976 * @three_stage_setup: set if we perform a three phase setup
977 * @usb3_lpm_capable: set if hadrware supports Link Power Management
978 * @disable_scramble_quirk: set if we enable the disable scramble quirk
979 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
980 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
981 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
982 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
983 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
984 * @lfps_filter_quirk: set if we enable LFPS filter quirk
985 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
986 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
987 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
988 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
989 * disabling the suspend signal to the PHY.
990 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
991 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
992 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
993 * provide a free-running PHY clock.
994 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
996 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
997 * check during HS transmit.
998 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
999 * instances in park mode.
1000 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1001 * @tx_de_emphasis: Tx de-emphasis value
1002 * 0 - -6dB de-emphasis
1003 * 1 - -3.5dB de-emphasis
1004 * 2 - No de-emphasis
1006 * @dis_metastability_quirk: set to disable metastability quirk.
1007 * @imod_interval: set the interrupt moderation interval in 250ns
1008 * increments or 0 to disable.
1011 struct work_struct drd_work;
1012 struct dwc3_trb *ep0_trb;
1016 dma_addr_t ep0_trb_addr;
1017 dma_addr_t bounce_addr;
1018 dma_addr_t scratch_addr;
1019 struct dwc3_request ep0_usb_req;
1020 struct completion ep0_in_setup;
1026 struct device *sysdev;
1028 struct platform_device *xhci;
1029 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1031 struct dwc3_event_buffer *ev_buf;
1032 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1034 struct usb_gadget gadget;
1035 struct usb_gadget_driver *gadget_driver;
1037 struct clk_bulk_data *clks;
1040 struct reset_control *reset;
1042 struct usb_phy *usb2_phy;
1043 struct usb_phy *usb3_phy;
1045 struct phy *usb2_generic_phy;
1046 struct phy *usb3_generic_phy;
1056 enum usb_dr_mode dr_mode;
1057 u32 current_dr_role;
1058 u32 desired_dr_role;
1059 struct extcon_dev *edev;
1060 struct notifier_block edev_nb;
1061 enum usb_phy_interface hsphy_mode;
1066 u32 current_otg_role;
1067 u32 desired_otg_role;
1068 bool otg_restart_host;
1074 * All 3.1 IP version constants are greater than the 3.0 IP
1075 * version constants. This works for most version checks in
1076 * dwc3. However, in the future, this may not apply as
1077 * features may be developed on newer versions of the 3.0 IP
1078 * that are not in the 3.1 IP.
1082 #define DWC3_REVISION_173A 0x5533173a
1083 #define DWC3_REVISION_175A 0x5533175a
1084 #define DWC3_REVISION_180A 0x5533180a
1085 #define DWC3_REVISION_183A 0x5533183a
1086 #define DWC3_REVISION_185A 0x5533185a
1087 #define DWC3_REVISION_187A 0x5533187a
1088 #define DWC3_REVISION_188A 0x5533188a
1089 #define DWC3_REVISION_190A 0x5533190a
1090 #define DWC3_REVISION_194A 0x5533194a
1091 #define DWC3_REVISION_200A 0x5533200a
1092 #define DWC3_REVISION_202A 0x5533202a
1093 #define DWC3_REVISION_210A 0x5533210a
1094 #define DWC3_REVISION_220A 0x5533220a
1095 #define DWC3_REVISION_230A 0x5533230a
1096 #define DWC3_REVISION_240A 0x5533240a
1097 #define DWC3_REVISION_250A 0x5533250a
1098 #define DWC3_REVISION_260A 0x5533260a
1099 #define DWC3_REVISION_270A 0x5533270a
1100 #define DWC3_REVISION_280A 0x5533280a
1101 #define DWC3_REVISION_290A 0x5533290a
1102 #define DWC3_REVISION_300A 0x5533300a
1103 #define DWC3_REVISION_310A 0x5533310a
1106 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
1107 * just so dwc31 revisions are always larger than dwc3.
1109 #define DWC3_REVISION_IS_DWC31 0x80000000
1110 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
1111 #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
1113 enum dwc3_ep0_next ep0_next_event;
1114 enum dwc3_ep0_state ep0state;
1115 enum dwc3_link_state link_state;
1126 struct dwc3_hwparams hwparams;
1127 struct dentry *root;
1128 struct debugfs_regset32 *regset;
1132 u8 lpm_nyet_threshold;
1134 u8 rx_thr_num_pkt_prd;
1135 u8 rx_max_burst_prd;
1136 u8 tx_thr_num_pkt_prd;
1137 u8 tx_max_burst_prd;
1139 const char *hsphy_interface;
1141 unsigned connected:1;
1142 unsigned delayed_status:1;
1143 unsigned ep0_bounced:1;
1144 unsigned ep0_expect_in:1;
1145 unsigned has_hibernation:1;
1146 unsigned sysdev_is_parent:1;
1147 unsigned has_lpm_erratum:1;
1148 unsigned is_utmi_l1_suspend:1;
1150 unsigned pending_events:1;
1151 unsigned pullups_connected:1;
1152 unsigned setup_packet_pending:1;
1153 unsigned three_stage_setup:1;
1154 unsigned usb3_lpm_capable:1;
1156 unsigned disable_scramble_quirk:1;
1157 unsigned u2exit_lfps_quirk:1;
1158 unsigned u2ss_inp3_quirk:1;
1159 unsigned req_p1p2p3_quirk:1;
1160 unsigned del_p1p2p3_quirk:1;
1161 unsigned del_phy_power_chg_quirk:1;
1162 unsigned lfps_filter_quirk:1;
1163 unsigned rx_detect_poll_quirk:1;
1164 unsigned dis_u3_susphy_quirk:1;
1165 unsigned dis_u2_susphy_quirk:1;
1166 unsigned dis_enblslpm_quirk:1;
1167 unsigned dis_rxdet_inp3_quirk:1;
1168 unsigned dis_u2_freeclk_exists_quirk:1;
1169 unsigned dis_del_phy_power_chg_quirk:1;
1170 unsigned dis_tx_ipgap_linecheck_quirk:1;
1171 unsigned parkmode_disable_ss_quirk:1;
1173 unsigned tx_de_emphasis_quirk:1;
1174 unsigned tx_de_emphasis:2;
1176 unsigned dis_metastability_quirk:1;
1181 #define INCRX_BURST_MODE 0
1182 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1184 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1186 /* -------------------------------------------------------------------------- */
1188 struct dwc3_event_type {
1191 u32 reserved8_31:24;
1194 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1195 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1196 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1197 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1198 #define DWC3_DEPEVT_STREAMEVT 0x06
1199 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1202 * struct dwc3_event_depvt - Device Endpoint Events
1203 * @one_bit: indicates this is an endpoint event (not used)
1204 * @endpoint_number: number of the endpoint
1205 * @endpoint_event: The event we have:
1207 * 0x01 - XferComplete
1208 * 0x02 - XferInProgress
1209 * 0x03 - XferNotReady
1210 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1214 * @reserved11_10: Reserved, don't use.
1215 * @status: Indicates the status of the event. Refer to databook for
1217 * @parameters: Parameters of the current event. Refer to databook for
1220 struct dwc3_event_depevt {
1222 u32 endpoint_number:5;
1223 u32 endpoint_event:4;
1224 u32 reserved11_10:2;
1227 /* Within XferNotReady */
1228 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1230 /* Within XferComplete or XferInProgress */
1231 #define DEPEVT_STATUS_BUSERR BIT(0)
1232 #define DEPEVT_STATUS_SHORT BIT(1)
1233 #define DEPEVT_STATUS_IOC BIT(2)
1234 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1235 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1237 /* Stream event only */
1238 #define DEPEVT_STREAMEVT_FOUND 1
1239 #define DEPEVT_STREAMEVT_NOTFOUND 2
1241 /* Control-only Status */
1242 #define DEPEVT_STATUS_CONTROL_DATA 1
1243 #define DEPEVT_STATUS_CONTROL_STATUS 2
1244 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1246 /* In response to Start Transfer */
1247 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1248 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1252 /* For Command Complete Events */
1253 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1257 * struct dwc3_event_devt - Device Events
1258 * @one_bit: indicates this is a non-endpoint event (not used)
1259 * @device_event: indicates it's a device event. Should read as 0x00
1260 * @type: indicates the type of device event.
1273 * 12 - VndrDevTstRcved
1274 * @reserved15_12: Reserved, not used
1275 * @event_info: Information about this event
1276 * @reserved31_25: Reserved, not used
1278 struct dwc3_event_devt {
1282 u32 reserved15_12:4;
1284 u32 reserved31_25:7;
1288 * struct dwc3_event_gevt - Other Core Events
1289 * @one_bit: indicates this is a non-endpoint event (not used)
1290 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1291 * @phy_port_number: self-explanatory
1292 * @reserved31_12: Reserved, not used.
1294 struct dwc3_event_gevt {
1297 u32 phy_port_number:4;
1298 u32 reserved31_12:20;
1302 * union dwc3_event - representation of Event Buffer contents
1303 * @raw: raw 32-bit event
1304 * @type: the type of the event
1305 * @depevt: Device Endpoint Event
1306 * @devt: Device Event
1307 * @gevt: Global Event
1311 struct dwc3_event_type type;
1312 struct dwc3_event_depevt depevt;
1313 struct dwc3_event_devt devt;
1314 struct dwc3_event_gevt gevt;
1318 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1320 * @param2: third parameter
1321 * @param1: second parameter
1322 * @param0: first parameter
1324 struct dwc3_gadget_ep_cmd_params {
1331 * DWC3 Features to be used as Driver Data
1334 #define DWC3_HAS_PERIPHERAL BIT(0)
1335 #define DWC3_HAS_XHCI BIT(1)
1336 #define DWC3_HAS_OTG BIT(3)
1339 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1340 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1341 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1343 /* check whether we are on the DWC_usb3 core */
1344 static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1346 return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1349 /* check whether we are on the DWC_usb31 core */
1350 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1352 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1355 bool dwc3_has_imod(struct dwc3 *dwc);
1357 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1358 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1360 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1361 int dwc3_host_init(struct dwc3 *dwc);
1362 void dwc3_host_exit(struct dwc3 *dwc);
1364 static inline int dwc3_host_init(struct dwc3 *dwc)
1366 static inline void dwc3_host_exit(struct dwc3 *dwc)
1370 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1371 int dwc3_gadget_init(struct dwc3 *dwc);
1372 void dwc3_gadget_exit(struct dwc3 *dwc);
1373 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1374 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1375 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1376 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1377 struct dwc3_gadget_ep_cmd_params *params);
1378 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1380 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1382 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1384 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1386 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1388 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1389 enum dwc3_link_state state)
1392 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1393 struct dwc3_gadget_ep_cmd_params *params)
1395 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1400 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1401 int dwc3_drd_init(struct dwc3 *dwc);
1402 void dwc3_drd_exit(struct dwc3 *dwc);
1403 void dwc3_otg_init(struct dwc3 *dwc);
1404 void dwc3_otg_exit(struct dwc3 *dwc);
1405 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1406 void dwc3_otg_host_init(struct dwc3 *dwc);
1408 static inline int dwc3_drd_init(struct dwc3 *dwc)
1410 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1412 static inline void dwc3_otg_init(struct dwc3 *dwc)
1414 static inline void dwc3_otg_exit(struct dwc3 *dwc)
1416 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1418 static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1422 /* power management interface */
1423 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1424 int dwc3_gadget_suspend(struct dwc3 *dwc);
1425 int dwc3_gadget_resume(struct dwc3 *dwc);
1426 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1428 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1433 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1438 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1441 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1443 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1444 int dwc3_ulpi_init(struct dwc3 *dwc);
1445 void dwc3_ulpi_exit(struct dwc3 *dwc);
1447 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1449 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1453 #endif /* __DRIVERS_USB_DWC3_CORE_H */