1 // SPDX-License-Identifier: GPL-2.0
3 * core.h - DesignWare USB3 DRD Core Header
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #ifndef __DRIVERS_USB_DWC3_CORE_H
12 #define __DRIVERS_USB_DWC3_CORE_H
14 #include <linux/device.h>
15 #include <linux/spinlock.h>
16 #include <linux/ioport.h>
17 #include <linux/list.h>
18 #include <linux/bitops.h>
19 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/wait.h>
23 #include <linux/workqueue.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27 #include <linux/usb/otg.h>
28 #include <linux/ulpi/interface.h>
30 #include <linux/phy/phy.h>
32 #define DWC3_MSG_MAX 500
34 /* Global constants */
35 #define DWC3_PULL_UP_TIMEOUT 500 /* ms */
36 #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
37 #define DWC3_EP0_SETUP_SIZE 512
38 #define DWC3_ENDPOINTS_NUM 32
39 #define DWC3_XHCI_RESOURCES_NUM 2
41 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
42 #define DWC3_EVENT_BUFFERS_SIZE 4096
43 #define DWC3_EVENT_TYPE_MASK 0xfe
45 #define DWC3_EVENT_TYPE_DEV 0
46 #define DWC3_EVENT_TYPE_CARKIT 3
47 #define DWC3_EVENT_TYPE_I2C 4
49 #define DWC3_DEVICE_EVENT_DISCONNECT 0
50 #define DWC3_DEVICE_EVENT_RESET 1
51 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
52 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
53 #define DWC3_DEVICE_EVENT_WAKEUP 4
54 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
55 #define DWC3_DEVICE_EVENT_EOPF 6
56 #define DWC3_DEVICE_EVENT_SOF 7
57 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
58 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
59 #define DWC3_DEVICE_EVENT_OVERFLOW 11
61 /* Controller's role while using the OTG block */
62 #define DWC3_OTG_ROLE_IDLE 0
63 #define DWC3_OTG_ROLE_HOST 1
64 #define DWC3_OTG_ROLE_DEVICE 2
66 #define DWC3_GEVNTCOUNT_MASK 0xfffc
67 #define DWC3_GEVNTCOUNT_EHB BIT(31)
68 #define DWC3_GSNPSID_MASK 0xffff0000
69 #define DWC3_GSNPSREV_MASK 0xffff
71 /* DWC3 registers memory space boundries */
72 #define DWC3_XHCI_REGS_START 0x0
73 #define DWC3_XHCI_REGS_END 0x7fff
74 #define DWC3_GLOBALS_REGS_START 0xc100
75 #define DWC3_GLOBALS_REGS_END 0xc6ff
76 #define DWC3_DEVICE_REGS_START 0xc700
77 #define DWC3_DEVICE_REGS_END 0xcbff
78 #define DWC3_OTG_REGS_START 0xcc00
79 #define DWC3_OTG_REGS_END 0xccff
81 /* Global Registers */
82 #define DWC3_GSBUSCFG0 0xc100
83 #define DWC3_GSBUSCFG1 0xc104
84 #define DWC3_GTXTHRCFG 0xc108
85 #define DWC3_GRXTHRCFG 0xc10c
86 #define DWC3_GCTL 0xc110
87 #define DWC3_GEVTEN 0xc114
88 #define DWC3_GSTS 0xc118
89 #define DWC3_GUCTL1 0xc11c
90 #define DWC3_GSNPSID 0xc120
91 #define DWC3_GGPIO 0xc124
92 #define DWC3_GUID 0xc128
93 #define DWC3_GUCTL 0xc12c
94 #define DWC3_GBUSERRADDR0 0xc130
95 #define DWC3_GBUSERRADDR1 0xc134
96 #define DWC3_GPRTBIMAP0 0xc138
97 #define DWC3_GPRTBIMAP1 0xc13c
98 #define DWC3_GHWPARAMS0 0xc140
99 #define DWC3_GHWPARAMS1 0xc144
100 #define DWC3_GHWPARAMS2 0xc148
101 #define DWC3_GHWPARAMS3 0xc14c
102 #define DWC3_GHWPARAMS4 0xc150
103 #define DWC3_GHWPARAMS5 0xc154
104 #define DWC3_GHWPARAMS6 0xc158
105 #define DWC3_GHWPARAMS7 0xc15c
106 #define DWC3_GDBGFIFOSPACE 0xc160
107 #define DWC3_GDBGLTSSM 0xc164
108 #define DWC3_GDBGBMU 0xc16c
109 #define DWC3_GDBGLSPMUX 0xc170
110 #define DWC3_GDBGLSP 0xc174
111 #define DWC3_GDBGEPINFO0 0xc178
112 #define DWC3_GDBGEPINFO1 0xc17c
113 #define DWC3_GPRTBIMAP_HS0 0xc180
114 #define DWC3_GPRTBIMAP_HS1 0xc184
115 #define DWC3_GPRTBIMAP_FS0 0xc188
116 #define DWC3_GPRTBIMAP_FS1 0xc18c
117 #define DWC3_GUCTL2 0xc19c
119 #define DWC3_VER_NUMBER 0xc1a0
120 #define DWC3_VER_TYPE 0xc1a4
122 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
123 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
125 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
127 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
129 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
130 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
132 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
133 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
134 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
135 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
137 #define DWC3_GHWPARAMS8 0xc600
138 #define DWC3_GFLADJ 0xc630
140 /* Device Registers */
141 #define DWC3_DCFG 0xc700
142 #define DWC3_DCTL 0xc704
143 #define DWC3_DEVTEN 0xc708
144 #define DWC3_DSTS 0xc70c
145 #define DWC3_DGCMDPAR 0xc710
146 #define DWC3_DGCMD 0xc714
147 #define DWC3_DALEPENA 0xc720
149 #define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
150 #define DWC3_DEPCMDPAR2 0x00
151 #define DWC3_DEPCMDPAR1 0x04
152 #define DWC3_DEPCMDPAR0 0x08
153 #define DWC3_DEPCMD 0x0c
155 #define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
158 #define DWC3_OCFG 0xcc00
159 #define DWC3_OCTL 0xcc04
160 #define DWC3_OEVT 0xcc08
161 #define DWC3_OEVTEN 0xcc0C
162 #define DWC3_OSTS 0xcc10
166 /* Global SoC Bus Configuration INCRx Register 0 */
167 #define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
168 #define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
169 #define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
170 #define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
171 #define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
172 #define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
173 #define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
174 #define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
175 #define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
177 /* Global Debug Queue/FIFO Space Available Register */
178 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
179 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
180 #define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
182 #define DWC3_TXFIFOQ 0
183 #define DWC3_RXFIFOQ 1
184 #define DWC3_TXREQQ 2
185 #define DWC3_RXREQQ 3
186 #define DWC3_RXINFOQ 4
187 #define DWC3_PSTATQ 5
188 #define DWC3_DESCFETCHQ 6
189 #define DWC3_EVENTQ 7
190 #define DWC3_AUXEVENTQ 8
192 /* Global RX Threshold Configuration Register */
193 #define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
194 #define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
195 #define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
197 /* Global RX Threshold Configuration Register for DWC_usb31 only */
198 #define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
199 #define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
200 #define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
201 #define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
202 #define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
203 #define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
204 #define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
205 #define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
207 /* Global TX Threshold Configuration Register for DWC_usb31 only */
208 #define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
209 #define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
210 #define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
211 #define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
212 #define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
213 #define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
214 #define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
215 #define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
217 /* Global Configuration Register */
218 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
219 #define DWC3_GCTL_U2RSTECN BIT(16)
220 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
221 #define DWC3_GCTL_CLK_BUS (0)
222 #define DWC3_GCTL_CLK_PIPE (1)
223 #define DWC3_GCTL_CLK_PIPEHALF (2)
224 #define DWC3_GCTL_CLK_MASK (3)
226 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
227 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
228 #define DWC3_GCTL_PRTCAP_HOST 1
229 #define DWC3_GCTL_PRTCAP_DEVICE 2
230 #define DWC3_GCTL_PRTCAP_OTG 3
232 #define DWC3_GCTL_CORESOFTRESET BIT(11)
233 #define DWC3_GCTL_SOFITPSYNC BIT(10)
234 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
235 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
236 #define DWC3_GCTL_DISSCRAMBLE BIT(3)
237 #define DWC3_GCTL_U2EXIT_LFPS BIT(2)
238 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
239 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
241 /* Global User Control Register */
242 #define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
244 /* Global User Control 1 Register */
245 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
246 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
247 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
249 /* Global Status Register */
250 #define DWC3_GSTS_OTG_IP BIT(10)
251 #define DWC3_GSTS_BC_IP BIT(9)
252 #define DWC3_GSTS_ADP_IP BIT(8)
253 #define DWC3_GSTS_HOST_IP BIT(7)
254 #define DWC3_GSTS_DEVICE_IP BIT(6)
255 #define DWC3_GSTS_CSR_TIMEOUT BIT(5)
256 #define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
258 /* Global USB2 PHY Configuration Register */
259 #define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
260 #define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
261 #define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
262 #define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
263 #define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
264 #define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
265 #define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
266 #define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
267 #define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
268 #define USBTRDTIM_UTMI_8_BIT 9
269 #define USBTRDTIM_UTMI_16_BIT 5
270 #define UTMI_PHYIF_16_BIT 1
271 #define UTMI_PHYIF_8_BIT 0
273 /* Global USB2 PHY Vendor Control Register */
274 #define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
275 #define DWC3_GUSB2PHYACC_DONE BIT(24)
276 #define DWC3_GUSB2PHYACC_BUSY BIT(23)
277 #define DWC3_GUSB2PHYACC_WRITE BIT(22)
278 #define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
279 #define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
280 #define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
282 /* Global USB3 PIPE Control Register */
283 #define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
284 #define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
285 #define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
286 #define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
287 #define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
288 #define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
289 #define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
290 #define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
291 #define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
292 #define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
293 #define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
294 #define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
295 #define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
296 #define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
298 /* Global TX Fifo Size Register */
299 #define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
300 #define DWC31_GTXFIFOSIZ_TXFDEF(n) ((n) & 0x7fff) /* DWC_usb31 only */
301 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
302 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
304 /* Global RX Fifo Size Register */
305 #define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
306 #define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
308 /* Global Event Size Registers */
309 #define DWC3_GEVNTSIZ_INTMASK BIT(31)
310 #define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
312 /* Global HWPARAMS0 Register */
313 #define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
314 #define DWC3_GHWPARAMS0_MODE_GADGET 0
315 #define DWC3_GHWPARAMS0_MODE_HOST 1
316 #define DWC3_GHWPARAMS0_MODE_DRD 2
317 #define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
318 #define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
319 #define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
320 #define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
321 #define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
323 /* Global HWPARAMS1 Register */
324 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
325 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
326 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
327 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
328 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
329 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
331 /* Global HWPARAMS3 Register */
332 #define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
333 #define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
334 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
335 #define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
336 #define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
337 #define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
338 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
339 #define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
340 #define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
341 #define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
342 #define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
343 #define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
345 /* Global HWPARAMS4 Register */
346 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
347 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
349 /* Global HWPARAMS6 Register */
350 #define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
351 #define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
352 #define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
353 #define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
354 #define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
355 #define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
357 /* Global HWPARAMS7 Register */
358 #define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
359 #define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
361 /* Global Frame Length Adjustment Register */
362 #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
363 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
365 /* Global User Control Register 2 */
366 #define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
368 /* Device Configuration Register */
369 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
370 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
372 #define DWC3_DCFG_SPEED_MASK (7 << 0)
373 #define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
374 #define DWC3_DCFG_SUPERSPEED (4 << 0)
375 #define DWC3_DCFG_HIGHSPEED (0 << 0)
376 #define DWC3_DCFG_FULLSPEED BIT(0)
377 #define DWC3_DCFG_LOWSPEED (2 << 0)
379 #define DWC3_DCFG_NUMP_SHIFT 17
380 #define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
381 #define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
382 #define DWC3_DCFG_LPM_CAP BIT(22)
384 /* Device Control Register */
385 #define DWC3_DCTL_RUN_STOP BIT(31)
386 #define DWC3_DCTL_CSFTRST BIT(30)
387 #define DWC3_DCTL_LSFTRST BIT(29)
389 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
390 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
392 #define DWC3_DCTL_APPL1RES BIT(23)
394 /* These apply for core versions 1.87a and earlier */
395 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
396 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
397 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
398 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
399 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
400 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
401 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
403 /* These apply for core versions 1.94a and later */
404 #define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
405 #define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
407 #define DWC3_DCTL_KEEP_CONNECT BIT(19)
408 #define DWC3_DCTL_L1_HIBER_EN BIT(18)
409 #define DWC3_DCTL_CRS BIT(17)
410 #define DWC3_DCTL_CSS BIT(16)
412 #define DWC3_DCTL_INITU2ENA BIT(12)
413 #define DWC3_DCTL_ACCEPTU2ENA BIT(11)
414 #define DWC3_DCTL_INITU1ENA BIT(10)
415 #define DWC3_DCTL_ACCEPTU1ENA BIT(9)
416 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
418 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
419 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
421 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
422 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
423 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
424 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
425 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
426 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
427 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
429 /* Device Event Enable Register */
430 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
431 #define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
432 #define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
433 #define DWC3_DEVTEN_ERRTICERREN BIT(9)
434 #define DWC3_DEVTEN_SOFEN BIT(7)
435 #define DWC3_DEVTEN_EOPFEN BIT(6)
436 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
437 #define DWC3_DEVTEN_WKUPEVTEN BIT(4)
438 #define DWC3_DEVTEN_ULSTCNGEN BIT(3)
439 #define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
440 #define DWC3_DEVTEN_USBRSTEN BIT(1)
441 #define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
443 /* Device Status Register */
444 #define DWC3_DSTS_DCNRD BIT(29)
446 /* This applies for core versions 1.87a and earlier */
447 #define DWC3_DSTS_PWRUPREQ BIT(24)
449 /* These apply for core versions 1.94a and later */
450 #define DWC3_DSTS_RSS BIT(25)
451 #define DWC3_DSTS_SSS BIT(24)
453 #define DWC3_DSTS_COREIDLE BIT(23)
454 #define DWC3_DSTS_DEVCTRLHLT BIT(22)
456 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
457 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
459 #define DWC3_DSTS_RXFIFOEMPTY BIT(17)
461 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
462 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
464 #define DWC3_DSTS_CONNECTSPD (7 << 0)
466 #define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
467 #define DWC3_DSTS_SUPERSPEED (4 << 0)
468 #define DWC3_DSTS_HIGHSPEED (0 << 0)
469 #define DWC3_DSTS_FULLSPEED BIT(0)
470 #define DWC3_DSTS_LOWSPEED (2 << 0)
472 /* Device Generic Command Register */
473 #define DWC3_DGCMD_SET_LMP 0x01
474 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
475 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
477 /* These apply for core versions 1.94a and later */
478 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
479 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
481 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
482 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
483 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
484 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
486 #define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
487 #define DWC3_DGCMD_CMDACT BIT(10)
488 #define DWC3_DGCMD_CMDIOC BIT(8)
490 /* Device Generic Command Parameter Register */
491 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
492 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
493 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
494 #define DWC3_DGCMDPAR_TX_FIFO BIT(5)
495 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
496 #define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
498 /* Device Endpoint Command Register */
499 #define DWC3_DEPCMD_PARAM_SHIFT 16
500 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
501 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
502 #define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
503 #define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
504 #define DWC3_DEPCMD_CLEARPENDIN BIT(11)
505 #define DWC3_DEPCMD_CMDACT BIT(10)
506 #define DWC3_DEPCMD_CMDIOC BIT(8)
508 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
509 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
510 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
511 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
512 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
513 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
514 /* This applies for core versions 1.90a and earlier */
515 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
516 /* This applies for core versions 1.94a and later */
517 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
518 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
519 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
521 #define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
523 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
524 #define DWC3_DALEPENA_EP(n) BIT(n)
526 #define DWC3_DEPCMD_TYPE_CONTROL 0
527 #define DWC3_DEPCMD_TYPE_ISOC 1
528 #define DWC3_DEPCMD_TYPE_BULK 2
529 #define DWC3_DEPCMD_TYPE_INTR 3
531 #define DWC3_DEV_IMOD_COUNT_SHIFT 16
532 #define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
533 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
534 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
536 /* OTG Configuration Register */
537 #define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
538 #define DWC3_OCFG_HIBDISMASK BIT(4)
539 #define DWC3_OCFG_SFTRSTMASK BIT(3)
540 #define DWC3_OCFG_OTGVERSION BIT(2)
541 #define DWC3_OCFG_HNPCAP BIT(1)
542 #define DWC3_OCFG_SRPCAP BIT(0)
544 /* OTG CTL Register */
545 #define DWC3_OCTL_OTG3GOERR BIT(7)
546 #define DWC3_OCTL_PERIMODE BIT(6)
547 #define DWC3_OCTL_PRTPWRCTL BIT(5)
548 #define DWC3_OCTL_HNPREQ BIT(4)
549 #define DWC3_OCTL_SESREQ BIT(3)
550 #define DWC3_OCTL_TERMSELIDPULSE BIT(2)
551 #define DWC3_OCTL_DEVSETHNPEN BIT(1)
552 #define DWC3_OCTL_HSTSETHNPEN BIT(0)
554 /* OTG Event Register */
555 #define DWC3_OEVT_DEVICEMODE BIT(31)
556 #define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
557 #define DWC3_OEVT_DEVRUNSTPSET BIT(26)
558 #define DWC3_OEVT_HIBENTRY BIT(25)
559 #define DWC3_OEVT_CONIDSTSCHNG BIT(24)
560 #define DWC3_OEVT_HRRCONFNOTIF BIT(23)
561 #define DWC3_OEVT_HRRINITNOTIF BIT(22)
562 #define DWC3_OEVT_ADEVIDLE BIT(21)
563 #define DWC3_OEVT_ADEVBHOSTEND BIT(20)
564 #define DWC3_OEVT_ADEVHOST BIT(19)
565 #define DWC3_OEVT_ADEVHNPCHNG BIT(18)
566 #define DWC3_OEVT_ADEVSRPDET BIT(17)
567 #define DWC3_OEVT_ADEVSESSENDDET BIT(16)
568 #define DWC3_OEVT_BDEVBHOSTEND BIT(11)
569 #define DWC3_OEVT_BDEVHNPCHNG BIT(10)
570 #define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
571 #define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
572 #define DWC3_OEVT_BSESSVLD BIT(3)
573 #define DWC3_OEVT_HSTNEGSTS BIT(2)
574 #define DWC3_OEVT_SESREQSTS BIT(1)
575 #define DWC3_OEVT_ERROR BIT(0)
577 /* OTG Event Enable Register */
578 #define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
579 #define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
580 #define DWC3_OEVTEN_HIBENTRYEN BIT(25)
581 #define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
582 #define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
583 #define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
584 #define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
585 #define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
586 #define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
587 #define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
588 #define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
589 #define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
590 #define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
591 #define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
592 #define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
593 #define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
595 /* OTG Status Register */
596 #define DWC3_OSTS_DEVRUNSTP BIT(13)
597 #define DWC3_OSTS_XHCIRUNSTP BIT(12)
598 #define DWC3_OSTS_PERIPHERALSTATE BIT(4)
599 #define DWC3_OSTS_XHCIPRTPOWER BIT(3)
600 #define DWC3_OSTS_BSESVLD BIT(2)
601 #define DWC3_OSTS_VBUSVLD BIT(1)
602 #define DWC3_OSTS_CONIDSTS BIT(0)
609 * struct dwc3_event_buffer - Software event buffer representation
611 * @cache: The buffer cache used in the threaded interrupt
612 * @length: size of this buffer
613 * @lpos: event offset
614 * @count: cache of last read event count register
615 * @flags: flags related to this event buffer
617 * @dwc: pointer to DWC controller
619 struct dwc3_event_buffer {
627 #define DWC3_EVENT_PENDING BIT(0)
634 #define DWC3_EP_FLAG_STALLED BIT(0)
635 #define DWC3_EP_FLAG_WEDGED BIT(1)
637 #define DWC3_EP_DIRECTION_TX true
638 #define DWC3_EP_DIRECTION_RX false
640 #define DWC3_TRB_NUM 256
643 * struct dwc3_ep - device side endpoint representation
644 * @endpoint: usb endpoint
645 * @cancelled_list: list of cancelled requests for this endpoint
646 * @pending_list: list of pending requests for this endpoint
647 * @started_list: list of started requests on this endpoint
648 * @lock: spinlock for endpoint request queue traversal
649 * @regs: pointer to first endpoint register
650 * @trb_pool: array of transaction buffers
651 * @trb_pool_dma: dma address of @trb_pool
652 * @trb_enqueue: enqueue 'pointer' into TRB array
653 * @trb_dequeue: dequeue 'pointer' into TRB array
654 * @dwc: pointer to DWC controller
655 * @saved_state: ep state saved during hibernation
656 * @flags: endpoint flags (wedged, stalled, ...)
657 * @number: endpoint number (1 - 15)
658 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
659 * @resource_index: Resource transfer index
660 * @frame_number: set to the frame number we want this transfer to start (ISOC)
661 * @interval: the interval on which the ISOC transfer is started
662 * @name: a human readable name e.g. ep1out-bulk
663 * @direction: true for TX, false for RX
664 * @stream_capable: true when streams are enabled
667 struct usb_ep endpoint;
668 struct list_head cancelled_list;
669 struct list_head pending_list;
670 struct list_head started_list;
675 struct dwc3_trb *trb_pool;
676 dma_addr_t trb_pool_dma;
681 #define DWC3_EP_ENABLED BIT(0)
682 #define DWC3_EP_STALL BIT(1)
683 #define DWC3_EP_WEDGE BIT(2)
684 #define DWC3_EP_TRANSFER_STARTED BIT(3)
685 #define DWC3_EP_PENDING_REQUEST BIT(5)
686 #define DWC3_EP_END_TRANSFER_PENDING BIT(7)
688 /* This last one is specific to EP0 */
689 #define DWC3_EP0_DIR_IN BIT(31)
692 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
693 * use a u8 type here. If anybody decides to increase number of TRBs to
694 * anything larger than 256 - I can't see why people would want to do
695 * this though - then this type needs to be changed.
697 * By using u8 types we ensure that our % operator when incrementing
698 * enqueue and dequeue get optimized away by the compiler.
711 unsigned direction:1;
712 unsigned stream_capable:1;
716 DWC3_PHY_UNKNOWN = 0,
722 DWC3_EP0_UNKNOWN = 0,
725 DWC3_EP0_NRDY_STATUS,
728 enum dwc3_ep0_state {
735 enum dwc3_link_state {
737 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
738 DWC3_LINK_STATE_U1 = 0x01,
739 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
740 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
741 DWC3_LINK_STATE_SS_DIS = 0x04,
742 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
743 DWC3_LINK_STATE_SS_INACT = 0x06,
744 DWC3_LINK_STATE_POLL = 0x07,
745 DWC3_LINK_STATE_RECOV = 0x08,
746 DWC3_LINK_STATE_HRESET = 0x09,
747 DWC3_LINK_STATE_CMPLY = 0x0a,
748 DWC3_LINK_STATE_LPBK = 0x0b,
749 DWC3_LINK_STATE_RESET = 0x0e,
750 DWC3_LINK_STATE_RESUME = 0x0f,
751 DWC3_LINK_STATE_MASK = 0x0f,
754 /* TRB Length, PCM and Status */
755 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
756 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
757 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
758 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
760 #define DWC3_TRBSTS_OK 0
761 #define DWC3_TRBSTS_MISSED_ISOC 1
762 #define DWC3_TRBSTS_SETUP_PENDING 2
763 #define DWC3_TRB_STS_XFER_IN_PROG 4
766 #define DWC3_TRB_CTRL_HWO BIT(0)
767 #define DWC3_TRB_CTRL_LST BIT(1)
768 #define DWC3_TRB_CTRL_CHN BIT(2)
769 #define DWC3_TRB_CTRL_CSP BIT(3)
770 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
771 #define DWC3_TRB_CTRL_ISP_IMI BIT(10)
772 #define DWC3_TRB_CTRL_IOC BIT(11)
773 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
775 #define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
776 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
777 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
778 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
779 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
780 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
781 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
782 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
783 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
786 * struct dwc3_trb - transfer request block (hw format)
800 * struct dwc3_hwparams - copy of HWPARAMS registers
801 * @hwparams0: GHWPARAMS0
802 * @hwparams1: GHWPARAMS1
803 * @hwparams2: GHWPARAMS2
804 * @hwparams3: GHWPARAMS3
805 * @hwparams4: GHWPARAMS4
806 * @hwparams5: GHWPARAMS5
807 * @hwparams6: GHWPARAMS6
808 * @hwparams7: GHWPARAMS7
809 * @hwparams8: GHWPARAMS8
811 struct dwc3_hwparams {
824 #define DWC3_MODE(n) ((n) & 0x7)
826 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
829 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
832 #define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
833 #define DWC3_NUM_EPS_MASK (0x3f << 12)
834 #define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
835 (DWC3_NUM_EPS_MASK)) >> 12)
836 #define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
837 (DWC3_NUM_IN_EPS_MASK)) >> 18)
840 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
843 * struct dwc3_request - representation of a transfer request
844 * @request: struct usb_request to be transferred
845 * @list: a list_head used for request queueing
846 * @dep: struct dwc3_ep owning this request
847 * @sg: pointer to first incomplete sg
848 * @start_sg: pointer to the sg which should be queued next
849 * @num_pending_sgs: counter to pending sgs
850 * @num_queued_sgs: counter to the number of sgs which already got queued
851 * @remaining: amount of data remaining
852 * @epnum: endpoint number to which this request refers
853 * @trb: pointer to struct dwc3_trb
854 * @trb_dma: DMA address of @trb
855 * @num_trbs: number of TRBs used by this request
856 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
858 * @direction: IN or OUT direction flag
859 * @mapped: true when request has been dma-mapped
860 * @started: request is started
862 struct dwc3_request {
863 struct usb_request request;
864 struct list_head list;
866 struct scatterlist *sg;
867 struct scatterlist *start_sg;
869 unsigned num_pending_sgs;
870 unsigned int num_queued_sgs;
873 struct dwc3_trb *trb;
878 unsigned needs_extra_trb:1;
879 unsigned direction:1;
885 * struct dwc3_scratchpad_array - hibernation scratchpad array
886 * (format defined by hw)
888 struct dwc3_scratchpad_array {
889 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
893 * struct dwc3 - representation of our controller
894 * @drd_work: workqueue used for role swapping
895 * @ep0_trb: trb which is used for the ctrl_req
896 * @bounce: address of bounce buffer
897 * @scratchbuf: address of scratch buffer
898 * @setup_buf: used while precessing STD USB requests
899 * @ep0_trb_addr: dma address of @ep0_trb
900 * @bounce_addr: dma address of @bounce
901 * @ep0_usb_req: dummy req used while handling STD USB requests
902 * @scratch_addr: dma address of scratchbuf
903 * @ep0_in_setup: one control transfer is completed and enter setup phase
904 * @lock: for synchronizing
905 * @dev: pointer to our struct device
906 * @sysdev: pointer to the DMA-capable device
907 * @xhci: pointer to our xHCI child
908 * @xhci_resources: struct resources for our @xhci child
909 * @ev_buf: struct dwc3_event_buffer pointer
910 * @eps: endpoint array
911 * @gadget: device side representation of the peripheral controller
912 * @gadget_driver: pointer to the gadget driver
913 * @clks: array of clocks
914 * @num_clks: number of clocks
915 * @reset: reset control
916 * @regs: base address for our registers
917 * @regs_size: address space size
918 * @fladj: frame length adjustment
919 * @irq_gadget: peripheral controller's IRQ number
920 * @otg_irq: IRQ number for OTG IRQs
921 * @current_otg_role: current role of operation while using the OTG block
922 * @desired_otg_role: desired role of operation while using the OTG block
923 * @otg_restart_host: flag that OTG controller needs to restart host
924 * @nr_scratch: number of scratch buffers
925 * @u1u2: only used on revisions <1.83a for workaround
926 * @maximum_speed: maximum speed requested (mainly for testing purposes)
927 * @revision: revision register contents
928 * @dr_mode: requested mode of operation
929 * @current_dr_role: current role of operation when in dual-role mode
930 * @desired_dr_role: desired role of operation when in dual-role mode
931 * @edev: extcon handle
932 * @edev_nb: extcon notifier
933 * @hsphy_mode: UTMI phy mode, one of following:
934 * - USBPHY_INTERFACE_MODE_UTMI
935 * - USBPHY_INTERFACE_MODE_UTMIW
936 * @usb2_phy: pointer to USB2 PHY
937 * @usb3_phy: pointer to USB3 PHY
938 * @usb2_generic_phy: pointer to USB2 PHY
939 * @usb3_generic_phy: pointer to USB3 PHY
940 * @phys_ready: flag to indicate that PHYs are ready
941 * @ulpi: pointer to ulpi interface
942 * @ulpi_ready: flag to indicate that ULPI is initialized
943 * @u2sel: parameter from Set SEL request.
944 * @u2pel: parameter from Set SEL request.
945 * @u1sel: parameter from Set SEL request.
946 * @u1pel: parameter from Set SEL request.
947 * @num_eps: number of endpoints
948 * @ep0_next_event: hold the next expected event
949 * @ep0state: state of endpoint zero
950 * @link_state: link state
951 * @speed: device speed (super, high, full, low)
952 * @hwparams: copy of hwparams registers
953 * @root: debugfs root folder pointer
954 * @regset: debugfs pointer to regdump file
955 * @test_mode: true when we're entering a USB test mode
956 * @test_mode_nr: test feature selector
957 * @lpm_nyet_threshold: LPM NYET response threshold
958 * @hird_threshold: HIRD threshold
959 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
960 * @rx_max_burst_prd: max periodic ESS receive burst size
961 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
962 * @tx_max_burst_prd: max periodic ESS transmit burst size
963 * @hsphy_interface: "utmi" or "ulpi"
964 * @connected: true when we're connected to a host, false otherwise
965 * @delayed_status: true when gadget driver asks for delayed status
966 * @ep0_bounced: true when we used bounce buffer
967 * @ep0_expect_in: true when we expect a DATA IN transfer
968 * @has_hibernation: true when dwc3 was configured with Hibernation
969 * @sysdev_is_parent: true when dwc3 device has a parent driver
970 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
971 * there's now way for software to detect this in runtime.
972 * @is_utmi_l1_suspend: the core asserts output signal
974 * 1 - utmi_l1_suspend_n
975 * @is_fpga: true when we are using the FPGA board
976 * @pending_events: true when we have pending IRQs to be handled
977 * @pullups_connected: true when Run/Stop bit is set
978 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
979 * @three_stage_setup: set if we perform a three phase setup
980 * @usb3_lpm_capable: set if hadrware supports Link Power Management
981 * @disable_scramble_quirk: set if we enable the disable scramble quirk
982 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
983 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
984 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
985 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
986 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
987 * @lfps_filter_quirk: set if we enable LFPS filter quirk
988 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
989 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
990 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
991 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
992 * disabling the suspend signal to the PHY.
993 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
994 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
995 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
996 * provide a free-running PHY clock.
997 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
999 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1000 * check during HS transmit.
1001 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1002 * instances in park mode.
1003 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1004 * @tx_de_emphasis: Tx de-emphasis value
1005 * 0 - -6dB de-emphasis
1006 * 1 - -3.5dB de-emphasis
1007 * 2 - No de-emphasis
1009 * @dis_metastability_quirk: set to disable metastability quirk.
1010 * @imod_interval: set the interrupt moderation interval in 250ns
1011 * increments or 0 to disable.
1014 struct work_struct drd_work;
1015 struct dwc3_trb *ep0_trb;
1019 dma_addr_t ep0_trb_addr;
1020 dma_addr_t bounce_addr;
1021 dma_addr_t scratch_addr;
1022 struct dwc3_request ep0_usb_req;
1023 struct completion ep0_in_setup;
1029 struct device *sysdev;
1031 struct platform_device *xhci;
1032 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1034 struct dwc3_event_buffer *ev_buf;
1035 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1037 struct usb_gadget gadget;
1038 struct usb_gadget_driver *gadget_driver;
1040 struct clk_bulk_data *clks;
1043 struct reset_control *reset;
1045 struct usb_phy *usb2_phy;
1046 struct usb_phy *usb3_phy;
1048 struct phy *usb2_generic_phy;
1049 struct phy *usb3_generic_phy;
1059 enum usb_dr_mode dr_mode;
1060 u32 current_dr_role;
1061 u32 desired_dr_role;
1062 struct extcon_dev *edev;
1063 struct notifier_block edev_nb;
1064 enum usb_phy_interface hsphy_mode;
1069 u32 current_otg_role;
1070 u32 desired_otg_role;
1071 bool otg_restart_host;
1077 * All 3.1 IP version constants are greater than the 3.0 IP
1078 * version constants. This works for most version checks in
1079 * dwc3. However, in the future, this may not apply as
1080 * features may be developed on newer versions of the 3.0 IP
1081 * that are not in the 3.1 IP.
1085 #define DWC3_REVISION_173A 0x5533173a
1086 #define DWC3_REVISION_175A 0x5533175a
1087 #define DWC3_REVISION_180A 0x5533180a
1088 #define DWC3_REVISION_183A 0x5533183a
1089 #define DWC3_REVISION_185A 0x5533185a
1090 #define DWC3_REVISION_187A 0x5533187a
1091 #define DWC3_REVISION_188A 0x5533188a
1092 #define DWC3_REVISION_190A 0x5533190a
1093 #define DWC3_REVISION_194A 0x5533194a
1094 #define DWC3_REVISION_200A 0x5533200a
1095 #define DWC3_REVISION_202A 0x5533202a
1096 #define DWC3_REVISION_210A 0x5533210a
1097 #define DWC3_REVISION_220A 0x5533220a
1098 #define DWC3_REVISION_230A 0x5533230a
1099 #define DWC3_REVISION_240A 0x5533240a
1100 #define DWC3_REVISION_250A 0x5533250a
1101 #define DWC3_REVISION_260A 0x5533260a
1102 #define DWC3_REVISION_270A 0x5533270a
1103 #define DWC3_REVISION_280A 0x5533280a
1104 #define DWC3_REVISION_290A 0x5533290a
1105 #define DWC3_REVISION_300A 0x5533300a
1106 #define DWC3_REVISION_310A 0x5533310a
1109 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
1110 * just so dwc31 revisions are always larger than dwc3.
1112 #define DWC3_REVISION_IS_DWC31 0x80000000
1113 #define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_DWC31)
1114 #define DWC3_USB31_REVISION_120A (0x3132302a | DWC3_REVISION_IS_DWC31)
1116 enum dwc3_ep0_next ep0_next_event;
1117 enum dwc3_ep0_state ep0state;
1118 enum dwc3_link_state link_state;
1129 struct dwc3_hwparams hwparams;
1130 struct dentry *root;
1131 struct debugfs_regset32 *regset;
1135 u8 lpm_nyet_threshold;
1137 u8 rx_thr_num_pkt_prd;
1138 u8 rx_max_burst_prd;
1139 u8 tx_thr_num_pkt_prd;
1140 u8 tx_max_burst_prd;
1142 const char *hsphy_interface;
1144 unsigned connected:1;
1145 unsigned delayed_status:1;
1146 unsigned ep0_bounced:1;
1147 unsigned ep0_expect_in:1;
1148 unsigned has_hibernation:1;
1149 unsigned sysdev_is_parent:1;
1150 unsigned has_lpm_erratum:1;
1151 unsigned is_utmi_l1_suspend:1;
1153 unsigned pending_events:1;
1154 unsigned pullups_connected:1;
1155 unsigned setup_packet_pending:1;
1156 unsigned three_stage_setup:1;
1157 unsigned usb3_lpm_capable:1;
1159 unsigned disable_scramble_quirk:1;
1160 unsigned u2exit_lfps_quirk:1;
1161 unsigned u2ss_inp3_quirk:1;
1162 unsigned req_p1p2p3_quirk:1;
1163 unsigned del_p1p2p3_quirk:1;
1164 unsigned del_phy_power_chg_quirk:1;
1165 unsigned lfps_filter_quirk:1;
1166 unsigned rx_detect_poll_quirk:1;
1167 unsigned dis_u3_susphy_quirk:1;
1168 unsigned dis_u2_susphy_quirk:1;
1169 unsigned dis_enblslpm_quirk:1;
1170 unsigned dis_rxdet_inp3_quirk:1;
1171 unsigned dis_u2_freeclk_exists_quirk:1;
1172 unsigned dis_del_phy_power_chg_quirk:1;
1173 unsigned dis_tx_ipgap_linecheck_quirk:1;
1174 unsigned parkmode_disable_ss_quirk:1;
1176 unsigned tx_de_emphasis_quirk:1;
1177 unsigned tx_de_emphasis:2;
1179 unsigned dis_metastability_quirk:1;
1184 #define INCRX_BURST_MODE 0
1185 #define INCRX_UNDEF_LENGTH_BURST_MODE 1
1187 #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1189 /* -------------------------------------------------------------------------- */
1191 struct dwc3_event_type {
1194 u32 reserved8_31:24;
1197 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
1198 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
1199 #define DWC3_DEPEVT_XFERNOTREADY 0x03
1200 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1201 #define DWC3_DEPEVT_STREAMEVT 0x06
1202 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
1205 * struct dwc3_event_depvt - Device Endpoint Events
1206 * @one_bit: indicates this is an endpoint event (not used)
1207 * @endpoint_number: number of the endpoint
1208 * @endpoint_event: The event we have:
1210 * 0x01 - XferComplete
1211 * 0x02 - XferInProgress
1212 * 0x03 - XferNotReady
1213 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1217 * @reserved11_10: Reserved, don't use.
1218 * @status: Indicates the status of the event. Refer to databook for
1220 * @parameters: Parameters of the current event. Refer to databook for
1223 struct dwc3_event_depevt {
1225 u32 endpoint_number:5;
1226 u32 endpoint_event:4;
1227 u32 reserved11_10:2;
1230 /* Within XferNotReady */
1231 #define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1233 /* Within XferComplete or XferInProgress */
1234 #define DEPEVT_STATUS_BUSERR BIT(0)
1235 #define DEPEVT_STATUS_SHORT BIT(1)
1236 #define DEPEVT_STATUS_IOC BIT(2)
1237 #define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1238 #define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1240 /* Stream event only */
1241 #define DEPEVT_STREAMEVT_FOUND 1
1242 #define DEPEVT_STREAMEVT_NOTFOUND 2
1244 /* Control-only Status */
1245 #define DEPEVT_STATUS_CONTROL_DATA 1
1246 #define DEPEVT_STATUS_CONTROL_STATUS 2
1247 #define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1249 /* In response to Start Transfer */
1250 #define DEPEVT_TRANSFER_NO_RESOURCE 1
1251 #define DEPEVT_TRANSFER_BUS_EXPIRY 2
1255 /* For Command Complete Events */
1256 #define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1260 * struct dwc3_event_devt - Device Events
1261 * @one_bit: indicates this is a non-endpoint event (not used)
1262 * @device_event: indicates it's a device event. Should read as 0x00
1263 * @type: indicates the type of device event.
1276 * 12 - VndrDevTstRcved
1277 * @reserved15_12: Reserved, not used
1278 * @event_info: Information about this event
1279 * @reserved31_25: Reserved, not used
1281 struct dwc3_event_devt {
1285 u32 reserved15_12:4;
1287 u32 reserved31_25:7;
1291 * struct dwc3_event_gevt - Other Core Events
1292 * @one_bit: indicates this is a non-endpoint event (not used)
1293 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1294 * @phy_port_number: self-explanatory
1295 * @reserved31_12: Reserved, not used.
1297 struct dwc3_event_gevt {
1300 u32 phy_port_number:4;
1301 u32 reserved31_12:20;
1305 * union dwc3_event - representation of Event Buffer contents
1306 * @raw: raw 32-bit event
1307 * @type: the type of the event
1308 * @depevt: Device Endpoint Event
1309 * @devt: Device Event
1310 * @gevt: Global Event
1314 struct dwc3_event_type type;
1315 struct dwc3_event_depevt depevt;
1316 struct dwc3_event_devt devt;
1317 struct dwc3_event_gevt gevt;
1321 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1323 * @param2: third parameter
1324 * @param1: second parameter
1325 * @param0: first parameter
1327 struct dwc3_gadget_ep_cmd_params {
1334 * DWC3 Features to be used as Driver Data
1337 #define DWC3_HAS_PERIPHERAL BIT(0)
1338 #define DWC3_HAS_XHCI BIT(1)
1339 #define DWC3_HAS_OTG BIT(3)
1342 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1343 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1344 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1346 /* check whether we are on the DWC_usb3 core */
1347 static inline bool dwc3_is_usb3(struct dwc3 *dwc)
1349 return !(dwc->revision & DWC3_REVISION_IS_DWC31);
1352 /* check whether we are on the DWC_usb31 core */
1353 static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1355 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1358 bool dwc3_has_imod(struct dwc3 *dwc);
1360 int dwc3_event_buffers_setup(struct dwc3 *dwc);
1361 void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1363 #if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1364 int dwc3_host_init(struct dwc3 *dwc);
1365 void dwc3_host_exit(struct dwc3 *dwc);
1367 static inline int dwc3_host_init(struct dwc3 *dwc)
1369 static inline void dwc3_host_exit(struct dwc3 *dwc)
1373 #if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1374 int dwc3_gadget_init(struct dwc3 *dwc);
1375 void dwc3_gadget_exit(struct dwc3 *dwc);
1376 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1377 int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1378 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1379 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1380 struct dwc3_gadget_ep_cmd_params *params);
1381 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1383 static inline int dwc3_gadget_init(struct dwc3 *dwc)
1385 static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1387 static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1389 static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1391 static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1392 enum dwc3_link_state state)
1395 static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
1396 struct dwc3_gadget_ep_cmd_params *params)
1398 static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1403 #if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1404 int dwc3_drd_init(struct dwc3 *dwc);
1405 void dwc3_drd_exit(struct dwc3 *dwc);
1406 void dwc3_otg_init(struct dwc3 *dwc);
1407 void dwc3_otg_exit(struct dwc3 *dwc);
1408 void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1409 void dwc3_otg_host_init(struct dwc3 *dwc);
1411 static inline int dwc3_drd_init(struct dwc3 *dwc)
1413 static inline void dwc3_drd_exit(struct dwc3 *dwc)
1415 static inline void dwc3_otg_init(struct dwc3 *dwc)
1417 static inline void dwc3_otg_exit(struct dwc3 *dwc)
1419 static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1421 static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1425 /* power management interface */
1426 #if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1427 int dwc3_gadget_suspend(struct dwc3 *dwc);
1428 int dwc3_gadget_resume(struct dwc3 *dwc);
1429 void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1431 static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1436 static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1441 static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1444 #endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1446 #if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1447 int dwc3_ulpi_init(struct dwc3 *dwc);
1448 void dwc3_ulpi_exit(struct dwc3 *dwc);
1450 static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1452 static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1456 #endif /* __DRIVERS_USB_DWC3_CORE_H */