1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
65 "Controller does not support host mode.\n");
68 mode = USB_DR_MODE_PERIPHERAL;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
73 "Controller does not support device mode.\n");
76 mode = USB_DR_MODE_HOST;
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
96 if (mode != dwc->dr_mode) {
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
111 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
112 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
113 reg |= DWC3_GCTL_PRTCAPDIR(mode);
114 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
116 dwc->current_dr_role = mode;
119 static void __dwc3_set_mode(struct work_struct *work)
121 struct dwc3 *dwc = work_to_dwc(work);
127 mutex_lock(&dwc->mutex);
128 spin_lock_irqsave(&dwc->lock, flags);
129 desired_dr_role = dwc->desired_dr_role;
130 spin_unlock_irqrestore(&dwc->lock, flags);
132 pm_runtime_get_sync(dwc->dev);
134 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
135 dwc3_otg_update(dwc, 0);
137 if (!desired_dr_role)
140 if (desired_dr_role == dwc->current_dr_role)
143 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
146 switch (dwc->current_dr_role) {
147 case DWC3_GCTL_PRTCAP_HOST:
150 case DWC3_GCTL_PRTCAP_DEVICE:
151 dwc3_gadget_exit(dwc);
152 dwc3_event_buffers_cleanup(dwc);
154 case DWC3_GCTL_PRTCAP_OTG:
156 spin_lock_irqsave(&dwc->lock, flags);
157 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
158 spin_unlock_irqrestore(&dwc->lock, flags);
159 dwc3_otg_update(dwc, 1);
166 * When current_dr_role is not set, there's no role switching.
167 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
169 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
170 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
171 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
172 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
173 reg |= DWC3_GCTL_CORESOFTRESET;
174 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
177 * Wait for internal clocks to synchronized. DWC_usb31 and
178 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
179 * keep it consistent across different IPs, let's wait up to
180 * 100ms before clearing GCTL.CORESOFTRESET.
184 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
185 reg &= ~DWC3_GCTL_CORESOFTRESET;
186 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
189 spin_lock_irqsave(&dwc->lock, flags);
191 dwc3_set_prtcap(dwc, desired_dr_role);
193 spin_unlock_irqrestore(&dwc->lock, flags);
195 switch (desired_dr_role) {
196 case DWC3_GCTL_PRTCAP_HOST:
197 ret = dwc3_host_init(dwc);
199 dev_err(dwc->dev, "failed to initialize host\n");
202 otg_set_vbus(dwc->usb2_phy->otg, true);
203 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
204 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
205 if (dwc->dis_split_quirk) {
206 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
207 reg |= DWC3_GUCTL3_SPLITDISABLE;
208 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
212 case DWC3_GCTL_PRTCAP_DEVICE:
213 dwc3_core_soft_reset(dwc);
215 dwc3_event_buffers_setup(dwc);
218 otg_set_vbus(dwc->usb2_phy->otg, false);
219 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
220 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
222 ret = dwc3_gadget_init(dwc);
224 dev_err(dwc->dev, "failed to initialize peripheral\n");
226 case DWC3_GCTL_PRTCAP_OTG:
228 dwc3_otg_update(dwc, 0);
235 pm_runtime_mark_last_busy(dwc->dev);
236 pm_runtime_put_autosuspend(dwc->dev);
237 mutex_unlock(&dwc->mutex);
240 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
244 if (dwc->dr_mode != USB_DR_MODE_OTG)
247 spin_lock_irqsave(&dwc->lock, flags);
248 dwc->desired_dr_role = mode;
249 spin_unlock_irqrestore(&dwc->lock, flags);
251 queue_work(system_freezable_wq, &dwc->drd_work);
254 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
256 struct dwc3 *dwc = dep->dwc;
259 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
260 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
261 DWC3_GDBGFIFOSPACE_TYPE(type));
263 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
265 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
269 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
270 * @dwc: pointer to our context structure
272 int dwc3_core_soft_reset(struct dwc3 *dwc)
278 * We're resetting only the device side because, if we're in host mode,
279 * XHCI driver will reset the host block. If dwc3 was configured for
280 * host-only mode, then we can return early.
282 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
285 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
286 reg |= DWC3_DCTL_CSFTRST;
287 reg &= ~DWC3_DCTL_RUN_STOP;
288 dwc3_gadget_dctl_write_safe(dwc, reg);
291 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
292 * is cleared only after all the clocks are synchronized. This can
293 * take a little more than 50ms. Set the polling rate at 20ms
294 * for 10 times instead.
296 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
300 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
301 if (!(reg & DWC3_DCTL_CSFTRST))
304 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
310 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
315 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
316 * is cleared, we must wait at least 50ms before accessing the PHY
317 * domain (synchronization delay).
319 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
326 * dwc3_frame_length_adjustment - Adjusts frame length if required
327 * @dwc3: Pointer to our controller context structure
329 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
334 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
340 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
341 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
342 if (dft != dwc->fladj) {
343 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
344 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
345 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
350 * dwc3_ref_clk_period - Reference clock period configuration
351 * Default reference clock period depends on hardware
352 * configuration. For systems with reference clock that differs
353 * from the default, this will set clock period in DWC3_GUCTL
355 * @dwc: Pointer to our controller context structure
357 static void dwc3_ref_clk_period(struct dwc3 *dwc)
359 unsigned long period;
366 rate = clk_get_rate(dwc->ref_clk);
369 period = NSEC_PER_SEC / rate;
370 } else if (dwc->ref_clk_per) {
371 period = dwc->ref_clk_per;
372 rate = NSEC_PER_SEC / period;
377 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
378 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
379 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
380 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
382 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
386 * The calculation below is
388 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
390 * but rearranged for fixed-point arithmetic. The division must be
391 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
392 * neither does rate * period).
394 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
395 * nanoseconds of error caused by the truncation which happened during
396 * the division when calculating rate or period (whichever one was
397 * derived from the other). We first calculate the relative error, then
398 * scale it to units of 8 ppm.
400 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
404 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
406 decr = 480000000 / rate;
408 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
409 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
410 & ~DWC3_GFLADJ_240MHZDECR
411 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
412 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
413 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
414 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
416 if (dwc->gfladj_refclk_lpm_sel)
417 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
419 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
423 * dwc3_free_one_event_buffer - Frees one event buffer
424 * @dwc: Pointer to our controller context structure
425 * @evt: Pointer to event buffer to be freed
427 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
428 struct dwc3_event_buffer *evt)
430 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
434 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
435 * @dwc: Pointer to our controller context structure
436 * @length: size of the event buffer
438 * Returns a pointer to the allocated event buffer structure on success
439 * otherwise ERR_PTR(errno).
441 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
444 struct dwc3_event_buffer *evt;
446 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
448 return ERR_PTR(-ENOMEM);
451 evt->length = length;
452 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
454 return ERR_PTR(-ENOMEM);
456 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
457 &evt->dma, GFP_KERNEL);
459 return ERR_PTR(-ENOMEM);
465 * dwc3_free_event_buffers - frees all allocated event buffers
466 * @dwc: Pointer to our controller context structure
468 static void dwc3_free_event_buffers(struct dwc3 *dwc)
470 struct dwc3_event_buffer *evt;
474 dwc3_free_one_event_buffer(dwc, evt);
478 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
479 * @dwc: pointer to our controller context structure
480 * @length: size of event buffer
482 * Returns 0 on success otherwise negative errno. In the error case, dwc
483 * may contain some buffers allocated but not all which were requested.
485 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
487 struct dwc3_event_buffer *evt;
489 evt = dwc3_alloc_one_event_buffer(dwc, length);
491 dev_err(dwc->dev, "can't allocate event buffer\n");
500 * dwc3_event_buffers_setup - setup our allocated event buffers
501 * @dwc: pointer to our controller context structure
503 * Returns 0 on success otherwise negative errno.
505 int dwc3_event_buffers_setup(struct dwc3 *dwc)
507 struct dwc3_event_buffer *evt;
511 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
512 lower_32_bits(evt->dma));
513 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
514 upper_32_bits(evt->dma));
515 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
516 DWC3_GEVNTSIZ_SIZE(evt->length));
517 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
522 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
524 struct dwc3_event_buffer *evt;
530 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
531 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
532 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
533 | DWC3_GEVNTSIZ_SIZE(0));
534 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
537 static void dwc3_core_num_eps(struct dwc3 *dwc)
539 struct dwc3_hwparams *parms = &dwc->hwparams;
541 dwc->num_eps = DWC3_NUM_EPS(parms);
544 static void dwc3_cache_hwparams(struct dwc3 *dwc)
546 struct dwc3_hwparams *parms = &dwc->hwparams;
548 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
549 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
550 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
551 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
552 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
553 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
554 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
555 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
556 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
558 if (DWC3_IP_IS(DWC32))
559 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
562 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
567 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
569 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
570 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
571 dwc->hsphy_interface &&
572 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
573 ret = dwc3_ulpi_init(dwc);
579 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
580 * @dwc: Pointer to our controller context structure
582 * Returns 0 on success. The USB PHY interfaces are configured but not
583 * initialized. The PHY interfaces and the PHYs get initialized together with
584 * the core in dwc3_core_init.
586 static int dwc3_phy_setup(struct dwc3 *dwc)
588 unsigned int hw_mode;
591 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
593 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
596 * Make sure UX_EXIT_PX is cleared as that causes issues with some
597 * PHYs. Also, this bit is not supposed to be used in normal operation.
599 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
602 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
603 * to '0' during coreConsultant configuration. So default value
604 * will be '0' when the core is reset. Application needs to set it
605 * to '1' after the core initialization is completed.
607 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
608 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
611 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
612 * power-on reset, and it can be set after core initialization, which is
613 * after device soft-reset during initialization.
615 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
616 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
618 if (dwc->u2ss_inp3_quirk)
619 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
621 if (dwc->dis_rxdet_inp3_quirk)
622 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
624 if (dwc->req_p1p2p3_quirk)
625 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
627 if (dwc->del_p1p2p3_quirk)
628 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
630 if (dwc->del_phy_power_chg_quirk)
631 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
633 if (dwc->lfps_filter_quirk)
634 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
636 if (dwc->rx_detect_poll_quirk)
637 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
639 if (dwc->tx_de_emphasis_quirk)
640 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
642 if (dwc->dis_u3_susphy_quirk)
643 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
645 if (dwc->dis_del_phy_power_chg_quirk)
646 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
648 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
650 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
652 /* Select the HS PHY interface */
653 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
654 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
655 if (dwc->hsphy_interface &&
656 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
657 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
659 } else if (dwc->hsphy_interface &&
660 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
661 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
662 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
664 /* Relying on default value. */
665 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
669 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
674 switch (dwc->hsphy_mode) {
675 case USBPHY_INTERFACE_MODE_UTMI:
676 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
677 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
678 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
679 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
681 case USBPHY_INTERFACE_MODE_UTMIW:
682 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
683 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
684 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
685 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
692 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
693 * '0' during coreConsultant configuration. So default value will
694 * be '0' when the core is reset. Application needs to set it to
695 * '1' after the core initialization is completed.
697 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
698 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
701 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
702 * power-on reset, and it can be set after core initialization, which is
703 * after device soft-reset during initialization.
705 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
706 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
708 if (dwc->dis_u2_susphy_quirk)
709 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
711 if (dwc->dis_enblslpm_quirk)
712 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
714 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
716 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
717 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
720 * Some ULPI USB PHY does not support internal VBUS supply, to drive
721 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
722 * bit of OTG_CTRL register. Controller configures the USB2 PHY
723 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
724 * with an external supply.
726 if (dwc->ulpi_ext_vbus_drv)
727 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
729 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
734 static int dwc3_phy_init(struct dwc3 *dwc)
738 usb_phy_init(dwc->usb2_phy);
739 usb_phy_init(dwc->usb3_phy);
741 ret = phy_init(dwc->usb2_generic_phy);
743 goto err_shutdown_usb3_phy;
745 ret = phy_init(dwc->usb3_generic_phy);
747 goto err_exit_usb2_phy;
752 phy_exit(dwc->usb2_generic_phy);
753 err_shutdown_usb3_phy:
754 usb_phy_shutdown(dwc->usb3_phy);
755 usb_phy_shutdown(dwc->usb2_phy);
760 static void dwc3_phy_exit(struct dwc3 *dwc)
762 phy_exit(dwc->usb3_generic_phy);
763 phy_exit(dwc->usb2_generic_phy);
765 usb_phy_shutdown(dwc->usb3_phy);
766 usb_phy_shutdown(dwc->usb2_phy);
769 static int dwc3_phy_power_on(struct dwc3 *dwc)
773 usb_phy_set_suspend(dwc->usb2_phy, 0);
774 usb_phy_set_suspend(dwc->usb3_phy, 0);
776 ret = phy_power_on(dwc->usb2_generic_phy);
778 goto err_suspend_usb3_phy;
780 ret = phy_power_on(dwc->usb3_generic_phy);
782 goto err_power_off_usb2_phy;
786 err_power_off_usb2_phy:
787 phy_power_off(dwc->usb2_generic_phy);
788 err_suspend_usb3_phy:
789 usb_phy_set_suspend(dwc->usb3_phy, 1);
790 usb_phy_set_suspend(dwc->usb2_phy, 1);
795 static void dwc3_phy_power_off(struct dwc3 *dwc)
797 phy_power_off(dwc->usb3_generic_phy);
798 phy_power_off(dwc->usb2_generic_phy);
800 usb_phy_set_suspend(dwc->usb3_phy, 1);
801 usb_phy_set_suspend(dwc->usb2_phy, 1);
804 static int dwc3_clk_enable(struct dwc3 *dwc)
808 ret = clk_prepare_enable(dwc->bus_clk);
812 ret = clk_prepare_enable(dwc->ref_clk);
814 goto disable_bus_clk;
816 ret = clk_prepare_enable(dwc->susp_clk);
818 goto disable_ref_clk;
820 ret = clk_prepare_enable(dwc->utmi_clk);
822 goto disable_susp_clk;
824 ret = clk_prepare_enable(dwc->pipe_clk);
826 goto disable_utmi_clk;
831 clk_disable_unprepare(dwc->utmi_clk);
833 clk_disable_unprepare(dwc->susp_clk);
835 clk_disable_unprepare(dwc->ref_clk);
837 clk_disable_unprepare(dwc->bus_clk);
841 static void dwc3_clk_disable(struct dwc3 *dwc)
843 clk_disable_unprepare(dwc->pipe_clk);
844 clk_disable_unprepare(dwc->utmi_clk);
845 clk_disable_unprepare(dwc->susp_clk);
846 clk_disable_unprepare(dwc->ref_clk);
847 clk_disable_unprepare(dwc->bus_clk);
850 static void dwc3_core_exit(struct dwc3 *dwc)
852 dwc3_event_buffers_cleanup(dwc);
853 dwc3_phy_power_off(dwc);
855 dwc3_clk_disable(dwc);
856 reset_control_assert(dwc->reset);
859 static bool dwc3_core_is_valid(struct dwc3 *dwc)
863 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
864 dwc->ip = DWC3_GSNPS_ID(reg);
866 /* This should read as U3 followed by revision number */
867 if (DWC3_IP_IS(DWC3)) {
869 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
870 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
871 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
879 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
883 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
884 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
886 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
887 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
889 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
890 * issue which would cause xHCI compliance tests to fail.
892 * Because of that we cannot enable clock gating on such
897 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
900 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
901 dwc->dr_mode == USB_DR_MODE_OTG) &&
902 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
903 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
905 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
907 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
909 * REVISIT Enabling this bit so that host-mode hibernation
910 * will work. Device-mode hibernation is not yet implemented.
912 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
919 /* check if current dwc3 is on simulation board */
920 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
921 dev_info(dwc->dev, "Running with FPGA optimizations\n");
925 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
926 "disable_scramble cannot be used on non-FPGA builds\n");
928 if (dwc->disable_scramble_quirk && dwc->is_fpga)
929 reg |= DWC3_GCTL_DISSCRAMBLE;
931 reg &= ~DWC3_GCTL_DISSCRAMBLE;
933 if (dwc->u2exit_lfps_quirk)
934 reg |= DWC3_GCTL_U2EXIT_LFPS;
937 * WORKAROUND: DWC3 revisions <1.90a have a bug
938 * where the device can fail to connect at SuperSpeed
939 * and falls back to high-speed mode which causes
940 * the device to enter a Connect/Disconnect loop
942 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
943 reg |= DWC3_GCTL_U2RSTECN;
945 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
948 static int dwc3_core_get_phy(struct dwc3 *dwc);
949 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
951 /* set global incr burst type configuration registers */
952 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
954 struct device *dev = dwc->dev;
955 /* incrx_mode : for INCR burst type. */
957 /* incrx_size : for size of INCRX burst. */
965 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
968 * Handle property "snps,incr-burst-type-adjustment".
969 * Get the number of value from this property:
970 * result <= 0, means this property is not supported.
971 * result = 1, means INCRx burst mode supported.
972 * result > 1, means undefined length burst mode supported.
974 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
978 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
982 /* Get INCR burst type, and parse it */
983 ret = device_property_read_u32_array(dev,
984 "snps,incr-burst-type-adjustment", vals, ntype);
987 dev_err(dev, "Error to get property\n");
994 /* INCRX (undefined length) burst mode */
995 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
996 for (i = 1; i < ntype; i++) {
997 if (vals[i] > incrx_size)
998 incrx_size = vals[i];
1001 /* INCRX burst mode */
1002 incrx_mode = INCRX_BURST_MODE;
1007 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1008 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1010 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1011 switch (incrx_size) {
1013 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1016 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1019 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1022 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1025 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1028 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1031 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1036 dev_err(dev, "Invalid property\n");
1040 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1043 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1052 * The power down scale field specifies how many suspend_clk
1053 * periods fit into a 16KHz clock period. When performing
1054 * the division, round up the remainder.
1056 * The power down scale value is calculated using the fastest
1057 * frequency of the suspend_clk. If it isn't fixed (but within
1058 * the accuracy requirement), the driver may not know the max
1059 * rate of the suspend_clk, so only update the power down scale
1060 * if the default is less than the calculated value from
1061 * clk_get_rate() or if the default is questionably high
1062 * (3x or more) to be within the requirement.
1064 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1065 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1066 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1067 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1068 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1069 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1070 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1074 static void dwc3_config_threshold(struct dwc3 *dwc)
1083 * Must config both number of packets and max burst settings to enable
1084 * RX and/or TX threshold.
1086 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1087 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1088 rx_maxburst = dwc->rx_max_burst_prd;
1089 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1090 tx_maxburst = dwc->tx_max_burst_prd;
1092 if (rx_thr_num && rx_maxburst) {
1093 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1094 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1096 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1097 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1099 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1100 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1102 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1105 if (tx_thr_num && tx_maxburst) {
1106 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1107 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1109 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1110 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1112 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1113 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1115 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1119 rx_thr_num = dwc->rx_thr_num_pkt;
1120 rx_maxburst = dwc->rx_max_burst;
1121 tx_thr_num = dwc->tx_thr_num_pkt;
1122 tx_maxburst = dwc->tx_max_burst;
1124 if (DWC3_IP_IS(DWC3)) {
1125 if (rx_thr_num && rx_maxburst) {
1126 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1127 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1129 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1130 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1132 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1133 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1135 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1138 if (tx_thr_num && tx_maxburst) {
1139 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1140 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1142 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1143 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1145 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1146 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1148 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1151 if (rx_thr_num && rx_maxburst) {
1152 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1153 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1155 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1156 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1158 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1159 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1161 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1164 if (tx_thr_num && tx_maxburst) {
1165 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1166 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1168 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1169 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1171 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1172 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1174 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1180 * dwc3_core_init - Low-level initialization of DWC3 Core
1181 * @dwc: Pointer to our controller context structure
1183 * Returns 0 on success otherwise negative errno.
1185 static int dwc3_core_init(struct dwc3 *dwc)
1187 unsigned int hw_mode;
1191 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1194 * Write Linux Version Code to our GUID register so it's easy to figure
1195 * out which kernel version a bug was found.
1197 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1199 ret = dwc3_phy_setup(dwc);
1203 if (!dwc->ulpi_ready) {
1204 ret = dwc3_core_ulpi_init(dwc);
1206 if (ret == -ETIMEDOUT) {
1207 dwc3_core_soft_reset(dwc);
1208 ret = -EPROBE_DEFER;
1212 dwc->ulpi_ready = true;
1215 if (!dwc->phys_ready) {
1216 ret = dwc3_core_get_phy(dwc);
1219 dwc->phys_ready = true;
1222 ret = dwc3_phy_init(dwc);
1226 ret = dwc3_core_soft_reset(dwc);
1230 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1231 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1232 if (!dwc->dis_u3_susphy_quirk) {
1233 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1234 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1235 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1238 if (!dwc->dis_u2_susphy_quirk) {
1239 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1240 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1241 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1245 dwc3_core_setup_global_control(dwc);
1246 dwc3_core_num_eps(dwc);
1248 /* Set power down scale of suspend_clk */
1249 dwc3_set_power_down_clk_scale(dwc);
1251 /* Adjust Frame Length */
1252 dwc3_frame_length_adjustment(dwc);
1254 /* Adjust Reference Clock Period */
1255 dwc3_ref_clk_period(dwc);
1257 dwc3_set_incr_burst_type(dwc);
1259 ret = dwc3_phy_power_on(dwc);
1263 ret = dwc3_event_buffers_setup(dwc);
1265 dev_err(dwc->dev, "failed to setup event buffers\n");
1266 goto err_power_off_phy;
1270 * ENDXFER polling is available on version 3.10a and later of
1271 * the DWC_usb3 controller. It is NOT available in the
1272 * DWC_usb31 controller.
1274 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1275 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1276 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1277 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1281 * When configured in HOST mode, after issuing U3/L2 exit controller
1282 * fails to send proper CRC checksum in CRC5 feild. Because of this
1283 * behaviour Transaction Error is generated, resulting in reset and
1284 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1285 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1286 * will correct this problem. This option is to support certain
1289 if (dwc->resume_hs_terminations) {
1290 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1291 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1292 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1295 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1296 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1299 * Enable hardware control of sending remote wakeup
1300 * in HS when the device is in the L1 state.
1302 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1303 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1306 * Decouple USB 2.0 L1 & L2 events which will allow for
1307 * gadget driver to only receive U3/L2 suspend & wakeup
1308 * events and prevent the more frequent L1 LPM transitions
1309 * from interrupting the driver.
1311 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1312 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1314 if (dwc->dis_tx_ipgap_linecheck_quirk)
1315 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1317 if (dwc->parkmode_disable_ss_quirk)
1318 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1320 if (dwc->parkmode_disable_hs_quirk)
1321 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1323 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1324 (dwc->maximum_speed == USB_SPEED_HIGH ||
1325 dwc->maximum_speed == USB_SPEED_FULL))
1326 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1328 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1331 dwc3_config_threshold(dwc);
1336 dwc3_phy_power_off(dwc);
1340 dwc3_ulpi_exit(dwc);
1345 static int dwc3_core_get_phy(struct dwc3 *dwc)
1347 struct device *dev = dwc->dev;
1348 struct device_node *node = dev->of_node;
1352 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1353 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1355 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1356 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1359 if (IS_ERR(dwc->usb2_phy)) {
1360 ret = PTR_ERR(dwc->usb2_phy);
1361 if (ret == -ENXIO || ret == -ENODEV)
1362 dwc->usb2_phy = NULL;
1364 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1367 if (IS_ERR(dwc->usb3_phy)) {
1368 ret = PTR_ERR(dwc->usb3_phy);
1369 if (ret == -ENXIO || ret == -ENODEV)
1370 dwc->usb3_phy = NULL;
1372 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1375 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1376 if (IS_ERR(dwc->usb2_generic_phy)) {
1377 ret = PTR_ERR(dwc->usb2_generic_phy);
1378 if (ret == -ENOSYS || ret == -ENODEV)
1379 dwc->usb2_generic_phy = NULL;
1381 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1384 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1385 if (IS_ERR(dwc->usb3_generic_phy)) {
1386 ret = PTR_ERR(dwc->usb3_generic_phy);
1387 if (ret == -ENOSYS || ret == -ENODEV)
1388 dwc->usb3_generic_phy = NULL;
1390 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1396 static int dwc3_core_init_mode(struct dwc3 *dwc)
1398 struct device *dev = dwc->dev;
1401 switch (dwc->dr_mode) {
1402 case USB_DR_MODE_PERIPHERAL:
1403 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1406 otg_set_vbus(dwc->usb2_phy->otg, false);
1407 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1408 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1410 ret = dwc3_gadget_init(dwc);
1412 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1414 case USB_DR_MODE_HOST:
1415 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1418 otg_set_vbus(dwc->usb2_phy->otg, true);
1419 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1420 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1422 ret = dwc3_host_init(dwc);
1424 return dev_err_probe(dev, ret, "failed to initialize host\n");
1426 case USB_DR_MODE_OTG:
1427 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1428 ret = dwc3_drd_init(dwc);
1430 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1433 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1440 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1442 switch (dwc->dr_mode) {
1443 case USB_DR_MODE_PERIPHERAL:
1444 dwc3_gadget_exit(dwc);
1446 case USB_DR_MODE_HOST:
1447 dwc3_host_exit(dwc);
1449 case USB_DR_MODE_OTG:
1457 /* de-assert DRVVBUS for HOST and OTG mode */
1458 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1461 static void dwc3_get_properties(struct dwc3 *dwc)
1463 struct device *dev = dwc->dev;
1464 u8 lpm_nyet_threshold;
1467 u8 rx_thr_num_pkt = 0;
1468 u8 rx_max_burst = 0;
1469 u8 tx_thr_num_pkt = 0;
1470 u8 tx_max_burst = 0;
1471 u8 rx_thr_num_pkt_prd = 0;
1472 u8 rx_max_burst_prd = 0;
1473 u8 tx_thr_num_pkt_prd = 0;
1474 u8 tx_max_burst_prd = 0;
1475 u8 tx_fifo_resize_max_num;
1476 const char *usb_psy_name;
1479 /* default to highest possible threshold */
1480 lpm_nyet_threshold = 0xf;
1482 /* default to -3.5dB de-emphasis */
1486 * default to assert utmi_sleep_n and use maximum allowed HIRD
1487 * threshold value of 0b1100
1489 hird_threshold = 12;
1492 * default to a TXFIFO size large enough to fit 6 max packets. This
1493 * allows for systems with larger bus latencies to have some headroom
1494 * for endpoints that have a large bMaxBurst value.
1496 tx_fifo_resize_max_num = 6;
1498 dwc->maximum_speed = usb_get_maximum_speed(dev);
1499 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1500 dwc->dr_mode = usb_get_dr_mode(dev);
1501 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1503 dwc->sysdev_is_parent = device_property_read_bool(dev,
1504 "linux,sysdev_is_parent");
1505 if (dwc->sysdev_is_parent)
1506 dwc->sysdev = dwc->dev->parent;
1508 dwc->sysdev = dwc->dev;
1510 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1512 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1514 dev_err(dev, "couldn't get usb power supply\n");
1517 dwc->has_lpm_erratum = device_property_read_bool(dev,
1518 "snps,has-lpm-erratum");
1519 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1520 &lpm_nyet_threshold);
1521 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1522 "snps,is-utmi-l1-suspend");
1523 device_property_read_u8(dev, "snps,hird-threshold",
1525 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1526 "snps,dis-start-transfer-quirk");
1527 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1528 "snps,usb3_lpm_capable");
1529 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1530 "snps,usb2-lpm-disable");
1531 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1532 "snps,usb2-gadget-lpm-disable");
1533 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1535 device_property_read_u8(dev, "snps,rx-max-burst",
1537 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1539 device_property_read_u8(dev, "snps,tx-max-burst",
1541 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1542 &rx_thr_num_pkt_prd);
1543 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1545 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1546 &tx_thr_num_pkt_prd);
1547 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1549 dwc->do_fifo_resize = device_property_read_bool(dev,
1551 if (dwc->do_fifo_resize)
1552 device_property_read_u8(dev, "tx-fifo-max-num",
1553 &tx_fifo_resize_max_num);
1555 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1556 "snps,disable_scramble_quirk");
1557 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1558 "snps,u2exit_lfps_quirk");
1559 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1560 "snps,u2ss_inp3_quirk");
1561 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1562 "snps,req_p1p2p3_quirk");
1563 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1564 "snps,del_p1p2p3_quirk");
1565 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1566 "snps,del_phy_power_chg_quirk");
1567 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1568 "snps,lfps_filter_quirk");
1569 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1570 "snps,rx_detect_poll_quirk");
1571 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1572 "snps,dis_u3_susphy_quirk");
1573 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1574 "snps,dis_u2_susphy_quirk");
1575 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1576 "snps,dis_enblslpm_quirk");
1577 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1578 "snps,dis-u1-entry-quirk");
1579 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1580 "snps,dis-u2-entry-quirk");
1581 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1582 "snps,dis_rxdet_inp3_quirk");
1583 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1584 "snps,dis-u2-freeclk-exists-quirk");
1585 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1586 "snps,dis-del-phy-power-chg-quirk");
1587 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1588 "snps,dis-tx-ipgap-linecheck-quirk");
1589 dwc->resume_hs_terminations = device_property_read_bool(dev,
1590 "snps,resume-hs-terminations");
1591 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1592 "snps,ulpi-ext-vbus-drv");
1593 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1594 "snps,parkmode-disable-ss-quirk");
1595 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1596 "snps,parkmode-disable-hs-quirk");
1597 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1598 "snps,gfladj-refclk-lpm-sel-quirk");
1600 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1601 "snps,tx_de_emphasis_quirk");
1602 device_property_read_u8(dev, "snps,tx_de_emphasis",
1604 device_property_read_string(dev, "snps,hsphy_interface",
1605 &dwc->hsphy_interface);
1606 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1608 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1611 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1612 "snps,dis_metastability_quirk");
1614 dwc->dis_split_quirk = device_property_read_bool(dev,
1615 "snps,dis-split-quirk");
1617 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1618 dwc->tx_de_emphasis = tx_de_emphasis;
1620 dwc->hird_threshold = hird_threshold;
1622 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1623 dwc->rx_max_burst = rx_max_burst;
1625 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1626 dwc->tx_max_burst = tx_max_burst;
1628 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1629 dwc->rx_max_burst_prd = rx_max_burst_prd;
1631 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1632 dwc->tx_max_burst_prd = tx_max_burst_prd;
1634 dwc->imod_interval = 0;
1636 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1639 /* check whether the core supports IMOD */
1640 bool dwc3_has_imod(struct dwc3 *dwc)
1642 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1643 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1647 static void dwc3_check_params(struct dwc3 *dwc)
1649 struct device *dev = dwc->dev;
1650 unsigned int hwparam_gen =
1651 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1653 /* Check for proper value of imod_interval */
1654 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1655 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1656 dwc->imod_interval = 0;
1660 * Workaround for STAR 9000961433 which affects only version
1661 * 3.00a of the DWC_usb3 core. This prevents the controller
1662 * interrupt from being masked while handling events. IMOD
1663 * allows us to work around this issue. Enable it for the
1666 if (!dwc->imod_interval &&
1667 DWC3_VER_IS(DWC3, 300A))
1668 dwc->imod_interval = 1;
1670 /* Check the maximum_speed parameter */
1671 switch (dwc->maximum_speed) {
1672 case USB_SPEED_FULL:
1673 case USB_SPEED_HIGH:
1675 case USB_SPEED_SUPER:
1676 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1677 dev_warn(dev, "UDC doesn't support Gen 1\n");
1679 case USB_SPEED_SUPER_PLUS:
1680 if ((DWC3_IP_IS(DWC32) &&
1681 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1682 (!DWC3_IP_IS(DWC32) &&
1683 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1684 dev_warn(dev, "UDC doesn't support SSP\n");
1687 dev_err(dev, "invalid maximum_speed parameter %d\n",
1688 dwc->maximum_speed);
1690 case USB_SPEED_UNKNOWN:
1691 switch (hwparam_gen) {
1692 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1693 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1695 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1696 if (DWC3_IP_IS(DWC32))
1697 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1699 dwc->maximum_speed = USB_SPEED_SUPER;
1701 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1702 dwc->maximum_speed = USB_SPEED_HIGH;
1705 dwc->maximum_speed = USB_SPEED_SUPER;
1712 * Currently the controller does not have visibility into the HW
1713 * parameter to determine the maximum number of lanes the HW supports.
1714 * If the number of lanes is not specified in the device property, then
1715 * set the default to support dual-lane for DWC_usb32 and single-lane
1716 * for DWC_usb31 for super-speed-plus.
1718 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1719 switch (dwc->max_ssp_rate) {
1720 case USB_SSP_GEN_2x1:
1721 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1722 dev_warn(dev, "UDC only supports Gen 1\n");
1724 case USB_SSP_GEN_1x2:
1725 case USB_SSP_GEN_2x2:
1726 if (DWC3_IP_IS(DWC31))
1727 dev_warn(dev, "UDC only supports single lane\n");
1729 case USB_SSP_GEN_UNKNOWN:
1731 switch (hwparam_gen) {
1732 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1733 if (DWC3_IP_IS(DWC32))
1734 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1736 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1738 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1739 if (DWC3_IP_IS(DWC32))
1740 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1748 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1750 struct device *dev = dwc->dev;
1751 struct device_node *np_phy;
1752 struct extcon_dev *edev = NULL;
1755 if (device_property_read_bool(dev, "extcon"))
1756 return extcon_get_edev_by_phandle(dev, 0);
1759 * Device tree platforms should get extcon via phandle.
1760 * On ACPI platforms, we get the name from a device property.
1761 * This device property is for kernel internal use only and
1762 * is expected to be set by the glue code.
1764 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1765 return extcon_get_extcon_dev(name);
1768 * Check explicitly if "usb-role-switch" is used since
1769 * extcon_find_edev_by_node() can not be used to check the absence of
1770 * an extcon device. In the absence of an device it will always return
1773 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1774 device_property_read_bool(dev, "usb-role-switch"))
1778 * Try to get an extcon device from the USB PHY controller's "port"
1779 * node. Check if it has the "port" node first, to avoid printing the
1780 * error message from underlying code, as it's a valid case: extcon
1781 * device (and "port" node) may be missing in case of "usb-role-switch"
1784 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1785 if (of_graph_is_present(np_phy)) {
1786 struct device_node *np_conn;
1788 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1790 edev = extcon_find_edev_by_node(np_conn);
1791 of_node_put(np_conn);
1793 of_node_put(np_phy);
1798 static int dwc3_get_clocks(struct dwc3 *dwc)
1800 struct device *dev = dwc->dev;
1806 * Clocks are optional, but new DT platforms should support all clocks
1807 * as required by the DT-binding.
1808 * Some devices have different clock names in legacy device trees,
1809 * check for them to retain backwards compatibility.
1811 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1812 if (IS_ERR(dwc->bus_clk)) {
1813 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1814 "could not get bus clock\n");
1817 if (dwc->bus_clk == NULL) {
1818 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1819 if (IS_ERR(dwc->bus_clk)) {
1820 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1821 "could not get bus clock\n");
1825 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1826 if (IS_ERR(dwc->ref_clk)) {
1827 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1828 "could not get ref clock\n");
1831 if (dwc->ref_clk == NULL) {
1832 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1833 if (IS_ERR(dwc->ref_clk)) {
1834 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1835 "could not get ref clock\n");
1839 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1840 if (IS_ERR(dwc->susp_clk)) {
1841 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1842 "could not get suspend clock\n");
1845 if (dwc->susp_clk == NULL) {
1846 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1847 if (IS_ERR(dwc->susp_clk)) {
1848 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1849 "could not get suspend clock\n");
1853 /* specific to Rockchip RK3588 */
1854 dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
1855 if (IS_ERR(dwc->utmi_clk)) {
1856 return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
1857 "could not get utmi clock\n");
1860 /* specific to Rockchip RK3588 */
1861 dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
1862 if (IS_ERR(dwc->pipe_clk)) {
1863 return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
1864 "could not get pipe clock\n");
1870 static int dwc3_probe(struct platform_device *pdev)
1872 struct device *dev = &pdev->dev;
1873 struct resource *res, dwc_res;
1878 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1884 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886 dev_err(dev, "missing memory resource\n");
1890 dwc->xhci_resources[0].start = res->start;
1891 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1893 dwc->xhci_resources[0].flags = res->flags;
1894 dwc->xhci_resources[0].name = res->name;
1897 * Request memory region but exclude xHCI regs,
1898 * since it will be requested by the xhci-plat driver.
1901 dwc_res.start += DWC3_GLOBALS_REGS_START;
1904 struct device_node *parent = of_get_parent(dev->of_node);
1906 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1907 dwc_res.start -= DWC3_GLOBALS_REGS_START;
1908 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1911 of_node_put(parent);
1914 regs = devm_ioremap_resource(dev, &dwc_res);
1916 return PTR_ERR(regs);
1919 dwc->regs_size = resource_size(&dwc_res);
1921 dwc3_get_properties(dwc);
1923 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1924 if (IS_ERR(dwc->reset)) {
1925 ret = PTR_ERR(dwc->reset);
1929 ret = dwc3_get_clocks(dwc);
1933 ret = reset_control_deassert(dwc->reset);
1937 ret = dwc3_clk_enable(dwc);
1939 goto err_assert_reset;
1941 if (!dwc3_core_is_valid(dwc)) {
1942 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1944 goto err_disable_clks;
1947 platform_set_drvdata(pdev, dwc);
1948 dwc3_cache_hwparams(dwc);
1950 if (!dwc->sysdev_is_parent &&
1951 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1952 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1954 goto err_disable_clks;
1957 spin_lock_init(&dwc->lock);
1958 mutex_init(&dwc->mutex);
1960 pm_runtime_get_noresume(dev);
1961 pm_runtime_set_active(dev);
1962 pm_runtime_use_autosuspend(dev);
1963 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1964 pm_runtime_enable(dev);
1966 pm_runtime_forbid(dev);
1968 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1970 dev_err(dwc->dev, "failed to allocate event buffers\n");
1975 dwc->edev = dwc3_get_extcon(dwc);
1976 if (IS_ERR(dwc->edev)) {
1977 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
1978 goto err_free_event_buffers;
1981 ret = dwc3_get_dr_mode(dwc);
1983 goto err_free_event_buffers;
1985 ret = dwc3_core_init(dwc);
1987 dev_err_probe(dev, ret, "failed to initialize core\n");
1988 goto err_free_event_buffers;
1991 dwc3_check_params(dwc);
1992 dwc3_debugfs_init(dwc);
1994 ret = dwc3_core_init_mode(dwc);
1996 goto err_exit_debugfs;
1998 pm_runtime_put(dev);
2000 dma_set_max_seg_size(dev, UINT_MAX);
2005 dwc3_debugfs_exit(dwc);
2006 dwc3_event_buffers_cleanup(dwc);
2007 dwc3_phy_power_off(dwc);
2009 dwc3_ulpi_exit(dwc);
2010 err_free_event_buffers:
2011 dwc3_free_event_buffers(dwc);
2013 pm_runtime_allow(dev);
2014 pm_runtime_disable(dev);
2015 pm_runtime_dont_use_autosuspend(dev);
2016 pm_runtime_set_suspended(dev);
2017 pm_runtime_put_noidle(dev);
2019 dwc3_clk_disable(dwc);
2021 reset_control_assert(dwc->reset);
2024 power_supply_put(dwc->usb_psy);
2029 static void dwc3_remove(struct platform_device *pdev)
2031 struct dwc3 *dwc = platform_get_drvdata(pdev);
2033 pm_runtime_get_sync(&pdev->dev);
2035 dwc3_core_exit_mode(dwc);
2036 dwc3_debugfs_exit(dwc);
2038 dwc3_core_exit(dwc);
2039 dwc3_ulpi_exit(dwc);
2041 pm_runtime_allow(&pdev->dev);
2042 pm_runtime_disable(&pdev->dev);
2043 pm_runtime_dont_use_autosuspend(&pdev->dev);
2044 pm_runtime_put_noidle(&pdev->dev);
2046 * HACK: Clear the driver data, which is currently accessed by parent
2047 * glue drivers, before allowing the parent to suspend.
2049 platform_set_drvdata(pdev, NULL);
2050 pm_runtime_set_suspended(&pdev->dev);
2052 dwc3_free_event_buffers(dwc);
2055 power_supply_put(dwc->usb_psy);
2059 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2063 ret = reset_control_deassert(dwc->reset);
2067 ret = dwc3_clk_enable(dwc);
2071 ret = dwc3_core_init(dwc);
2078 dwc3_clk_disable(dwc);
2080 reset_control_assert(dwc->reset);
2085 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2087 unsigned long flags;
2090 switch (dwc->current_dr_role) {
2091 case DWC3_GCTL_PRTCAP_DEVICE:
2092 if (pm_runtime_suspended(dwc->dev))
2094 dwc3_gadget_suspend(dwc);
2095 synchronize_irq(dwc->irq_gadget);
2096 dwc3_core_exit(dwc);
2098 case DWC3_GCTL_PRTCAP_HOST:
2099 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2100 dwc3_core_exit(dwc);
2104 /* Let controller to suspend HSPHY before PHY driver suspends */
2105 if (dwc->dis_u2_susphy_quirk ||
2106 dwc->dis_enblslpm_quirk) {
2107 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2108 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2109 DWC3_GUSB2PHYCFG_SUSPHY;
2110 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2112 /* Give some time for USB2 PHY to suspend */
2113 usleep_range(5000, 6000);
2116 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2117 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2119 case DWC3_GCTL_PRTCAP_OTG:
2120 /* do nothing during runtime_suspend */
2121 if (PMSG_IS_AUTO(msg))
2124 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2125 spin_lock_irqsave(&dwc->lock, flags);
2126 dwc3_gadget_suspend(dwc);
2127 spin_unlock_irqrestore(&dwc->lock, flags);
2128 synchronize_irq(dwc->irq_gadget);
2132 dwc3_core_exit(dwc);
2142 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2144 unsigned long flags;
2148 switch (dwc->current_dr_role) {
2149 case DWC3_GCTL_PRTCAP_DEVICE:
2150 ret = dwc3_core_init_for_resume(dwc);
2154 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2155 dwc3_gadget_resume(dwc);
2157 case DWC3_GCTL_PRTCAP_HOST:
2158 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2159 ret = dwc3_core_init_for_resume(dwc);
2162 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2165 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2166 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2167 if (dwc->dis_u2_susphy_quirk)
2168 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2170 if (dwc->dis_enblslpm_quirk)
2171 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2173 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2175 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2176 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2178 case DWC3_GCTL_PRTCAP_OTG:
2179 /* nothing to do on runtime_resume */
2180 if (PMSG_IS_AUTO(msg))
2183 ret = dwc3_core_init_for_resume(dwc);
2187 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2190 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2191 dwc3_otg_host_init(dwc);
2192 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2193 spin_lock_irqsave(&dwc->lock, flags);
2194 dwc3_gadget_resume(dwc);
2195 spin_unlock_irqrestore(&dwc->lock, flags);
2207 static int dwc3_runtime_checks(struct dwc3 *dwc)
2209 switch (dwc->current_dr_role) {
2210 case DWC3_GCTL_PRTCAP_DEVICE:
2214 case DWC3_GCTL_PRTCAP_HOST:
2223 static int dwc3_runtime_suspend(struct device *dev)
2225 struct dwc3 *dwc = dev_get_drvdata(dev);
2228 if (dwc3_runtime_checks(dwc))
2231 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2238 static int dwc3_runtime_resume(struct device *dev)
2240 struct dwc3 *dwc = dev_get_drvdata(dev);
2243 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2247 switch (dwc->current_dr_role) {
2248 case DWC3_GCTL_PRTCAP_DEVICE:
2249 dwc3_gadget_process_pending_events(dwc);
2251 case DWC3_GCTL_PRTCAP_HOST:
2257 pm_runtime_mark_last_busy(dev);
2262 static int dwc3_runtime_idle(struct device *dev)
2264 struct dwc3 *dwc = dev_get_drvdata(dev);
2266 switch (dwc->current_dr_role) {
2267 case DWC3_GCTL_PRTCAP_DEVICE:
2268 if (dwc3_runtime_checks(dwc))
2271 case DWC3_GCTL_PRTCAP_HOST:
2277 pm_runtime_mark_last_busy(dev);
2278 pm_runtime_autosuspend(dev);
2282 #endif /* CONFIG_PM */
2284 #ifdef CONFIG_PM_SLEEP
2285 static int dwc3_suspend(struct device *dev)
2287 struct dwc3 *dwc = dev_get_drvdata(dev);
2290 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2294 pinctrl_pm_select_sleep_state(dev);
2299 static int dwc3_resume(struct device *dev)
2301 struct dwc3 *dwc = dev_get_drvdata(dev);
2304 pinctrl_pm_select_default_state(dev);
2306 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2310 pm_runtime_disable(dev);
2311 pm_runtime_set_active(dev);
2312 pm_runtime_enable(dev);
2317 static void dwc3_complete(struct device *dev)
2319 struct dwc3 *dwc = dev_get_drvdata(dev);
2322 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2323 dwc->dis_split_quirk) {
2324 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2325 reg |= DWC3_GUCTL3_SPLITDISABLE;
2326 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2330 #define dwc3_complete NULL
2331 #endif /* CONFIG_PM_SLEEP */
2333 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2334 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2335 .complete = dwc3_complete,
2336 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2341 static const struct of_device_id of_dwc3_match[] = {
2343 .compatible = "snps,dwc3"
2346 .compatible = "synopsys,dwc3"
2350 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2355 #define ACPI_ID_INTEL_BSW "808622B7"
2357 static const struct acpi_device_id dwc3_acpi_match[] = {
2358 { ACPI_ID_INTEL_BSW, 0 },
2361 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2364 static struct platform_driver dwc3_driver = {
2365 .probe = dwc3_probe,
2366 .remove_new = dwc3_remove,
2369 .of_match_table = of_match_ptr(of_dwc3_match),
2370 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2371 .pm = &dwc3_dev_pm_ops,
2375 module_platform_driver(dwc3_driver);
2377 MODULE_ALIAS("platform:dwc3");
2378 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2379 MODULE_LICENSE("GPL v2");
2380 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");