1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
63 "Controller does not support host mode.\n");
66 mode = USB_DR_MODE_PERIPHERAL;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
71 "Controller does not support device mode.\n");
74 mode = USB_DR_MODE_HOST;
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
94 if (mode != dwc->dr_mode) {
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
105 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
109 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
110 if (enable && !dwc->dis_u3_susphy_quirk)
111 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
113 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
115 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
117 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
118 if (enable && !dwc->dis_u2_susphy_quirk)
119 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
121 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
123 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
126 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
130 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
131 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
132 reg |= DWC3_GCTL_PRTCAPDIR(mode);
133 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
135 dwc->current_dr_role = mode;
138 static void __dwc3_set_mode(struct work_struct *work)
140 struct dwc3 *dwc = work_to_dwc(work);
146 mutex_lock(&dwc->mutex);
147 spin_lock_irqsave(&dwc->lock, flags);
148 desired_dr_role = dwc->desired_dr_role;
149 spin_unlock_irqrestore(&dwc->lock, flags);
151 pm_runtime_get_sync(dwc->dev);
153 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
154 dwc3_otg_update(dwc, 0);
156 if (!desired_dr_role)
159 if (desired_dr_role == dwc->current_dr_role)
162 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
165 switch (dwc->current_dr_role) {
166 case DWC3_GCTL_PRTCAP_HOST:
169 case DWC3_GCTL_PRTCAP_DEVICE:
170 dwc3_gadget_exit(dwc);
171 dwc3_event_buffers_cleanup(dwc);
173 case DWC3_GCTL_PRTCAP_OTG:
175 spin_lock_irqsave(&dwc->lock, flags);
176 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
177 spin_unlock_irqrestore(&dwc->lock, flags);
178 dwc3_otg_update(dwc, 1);
185 * When current_dr_role is not set, there's no role switching.
186 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
188 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
189 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
190 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
191 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
192 reg |= DWC3_GCTL_CORESOFTRESET;
193 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
196 * Wait for internal clocks to synchronized. DWC_usb31 and
197 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
198 * keep it consistent across different IPs, let's wait up to
199 * 100ms before clearing GCTL.CORESOFTRESET.
203 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
204 reg &= ~DWC3_GCTL_CORESOFTRESET;
205 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
208 spin_lock_irqsave(&dwc->lock, flags);
210 dwc3_set_prtcap(dwc, desired_dr_role);
212 spin_unlock_irqrestore(&dwc->lock, flags);
214 switch (desired_dr_role) {
215 case DWC3_GCTL_PRTCAP_HOST:
216 ret = dwc3_host_init(dwc);
218 dev_err(dwc->dev, "failed to initialize host\n");
221 otg_set_vbus(dwc->usb2_phy->otg, true);
222 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
223 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
224 if (dwc->dis_split_quirk) {
225 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
226 reg |= DWC3_GUCTL3_SPLITDISABLE;
227 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
231 case DWC3_GCTL_PRTCAP_DEVICE:
232 dwc3_core_soft_reset(dwc);
234 dwc3_event_buffers_setup(dwc);
237 otg_set_vbus(dwc->usb2_phy->otg, false);
238 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
239 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
241 ret = dwc3_gadget_init(dwc);
243 dev_err(dwc->dev, "failed to initialize peripheral\n");
245 case DWC3_GCTL_PRTCAP_OTG:
247 dwc3_otg_update(dwc, 0);
254 pm_runtime_mark_last_busy(dwc->dev);
255 pm_runtime_put_autosuspend(dwc->dev);
256 mutex_unlock(&dwc->mutex);
259 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
263 if (dwc->dr_mode != USB_DR_MODE_OTG)
266 spin_lock_irqsave(&dwc->lock, flags);
267 dwc->desired_dr_role = mode;
268 spin_unlock_irqrestore(&dwc->lock, flags);
270 queue_work(system_freezable_wq, &dwc->drd_work);
273 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
275 struct dwc3 *dwc = dep->dwc;
278 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
279 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
280 DWC3_GDBGFIFOSPACE_TYPE(type));
282 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
284 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
288 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
289 * @dwc: pointer to our context structure
291 int dwc3_core_soft_reset(struct dwc3 *dwc)
297 * We're resetting only the device side because, if we're in host mode,
298 * XHCI driver will reset the host block. If dwc3 was configured for
299 * host-only mode, then we can return early.
301 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
304 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
305 reg |= DWC3_DCTL_CSFTRST;
306 reg &= ~DWC3_DCTL_RUN_STOP;
307 dwc3_gadget_dctl_write_safe(dwc, reg);
310 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
311 * is cleared only after all the clocks are synchronized. This can
312 * take a little more than 50ms. Set the polling rate at 20ms
313 * for 10 times instead.
315 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
319 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
320 if (!(reg & DWC3_DCTL_CSFTRST))
323 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
333 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
334 * is cleared, we must wait at least 50ms before accessing the PHY
335 * domain (synchronization delay).
337 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
344 * dwc3_frame_length_adjustment - Adjusts frame length if required
345 * @dwc3: Pointer to our controller context structure
347 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
352 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
358 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
359 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
360 if (dft != dwc->fladj) {
361 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
362 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
363 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
368 * dwc3_free_one_event_buffer - Frees one event buffer
369 * @dwc: Pointer to our controller context structure
370 * @evt: Pointer to event buffer to be freed
372 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
373 struct dwc3_event_buffer *evt)
375 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
379 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
380 * @dwc: Pointer to our controller context structure
381 * @length: size of the event buffer
383 * Returns a pointer to the allocated event buffer structure on success
384 * otherwise ERR_PTR(errno).
386 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
389 struct dwc3_event_buffer *evt;
391 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
393 return ERR_PTR(-ENOMEM);
396 evt->length = length;
397 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
399 return ERR_PTR(-ENOMEM);
401 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
402 &evt->dma, GFP_KERNEL);
404 return ERR_PTR(-ENOMEM);
410 * dwc3_free_event_buffers - frees all allocated event buffers
411 * @dwc: Pointer to our controller context structure
413 static void dwc3_free_event_buffers(struct dwc3 *dwc)
415 struct dwc3_event_buffer *evt;
419 dwc3_free_one_event_buffer(dwc, evt);
423 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
424 * @dwc: pointer to our controller context structure
425 * @length: size of event buffer
427 * Returns 0 on success otherwise negative errno. In the error case, dwc
428 * may contain some buffers allocated but not all which were requested.
430 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
432 struct dwc3_event_buffer *evt;
434 evt = dwc3_alloc_one_event_buffer(dwc, length);
436 dev_err(dwc->dev, "can't allocate event buffer\n");
445 * dwc3_event_buffers_setup - setup our allocated event buffers
446 * @dwc: pointer to our controller context structure
448 * Returns 0 on success otherwise negative errno.
450 int dwc3_event_buffers_setup(struct dwc3 *dwc)
452 struct dwc3_event_buffer *evt;
456 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
457 lower_32_bits(evt->dma));
458 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
459 upper_32_bits(evt->dma));
460 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
461 DWC3_GEVNTSIZ_SIZE(evt->length));
462 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
467 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
469 struct dwc3_event_buffer *evt;
475 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
476 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
477 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
478 | DWC3_GEVNTSIZ_SIZE(0));
479 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
482 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
484 if (!dwc->has_hibernation)
487 if (!dwc->nr_scratch)
490 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
491 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
492 if (!dwc->scratchbuf)
498 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
500 dma_addr_t scratch_addr;
504 if (!dwc->has_hibernation)
507 if (!dwc->nr_scratch)
510 /* should never fall here */
511 if (!WARN_ON(dwc->scratchbuf))
514 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
515 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
517 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
518 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
523 dwc->scratch_addr = scratch_addr;
525 param = lower_32_bits(scratch_addr);
527 ret = dwc3_send_gadget_generic_command(dwc,
528 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
532 param = upper_32_bits(scratch_addr);
534 ret = dwc3_send_gadget_generic_command(dwc,
535 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
542 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
543 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
549 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
551 if (!dwc->has_hibernation)
554 if (!dwc->nr_scratch)
557 /* should never fall here */
558 if (!WARN_ON(dwc->scratchbuf))
561 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
562 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
563 kfree(dwc->scratchbuf);
566 static void dwc3_core_num_eps(struct dwc3 *dwc)
568 struct dwc3_hwparams *parms = &dwc->hwparams;
570 dwc->num_eps = DWC3_NUM_EPS(parms);
573 static void dwc3_cache_hwparams(struct dwc3 *dwc)
575 struct dwc3_hwparams *parms = &dwc->hwparams;
577 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
578 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
579 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
580 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
581 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
582 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
583 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
584 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
585 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
588 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
593 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
595 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
596 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
597 dwc->hsphy_interface &&
598 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
599 ret = dwc3_ulpi_init(dwc);
605 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
606 * @dwc: Pointer to our controller context structure
608 * Returns 0 on success. The USB PHY interfaces are configured but not
609 * initialized. The PHY interfaces and the PHYs get initialized together with
610 * the core in dwc3_core_init.
612 static int dwc3_phy_setup(struct dwc3 *dwc)
616 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
619 * Make sure UX_EXIT_PX is cleared as that causes issues with some
620 * PHYs. Also, this bit is not supposed to be used in normal operation.
622 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
625 * Above DWC_usb3.0 1.94a, it is recommended to set
626 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
627 * So default value will be '0' when the core is reset. Application
628 * needs to set it to '1' after the core initialization is completed.
630 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
631 * cleared after power-on reset, and it can be set after core
634 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
636 if (dwc->u2ss_inp3_quirk)
637 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
639 if (dwc->dis_rxdet_inp3_quirk)
640 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
642 if (dwc->req_p1p2p3_quirk)
643 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
645 if (dwc->del_p1p2p3_quirk)
646 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
648 if (dwc->del_phy_power_chg_quirk)
649 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
651 if (dwc->lfps_filter_quirk)
652 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
654 if (dwc->rx_detect_poll_quirk)
655 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
657 if (dwc->tx_de_emphasis_quirk)
658 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
660 if (dwc->dis_del_phy_power_chg_quirk)
661 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
663 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
665 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
667 /* Select the HS PHY interface */
668 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
669 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
670 if (dwc->hsphy_interface &&
671 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
672 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
674 } else if (dwc->hsphy_interface &&
675 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
676 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
677 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
679 /* Relying on default value. */
680 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
684 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
689 switch (dwc->hsphy_mode) {
690 case USBPHY_INTERFACE_MODE_UTMI:
691 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
692 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
693 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
694 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
696 case USBPHY_INTERFACE_MODE_UTMIW:
697 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
698 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
699 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
700 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
707 * Above DWC_usb3.0 1.94a, it is recommended to set
708 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
709 * So default value will be '0' when the core is reset. Application
710 * needs to set it to '1' after the core initialization is completed.
712 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
713 * after power-on reset, and it can be set after core initialization.
715 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
717 if (dwc->dis_enblslpm_quirk)
718 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
720 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
722 if (dwc->dis_u2_freeclk_exists_quirk)
723 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
725 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
730 static void dwc3_core_exit(struct dwc3 *dwc)
732 dwc3_event_buffers_cleanup(dwc);
734 usb_phy_set_suspend(dwc->usb2_phy, 1);
735 usb_phy_set_suspend(dwc->usb3_phy, 1);
736 phy_power_off(dwc->usb2_generic_phy);
737 phy_power_off(dwc->usb3_generic_phy);
739 usb_phy_shutdown(dwc->usb2_phy);
740 usb_phy_shutdown(dwc->usb3_phy);
741 phy_exit(dwc->usb2_generic_phy);
742 phy_exit(dwc->usb3_generic_phy);
744 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
745 reset_control_assert(dwc->reset);
748 static bool dwc3_core_is_valid(struct dwc3 *dwc)
752 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
753 dwc->ip = DWC3_GSNPS_ID(reg);
755 /* This should read as U3 followed by revision number */
756 if (DWC3_IP_IS(DWC3)) {
758 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
759 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
760 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
768 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
770 u32 hwparams4 = dwc->hwparams.hwparams4;
773 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
774 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
776 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
777 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
779 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
780 * issue which would cause xHCI compliance tests to fail.
782 * Because of that we cannot enable clock gating on such
787 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
790 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
791 dwc->dr_mode == USB_DR_MODE_OTG) &&
792 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
793 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
795 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
797 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
798 /* enable hibernation here */
799 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
802 * REVISIT Enabling this bit so that host-mode hibernation
803 * will work. Device-mode hibernation is not yet implemented.
805 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
812 /* check if current dwc3 is on simulation board */
813 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
814 dev_info(dwc->dev, "Running with FPGA optimizations\n");
818 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
819 "disable_scramble cannot be used on non-FPGA builds\n");
821 if (dwc->disable_scramble_quirk && dwc->is_fpga)
822 reg |= DWC3_GCTL_DISSCRAMBLE;
824 reg &= ~DWC3_GCTL_DISSCRAMBLE;
826 if (dwc->u2exit_lfps_quirk)
827 reg |= DWC3_GCTL_U2EXIT_LFPS;
830 * WORKAROUND: DWC3 revisions <1.90a have a bug
831 * where the device can fail to connect at SuperSpeed
832 * and falls back to high-speed mode which causes
833 * the device to enter a Connect/Disconnect loop
835 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
836 reg |= DWC3_GCTL_U2RSTECN;
838 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
841 static int dwc3_core_get_phy(struct dwc3 *dwc);
842 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
844 /* set global incr burst type configuration registers */
845 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
847 struct device *dev = dwc->dev;
848 /* incrx_mode : for INCR burst type. */
850 /* incrx_size : for size of INCRX burst. */
858 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
861 * Handle property "snps,incr-burst-type-adjustment".
862 * Get the number of value from this property:
863 * result <= 0, means this property is not supported.
864 * result = 1, means INCRx burst mode supported.
865 * result > 1, means undefined length burst mode supported.
867 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
871 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
873 dev_err(dev, "Error to get memory\n");
877 /* Get INCR burst type, and parse it */
878 ret = device_property_read_u32_array(dev,
879 "snps,incr-burst-type-adjustment", vals, ntype);
882 dev_err(dev, "Error to get property\n");
889 /* INCRX (undefined length) burst mode */
890 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
891 for (i = 1; i < ntype; i++) {
892 if (vals[i] > incrx_size)
893 incrx_size = vals[i];
896 /* INCRX burst mode */
897 incrx_mode = INCRX_BURST_MODE;
902 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
903 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
905 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
906 switch (incrx_size) {
908 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
911 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
914 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
917 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
920 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
923 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
926 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
931 dev_err(dev, "Invalid property\n");
935 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
939 * dwc3_core_init - Low-level initialization of DWC3 Core
940 * @dwc: Pointer to our controller context structure
942 * Returns 0 on success otherwise negative errno.
944 static int dwc3_core_init(struct dwc3 *dwc)
946 unsigned int hw_mode;
950 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
953 * Write Linux Version Code to our GUID register so it's easy to figure
954 * out which kernel version a bug was found.
956 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
958 ret = dwc3_phy_setup(dwc);
962 if (!dwc->ulpi_ready) {
963 ret = dwc3_core_ulpi_init(dwc);
965 if (ret == -ETIMEDOUT) {
966 dwc3_core_soft_reset(dwc);
971 dwc->ulpi_ready = true;
974 if (!dwc->phys_ready) {
975 ret = dwc3_core_get_phy(dwc);
978 dwc->phys_ready = true;
981 usb_phy_init(dwc->usb2_phy);
982 usb_phy_init(dwc->usb3_phy);
983 ret = phy_init(dwc->usb2_generic_phy);
987 ret = phy_init(dwc->usb3_generic_phy);
989 phy_exit(dwc->usb2_generic_phy);
993 ret = dwc3_core_soft_reset(dwc);
997 dwc3_core_setup_global_control(dwc);
998 dwc3_core_num_eps(dwc);
1000 ret = dwc3_setup_scratch_buffers(dwc);
1004 /* Adjust Frame Length */
1005 dwc3_frame_length_adjustment(dwc);
1007 dwc3_set_incr_burst_type(dwc);
1009 usb_phy_set_suspend(dwc->usb2_phy, 0);
1010 usb_phy_set_suspend(dwc->usb3_phy, 0);
1011 ret = phy_power_on(dwc->usb2_generic_phy);
1015 ret = phy_power_on(dwc->usb3_generic_phy);
1019 ret = dwc3_event_buffers_setup(dwc);
1021 dev_err(dwc->dev, "failed to setup event buffers\n");
1026 * ENDXFER polling is available on version 3.10a and later of
1027 * the DWC_usb3 controller. It is NOT available in the
1028 * DWC_usb31 controller.
1030 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1031 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1032 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1033 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1036 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1037 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1040 * Enable hardware control of sending remote wakeup
1041 * in HS when the device is in the L1 state.
1043 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1044 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1046 if (dwc->dis_tx_ipgap_linecheck_quirk)
1047 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1049 if (dwc->parkmode_disable_ss_quirk)
1050 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1052 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1056 * Must config both number of packets and max burst settings to enable
1057 * RX and/or TX threshold.
1059 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1060 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1061 u8 rx_maxburst = dwc->rx_max_burst_prd;
1062 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1063 u8 tx_maxburst = dwc->tx_max_burst_prd;
1065 if (rx_thr_num && rx_maxburst) {
1066 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1067 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1069 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1070 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1072 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1073 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1075 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1078 if (tx_thr_num && tx_maxburst) {
1079 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1080 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1082 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1083 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1085 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1086 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1088 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1095 phy_power_off(dwc->usb3_generic_phy);
1098 phy_power_off(dwc->usb2_generic_phy);
1101 usb_phy_set_suspend(dwc->usb2_phy, 1);
1102 usb_phy_set_suspend(dwc->usb3_phy, 1);
1105 usb_phy_shutdown(dwc->usb2_phy);
1106 usb_phy_shutdown(dwc->usb3_phy);
1107 phy_exit(dwc->usb2_generic_phy);
1108 phy_exit(dwc->usb3_generic_phy);
1111 dwc3_ulpi_exit(dwc);
1117 static int dwc3_core_get_phy(struct dwc3 *dwc)
1119 struct device *dev = dwc->dev;
1120 struct device_node *node = dev->of_node;
1124 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1125 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1127 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1128 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1131 if (IS_ERR(dwc->usb2_phy)) {
1132 ret = PTR_ERR(dwc->usb2_phy);
1133 if (ret == -ENXIO || ret == -ENODEV) {
1134 dwc->usb2_phy = NULL;
1135 } else if (ret == -EPROBE_DEFER) {
1138 dev_err(dev, "no usb2 phy configured\n");
1143 if (IS_ERR(dwc->usb3_phy)) {
1144 ret = PTR_ERR(dwc->usb3_phy);
1145 if (ret == -ENXIO || ret == -ENODEV) {
1146 dwc->usb3_phy = NULL;
1147 } else if (ret == -EPROBE_DEFER) {
1150 dev_err(dev, "no usb3 phy configured\n");
1155 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1156 if (IS_ERR(dwc->usb2_generic_phy)) {
1157 ret = PTR_ERR(dwc->usb2_generic_phy);
1158 if (ret == -ENOSYS || ret == -ENODEV) {
1159 dwc->usb2_generic_phy = NULL;
1160 } else if (ret == -EPROBE_DEFER) {
1163 dev_err(dev, "no usb2 phy configured\n");
1168 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1169 if (IS_ERR(dwc->usb3_generic_phy)) {
1170 ret = PTR_ERR(dwc->usb3_generic_phy);
1171 if (ret == -ENOSYS || ret == -ENODEV) {
1172 dwc->usb3_generic_phy = NULL;
1173 } else if (ret == -EPROBE_DEFER) {
1176 dev_err(dev, "no usb3 phy configured\n");
1184 static int dwc3_core_init_mode(struct dwc3 *dwc)
1186 struct device *dev = dwc->dev;
1189 switch (dwc->dr_mode) {
1190 case USB_DR_MODE_PERIPHERAL:
1191 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1194 otg_set_vbus(dwc->usb2_phy->otg, false);
1195 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1196 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1198 ret = dwc3_gadget_init(dwc);
1200 if (ret != -EPROBE_DEFER)
1201 dev_err(dev, "failed to initialize gadget\n");
1205 case USB_DR_MODE_HOST:
1206 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1209 otg_set_vbus(dwc->usb2_phy->otg, true);
1210 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1211 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1213 ret = dwc3_host_init(dwc);
1215 if (ret != -EPROBE_DEFER)
1216 dev_err(dev, "failed to initialize host\n");
1220 case USB_DR_MODE_OTG:
1221 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1222 ret = dwc3_drd_init(dwc);
1224 if (ret != -EPROBE_DEFER)
1225 dev_err(dev, "failed to initialize dual-role\n");
1230 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1237 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1239 switch (dwc->dr_mode) {
1240 case USB_DR_MODE_PERIPHERAL:
1241 dwc3_gadget_exit(dwc);
1243 case USB_DR_MODE_HOST:
1244 dwc3_host_exit(dwc);
1246 case USB_DR_MODE_OTG:
1254 /* de-assert DRVVBUS for HOST and OTG mode */
1255 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1258 static void dwc3_get_properties(struct dwc3 *dwc)
1260 struct device *dev = dwc->dev;
1261 u8 lpm_nyet_threshold;
1264 u8 rx_thr_num_pkt_prd = 0;
1265 u8 rx_max_burst_prd = 0;
1266 u8 tx_thr_num_pkt_prd = 0;
1267 u8 tx_max_burst_prd = 0;
1269 /* default to highest possible threshold */
1270 lpm_nyet_threshold = 0xf;
1272 /* default to -3.5dB de-emphasis */
1276 * default to assert utmi_sleep_n and use maximum allowed HIRD
1277 * threshold value of 0b1100
1279 hird_threshold = 12;
1281 dwc->maximum_speed = usb_get_maximum_speed(dev);
1282 dwc->dr_mode = usb_get_dr_mode(dev);
1283 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1285 dwc->sysdev_is_parent = device_property_read_bool(dev,
1286 "linux,sysdev_is_parent");
1287 if (dwc->sysdev_is_parent)
1288 dwc->sysdev = dwc->dev->parent;
1290 dwc->sysdev = dwc->dev;
1292 dwc->has_lpm_erratum = device_property_read_bool(dev,
1293 "snps,has-lpm-erratum");
1294 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1295 &lpm_nyet_threshold);
1296 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1297 "snps,is-utmi-l1-suspend");
1298 device_property_read_u8(dev, "snps,hird-threshold",
1300 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1301 "snps,dis-start-transfer-quirk");
1302 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1303 "snps,usb3_lpm_capable");
1304 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1305 "snps,usb2-lpm-disable");
1306 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1307 "snps,usb2-gadget-lpm-disable");
1308 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1309 &rx_thr_num_pkt_prd);
1310 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1312 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1313 &tx_thr_num_pkt_prd);
1314 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1317 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1318 "snps,disable_scramble_quirk");
1319 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1320 "snps,u2exit_lfps_quirk");
1321 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1322 "snps,u2ss_inp3_quirk");
1323 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1324 "snps,req_p1p2p3_quirk");
1325 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1326 "snps,del_p1p2p3_quirk");
1327 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1328 "snps,del_phy_power_chg_quirk");
1329 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1330 "snps,lfps_filter_quirk");
1331 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1332 "snps,rx_detect_poll_quirk");
1333 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1334 "snps,dis_u3_susphy_quirk");
1335 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1336 "snps,dis_u2_susphy_quirk");
1337 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1338 "snps,dis_enblslpm_quirk");
1339 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1340 "snps,dis-u1-entry-quirk");
1341 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1342 "snps,dis-u2-entry-quirk");
1343 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1344 "snps,dis_rxdet_inp3_quirk");
1345 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1346 "snps,dis-u2-freeclk-exists-quirk");
1347 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1348 "snps,dis-del-phy-power-chg-quirk");
1349 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1350 "snps,dis-tx-ipgap-linecheck-quirk");
1351 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1352 "snps,parkmode-disable-ss-quirk");
1354 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1355 "snps,tx_de_emphasis_quirk");
1356 device_property_read_u8(dev, "snps,tx_de_emphasis",
1358 device_property_read_string(dev, "snps,hsphy_interface",
1359 &dwc->hsphy_interface);
1360 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1363 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1364 "snps,dis_metastability_quirk");
1366 dwc->dis_split_quirk = device_property_read_bool(dev,
1367 "snps,dis-split-quirk");
1369 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1370 dwc->tx_de_emphasis = tx_de_emphasis;
1372 dwc->hird_threshold = hird_threshold;
1374 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1375 dwc->rx_max_burst_prd = rx_max_burst_prd;
1377 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1378 dwc->tx_max_burst_prd = tx_max_burst_prd;
1380 dwc->imod_interval = 0;
1383 /* check whether the core supports IMOD */
1384 bool dwc3_has_imod(struct dwc3 *dwc)
1386 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1387 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1391 static void dwc3_check_params(struct dwc3 *dwc)
1393 struct device *dev = dwc->dev;
1394 unsigned int hwparam_gen =
1395 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1397 /* Check for proper value of imod_interval */
1398 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1399 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1400 dwc->imod_interval = 0;
1404 * Workaround for STAR 9000961433 which affects only version
1405 * 3.00a of the DWC_usb3 core. This prevents the controller
1406 * interrupt from being masked while handling events. IMOD
1407 * allows us to work around this issue. Enable it for the
1410 if (!dwc->imod_interval &&
1411 DWC3_VER_IS(DWC3, 300A))
1412 dwc->imod_interval = 1;
1414 /* Check the maximum_speed parameter */
1415 switch (dwc->maximum_speed) {
1417 case USB_SPEED_FULL:
1418 case USB_SPEED_HIGH:
1420 case USB_SPEED_SUPER:
1421 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1422 dev_warn(dev, "UDC doesn't support Gen 1\n");
1424 case USB_SPEED_SUPER_PLUS:
1425 if ((DWC3_IP_IS(DWC32) &&
1426 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1427 (!DWC3_IP_IS(DWC32) &&
1428 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1429 dev_warn(dev, "UDC doesn't support SSP\n");
1432 dev_err(dev, "invalid maximum_speed parameter %d\n",
1433 dwc->maximum_speed);
1435 case USB_SPEED_UNKNOWN:
1436 switch (hwparam_gen) {
1437 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1438 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1440 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1441 if (DWC3_IP_IS(DWC32))
1442 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1444 dwc->maximum_speed = USB_SPEED_SUPER;
1446 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1447 dwc->maximum_speed = USB_SPEED_HIGH;
1450 dwc->maximum_speed = USB_SPEED_SUPER;
1457 static int dwc3_probe(struct platform_device *pdev)
1459 struct device *dev = &pdev->dev;
1460 struct resource *res, dwc_res;
1467 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1473 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1475 dev_err(dev, "missing memory resource\n");
1479 dwc->xhci_resources[0].start = res->start;
1480 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1482 dwc->xhci_resources[0].flags = res->flags;
1483 dwc->xhci_resources[0].name = res->name;
1486 * Request memory region but exclude xHCI regs,
1487 * since it will be requested by the xhci-plat driver.
1490 dwc_res.start += DWC3_GLOBALS_REGS_START;
1492 regs = devm_ioremap_resource(dev, &dwc_res);
1494 return PTR_ERR(regs);
1497 dwc->regs_size = resource_size(&dwc_res);
1499 dwc3_get_properties(dwc);
1501 dwc->reset = devm_reset_control_array_get(dev, true, true);
1502 if (IS_ERR(dwc->reset))
1503 return PTR_ERR(dwc->reset);
1506 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1507 if (ret == -EPROBE_DEFER)
1510 * Clocks are optional, but new DT platforms should support all
1511 * clocks as required by the DT-binding.
1516 dwc->num_clks = ret;
1520 ret = reset_control_deassert(dwc->reset);
1524 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1528 if (!dwc3_core_is_valid(dwc)) {
1529 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1534 platform_set_drvdata(pdev, dwc);
1535 dwc3_cache_hwparams(dwc);
1537 spin_lock_init(&dwc->lock);
1538 mutex_init(&dwc->mutex);
1540 pm_runtime_get_noresume(dev);
1541 pm_runtime_set_active(dev);
1542 pm_runtime_use_autosuspend(dev);
1543 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1544 pm_runtime_enable(dev);
1546 pm_runtime_forbid(dev);
1548 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1550 dev_err(dwc->dev, "failed to allocate event buffers\n");
1555 ret = dwc3_get_dr_mode(dwc);
1559 ret = dwc3_alloc_scratch_buffers(dwc);
1563 ret = dwc3_core_init(dwc);
1565 if (ret != -EPROBE_DEFER)
1566 dev_err(dev, "failed to initialize core: %d\n", ret);
1570 dwc3_check_params(dwc);
1571 dwc3_debugfs_init(dwc);
1573 ret = dwc3_core_init_mode(dwc);
1577 pm_runtime_put(dev);
1579 dma_set_max_seg_size(dev, UINT_MAX);
1584 dwc3_debugfs_exit(dwc);
1585 dwc3_event_buffers_cleanup(dwc);
1587 usb_phy_set_suspend(dwc->usb2_phy, 1);
1588 usb_phy_set_suspend(dwc->usb3_phy, 1);
1589 phy_power_off(dwc->usb2_generic_phy);
1590 phy_power_off(dwc->usb3_generic_phy);
1592 usb_phy_shutdown(dwc->usb2_phy);
1593 usb_phy_shutdown(dwc->usb3_phy);
1594 phy_exit(dwc->usb2_generic_phy);
1595 phy_exit(dwc->usb3_generic_phy);
1597 dwc3_ulpi_exit(dwc);
1600 dwc3_free_scratch_buffers(dwc);
1603 dwc3_free_event_buffers(dwc);
1606 pm_runtime_allow(dev);
1607 pm_runtime_disable(dev);
1608 pm_runtime_set_suspended(dev);
1609 pm_runtime_put_noidle(dev);
1611 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1613 reset_control_assert(dwc->reset);
1618 static int dwc3_remove(struct platform_device *pdev)
1620 struct dwc3 *dwc = platform_get_drvdata(pdev);
1622 pm_runtime_get_sync(&pdev->dev);
1624 dwc3_core_exit_mode(dwc);
1625 dwc3_debugfs_exit(dwc);
1627 dwc3_core_exit(dwc);
1628 dwc3_ulpi_exit(dwc);
1630 pm_runtime_allow(&pdev->dev);
1631 pm_runtime_disable(&pdev->dev);
1632 pm_runtime_put_noidle(&pdev->dev);
1633 pm_runtime_set_suspended(&pdev->dev);
1635 dwc3_free_event_buffers(dwc);
1636 dwc3_free_scratch_buffers(dwc);
1642 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1646 ret = reset_control_deassert(dwc->reset);
1650 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1654 ret = dwc3_core_init(dwc);
1661 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1663 reset_control_assert(dwc->reset);
1668 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1670 unsigned long flags;
1673 switch (dwc->current_dr_role) {
1674 case DWC3_GCTL_PRTCAP_DEVICE:
1675 if (pm_runtime_suspended(dwc->dev))
1677 spin_lock_irqsave(&dwc->lock, flags);
1678 dwc3_gadget_suspend(dwc);
1679 spin_unlock_irqrestore(&dwc->lock, flags);
1680 synchronize_irq(dwc->irq_gadget);
1681 dwc3_core_exit(dwc);
1683 case DWC3_GCTL_PRTCAP_HOST:
1684 if (!PMSG_IS_AUTO(msg)) {
1685 dwc3_core_exit(dwc);
1689 /* Let controller to suspend HSPHY before PHY driver suspends */
1690 if (dwc->dis_u2_susphy_quirk ||
1691 dwc->dis_enblslpm_quirk) {
1692 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1693 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1694 DWC3_GUSB2PHYCFG_SUSPHY;
1695 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1697 /* Give some time for USB2 PHY to suspend */
1698 usleep_range(5000, 6000);
1701 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1702 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1704 case DWC3_GCTL_PRTCAP_OTG:
1705 /* do nothing during runtime_suspend */
1706 if (PMSG_IS_AUTO(msg))
1709 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1710 spin_lock_irqsave(&dwc->lock, flags);
1711 dwc3_gadget_suspend(dwc);
1712 spin_unlock_irqrestore(&dwc->lock, flags);
1713 synchronize_irq(dwc->irq_gadget);
1717 dwc3_core_exit(dwc);
1727 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1729 unsigned long flags;
1733 switch (dwc->current_dr_role) {
1734 case DWC3_GCTL_PRTCAP_DEVICE:
1735 ret = dwc3_core_init_for_resume(dwc);
1739 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1740 spin_lock_irqsave(&dwc->lock, flags);
1741 dwc3_gadget_resume(dwc);
1742 spin_unlock_irqrestore(&dwc->lock, flags);
1744 case DWC3_GCTL_PRTCAP_HOST:
1745 if (!PMSG_IS_AUTO(msg)) {
1746 ret = dwc3_core_init_for_resume(dwc);
1749 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1752 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1753 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1754 if (dwc->dis_u2_susphy_quirk)
1755 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1757 if (dwc->dis_enblslpm_quirk)
1758 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1760 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1762 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1763 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1765 case DWC3_GCTL_PRTCAP_OTG:
1766 /* nothing to do on runtime_resume */
1767 if (PMSG_IS_AUTO(msg))
1770 ret = dwc3_core_init_for_resume(dwc);
1774 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1777 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1778 dwc3_otg_host_init(dwc);
1779 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1780 spin_lock_irqsave(&dwc->lock, flags);
1781 dwc3_gadget_resume(dwc);
1782 spin_unlock_irqrestore(&dwc->lock, flags);
1794 static int dwc3_runtime_checks(struct dwc3 *dwc)
1796 switch (dwc->current_dr_role) {
1797 case DWC3_GCTL_PRTCAP_DEVICE:
1801 case DWC3_GCTL_PRTCAP_HOST:
1810 static int dwc3_runtime_suspend(struct device *dev)
1812 struct dwc3 *dwc = dev_get_drvdata(dev);
1815 if (dwc3_runtime_checks(dwc))
1818 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1822 device_init_wakeup(dev, true);
1827 static int dwc3_runtime_resume(struct device *dev)
1829 struct dwc3 *dwc = dev_get_drvdata(dev);
1832 device_init_wakeup(dev, false);
1834 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1838 switch (dwc->current_dr_role) {
1839 case DWC3_GCTL_PRTCAP_DEVICE:
1840 dwc3_gadget_process_pending_events(dwc);
1842 case DWC3_GCTL_PRTCAP_HOST:
1848 pm_runtime_mark_last_busy(dev);
1853 static int dwc3_runtime_idle(struct device *dev)
1855 struct dwc3 *dwc = dev_get_drvdata(dev);
1857 switch (dwc->current_dr_role) {
1858 case DWC3_GCTL_PRTCAP_DEVICE:
1859 if (dwc3_runtime_checks(dwc))
1862 case DWC3_GCTL_PRTCAP_HOST:
1868 pm_runtime_mark_last_busy(dev);
1869 pm_runtime_autosuspend(dev);
1873 #endif /* CONFIG_PM */
1875 #ifdef CONFIG_PM_SLEEP
1876 static int dwc3_suspend(struct device *dev)
1878 struct dwc3 *dwc = dev_get_drvdata(dev);
1881 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1885 pinctrl_pm_select_sleep_state(dev);
1890 static int dwc3_resume(struct device *dev)
1892 struct dwc3 *dwc = dev_get_drvdata(dev);
1895 pinctrl_pm_select_default_state(dev);
1897 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1901 pm_runtime_disable(dev);
1902 pm_runtime_set_active(dev);
1903 pm_runtime_enable(dev);
1908 static void dwc3_complete(struct device *dev)
1910 struct dwc3 *dwc = dev_get_drvdata(dev);
1913 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1914 dwc->dis_split_quirk) {
1915 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1916 reg |= DWC3_GUCTL3_SPLITDISABLE;
1917 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1921 #define dwc3_complete NULL
1922 #endif /* CONFIG_PM_SLEEP */
1924 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1925 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1926 .complete = dwc3_complete,
1927 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1932 static const struct of_device_id of_dwc3_match[] = {
1934 .compatible = "snps,dwc3"
1937 .compatible = "synopsys,dwc3"
1941 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1946 #define ACPI_ID_INTEL_BSW "808622B7"
1948 static const struct acpi_device_id dwc3_acpi_match[] = {
1949 { ACPI_ID_INTEL_BSW, 0 },
1952 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1955 static struct platform_driver dwc3_driver = {
1956 .probe = dwc3_probe,
1957 .remove = dwc3_remove,
1960 .of_match_table = of_match_ptr(of_dwc3_match),
1961 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1962 .pm = &dwc3_dev_pm_ops,
1966 module_platform_driver(dwc3_driver);
1968 MODULE_ALIAS("platform:dwc3");
1969 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1970 MODULE_LICENSE("GPL v2");
1971 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");