1 // SPDX-License-Identifier: GPL-2.0
3 * core.c - DesignWare USB3 DRD Controller Core file
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
26 #include <linux/acpi.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/reset.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/of.h>
33 #include <linux/usb/otg.h>
41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44 * dwc3_get_dr_mode - Validates and sets dr_mode
45 * @dwc: pointer to our context structure
47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
63 "Controller does not support host mode.\n");
66 mode = USB_DR_MODE_PERIPHERAL;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
71 "Controller does not support device mode.\n");
74 mode = USB_DR_MODE_HOST;
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
83 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
84 * mode. If the controller supports DRD but the dr_mode is not
85 * specified or set to OTG, then set the mode to peripheral.
87 if (mode == USB_DR_MODE_OTG &&
88 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
89 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
90 !DWC3_VER_IS_PRIOR(DWC3, 330A))
91 mode = USB_DR_MODE_PERIPHERAL;
94 if (mode != dwc->dr_mode) {
96 "Configuration mismatch. dr_mode forced to %s\n",
97 mode == USB_DR_MODE_HOST ? "host" : "gadget");
105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
109 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
110 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
111 reg |= DWC3_GCTL_PRTCAPDIR(mode);
112 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
114 dwc->current_dr_role = mode;
117 static void __dwc3_set_mode(struct work_struct *work)
119 struct dwc3 *dwc = work_to_dwc(work);
124 mutex_lock(&dwc->mutex);
126 pm_runtime_get_sync(dwc->dev);
128 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
129 dwc3_otg_update(dwc, 0);
131 if (!dwc->desired_dr_role)
134 if (dwc->desired_dr_role == dwc->current_dr_role)
137 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
140 switch (dwc->current_dr_role) {
141 case DWC3_GCTL_PRTCAP_HOST:
144 case DWC3_GCTL_PRTCAP_DEVICE:
145 dwc3_gadget_exit(dwc);
146 dwc3_event_buffers_cleanup(dwc);
148 case DWC3_GCTL_PRTCAP_OTG:
150 spin_lock_irqsave(&dwc->lock, flags);
151 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
152 spin_unlock_irqrestore(&dwc->lock, flags);
153 dwc3_otg_update(dwc, 1);
160 * When current_dr_role is not set, there's no role switching.
161 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
163 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
164 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
165 dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
166 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
167 reg |= DWC3_GCTL_CORESOFTRESET;
168 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
171 * Wait for internal clocks to synchronized. DWC_usb31 and
172 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
173 * keep it consistent across different IPs, let's wait up to
174 * 100ms before clearing GCTL.CORESOFTRESET.
178 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
179 reg &= ~DWC3_GCTL_CORESOFTRESET;
180 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
183 spin_lock_irqsave(&dwc->lock, flags);
185 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
187 spin_unlock_irqrestore(&dwc->lock, flags);
189 switch (dwc->desired_dr_role) {
190 case DWC3_GCTL_PRTCAP_HOST:
191 ret = dwc3_host_init(dwc);
193 dev_err(dwc->dev, "failed to initialize host\n");
196 otg_set_vbus(dwc->usb2_phy->otg, true);
197 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
198 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
199 if (dwc->dis_split_quirk) {
200 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
201 reg |= DWC3_GUCTL3_SPLITDISABLE;
202 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
206 case DWC3_GCTL_PRTCAP_DEVICE:
207 dwc3_core_soft_reset(dwc);
209 dwc3_event_buffers_setup(dwc);
212 otg_set_vbus(dwc->usb2_phy->otg, false);
213 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
214 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
216 ret = dwc3_gadget_init(dwc);
218 dev_err(dwc->dev, "failed to initialize peripheral\n");
220 case DWC3_GCTL_PRTCAP_OTG:
222 dwc3_otg_update(dwc, 0);
229 pm_runtime_mark_last_busy(dwc->dev);
230 pm_runtime_put_autosuspend(dwc->dev);
231 mutex_unlock(&dwc->mutex);
234 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
238 if (dwc->dr_mode != USB_DR_MODE_OTG)
241 spin_lock_irqsave(&dwc->lock, flags);
242 dwc->desired_dr_role = mode;
243 spin_unlock_irqrestore(&dwc->lock, flags);
245 queue_work(system_freezable_wq, &dwc->drd_work);
248 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
250 struct dwc3 *dwc = dep->dwc;
253 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
254 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
255 DWC3_GDBGFIFOSPACE_TYPE(type));
257 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
259 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
263 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
264 * @dwc: pointer to our context structure
266 int dwc3_core_soft_reset(struct dwc3 *dwc)
272 * We're resetting only the device side because, if we're in host mode,
273 * XHCI driver will reset the host block. If dwc3 was configured for
274 * host-only mode, then we can return early.
276 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
279 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
280 reg |= DWC3_DCTL_CSFTRST;
281 reg &= ~DWC3_DCTL_RUN_STOP;
282 dwc3_gadget_dctl_write_safe(dwc, reg);
285 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
286 * is cleared only after all the clocks are synchronized. This can
287 * take a little more than 50ms. Set the polling rate at 20ms
288 * for 10 times instead.
290 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
294 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
295 if (!(reg & DWC3_DCTL_CSFTRST))
298 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
308 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
309 * is cleared, we must wait at least 50ms before accessing the PHY
310 * domain (synchronization delay).
312 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
319 * dwc3_frame_length_adjustment - Adjusts frame length if required
320 * @dwc3: Pointer to our controller context structure
322 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
327 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
333 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
334 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
335 if (dft != dwc->fladj) {
336 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
337 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
338 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
343 * dwc3_free_one_event_buffer - Frees one event buffer
344 * @dwc: Pointer to our controller context structure
345 * @evt: Pointer to event buffer to be freed
347 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
348 struct dwc3_event_buffer *evt)
350 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
354 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
355 * @dwc: Pointer to our controller context structure
356 * @length: size of the event buffer
358 * Returns a pointer to the allocated event buffer structure on success
359 * otherwise ERR_PTR(errno).
361 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
364 struct dwc3_event_buffer *evt;
366 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
368 return ERR_PTR(-ENOMEM);
371 evt->length = length;
372 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
374 return ERR_PTR(-ENOMEM);
376 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
377 &evt->dma, GFP_KERNEL);
379 return ERR_PTR(-ENOMEM);
385 * dwc3_free_event_buffers - frees all allocated event buffers
386 * @dwc: Pointer to our controller context structure
388 static void dwc3_free_event_buffers(struct dwc3 *dwc)
390 struct dwc3_event_buffer *evt;
394 dwc3_free_one_event_buffer(dwc, evt);
398 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
399 * @dwc: pointer to our controller context structure
400 * @length: size of event buffer
402 * Returns 0 on success otherwise negative errno. In the error case, dwc
403 * may contain some buffers allocated but not all which were requested.
405 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
407 struct dwc3_event_buffer *evt;
409 evt = dwc3_alloc_one_event_buffer(dwc, length);
411 dev_err(dwc->dev, "can't allocate event buffer\n");
420 * dwc3_event_buffers_setup - setup our allocated event buffers
421 * @dwc: pointer to our controller context structure
423 * Returns 0 on success otherwise negative errno.
425 int dwc3_event_buffers_setup(struct dwc3 *dwc)
427 struct dwc3_event_buffer *evt;
431 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
432 lower_32_bits(evt->dma));
433 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
434 upper_32_bits(evt->dma));
435 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
436 DWC3_GEVNTSIZ_SIZE(evt->length));
437 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
442 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
444 struct dwc3_event_buffer *evt;
450 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
451 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
452 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
453 | DWC3_GEVNTSIZ_SIZE(0));
454 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
457 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
459 if (!dwc->has_hibernation)
462 if (!dwc->nr_scratch)
465 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
466 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
467 if (!dwc->scratchbuf)
473 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
475 dma_addr_t scratch_addr;
479 if (!dwc->has_hibernation)
482 if (!dwc->nr_scratch)
485 /* should never fall here */
486 if (!WARN_ON(dwc->scratchbuf))
489 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
490 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
492 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
493 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
498 dwc->scratch_addr = scratch_addr;
500 param = lower_32_bits(scratch_addr);
502 ret = dwc3_send_gadget_generic_command(dwc,
503 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
507 param = upper_32_bits(scratch_addr);
509 ret = dwc3_send_gadget_generic_command(dwc,
510 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
517 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
518 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
524 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
526 if (!dwc->has_hibernation)
529 if (!dwc->nr_scratch)
532 /* should never fall here */
533 if (!WARN_ON(dwc->scratchbuf))
536 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
537 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
538 kfree(dwc->scratchbuf);
541 static void dwc3_core_num_eps(struct dwc3 *dwc)
543 struct dwc3_hwparams *parms = &dwc->hwparams;
545 dwc->num_eps = DWC3_NUM_EPS(parms);
548 static void dwc3_cache_hwparams(struct dwc3 *dwc)
550 struct dwc3_hwparams *parms = &dwc->hwparams;
552 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
553 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
554 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
555 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
556 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
557 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
558 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
559 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
560 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
563 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
568 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
570 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
571 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
572 dwc->hsphy_interface &&
573 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
574 ret = dwc3_ulpi_init(dwc);
580 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
581 * @dwc: Pointer to our controller context structure
583 * Returns 0 on success. The USB PHY interfaces are configured but not
584 * initialized. The PHY interfaces and the PHYs get initialized together with
585 * the core in dwc3_core_init.
587 static int dwc3_phy_setup(struct dwc3 *dwc)
589 unsigned int hw_mode;
592 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
594 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
597 * Make sure UX_EXIT_PX is cleared as that causes issues with some
598 * PHYs. Also, this bit is not supposed to be used in normal operation.
600 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
603 * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
604 * to '0' during coreConsultant configuration. So default value
605 * will be '0' when the core is reset. Application needs to set it
606 * to '1' after the core initialization is completed.
608 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
609 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
612 * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
613 * power-on reset, and it can be set after core initialization, which is
614 * after device soft-reset during initialization.
616 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
617 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
619 if (dwc->u2ss_inp3_quirk)
620 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
622 if (dwc->dis_rxdet_inp3_quirk)
623 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
625 if (dwc->req_p1p2p3_quirk)
626 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
628 if (dwc->del_p1p2p3_quirk)
629 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
631 if (dwc->del_phy_power_chg_quirk)
632 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
634 if (dwc->lfps_filter_quirk)
635 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
637 if (dwc->rx_detect_poll_quirk)
638 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
640 if (dwc->tx_de_emphasis_quirk)
641 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
643 if (dwc->dis_u3_susphy_quirk)
644 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
646 if (dwc->dis_del_phy_power_chg_quirk)
647 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
649 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
651 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
653 /* Select the HS PHY interface */
654 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
655 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
656 if (dwc->hsphy_interface &&
657 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
658 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
660 } else if (dwc->hsphy_interface &&
661 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
662 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
663 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
665 /* Relying on default value. */
666 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
670 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
675 switch (dwc->hsphy_mode) {
676 case USBPHY_INTERFACE_MODE_UTMI:
677 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
678 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
679 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
680 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
682 case USBPHY_INTERFACE_MODE_UTMIW:
683 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
684 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
685 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
686 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
693 * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
694 * '0' during coreConsultant configuration. So default value will
695 * be '0' when the core is reset. Application needs to set it to
696 * '1' after the core initialization is completed.
698 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
699 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
702 * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
703 * power-on reset, and it can be set after core initialization, which is
704 * after device soft-reset during initialization.
706 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
707 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
709 if (dwc->dis_u2_susphy_quirk)
710 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
712 if (dwc->dis_enblslpm_quirk)
713 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
715 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
717 if (dwc->dis_u2_freeclk_exists_quirk)
718 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
720 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
725 static void dwc3_core_exit(struct dwc3 *dwc)
727 dwc3_event_buffers_cleanup(dwc);
729 usb_phy_set_suspend(dwc->usb2_phy, 1);
730 usb_phy_set_suspend(dwc->usb3_phy, 1);
731 phy_power_off(dwc->usb2_generic_phy);
732 phy_power_off(dwc->usb3_generic_phy);
734 usb_phy_shutdown(dwc->usb2_phy);
735 usb_phy_shutdown(dwc->usb3_phy);
736 phy_exit(dwc->usb2_generic_phy);
737 phy_exit(dwc->usb3_generic_phy);
739 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
740 reset_control_assert(dwc->reset);
743 static bool dwc3_core_is_valid(struct dwc3 *dwc)
747 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
748 dwc->ip = DWC3_GSNPS_ID(reg);
750 /* This should read as U3 followed by revision number */
751 if (DWC3_IP_IS(DWC3)) {
753 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
754 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
755 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
763 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
765 u32 hwparams4 = dwc->hwparams.hwparams4;
768 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
769 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
771 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
772 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
774 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
775 * issue which would cause xHCI compliance tests to fail.
777 * Because of that we cannot enable clock gating on such
782 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
785 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
786 dwc->dr_mode == USB_DR_MODE_OTG) &&
787 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
788 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
790 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
792 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
793 /* enable hibernation here */
794 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
797 * REVISIT Enabling this bit so that host-mode hibernation
798 * will work. Device-mode hibernation is not yet implemented.
800 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
807 /* check if current dwc3 is on simulation board */
808 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
809 dev_info(dwc->dev, "Running with FPGA optimizations\n");
813 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
814 "disable_scramble cannot be used on non-FPGA builds\n");
816 if (dwc->disable_scramble_quirk && dwc->is_fpga)
817 reg |= DWC3_GCTL_DISSCRAMBLE;
819 reg &= ~DWC3_GCTL_DISSCRAMBLE;
821 if (dwc->u2exit_lfps_quirk)
822 reg |= DWC3_GCTL_U2EXIT_LFPS;
825 * WORKAROUND: DWC3 revisions <1.90a have a bug
826 * where the device can fail to connect at SuperSpeed
827 * and falls back to high-speed mode which causes
828 * the device to enter a Connect/Disconnect loop
830 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
831 reg |= DWC3_GCTL_U2RSTECN;
833 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
836 static int dwc3_core_get_phy(struct dwc3 *dwc);
837 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
839 /* set global incr burst type configuration registers */
840 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
842 struct device *dev = dwc->dev;
843 /* incrx_mode : for INCR burst type. */
845 /* incrx_size : for size of INCRX burst. */
853 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
856 * Handle property "snps,incr-burst-type-adjustment".
857 * Get the number of value from this property:
858 * result <= 0, means this property is not supported.
859 * result = 1, means INCRx burst mode supported.
860 * result > 1, means undefined length burst mode supported.
862 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
866 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
868 dev_err(dev, "Error to get memory\n");
872 /* Get INCR burst type, and parse it */
873 ret = device_property_read_u32_array(dev,
874 "snps,incr-burst-type-adjustment", vals, ntype);
877 dev_err(dev, "Error to get property\n");
884 /* INCRX (undefined length) burst mode */
885 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
886 for (i = 1; i < ntype; i++) {
887 if (vals[i] > incrx_size)
888 incrx_size = vals[i];
891 /* INCRX burst mode */
892 incrx_mode = INCRX_BURST_MODE;
897 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
898 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
900 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
901 switch (incrx_size) {
903 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
906 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
909 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
912 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
915 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
918 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
921 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
926 dev_err(dev, "Invalid property\n");
930 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
934 * dwc3_core_init - Low-level initialization of DWC3 Core
935 * @dwc: Pointer to our controller context structure
937 * Returns 0 on success otherwise negative errno.
939 static int dwc3_core_init(struct dwc3 *dwc)
941 unsigned int hw_mode;
945 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
948 * Write Linux Version Code to our GUID register so it's easy to figure
949 * out which kernel version a bug was found.
951 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
953 ret = dwc3_phy_setup(dwc);
957 if (!dwc->ulpi_ready) {
958 ret = dwc3_core_ulpi_init(dwc);
961 dwc->ulpi_ready = true;
964 if (!dwc->phys_ready) {
965 ret = dwc3_core_get_phy(dwc);
968 dwc->phys_ready = true;
971 usb_phy_init(dwc->usb2_phy);
972 usb_phy_init(dwc->usb3_phy);
973 ret = phy_init(dwc->usb2_generic_phy);
977 ret = phy_init(dwc->usb3_generic_phy);
979 phy_exit(dwc->usb2_generic_phy);
983 ret = dwc3_core_soft_reset(dwc);
987 if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
988 !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
989 if (!dwc->dis_u3_susphy_quirk) {
990 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
991 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
992 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
995 if (!dwc->dis_u2_susphy_quirk) {
996 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
997 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
998 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1002 dwc3_core_setup_global_control(dwc);
1003 dwc3_core_num_eps(dwc);
1005 ret = dwc3_setup_scratch_buffers(dwc);
1009 /* Adjust Frame Length */
1010 dwc3_frame_length_adjustment(dwc);
1012 dwc3_set_incr_burst_type(dwc);
1014 usb_phy_set_suspend(dwc->usb2_phy, 0);
1015 usb_phy_set_suspend(dwc->usb3_phy, 0);
1016 ret = phy_power_on(dwc->usb2_generic_phy);
1020 ret = phy_power_on(dwc->usb3_generic_phy);
1024 ret = dwc3_event_buffers_setup(dwc);
1026 dev_err(dwc->dev, "failed to setup event buffers\n");
1031 * ENDXFER polling is available on version 3.10a and later of
1032 * the DWC_usb3 controller. It is NOT available in the
1033 * DWC_usb31 controller.
1035 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1036 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1037 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1038 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1041 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1042 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1045 * Enable hardware control of sending remote wakeup
1046 * in HS when the device is in the L1 state.
1048 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1049 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1051 if (dwc->dis_tx_ipgap_linecheck_quirk)
1052 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1054 if (dwc->parkmode_disable_ss_quirk)
1055 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1057 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1060 if (dwc->dr_mode == USB_DR_MODE_HOST ||
1061 dwc->dr_mode == USB_DR_MODE_OTG) {
1062 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1065 * Enable Auto retry Feature to make the controller operating in
1066 * Host mode on seeing transaction errors(CRC errors or internal
1067 * overrun scenerios) on IN transfers to reply to the device
1068 * with a non-terminating retry ACK (i.e, an ACK transcation
1069 * packet with Retry=1 & Nump != 0)
1071 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1073 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1077 * Must config both number of packets and max burst settings to enable
1078 * RX and/or TX threshold.
1080 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1081 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1082 u8 rx_maxburst = dwc->rx_max_burst_prd;
1083 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1084 u8 tx_maxburst = dwc->tx_max_burst_prd;
1086 if (rx_thr_num && rx_maxburst) {
1087 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1088 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1090 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1091 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1093 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1094 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1096 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1099 if (tx_thr_num && tx_maxburst) {
1100 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1101 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1103 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1104 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1106 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1107 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1109 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1116 phy_power_off(dwc->usb3_generic_phy);
1119 phy_power_off(dwc->usb2_generic_phy);
1122 usb_phy_set_suspend(dwc->usb2_phy, 1);
1123 usb_phy_set_suspend(dwc->usb3_phy, 1);
1126 usb_phy_shutdown(dwc->usb2_phy);
1127 usb_phy_shutdown(dwc->usb3_phy);
1128 phy_exit(dwc->usb2_generic_phy);
1129 phy_exit(dwc->usb3_generic_phy);
1132 dwc3_ulpi_exit(dwc);
1138 static int dwc3_core_get_phy(struct dwc3 *dwc)
1140 struct device *dev = dwc->dev;
1141 struct device_node *node = dev->of_node;
1145 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1146 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1148 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1149 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1152 if (IS_ERR(dwc->usb2_phy)) {
1153 ret = PTR_ERR(dwc->usb2_phy);
1154 if (ret == -ENXIO || ret == -ENODEV) {
1155 dwc->usb2_phy = NULL;
1156 } else if (ret == -EPROBE_DEFER) {
1159 dev_err(dev, "no usb2 phy configured\n");
1164 if (IS_ERR(dwc->usb3_phy)) {
1165 ret = PTR_ERR(dwc->usb3_phy);
1166 if (ret == -ENXIO || ret == -ENODEV) {
1167 dwc->usb3_phy = NULL;
1168 } else if (ret == -EPROBE_DEFER) {
1171 dev_err(dev, "no usb3 phy configured\n");
1176 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1177 if (IS_ERR(dwc->usb2_generic_phy)) {
1178 ret = PTR_ERR(dwc->usb2_generic_phy);
1179 if (ret == -ENOSYS || ret == -ENODEV) {
1180 dwc->usb2_generic_phy = NULL;
1181 } else if (ret == -EPROBE_DEFER) {
1184 dev_err(dev, "no usb2 phy configured\n");
1189 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1190 if (IS_ERR(dwc->usb3_generic_phy)) {
1191 ret = PTR_ERR(dwc->usb3_generic_phy);
1192 if (ret == -ENOSYS || ret == -ENODEV) {
1193 dwc->usb3_generic_phy = NULL;
1194 } else if (ret == -EPROBE_DEFER) {
1197 dev_err(dev, "no usb3 phy configured\n");
1205 static int dwc3_core_init_mode(struct dwc3 *dwc)
1207 struct device *dev = dwc->dev;
1210 switch (dwc->dr_mode) {
1211 case USB_DR_MODE_PERIPHERAL:
1212 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1215 otg_set_vbus(dwc->usb2_phy->otg, false);
1216 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1217 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1219 ret = dwc3_gadget_init(dwc);
1221 if (ret != -EPROBE_DEFER)
1222 dev_err(dev, "failed to initialize gadget\n");
1226 case USB_DR_MODE_HOST:
1227 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1230 otg_set_vbus(dwc->usb2_phy->otg, true);
1231 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1232 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1234 ret = dwc3_host_init(dwc);
1236 if (ret != -EPROBE_DEFER)
1237 dev_err(dev, "failed to initialize host\n");
1241 case USB_DR_MODE_OTG:
1242 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1243 ret = dwc3_drd_init(dwc);
1245 if (ret != -EPROBE_DEFER)
1246 dev_err(dev, "failed to initialize dual-role\n");
1251 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1258 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1260 switch (dwc->dr_mode) {
1261 case USB_DR_MODE_PERIPHERAL:
1262 dwc3_gadget_exit(dwc);
1264 case USB_DR_MODE_HOST:
1265 dwc3_host_exit(dwc);
1267 case USB_DR_MODE_OTG:
1275 /* de-assert DRVVBUS for HOST and OTG mode */
1276 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1279 static void dwc3_get_properties(struct dwc3 *dwc)
1281 struct device *dev = dwc->dev;
1282 u8 lpm_nyet_threshold;
1285 u8 rx_thr_num_pkt_prd = 0;
1286 u8 rx_max_burst_prd = 0;
1287 u8 tx_thr_num_pkt_prd = 0;
1288 u8 tx_max_burst_prd = 0;
1290 /* default to highest possible threshold */
1291 lpm_nyet_threshold = 0xf;
1293 /* default to -3.5dB de-emphasis */
1297 * default to assert utmi_sleep_n and use maximum allowed HIRD
1298 * threshold value of 0b1100
1300 hird_threshold = 12;
1302 dwc->maximum_speed = usb_get_maximum_speed(dev);
1303 dwc->dr_mode = usb_get_dr_mode(dev);
1304 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1306 dwc->sysdev_is_parent = device_property_read_bool(dev,
1307 "linux,sysdev_is_parent");
1308 if (dwc->sysdev_is_parent)
1309 dwc->sysdev = dwc->dev->parent;
1311 dwc->sysdev = dwc->dev;
1313 dwc->has_lpm_erratum = device_property_read_bool(dev,
1314 "snps,has-lpm-erratum");
1315 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1316 &lpm_nyet_threshold);
1317 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1318 "snps,is-utmi-l1-suspend");
1319 device_property_read_u8(dev, "snps,hird-threshold",
1321 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1322 "snps,dis-start-transfer-quirk");
1323 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1324 "snps,usb3_lpm_capable");
1325 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1326 "snps,usb2-lpm-disable");
1327 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1328 "snps,usb2-gadget-lpm-disable");
1329 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1330 &rx_thr_num_pkt_prd);
1331 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1333 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1334 &tx_thr_num_pkt_prd);
1335 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1338 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1339 "snps,disable_scramble_quirk");
1340 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1341 "snps,u2exit_lfps_quirk");
1342 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1343 "snps,u2ss_inp3_quirk");
1344 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1345 "snps,req_p1p2p3_quirk");
1346 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1347 "snps,del_p1p2p3_quirk");
1348 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1349 "snps,del_phy_power_chg_quirk");
1350 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1351 "snps,lfps_filter_quirk");
1352 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1353 "snps,rx_detect_poll_quirk");
1354 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1355 "snps,dis_u3_susphy_quirk");
1356 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1357 "snps,dis_u2_susphy_quirk");
1358 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1359 "snps,dis_enblslpm_quirk");
1360 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1361 "snps,dis-u1-entry-quirk");
1362 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1363 "snps,dis-u2-entry-quirk");
1364 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1365 "snps,dis_rxdet_inp3_quirk");
1366 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1367 "snps,dis-u2-freeclk-exists-quirk");
1368 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1369 "snps,dis-del-phy-power-chg-quirk");
1370 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1371 "snps,dis-tx-ipgap-linecheck-quirk");
1372 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1373 "snps,parkmode-disable-ss-quirk");
1375 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1376 "snps,tx_de_emphasis_quirk");
1377 device_property_read_u8(dev, "snps,tx_de_emphasis",
1379 device_property_read_string(dev, "snps,hsphy_interface",
1380 &dwc->hsphy_interface);
1381 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1384 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1385 "snps,dis_metastability_quirk");
1387 dwc->dis_split_quirk = device_property_read_bool(dev,
1388 "snps,dis-split-quirk");
1390 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1391 dwc->tx_de_emphasis = tx_de_emphasis;
1393 dwc->hird_threshold = hird_threshold;
1395 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1396 dwc->rx_max_burst_prd = rx_max_burst_prd;
1398 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1399 dwc->tx_max_burst_prd = tx_max_burst_prd;
1401 dwc->imod_interval = 0;
1404 /* check whether the core supports IMOD */
1405 bool dwc3_has_imod(struct dwc3 *dwc)
1407 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1408 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1412 static void dwc3_check_params(struct dwc3 *dwc)
1414 struct device *dev = dwc->dev;
1415 unsigned int hwparam_gen =
1416 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1418 /* Check for proper value of imod_interval */
1419 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1420 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1421 dwc->imod_interval = 0;
1425 * Workaround for STAR 9000961433 which affects only version
1426 * 3.00a of the DWC_usb3 core. This prevents the controller
1427 * interrupt from being masked while handling events. IMOD
1428 * allows us to work around this issue. Enable it for the
1431 if (!dwc->imod_interval &&
1432 DWC3_VER_IS(DWC3, 300A))
1433 dwc->imod_interval = 1;
1435 /* Check the maximum_speed parameter */
1436 switch (dwc->maximum_speed) {
1438 case USB_SPEED_FULL:
1439 case USB_SPEED_HIGH:
1441 case USB_SPEED_SUPER:
1442 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1443 dev_warn(dev, "UDC doesn't support Gen 1\n");
1445 case USB_SPEED_SUPER_PLUS:
1446 if ((DWC3_IP_IS(DWC32) &&
1447 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1448 (!DWC3_IP_IS(DWC32) &&
1449 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1450 dev_warn(dev, "UDC doesn't support SSP\n");
1453 dev_err(dev, "invalid maximum_speed parameter %d\n",
1454 dwc->maximum_speed);
1456 case USB_SPEED_UNKNOWN:
1457 switch (hwparam_gen) {
1458 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1459 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1461 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1462 if (DWC3_IP_IS(DWC32))
1463 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1465 dwc->maximum_speed = USB_SPEED_SUPER;
1467 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1468 dwc->maximum_speed = USB_SPEED_HIGH;
1471 dwc->maximum_speed = USB_SPEED_SUPER;
1478 static int dwc3_probe(struct platform_device *pdev)
1480 struct device *dev = &pdev->dev;
1481 struct resource *res, dwc_res;
1488 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1494 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1496 dev_err(dev, "missing memory resource\n");
1500 dwc->xhci_resources[0].start = res->start;
1501 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1503 dwc->xhci_resources[0].flags = res->flags;
1504 dwc->xhci_resources[0].name = res->name;
1507 * Request memory region but exclude xHCI regs,
1508 * since it will be requested by the xhci-plat driver.
1511 dwc_res.start += DWC3_GLOBALS_REGS_START;
1513 regs = devm_ioremap_resource(dev, &dwc_res);
1515 return PTR_ERR(regs);
1518 dwc->regs_size = resource_size(&dwc_res);
1520 dwc3_get_properties(dwc);
1522 dwc->reset = devm_reset_control_array_get(dev, true, true);
1523 if (IS_ERR(dwc->reset))
1524 return PTR_ERR(dwc->reset);
1527 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1528 if (ret == -EPROBE_DEFER)
1531 * Clocks are optional, but new DT platforms should support all
1532 * clocks as required by the DT-binding.
1537 dwc->num_clks = ret;
1541 ret = reset_control_deassert(dwc->reset);
1545 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1549 if (!dwc3_core_is_valid(dwc)) {
1550 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1555 platform_set_drvdata(pdev, dwc);
1556 dwc3_cache_hwparams(dwc);
1558 spin_lock_init(&dwc->lock);
1559 mutex_init(&dwc->mutex);
1561 pm_runtime_set_active(dev);
1562 pm_runtime_use_autosuspend(dev);
1563 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1564 pm_runtime_enable(dev);
1565 ret = pm_runtime_get_sync(dev);
1569 pm_runtime_forbid(dev);
1571 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1573 dev_err(dwc->dev, "failed to allocate event buffers\n");
1578 ret = dwc3_get_dr_mode(dwc);
1582 ret = dwc3_alloc_scratch_buffers(dwc);
1586 ret = dwc3_core_init(dwc);
1588 if (ret != -EPROBE_DEFER)
1589 dev_err(dev, "failed to initialize core: %d\n", ret);
1593 dwc3_check_params(dwc);
1594 dwc3_debugfs_init(dwc);
1596 ret = dwc3_core_init_mode(dwc);
1600 pm_runtime_put(dev);
1605 dwc3_debugfs_exit(dwc);
1606 dwc3_event_buffers_cleanup(dwc);
1608 usb_phy_set_suspend(dwc->usb2_phy, 1);
1609 usb_phy_set_suspend(dwc->usb3_phy, 1);
1610 phy_power_off(dwc->usb2_generic_phy);
1611 phy_power_off(dwc->usb3_generic_phy);
1613 usb_phy_shutdown(dwc->usb2_phy);
1614 usb_phy_shutdown(dwc->usb3_phy);
1615 phy_exit(dwc->usb2_generic_phy);
1616 phy_exit(dwc->usb3_generic_phy);
1618 dwc3_ulpi_exit(dwc);
1621 dwc3_free_scratch_buffers(dwc);
1624 dwc3_free_event_buffers(dwc);
1627 pm_runtime_allow(&pdev->dev);
1630 pm_runtime_put_sync(&pdev->dev);
1631 pm_runtime_disable(&pdev->dev);
1634 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1636 reset_control_assert(dwc->reset);
1641 static int dwc3_remove(struct platform_device *pdev)
1643 struct dwc3 *dwc = platform_get_drvdata(pdev);
1645 pm_runtime_get_sync(&pdev->dev);
1647 dwc3_core_exit_mode(dwc);
1648 dwc3_debugfs_exit(dwc);
1650 dwc3_core_exit(dwc);
1651 dwc3_ulpi_exit(dwc);
1653 pm_runtime_disable(&pdev->dev);
1654 pm_runtime_put_noidle(&pdev->dev);
1655 pm_runtime_set_suspended(&pdev->dev);
1657 dwc3_free_event_buffers(dwc);
1658 dwc3_free_scratch_buffers(dwc);
1664 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1668 ret = reset_control_deassert(dwc->reset);
1672 ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1676 ret = dwc3_core_init(dwc);
1683 clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1685 reset_control_assert(dwc->reset);
1690 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1692 unsigned long flags;
1695 switch (dwc->current_dr_role) {
1696 case DWC3_GCTL_PRTCAP_DEVICE:
1697 if (pm_runtime_suspended(dwc->dev))
1699 spin_lock_irqsave(&dwc->lock, flags);
1700 dwc3_gadget_suspend(dwc);
1701 spin_unlock_irqrestore(&dwc->lock, flags);
1702 synchronize_irq(dwc->irq_gadget);
1703 dwc3_core_exit(dwc);
1705 case DWC3_GCTL_PRTCAP_HOST:
1706 if (!PMSG_IS_AUTO(msg)) {
1707 dwc3_core_exit(dwc);
1711 /* Let controller to suspend HSPHY before PHY driver suspends */
1712 if (dwc->dis_u2_susphy_quirk ||
1713 dwc->dis_enblslpm_quirk) {
1714 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1715 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1716 DWC3_GUSB2PHYCFG_SUSPHY;
1717 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1719 /* Give some time for USB2 PHY to suspend */
1720 usleep_range(5000, 6000);
1723 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1724 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1726 case DWC3_GCTL_PRTCAP_OTG:
1727 /* do nothing during runtime_suspend */
1728 if (PMSG_IS_AUTO(msg))
1731 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1732 spin_lock_irqsave(&dwc->lock, flags);
1733 dwc3_gadget_suspend(dwc);
1734 spin_unlock_irqrestore(&dwc->lock, flags);
1735 synchronize_irq(dwc->irq_gadget);
1739 dwc3_core_exit(dwc);
1749 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1751 unsigned long flags;
1755 switch (dwc->current_dr_role) {
1756 case DWC3_GCTL_PRTCAP_DEVICE:
1757 ret = dwc3_core_init_for_resume(dwc);
1761 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1762 spin_lock_irqsave(&dwc->lock, flags);
1763 dwc3_gadget_resume(dwc);
1764 spin_unlock_irqrestore(&dwc->lock, flags);
1766 case DWC3_GCTL_PRTCAP_HOST:
1767 if (!PMSG_IS_AUTO(msg)) {
1768 ret = dwc3_core_init_for_resume(dwc);
1771 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1774 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1775 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1776 if (dwc->dis_u2_susphy_quirk)
1777 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1779 if (dwc->dis_enblslpm_quirk)
1780 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1782 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1784 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1785 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1787 case DWC3_GCTL_PRTCAP_OTG:
1788 /* nothing to do on runtime_resume */
1789 if (PMSG_IS_AUTO(msg))
1792 ret = dwc3_core_init_for_resume(dwc);
1796 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1799 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1800 dwc3_otg_host_init(dwc);
1801 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1802 spin_lock_irqsave(&dwc->lock, flags);
1803 dwc3_gadget_resume(dwc);
1804 spin_unlock_irqrestore(&dwc->lock, flags);
1816 static int dwc3_runtime_checks(struct dwc3 *dwc)
1818 switch (dwc->current_dr_role) {
1819 case DWC3_GCTL_PRTCAP_DEVICE:
1823 case DWC3_GCTL_PRTCAP_HOST:
1832 static int dwc3_runtime_suspend(struct device *dev)
1834 struct dwc3 *dwc = dev_get_drvdata(dev);
1837 if (dwc3_runtime_checks(dwc))
1840 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1844 device_init_wakeup(dev, true);
1849 static int dwc3_runtime_resume(struct device *dev)
1851 struct dwc3 *dwc = dev_get_drvdata(dev);
1854 device_init_wakeup(dev, false);
1856 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1860 switch (dwc->current_dr_role) {
1861 case DWC3_GCTL_PRTCAP_DEVICE:
1862 dwc3_gadget_process_pending_events(dwc);
1864 case DWC3_GCTL_PRTCAP_HOST:
1870 pm_runtime_mark_last_busy(dev);
1875 static int dwc3_runtime_idle(struct device *dev)
1877 struct dwc3 *dwc = dev_get_drvdata(dev);
1879 switch (dwc->current_dr_role) {
1880 case DWC3_GCTL_PRTCAP_DEVICE:
1881 if (dwc3_runtime_checks(dwc))
1884 case DWC3_GCTL_PRTCAP_HOST:
1890 pm_runtime_mark_last_busy(dev);
1891 pm_runtime_autosuspend(dev);
1895 #endif /* CONFIG_PM */
1897 #ifdef CONFIG_PM_SLEEP
1898 static int dwc3_suspend(struct device *dev)
1900 struct dwc3 *dwc = dev_get_drvdata(dev);
1903 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1907 pinctrl_pm_select_sleep_state(dev);
1912 static int dwc3_resume(struct device *dev)
1914 struct dwc3 *dwc = dev_get_drvdata(dev);
1917 pinctrl_pm_select_default_state(dev);
1919 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1923 pm_runtime_disable(dev);
1924 pm_runtime_set_active(dev);
1925 pm_runtime_enable(dev);
1930 static void dwc3_complete(struct device *dev)
1932 struct dwc3 *dwc = dev_get_drvdata(dev);
1935 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1936 dwc->dis_split_quirk) {
1937 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1938 reg |= DWC3_GUCTL3_SPLITDISABLE;
1939 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1943 #define dwc3_complete NULL
1944 #endif /* CONFIG_PM_SLEEP */
1946 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1947 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1948 .complete = dwc3_complete,
1949 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1954 static const struct of_device_id of_dwc3_match[] = {
1956 .compatible = "snps,dwc3"
1959 .compatible = "synopsys,dwc3"
1963 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1968 #define ACPI_ID_INTEL_BSW "808622B7"
1970 static const struct acpi_device_id dwc3_acpi_match[] = {
1971 { ACPI_ID_INTEL_BSW, 0 },
1974 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1977 static struct platform_driver dwc3_driver = {
1978 .probe = dwc3_probe,
1979 .remove = dwc3_remove,
1982 .of_match_table = of_match_ptr(of_dwc3_match),
1983 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1984 .pm = &dwc3_dev_pm_ops,
1988 module_platform_driver(dwc3_driver);
1990 MODULE_ALIAS("platform:dwc3");
1991 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1992 MODULE_LICENSE("GPL v2");
1993 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");