drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                  * mode. If the controller supports DRD but the dr_mode is not
  85                  * specified or set to OTG, then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG &&
  88                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  89                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  90                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  91                         mode = USB_DR_MODE_PERIPHERAL;
  92         }
  93
  94         if (mode != dwc->dr_mode) {
  95                 dev_warn(dev,
  96                          "Configuration mismatch. dr_mode forced to %s\n",
  97                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  98
  99                 dwc->dr_mode = mode;
 100         }
 101
 102         return 0;
 103 }
 104
 105 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
 106 {
 107         u32 reg;
 108
 109         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 110         if (enable && !dwc->dis_u3_susphy_quirk)
 111                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 112         else
 113                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 114
 115         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 118         if (enable && !dwc->dis_u2_susphy_quirk)
 119                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 120         else
 121                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 122
 123         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 124 }
 125
 126 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 127 {
 128         u32 reg;
 129
 130         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 131         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 132         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 133         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 134
 135         dwc->current_dr_role = mode;
 136 }
 137
 138 static void __dwc3_set_mode(struct work_struct *work)
 139 {
 140         struct dwc3 *dwc = work_to_dwc(work);
 141         unsigned long flags;
 142         int ret;
 143         u32 reg;
 144         u32 desired_dr_role;
 145
 146         mutex_lock(&dwc->mutex);
 147         spin_lock_irqsave(&dwc->lock, flags);
 148         desired_dr_role = dwc->desired_dr_role;
 149         spin_unlock_irqrestore(&dwc->lock, flags);
 150
 151         pm_runtime_get_sync(dwc->dev);
 152
 153         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 154                 dwc3_otg_update(dwc, 0);
 155
 156         if (!desired_dr_role)
 157                 goto out;
 158
 159         if (desired_dr_role == dwc->current_dr_role)
 160                 goto out;
 161
 162         if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 163                 goto out;
 164
 165         switch (dwc->current_dr_role) {
 166         case DWC3_GCTL_PRTCAP_HOST:
 167                 dwc3_host_exit(dwc);
 168                 break;
 169         case DWC3_GCTL_PRTCAP_DEVICE:
 170                 dwc3_gadget_exit(dwc);
 171                 dwc3_event_buffers_cleanup(dwc);
 172                 break;
 173         case DWC3_GCTL_PRTCAP_OTG:
 174                 dwc3_otg_exit(dwc);
 175                 spin_lock_irqsave(&dwc->lock, flags);
 176                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 177                 spin_unlock_irqrestore(&dwc->lock, flags);
 178                 dwc3_otg_update(dwc, 1);
 179                 break;
 180         default:
 181                 break;
 182         }
 183
 184         /*
 185          * When current_dr_role is not set, there's no role switching.
 186          * Only perform GCTL.CoreSoftReset when there's DRD role switching.
 187          */
 188         if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
 189                         DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
 190                         desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
 191                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 192                 reg |= DWC3_GCTL_CORESOFTRESET;
 193                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 194
 195                 /*
 196                  * Wait for internal clocks to synchronized. DWC_usb31 and
 197                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 198                  * keep it consistent across different IPs, let's wait up to
 199                  * 100ms before clearing GCTL.CORESOFTRESET.
 200                  */
 201                 msleep(100);
 202
 203                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 204                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 205                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 206         }
 207
 208         spin_lock_irqsave(&dwc->lock, flags);
 209
 210         dwc3_set_prtcap(dwc, desired_dr_role);
 211
 212         spin_unlock_irqrestore(&dwc->lock, flags);
 213
 214         switch (desired_dr_role) {
 215         case DWC3_GCTL_PRTCAP_HOST:
 216                 ret = dwc3_host_init(dwc);
 217                 if (ret) {
 218                         dev_err(dwc->dev, "failed to initialize host\n");
 219                 } else {
 220                         if (dwc->usb2_phy)
 221                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 222                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 223                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 224                         if (dwc->dis_split_quirk) {
 225                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 226                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 227                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 228                         }
 229                 }
 230                 break;
 231         case DWC3_GCTL_PRTCAP_DEVICE:
 232                 dwc3_core_soft_reset(dwc);
 233
 234                 dwc3_event_buffers_setup(dwc);
 235
 236                 if (dwc->usb2_phy)
 237                         otg_set_vbus(dwc->usb2_phy->otg, false);
 238                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 239                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 240
 241                 ret = dwc3_gadget_init(dwc);
 242                 if (ret)
 243                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 244                 break;
 245         case DWC3_GCTL_PRTCAP_OTG:
 246                 dwc3_otg_init(dwc);
 247                 dwc3_otg_update(dwc, 0);
 248                 break;
 249         default:
 250                 break;
 251         }
 252
 253 out:
 254         pm_runtime_mark_last_busy(dwc->dev);
 255         pm_runtime_put_autosuspend(dwc->dev);
 256         mutex_unlock(&dwc->mutex);
 257 }
 258
 259 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 260 {
 261         unsigned long flags;
 262
 263         if (dwc->dr_mode != USB_DR_MODE_OTG)
 264                 return;
 265
 266         spin_lock_irqsave(&dwc->lock, flags);
 267         dwc->desired_dr_role = mode;
 268         spin_unlock_irqrestore(&dwc->lock, flags);
 269
 270         queue_work(system_freezable_wq, &dwc->drd_work);
 271 }
 272
 273 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 274 {
 275         struct dwc3             *dwc = dep->dwc;
 276         u32                     reg;
 277
 278         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 279                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 280                         DWC3_GDBGFIFOSPACE_TYPE(type));
 281
 282         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 283
 284         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 285 }
 286
 287 /**
 288  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 289  * @dwc: pointer to our context structure
 290  */
 291 int dwc3_core_soft_reset(struct dwc3 *dwc)
 292 {
 293         u32             reg;
 294         int             retries = 1000;
 295
 296         /*
 297          * We're resetting only the device side because, if we're in host mode,
 298          * XHCI driver will reset the host block. If dwc3 was configured for
 299          * host-only mode, then we can return early.
 300          */
 301         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 302                 return 0;
 303
 304         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 305         reg |= DWC3_DCTL_CSFTRST;
 306         reg &= ~DWC3_DCTL_RUN_STOP;
 307         dwc3_gadget_dctl_write_safe(dwc, reg);
 308
 309         /*
 310          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 311          * is cleared only after all the clocks are synchronized. This can
 312          * take a little more than 50ms. Set the polling rate at 20ms
 313          * for 10 times instead.
 314          */
 315         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 316                 retries = 10;
 317
 318         do {
 319                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 320                 if (!(reg & DWC3_DCTL_CSFTRST))
 321                         goto done;
 322
 323                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 324                         msleep(20);
 325                 else
 326                         udelay(1);
 327         } while (--retries);
 328
 329         return -ETIMEDOUT;
 330
 331 done:
 332         /*
 333          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 334          * is cleared, we must wait at least 50ms before accessing the PHY
 335          * domain (synchronization delay).
 336          */
 337         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 338                 msleep(50);
 339
 340         return 0;
 341 }
 342
 343 /*
 344  * dwc3_frame_length_adjustment - Adjusts frame length if required
 345  * @dwc3: Pointer to our controller context structure
 346  */
 347 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 348 {
 349         u32 reg;
 350         u32 dft;
 351
 352         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 353                 return;
 354
 355         if (dwc->fladj == 0)
 356                 return;
 357
 358         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 359         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 360         if (dft != dwc->fladj) {
 361                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 362                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 363                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 364         }
 365 }
 366
 367 /**
 368  * dwc3_free_one_event_buffer - Frees one event buffer
 369  * @dwc: Pointer to our controller context structure
 370  * @evt: Pointer to event buffer to be freed
 371  */
 372 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 373                 struct dwc3_event_buffer *evt)
 374 {
 375         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 376 }
 377
 378 /**
 379  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 380  * @dwc: Pointer to our controller context structure
 381  * @length: size of the event buffer
 382  *
 383  * Returns a pointer to the allocated event buffer structure on success
 384  * otherwise ERR_PTR(errno).
 385  */
 386 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 387                 unsigned length)
 388 {
 389         struct dwc3_event_buffer        *evt;
 390
 391         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 392         if (!evt)
 393                 return ERR_PTR(-ENOMEM);
 394
 395         evt->dwc        = dwc;
 396         evt->length     = length;
 397         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 398         if (!evt->cache)
 399                 return ERR_PTR(-ENOMEM);
 400
 401         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 402                         &evt->dma, GFP_KERNEL);
 403         if (!evt->buf)
 404                 return ERR_PTR(-ENOMEM);
 405
 406         return evt;
 407 }
 408
 409 /**
 410  * dwc3_free_event_buffers - frees all allocated event buffers
 411  * @dwc: Pointer to our controller context structure
 412  */
 413 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 414 {
 415         struct dwc3_event_buffer        *evt;
 416
 417         evt = dwc->ev_buf;
 418         if (evt)
 419                 dwc3_free_one_event_buffer(dwc, evt);
 420 }
 421
 422 /**
 423  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 424  * @dwc: pointer to our controller context structure
 425  * @length: size of event buffer
 426  *
 427  * Returns 0 on success otherwise negative errno. In the error case, dwc
 428  * may contain some buffers allocated but not all which were requested.
 429  */
 430 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 431 {
 432         struct dwc3_event_buffer *evt;
 433
 434         evt = dwc3_alloc_one_event_buffer(dwc, length);
 435         if (IS_ERR(evt)) {
 436                 dev_err(dwc->dev, "can't allocate event buffer\n");
 437                 return PTR_ERR(evt);
 438         }
 439         dwc->ev_buf = evt;
 440
 441         return 0;
 442 }
 443
 444 /**
 445  * dwc3_event_buffers_setup - setup our allocated event buffers
 446  * @dwc: pointer to our controller context structure
 447  *
 448  * Returns 0 on success otherwise negative errno.
 449  */
 450 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 451 {
 452         struct dwc3_event_buffer        *evt;
 453
 454         evt = dwc->ev_buf;
 455         evt->lpos = 0;
 456         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 457                         lower_32_bits(evt->dma));
 458         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 459                         upper_32_bits(evt->dma));
 460         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 461                         DWC3_GEVNTSIZ_SIZE(evt->length));
 462         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 463
 464         return 0;
 465 }
 466
 467 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 468 {
 469         struct dwc3_event_buffer        *evt;
 470
 471         evt = dwc->ev_buf;
 472
 473         evt->lpos = 0;
 474
 475         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 476         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 477         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 478                         | DWC3_GEVNTSIZ_SIZE(0));
 479         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 480 }
 481
 482 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 483 {
 484         if (!dwc->has_hibernation)
 485                 return 0;
 486
 487         if (!dwc->nr_scratch)
 488                 return 0;
 489
 490         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 491                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 492         if (!dwc->scratchbuf)
 493                 return -ENOMEM;
 494
 495         return 0;
 496 }
 497
 498 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 499 {
 500         dma_addr_t scratch_addr;
 501         u32 param;
 502         int ret;
 503
 504         if (!dwc->has_hibernation)
 505                 return 0;
 506
 507         if (!dwc->nr_scratch)
 508                 return 0;
 509
 510          /* should never fall here */
 511         if (!WARN_ON(dwc->scratchbuf))
 512                 return 0;
 513
 514         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 515                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 516                         DMA_BIDIRECTIONAL);
 517         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 518                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 519                 ret = -EFAULT;
 520                 goto err0;
 521         }
 522
 523         dwc->scratch_addr = scratch_addr;
 524
 525         param = lower_32_bits(scratch_addr);
 526
 527         ret = dwc3_send_gadget_generic_command(dwc,
 528                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 529         if (ret < 0)
 530                 goto err1;
 531
 532         param = upper_32_bits(scratch_addr);
 533
 534         ret = dwc3_send_gadget_generic_command(dwc,
 535                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 536         if (ret < 0)
 537                 goto err1;
 538
 539         return 0;
 540
 541 err1:
 542         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 543                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 544
 545 err0:
 546         return ret;
 547 }
 548
 549 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 550 {
 551         if (!dwc->has_hibernation)
 552                 return;
 553
 554         if (!dwc->nr_scratch)
 555                 return;
 556
 557          /* should never fall here */
 558         if (!WARN_ON(dwc->scratchbuf))
 559                 return;
 560
 561         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 562                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 563         kfree(dwc->scratchbuf);
 564 }
 565
 566 static void dwc3_core_num_eps(struct dwc3 *dwc)
 567 {
 568         struct dwc3_hwparams    *parms = &dwc->hwparams;
 569
 570         dwc->num_eps = DWC3_NUM_EPS(parms);
 571 }
 572
 573 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 574 {
 575         struct dwc3_hwparams    *parms = &dwc->hwparams;
 576
 577         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 578         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 579         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 580         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 581         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 582         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 583         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 584         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 585         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 586 }
 587
 588 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 589 {
 590         int intf;
 591         int ret = 0;
 592
 593         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 594
 595         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 596             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 597              dwc->hsphy_interface &&
 598              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 599                 ret = dwc3_ulpi_init(dwc);
 600
 601         return ret;
 602 }
 603
 604 /**
 605  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 606  * @dwc: Pointer to our controller context structure
 607  *
 608  * Returns 0 on success. The USB PHY interfaces are configured but not
 609  * initialized. The PHY interfaces and the PHYs get initialized together with
 610  * the core in dwc3_core_init.
 611  */
 612 static int dwc3_phy_setup(struct dwc3 *dwc)
 613 {
 614         u32 reg;
 615
 616         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 617
 618         /*
 619          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 620          * PHYs. Also, this bit is not supposed to be used in normal operation.
 621          */
 622         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 623
 624         /*
 625          * Above DWC_usb3.0 1.94a, it is recommended to set
 626          * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
 627          * So default value will be '0' when the core is reset. Application
 628          * needs to set it to '1' after the core initialization is completed.
 629          *
 630          * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
 631          * cleared after power-on reset, and it can be set after core
 632          * initialization.
 633          */
 634         reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 635
 636         if (dwc->u2ss_inp3_quirk)
 637                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 638
 639         if (dwc->dis_rxdet_inp3_quirk)
 640                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 641
 642         if (dwc->req_p1p2p3_quirk)
 643                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 644
 645         if (dwc->del_p1p2p3_quirk)
 646                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 647
 648         if (dwc->del_phy_power_chg_quirk)
 649                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 650
 651         if (dwc->lfps_filter_quirk)
 652                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 653
 654         if (dwc->rx_detect_poll_quirk)
 655                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 656
 657         if (dwc->tx_de_emphasis_quirk)
 658                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 659
 660         if (dwc->dis_del_phy_power_chg_quirk)
 661                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 662
 663         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 664
 665         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 666
 667         /* Select the HS PHY interface */
 668         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 669         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 670                 if (dwc->hsphy_interface &&
 671                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 672                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 673                         break;
 674                 } else if (dwc->hsphy_interface &&
 675                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 676                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 677                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 678                 } else {
 679                         /* Relying on default value. */
 680                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 681                                 break;
 682                 }
 683                 fallthrough;
 684         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 685         default:
 686                 break;
 687         }
 688
 689         switch (dwc->hsphy_mode) {
 690         case USBPHY_INTERFACE_MODE_UTMI:
 691                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 692                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 693                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 694                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 695                 break;
 696         case USBPHY_INTERFACE_MODE_UTMIW:
 697                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 698                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 699                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 700                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 701                 break;
 702         default:
 703                 break;
 704         }
 705
 706         /*
 707          * Above DWC_usb3.0 1.94a, it is recommended to set
 708          * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
 709          * So default value will be '0' when the core is reset. Application
 710          * needs to set it to '1' after the core initialization is completed.
 711          *
 712          * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
 713          * after power-on reset, and it can be set after core initialization.
 714          */
 715         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 716
 717         if (dwc->dis_enblslpm_quirk)
 718                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 719         else
 720                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 721
 722         if (dwc->dis_u2_freeclk_exists_quirk)
 723                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 724
 725         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 726
 727         return 0;
 728 }
 729
 730 static void dwc3_core_exit(struct dwc3 *dwc)
 731 {
 732         dwc3_event_buffers_cleanup(dwc);
 733
 734         usb_phy_set_suspend(dwc->usb2_phy, 1);
 735         usb_phy_set_suspend(dwc->usb3_phy, 1);
 736         phy_power_off(dwc->usb2_generic_phy);
 737         phy_power_off(dwc->usb3_generic_phy);
 738
 739         usb_phy_shutdown(dwc->usb2_phy);
 740         usb_phy_shutdown(dwc->usb3_phy);
 741         phy_exit(dwc->usb2_generic_phy);
 742         phy_exit(dwc->usb3_generic_phy);
 743
 744         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 745         reset_control_assert(dwc->reset);
 746 }
 747
 748 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 749 {
 750         u32 reg;
 751
 752         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 753         dwc->ip = DWC3_GSNPS_ID(reg);
 754
 755         /* This should read as U3 followed by revision number */
 756         if (DWC3_IP_IS(DWC3)) {
 757                 dwc->revision = reg;
 758         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 759                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 760                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 761         } else {
 762                 return false;
 763         }
 764
 765         return true;
 766 }
 767
 768 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 769 {
 770         u32 hwparams4 = dwc->hwparams.hwparams4;
 771         u32 reg;
 772
 773         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 774         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 775
 776         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 777         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 778                 /**
 779                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 780                  * issue which would cause xHCI compliance tests to fail.
 781                  *
 782                  * Because of that we cannot enable clock gating on such
 783                  * configurations.
 784                  *
 785                  * Refers to:
 786                  *
 787                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 788                  * SOF/ITP Mode Used
 789                  */
 790                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 791                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 792                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 793                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 794                 else
 795                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 796                 break;
 797         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 798                 /* enable hibernation here */
 799                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 800
 801                 /*
 802                  * REVISIT Enabling this bit so that host-mode hibernation
 803                  * will work. Device-mode hibernation is not yet implemented.
 804                  */
 805                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 806                 break;
 807         default:
 808                 /* nothing */
 809                 break;
 810         }
 811
 812         /* check if current dwc3 is on simulation board */
 813         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 814                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 815                 dwc->is_fpga = true;
 816         }
 817
 818         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 819                         "disable_scramble cannot be used on non-FPGA builds\n");
 820
 821         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 822                 reg |= DWC3_GCTL_DISSCRAMBLE;
 823         else
 824                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 825
 826         if (dwc->u2exit_lfps_quirk)
 827                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 828
 829         /*
 830          * WORKAROUND: DWC3 revisions <1.90a have a bug
 831          * where the device can fail to connect at SuperSpeed
 832          * and falls back to high-speed mode which causes
 833          * the device to enter a Connect/Disconnect loop
 834          */
 835         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 836                 reg |= DWC3_GCTL_U2RSTECN;
 837
 838         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 839 }
 840
 841 static int dwc3_core_get_phy(struct dwc3 *dwc);
 842 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 843
 844 /* set global incr burst type configuration registers */
 845 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 846 {
 847         struct device *dev = dwc->dev;
 848         /* incrx_mode : for INCR burst type. */
 849         bool incrx_mode;
 850         /* incrx_size : for size of INCRX burst. */
 851         u32 incrx_size;
 852         u32 *vals;
 853         u32 cfg;
 854         int ntype;
 855         int ret;
 856         int i;
 857
 858         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 859
 860         /*
 861          * Handle property "snps,incr-burst-type-adjustment".
 862          * Get the number of value from this property:
 863          * result <= 0, means this property is not supported.
 864          * result = 1, means INCRx burst mode supported.
 865          * result > 1, means undefined length burst mode supported.
 866          */
 867         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 868         if (ntype <= 0)
 869                 return;
 870
 871         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 872         if (!vals) {
 873                 dev_err(dev, "Error to get memory\n");
 874                 return;
 875         }
 876
 877         /* Get INCR burst type, and parse it */
 878         ret = device_property_read_u32_array(dev,
 879                         "snps,incr-burst-type-adjustment", vals, ntype);
 880         if (ret) {
 881                 kfree(vals);
 882                 dev_err(dev, "Error to get property\n");
 883                 return;
 884         }
 885
 886         incrx_size = *vals;
 887
 888         if (ntype > 1) {
 889                 /* INCRX (undefined length) burst mode */
 890                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 891                 for (i = 1; i < ntype; i++) {
 892                         if (vals[i] > incrx_size)
 893                                 incrx_size = vals[i];
 894                 }
 895         } else {
 896                 /* INCRX burst mode */
 897                 incrx_mode = INCRX_BURST_MODE;
 898         }
 899
 900         kfree(vals);
 901
 902         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 903         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 904         if (incrx_mode)
 905                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 906         switch (incrx_size) {
 907         case 256:
 908                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 909                 break;
 910         case 128:
 911                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 912                 break;
 913         case 64:
 914                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 915                 break;
 916         case 32:
 917                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 918                 break;
 919         case 16:
 920                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 921                 break;
 922         case 8:
 923                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 924                 break;
 925         case 4:
 926                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 927                 break;
 928         case 1:
 929                 break;
 930         default:
 931                 dev_err(dev, "Invalid property\n");
 932                 break;
 933         }
 934
 935         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 936 }
 937
 938 /**
 939  * dwc3_core_init - Low-level initialization of DWC3 Core
 940  * @dwc: Pointer to our controller context structure
 941  *
 942  * Returns 0 on success otherwise negative errno.
 943  */
 944 static int dwc3_core_init(struct dwc3 *dwc)
 945 {
 946         unsigned int            hw_mode;
 947         u32                     reg;
 948         int                     ret;
 949
 950         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 951
 952         /*
 953          * Write Linux Version Code to our GUID register so it's easy to figure
 954          * out which kernel version a bug was found.
 955          */
 956         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 957
 958         ret = dwc3_phy_setup(dwc);
 959         if (ret)
 960                 goto err0;
 961
 962         if (!dwc->ulpi_ready) {
 963                 ret = dwc3_core_ulpi_init(dwc);
 964                 if (ret) {
 965                         if (ret == -ETIMEDOUT) {
 966                                 dwc3_core_soft_reset(dwc);
 967                                 ret = -EPROBE_DEFER;
 968                         }
 969                         goto err0;
 970                 }
 971                 dwc->ulpi_ready = true;
 972         }
 973
 974         if (!dwc->phys_ready) {
 975                 ret = dwc3_core_get_phy(dwc);
 976                 if (ret)
 977                         goto err0a;
 978                 dwc->phys_ready = true;
 979         }
 980
 981         usb_phy_init(dwc->usb2_phy);
 982         usb_phy_init(dwc->usb3_phy);
 983         ret = phy_init(dwc->usb2_generic_phy);
 984         if (ret < 0)
 985                 goto err0a;
 986
 987         ret = phy_init(dwc->usb3_generic_phy);
 988         if (ret < 0) {
 989                 phy_exit(dwc->usb2_generic_phy);
 990                 goto err0a;
 991         }
 992
 993         ret = dwc3_core_soft_reset(dwc);
 994         if (ret)
 995                 goto err1;
 996
 997         dwc3_core_setup_global_control(dwc);
 998         dwc3_core_num_eps(dwc);
 999
1000         ret = dwc3_setup_scratch_buffers(dwc);
1001         if (ret)
1002                 goto err1;
1003
1004         /* Adjust Frame Length */
1005         dwc3_frame_length_adjustment(dwc);
1006
1007         dwc3_set_incr_burst_type(dwc);
1008
1009         usb_phy_set_suspend(dwc->usb2_phy, 0);
1010         usb_phy_set_suspend(dwc->usb3_phy, 0);
1011         ret = phy_power_on(dwc->usb2_generic_phy);
1012         if (ret < 0)
1013                 goto err2;
1014
1015         ret = phy_power_on(dwc->usb3_generic_phy);
1016         if (ret < 0)
1017                 goto err3;
1018
1019         ret = dwc3_event_buffers_setup(dwc);
1020         if (ret) {
1021                 dev_err(dwc->dev, "failed to setup event buffers\n");
1022                 goto err4;
1023         }
1024
1025         /*
1026          * ENDXFER polling is available on version 3.10a and later of
1027          * the DWC_usb3 controller. It is NOT available in the
1028          * DWC_usb31 controller.
1029          */
1030         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1031                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1032                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1033                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1034         }
1035
1036         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1037                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1038
1039                 /*
1040                  * Enable hardware control of sending remote wakeup
1041                  * in HS when the device is in the L1 state.
1042                  */
1043                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1044                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1045
1046                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1047                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1048
1049                 if (dwc->parkmode_disable_ss_quirk)
1050                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1051
1052                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1053         }
1054
1055         /*
1056          * Must config both number of packets and max burst settings to enable
1057          * RX and/or TX threshold.
1058          */
1059         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1060                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1061                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1062                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1063                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1064
1065                 if (rx_thr_num && rx_maxburst) {
1066                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1067                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1068
1069                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1070                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1071
1072                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1073                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1074
1075                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1076                 }
1077
1078                 if (tx_thr_num && tx_maxburst) {
1079                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1080                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1081
1082                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1083                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1084
1085                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1086                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1087
1088                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1089                 }
1090         }
1091
1092         return 0;
1093
1094 err4:
1095         phy_power_off(dwc->usb3_generic_phy);
1096
1097 err3:
1098         phy_power_off(dwc->usb2_generic_phy);
1099
1100 err2:
1101         usb_phy_set_suspend(dwc->usb2_phy, 1);
1102         usb_phy_set_suspend(dwc->usb3_phy, 1);
1103
1104 err1:
1105         usb_phy_shutdown(dwc->usb2_phy);
1106         usb_phy_shutdown(dwc->usb3_phy);
1107         phy_exit(dwc->usb2_generic_phy);
1108         phy_exit(dwc->usb3_generic_phy);
1109
1110 err0a:
1111         dwc3_ulpi_exit(dwc);
1112
1113 err0:
1114         return ret;
1115 }
1116
1117 static int dwc3_core_get_phy(struct dwc3 *dwc)
1118 {
1119         struct device           *dev = dwc->dev;
1120         struct device_node      *node = dev->of_node;
1121         int ret;
1122
1123         if (node) {
1124                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1125                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1126         } else {
1127                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1128                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1129         }
1130
1131         if (IS_ERR(dwc->usb2_phy)) {
1132                 ret = PTR_ERR(dwc->usb2_phy);
1133                 if (ret == -ENXIO || ret == -ENODEV) {
1134                         dwc->usb2_phy = NULL;
1135                 } else if (ret == -EPROBE_DEFER) {
1136                         return ret;
1137                 } else {
1138                         dev_err(dev, "no usb2 phy configured\n");
1139                         return ret;
1140                 }
1141         }
1142
1143         if (IS_ERR(dwc->usb3_phy)) {
1144                 ret = PTR_ERR(dwc->usb3_phy);
1145                 if (ret == -ENXIO || ret == -ENODEV) {
1146                         dwc->usb3_phy = NULL;
1147                 } else if (ret == -EPROBE_DEFER) {
1148                         return ret;
1149                 } else {
1150                         dev_err(dev, "no usb3 phy configured\n");
1151                         return ret;
1152                 }
1153         }
1154
1155         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1156         if (IS_ERR(dwc->usb2_generic_phy)) {
1157                 ret = PTR_ERR(dwc->usb2_generic_phy);
1158                 if (ret == -ENOSYS || ret == -ENODEV) {
1159                         dwc->usb2_generic_phy = NULL;
1160                 } else if (ret == -EPROBE_DEFER) {
1161                         return ret;
1162                 } else {
1163                         dev_err(dev, "no usb2 phy configured\n");
1164                         return ret;
1165                 }
1166         }
1167
1168         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1169         if (IS_ERR(dwc->usb3_generic_phy)) {
1170                 ret = PTR_ERR(dwc->usb3_generic_phy);
1171                 if (ret == -ENOSYS || ret == -ENODEV) {
1172                         dwc->usb3_generic_phy = NULL;
1173                 } else if (ret == -EPROBE_DEFER) {
1174                         return ret;
1175                 } else {
1176                         dev_err(dev, "no usb3 phy configured\n");
1177                         return ret;
1178                 }
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int dwc3_core_init_mode(struct dwc3 *dwc)
1185 {
1186         struct device *dev = dwc->dev;
1187         int ret;
1188
1189         switch (dwc->dr_mode) {
1190         case USB_DR_MODE_PERIPHERAL:
1191                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1192
1193                 if (dwc->usb2_phy)
1194                         otg_set_vbus(dwc->usb2_phy->otg, false);
1195                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1196                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1197
1198                 ret = dwc3_gadget_init(dwc);
1199                 if (ret) {
1200                         if (ret != -EPROBE_DEFER)
1201                                 dev_err(dev, "failed to initialize gadget\n");
1202                         return ret;
1203                 }
1204                 break;
1205         case USB_DR_MODE_HOST:
1206                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1207
1208                 if (dwc->usb2_phy)
1209                         otg_set_vbus(dwc->usb2_phy->otg, true);
1210                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1211                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1212
1213                 ret = dwc3_host_init(dwc);
1214                 if (ret) {
1215                         if (ret != -EPROBE_DEFER)
1216                                 dev_err(dev, "failed to initialize host\n");
1217                         return ret;
1218                 }
1219                 break;
1220         case USB_DR_MODE_OTG:
1221                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1222                 ret = dwc3_drd_init(dwc);
1223                 if (ret) {
1224                         if (ret != -EPROBE_DEFER)
1225                                 dev_err(dev, "failed to initialize dual-role\n");
1226                         return ret;
1227                 }
1228                 break;
1229         default:
1230                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1231                 return -EINVAL;
1232         }
1233
1234         return 0;
1235 }
1236
1237 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1238 {
1239         switch (dwc->dr_mode) {
1240         case USB_DR_MODE_PERIPHERAL:
1241                 dwc3_gadget_exit(dwc);
1242                 break;
1243         case USB_DR_MODE_HOST:
1244                 dwc3_host_exit(dwc);
1245                 break;
1246         case USB_DR_MODE_OTG:
1247                 dwc3_drd_exit(dwc);
1248                 break;
1249         default:
1250                 /* do nothing */
1251                 break;
1252         }
1253
1254         /* de-assert DRVVBUS for HOST and OTG mode */
1255         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1256 }
1257
1258 static void dwc3_get_properties(struct dwc3 *dwc)
1259 {
1260         struct device           *dev = dwc->dev;
1261         u8                      lpm_nyet_threshold;
1262         u8                      tx_de_emphasis;
1263         u8                      hird_threshold;
1264         u8                      rx_thr_num_pkt_prd = 0;
1265         u8                      rx_max_burst_prd = 0;
1266         u8                      tx_thr_num_pkt_prd = 0;
1267         u8                      tx_max_burst_prd = 0;
1268
1269         /* default to highest possible threshold */
1270         lpm_nyet_threshold = 0xf;
1271
1272         /* default to -3.5dB de-emphasis */
1273         tx_de_emphasis = 1;
1274
1275         /*
1276          * default to assert utmi_sleep_n and use maximum allowed HIRD
1277          * threshold value of 0b1100
1278          */
1279         hird_threshold = 12;
1280
1281         dwc->maximum_speed = usb_get_maximum_speed(dev);
1282         dwc->dr_mode = usb_get_dr_mode(dev);
1283         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1284
1285         dwc->sysdev_is_parent = device_property_read_bool(dev,
1286                                 "linux,sysdev_is_parent");
1287         if (dwc->sysdev_is_parent)
1288                 dwc->sysdev = dwc->dev->parent;
1289         else
1290                 dwc->sysdev = dwc->dev;
1291
1292         dwc->has_lpm_erratum = device_property_read_bool(dev,
1293                                 "snps,has-lpm-erratum");
1294         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1295                                 &lpm_nyet_threshold);
1296         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1297                                 "snps,is-utmi-l1-suspend");
1298         device_property_read_u8(dev, "snps,hird-threshold",
1299                                 &hird_threshold);
1300         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1301                                 "snps,dis-start-transfer-quirk");
1302         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1303                                 "snps,usb3_lpm_capable");
1304         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1305                                 "snps,usb2-lpm-disable");
1306         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1307                                 "snps,usb2-gadget-lpm-disable");
1308         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1309                                 &rx_thr_num_pkt_prd);
1310         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1311                                 &rx_max_burst_prd);
1312         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1313                                 &tx_thr_num_pkt_prd);
1314         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1315                                 &tx_max_burst_prd);
1316
1317         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1318                                 "snps,disable_scramble_quirk");
1319         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1320                                 "snps,u2exit_lfps_quirk");
1321         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1322                                 "snps,u2ss_inp3_quirk");
1323         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1324                                 "snps,req_p1p2p3_quirk");
1325         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1326                                 "snps,del_p1p2p3_quirk");
1327         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1328                                 "snps,del_phy_power_chg_quirk");
1329         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1330                                 "snps,lfps_filter_quirk");
1331         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1332                                 "snps,rx_detect_poll_quirk");
1333         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1334                                 "snps,dis_u3_susphy_quirk");
1335         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1336                                 "snps,dis_u2_susphy_quirk");
1337         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1338                                 "snps,dis_enblslpm_quirk");
1339         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1340                                 "snps,dis-u1-entry-quirk");
1341         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1342                                 "snps,dis-u2-entry-quirk");
1343         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1344                                 "snps,dis_rxdet_inp3_quirk");
1345         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1346                                 "snps,dis-u2-freeclk-exists-quirk");
1347         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1348                                 "snps,dis-del-phy-power-chg-quirk");
1349         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1350                                 "snps,dis-tx-ipgap-linecheck-quirk");
1351         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1352                                 "snps,parkmode-disable-ss-quirk");
1353
1354         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1355                                 "snps,tx_de_emphasis_quirk");
1356         device_property_read_u8(dev, "snps,tx_de_emphasis",
1357                                 &tx_de_emphasis);
1358         device_property_read_string(dev, "snps,hsphy_interface",
1359                                     &dwc->hsphy_interface);
1360         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1361                                  &dwc->fladj);
1362
1363         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1364                                 "snps,dis_metastability_quirk");
1365
1366         dwc->dis_split_quirk = device_property_read_bool(dev,
1367                                 "snps,dis-split-quirk");
1368
1369         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1370         dwc->tx_de_emphasis = tx_de_emphasis;
1371
1372         dwc->hird_threshold = hird_threshold;
1373
1374         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1375         dwc->rx_max_burst_prd = rx_max_burst_prd;
1376
1377         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1378         dwc->tx_max_burst_prd = tx_max_burst_prd;
1379
1380         dwc->imod_interval = 0;
1381 }
1382
1383 /* check whether the core supports IMOD */
1384 bool dwc3_has_imod(struct dwc3 *dwc)
1385 {
1386         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1387                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1388                 DWC3_IP_IS(DWC32);
1389 }
1390
1391 static void dwc3_check_params(struct dwc3 *dwc)
1392 {
1393         struct device *dev = dwc->dev;
1394         unsigned int hwparam_gen =
1395                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1396
1397         /* Check for proper value of imod_interval */
1398         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1399                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1400                 dwc->imod_interval = 0;
1401         }
1402
1403         /*
1404          * Workaround for STAR 9000961433 which affects only version
1405          * 3.00a of the DWC_usb3 core. This prevents the controller
1406          * interrupt from being masked while handling events. IMOD
1407          * allows us to work around this issue. Enable it for the
1408          * affected version.
1409          */
1410         if (!dwc->imod_interval &&
1411             DWC3_VER_IS(DWC3, 300A))
1412                 dwc->imod_interval = 1;
1413
1414         /* Check the maximum_speed parameter */
1415         switch (dwc->maximum_speed) {
1416         case USB_SPEED_LOW:
1417         case USB_SPEED_FULL:
1418         case USB_SPEED_HIGH:
1419                 break;
1420         case USB_SPEED_SUPER:
1421                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1422                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1423                 break;
1424         case USB_SPEED_SUPER_PLUS:
1425                 if ((DWC3_IP_IS(DWC32) &&
1426                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1427                     (!DWC3_IP_IS(DWC32) &&
1428                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1429                         dev_warn(dev, "UDC doesn't support SSP\n");
1430                 break;
1431         default:
1432                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1433                         dwc->maximum_speed);
1434                 fallthrough;
1435         case USB_SPEED_UNKNOWN:
1436                 switch (hwparam_gen) {
1437                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1438                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1439                         break;
1440                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1441                         if (DWC3_IP_IS(DWC32))
1442                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1443                         else
1444                                 dwc->maximum_speed = USB_SPEED_SUPER;
1445                         break;
1446                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1447                         dwc->maximum_speed = USB_SPEED_HIGH;
1448                         break;
1449                 default:
1450                         dwc->maximum_speed = USB_SPEED_SUPER;
1451                         break;
1452                 }
1453                 break;
1454         }
1455 }
1456
1457 static int dwc3_probe(struct platform_device *pdev)
1458 {
1459         struct device           *dev = &pdev->dev;
1460         struct resource         *res, dwc_res;
1461         struct dwc3             *dwc;
1462
1463         int                     ret;
1464
1465         void __iomem            *regs;
1466
1467         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1468         if (!dwc)
1469                 return -ENOMEM;
1470
1471         dwc->dev = dev;
1472
1473         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1474         if (!res) {
1475                 dev_err(dev, "missing memory resource\n");
1476                 return -ENODEV;
1477         }
1478
1479         dwc->xhci_resources[0].start = res->start;
1480         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1481                                         DWC3_XHCI_REGS_END;
1482         dwc->xhci_resources[0].flags = res->flags;
1483         dwc->xhci_resources[0].name = res->name;
1484
1485         /*
1486          * Request memory region but exclude xHCI regs,
1487          * since it will be requested by the xhci-plat driver.
1488          */
1489         dwc_res = *res;
1490         dwc_res.start += DWC3_GLOBALS_REGS_START;
1491
1492         regs = devm_ioremap_resource(dev, &dwc_res);
1493         if (IS_ERR(regs))
1494                 return PTR_ERR(regs);
1495
1496         dwc->regs       = regs;
1497         dwc->regs_size  = resource_size(&dwc_res);
1498
1499         dwc3_get_properties(dwc);
1500
1501         dwc->reset = devm_reset_control_array_get(dev, true, true);
1502         if (IS_ERR(dwc->reset))
1503                 return PTR_ERR(dwc->reset);
1504
1505         if (dev->of_node) {
1506                 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1507                 if (ret == -EPROBE_DEFER)
1508                         return ret;
1509                 /*
1510                  * Clocks are optional, but new DT platforms should support all
1511                  * clocks as required by the DT-binding.
1512                  */
1513                 if (ret < 0)
1514                         dwc->num_clks = 0;
1515                 else
1516                         dwc->num_clks = ret;
1517
1518         }
1519
1520         ret = reset_control_deassert(dwc->reset);
1521         if (ret)
1522                 return ret;
1523
1524         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1525         if (ret)
1526                 goto assert_reset;
1527
1528         if (!dwc3_core_is_valid(dwc)) {
1529                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1530                 ret = -ENODEV;
1531                 goto disable_clks;
1532         }
1533
1534         platform_set_drvdata(pdev, dwc);
1535         dwc3_cache_hwparams(dwc);
1536
1537         spin_lock_init(&dwc->lock);
1538         mutex_init(&dwc->mutex);
1539
1540         pm_runtime_get_noresume(dev);
1541         pm_runtime_set_active(dev);
1542         pm_runtime_use_autosuspend(dev);
1543         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1544         pm_runtime_enable(dev);
1545
1546         pm_runtime_forbid(dev);
1547
1548         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1549         if (ret) {
1550                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1551                 ret = -ENOMEM;
1552                 goto err2;
1553         }
1554
1555         ret = dwc3_get_dr_mode(dwc);
1556         if (ret)
1557                 goto err3;
1558
1559         ret = dwc3_alloc_scratch_buffers(dwc);
1560         if (ret)
1561                 goto err3;
1562
1563         ret = dwc3_core_init(dwc);
1564         if (ret) {
1565                 if (ret != -EPROBE_DEFER)
1566                         dev_err(dev, "failed to initialize core: %d\n", ret);
1567                 goto err4;
1568         }
1569
1570         dwc3_check_params(dwc);
1571         dwc3_debugfs_init(dwc);
1572
1573         ret = dwc3_core_init_mode(dwc);
1574         if (ret)
1575                 goto err5;
1576
1577         pm_runtime_put(dev);
1578
1579         dma_set_max_seg_size(dev, UINT_MAX);
1580
1581         return 0;
1582
1583 err5:
1584         dwc3_debugfs_exit(dwc);
1585         dwc3_event_buffers_cleanup(dwc);
1586
1587         usb_phy_set_suspend(dwc->usb2_phy, 1);
1588         usb_phy_set_suspend(dwc->usb3_phy, 1);
1589         phy_power_off(dwc->usb2_generic_phy);
1590         phy_power_off(dwc->usb3_generic_phy);
1591
1592         usb_phy_shutdown(dwc->usb2_phy);
1593         usb_phy_shutdown(dwc->usb3_phy);
1594         phy_exit(dwc->usb2_generic_phy);
1595         phy_exit(dwc->usb3_generic_phy);
1596
1597         dwc3_ulpi_exit(dwc);
1598
1599 err4:
1600         dwc3_free_scratch_buffers(dwc);
1601
1602 err3:
1603         dwc3_free_event_buffers(dwc);
1604
1605 err2:
1606         pm_runtime_allow(dev);
1607         pm_runtime_disable(dev);
1608         pm_runtime_set_suspended(dev);
1609         pm_runtime_put_noidle(dev);
1610 disable_clks:
1611         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1612 assert_reset:
1613         reset_control_assert(dwc->reset);
1614
1615         return ret;
1616 }
1617
1618 static int dwc3_remove(struct platform_device *pdev)
1619 {
1620         struct dwc3     *dwc = platform_get_drvdata(pdev);
1621
1622         pm_runtime_get_sync(&pdev->dev);
1623
1624         dwc3_core_exit_mode(dwc);
1625         dwc3_debugfs_exit(dwc);
1626
1627         dwc3_core_exit(dwc);
1628         dwc3_ulpi_exit(dwc);
1629
1630         pm_runtime_allow(&pdev->dev);
1631         pm_runtime_disable(&pdev->dev);
1632         pm_runtime_put_noidle(&pdev->dev);
1633         pm_runtime_set_suspended(&pdev->dev);
1634
1635         dwc3_free_event_buffers(dwc);
1636         dwc3_free_scratch_buffers(dwc);
1637
1638         return 0;
1639 }
1640
1641 #ifdef CONFIG_PM
1642 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1643 {
1644         int ret;
1645
1646         ret = reset_control_deassert(dwc->reset);
1647         if (ret)
1648                 return ret;
1649
1650         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1651         if (ret)
1652                 goto assert_reset;
1653
1654         ret = dwc3_core_init(dwc);
1655         if (ret)
1656                 goto disable_clks;
1657
1658         return 0;
1659
1660 disable_clks:
1661         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1662 assert_reset:
1663         reset_control_assert(dwc->reset);
1664
1665         return ret;
1666 }
1667
1668 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1669 {
1670         unsigned long   flags;
1671         u32 reg;
1672
1673         switch (dwc->current_dr_role) {
1674         case DWC3_GCTL_PRTCAP_DEVICE:
1675                 if (pm_runtime_suspended(dwc->dev))
1676                         break;
1677                 spin_lock_irqsave(&dwc->lock, flags);
1678                 dwc3_gadget_suspend(dwc);
1679                 spin_unlock_irqrestore(&dwc->lock, flags);
1680                 synchronize_irq(dwc->irq_gadget);
1681                 dwc3_core_exit(dwc);
1682                 break;
1683         case DWC3_GCTL_PRTCAP_HOST:
1684                 if (!PMSG_IS_AUTO(msg)) {
1685                         dwc3_core_exit(dwc);
1686                         break;
1687                 }
1688
1689                 /* Let controller to suspend HSPHY before PHY driver suspends */
1690                 if (dwc->dis_u2_susphy_quirk ||
1691                     dwc->dis_enblslpm_quirk) {
1692                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1693                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1694                                 DWC3_GUSB2PHYCFG_SUSPHY;
1695                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1696
1697                         /* Give some time for USB2 PHY to suspend */
1698                         usleep_range(5000, 6000);
1699                 }
1700
1701                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1702                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1703                 break;
1704         case DWC3_GCTL_PRTCAP_OTG:
1705                 /* do nothing during runtime_suspend */
1706                 if (PMSG_IS_AUTO(msg))
1707                         break;
1708
1709                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1710                         spin_lock_irqsave(&dwc->lock, flags);
1711                         dwc3_gadget_suspend(dwc);
1712                         spin_unlock_irqrestore(&dwc->lock, flags);
1713                         synchronize_irq(dwc->irq_gadget);
1714                 }
1715
1716                 dwc3_otg_exit(dwc);
1717                 dwc3_core_exit(dwc);
1718                 break;
1719         default:
1720                 /* do nothing */
1721                 break;
1722         }
1723
1724         return 0;
1725 }
1726
1727 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1728 {
1729         unsigned long   flags;
1730         int             ret;
1731         u32             reg;
1732
1733         switch (dwc->current_dr_role) {
1734         case DWC3_GCTL_PRTCAP_DEVICE:
1735                 ret = dwc3_core_init_for_resume(dwc);
1736                 if (ret)
1737                         return ret;
1738
1739                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1740                 spin_lock_irqsave(&dwc->lock, flags);
1741                 dwc3_gadget_resume(dwc);
1742                 spin_unlock_irqrestore(&dwc->lock, flags);
1743                 break;
1744         case DWC3_GCTL_PRTCAP_HOST:
1745                 if (!PMSG_IS_AUTO(msg)) {
1746                         ret = dwc3_core_init_for_resume(dwc);
1747                         if (ret)
1748                                 return ret;
1749                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1750                         break;
1751                 }
1752                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1753                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1754                 if (dwc->dis_u2_susphy_quirk)
1755                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1756
1757                 if (dwc->dis_enblslpm_quirk)
1758                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1759
1760                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1761
1762                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1763                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1764                 break;
1765         case DWC3_GCTL_PRTCAP_OTG:
1766                 /* nothing to do on runtime_resume */
1767                 if (PMSG_IS_AUTO(msg))
1768                         break;
1769
1770                 ret = dwc3_core_init_for_resume(dwc);
1771                 if (ret)
1772                         return ret;
1773
1774                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1775
1776                 dwc3_otg_init(dwc);
1777                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1778                         dwc3_otg_host_init(dwc);
1779                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1780                         spin_lock_irqsave(&dwc->lock, flags);
1781                         dwc3_gadget_resume(dwc);
1782                         spin_unlock_irqrestore(&dwc->lock, flags);
1783                 }
1784
1785                 break;
1786         default:
1787                 /* do nothing */
1788                 break;
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int dwc3_runtime_checks(struct dwc3 *dwc)
1795 {
1796         switch (dwc->current_dr_role) {
1797         case DWC3_GCTL_PRTCAP_DEVICE:
1798                 if (dwc->connected)
1799                         return -EBUSY;
1800                 break;
1801         case DWC3_GCTL_PRTCAP_HOST:
1802         default:
1803                 /* do nothing */
1804                 break;
1805         }
1806
1807         return 0;
1808 }
1809
1810 static int dwc3_runtime_suspend(struct device *dev)
1811 {
1812         struct dwc3     *dwc = dev_get_drvdata(dev);
1813         int             ret;
1814
1815         if (dwc3_runtime_checks(dwc))
1816                 return -EBUSY;
1817
1818         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1819         if (ret)
1820                 return ret;
1821
1822         device_init_wakeup(dev, true);
1823
1824         return 0;
1825 }
1826
1827 static int dwc3_runtime_resume(struct device *dev)
1828 {
1829         struct dwc3     *dwc = dev_get_drvdata(dev);
1830         int             ret;
1831
1832         device_init_wakeup(dev, false);
1833
1834         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1835         if (ret)
1836                 return ret;
1837
1838         switch (dwc->current_dr_role) {
1839         case DWC3_GCTL_PRTCAP_DEVICE:
1840                 dwc3_gadget_process_pending_events(dwc);
1841                 break;
1842         case DWC3_GCTL_PRTCAP_HOST:
1843         default:
1844                 /* do nothing */
1845                 break;
1846         }
1847
1848         pm_runtime_mark_last_busy(dev);
1849
1850         return 0;
1851 }
1852
1853 static int dwc3_runtime_idle(struct device *dev)
1854 {
1855         struct dwc3     *dwc = dev_get_drvdata(dev);
1856
1857         switch (dwc->current_dr_role) {
1858         case DWC3_GCTL_PRTCAP_DEVICE:
1859                 if (dwc3_runtime_checks(dwc))
1860                         return -EBUSY;
1861                 break;
1862         case DWC3_GCTL_PRTCAP_HOST:
1863         default:
1864                 /* do nothing */
1865                 break;
1866         }
1867
1868         pm_runtime_mark_last_busy(dev);
1869         pm_runtime_autosuspend(dev);
1870
1871         return 0;
1872 }
1873 #endif /* CONFIG_PM */
1874
1875 #ifdef CONFIG_PM_SLEEP
1876 static int dwc3_suspend(struct device *dev)
1877 {
1878         struct dwc3     *dwc = dev_get_drvdata(dev);
1879         int             ret;
1880
1881         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1882         if (ret)
1883                 return ret;
1884
1885         pinctrl_pm_select_sleep_state(dev);
1886
1887         return 0;
1888 }
1889
1890 static int dwc3_resume(struct device *dev)
1891 {
1892         struct dwc3     *dwc = dev_get_drvdata(dev);
1893         int             ret;
1894
1895         pinctrl_pm_select_default_state(dev);
1896
1897         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1898         if (ret)
1899                 return ret;
1900
1901         pm_runtime_disable(dev);
1902         pm_runtime_set_active(dev);
1903         pm_runtime_enable(dev);
1904
1905         return 0;
1906 }
1907
1908 static void dwc3_complete(struct device *dev)
1909 {
1910         struct dwc3     *dwc = dev_get_drvdata(dev);
1911         u32             reg;
1912
1913         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1914                         dwc->dis_split_quirk) {
1915                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1916                 reg |= DWC3_GUCTL3_SPLITDISABLE;
1917                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1918         }
1919 }
1920 #else
1921 #define dwc3_complete NULL
1922 #endif /* CONFIG_PM_SLEEP */
1923
1924 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1925         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1926         .complete = dwc3_complete,
1927         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1928                         dwc3_runtime_idle)
1929 };
1930
1931 #ifdef CONFIG_OF
1932 static const struct of_device_id of_dwc3_match[] = {
1933         {
1934                 .compatible = "snps,dwc3"
1935         },
1936         {
1937                 .compatible = "synopsys,dwc3"
1938         },
1939         { },
1940 };
1941 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1942 #endif
1943
1944 #ifdef CONFIG_ACPI
1945
1946 #define ACPI_ID_INTEL_BSW       "808622B7"
1947
1948 static const struct acpi_device_id dwc3_acpi_match[] = {
1949         { ACPI_ID_INTEL_BSW, 0 },
1950         { },
1951 };
1952 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1953 #endif
1954
1955 static struct platform_driver dwc3_driver = {
1956         .probe          = dwc3_probe,
1957         .remove         = dwc3_remove,
1958         .driver         = {
1959                 .name   = "dwc3",
1960                 .of_match_table = of_match_ptr(of_dwc3_match),
1961                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1962                 .pm     = &dwc3_dev_pm_ops,
1963         },
1964 };
1965
1966 module_platform_driver(dwc3_driver);
1967
1968 MODULE_ALIAS("platform:dwc3");
1969 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1970 MODULE_LICENSE("GPL v2");
1971 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");