drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/of_graph.h>
  27 #include <linux/acpi.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/bitfield.h>
  31
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/of.h>
  35 #include <linux/usb/otg.h>
  36
  37 #include "core.h"
  38 #include "gadget.h"
  39 #include "io.h"
  40
  41 #include "debug.h"
  42
  43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  44
  45 /**
  46  * dwc3_get_dr_mode - Validates and sets dr_mode
  47  * @dwc: pointer to our context structure
  48  */
  49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  50 {
  51         enum usb_dr_mode mode;
  52         struct device *dev = dwc->dev;
  53         unsigned int hw_mode;
  54
  55         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  56                 dwc->dr_mode = USB_DR_MODE_OTG;
  57
  58         mode = dwc->dr_mode;
  59         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  60
  61         switch (hw_mode) {
  62         case DWC3_GHWPARAMS0_MODE_GADGET:
  63                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  64                         dev_err(dev,
  65                                 "Controller does not support host mode.\n");
  66                         return -EINVAL;
  67                 }
  68                 mode = USB_DR_MODE_PERIPHERAL;
  69                 break;
  70         case DWC3_GHWPARAMS0_MODE_HOST:
  71                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  72                         dev_err(dev,
  73                                 "Controller does not support device mode.\n");
  74                         return -EINVAL;
  75                 }
  76                 mode = USB_DR_MODE_HOST;
  77                 break;
  78         default:
  79                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  80                         mode = USB_DR_MODE_HOST;
  81                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  82                         mode = USB_DR_MODE_PERIPHERAL;
  83
  84                 /*
  85                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  86                  * mode. If the controller supports DRD but the dr_mode is not
  87                  * specified or set to OTG, then set the mode to peripheral.
  88                  */
  89                 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
  90                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  91                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  92                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  93                         mode = USB_DR_MODE_PERIPHERAL;
  94         }
  95
  96         if (mode != dwc->dr_mode) {
  97                 dev_warn(dev,
  98                          "Configuration mismatch. dr_mode forced to %s\n",
  99                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
 100
 101                 dwc->dr_mode = mode;
 102         }
 103
 104         return 0;
 105 }
 106
 107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 108 {
 109         u32 reg;
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 112         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 113         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 114         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 115
 116         dwc->current_dr_role = mode;
 117 }
 118
 119 static void __dwc3_set_mode(struct work_struct *work)
 120 {
 121         struct dwc3 *dwc = work_to_dwc(work);
 122         unsigned long flags;
 123         int ret;
 124         u32 reg;
 125
 126         mutex_lock(&dwc->mutex);
 127
 128         pm_runtime_get_sync(dwc->dev);
 129
 130         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 131                 dwc3_otg_update(dwc, 0);
 132
 133         if (!dwc->desired_dr_role)
 134                 goto out;
 135
 136         if (dwc->desired_dr_role == dwc->current_dr_role)
 137                 goto out;
 138
 139         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 140                 goto out;
 141
 142         switch (dwc->current_dr_role) {
 143         case DWC3_GCTL_PRTCAP_HOST:
 144                 dwc3_host_exit(dwc);
 145                 break;
 146         case DWC3_GCTL_PRTCAP_DEVICE:
 147                 dwc3_gadget_exit(dwc);
 148                 dwc3_event_buffers_cleanup(dwc);
 149                 break;
 150         case DWC3_GCTL_PRTCAP_OTG:
 151                 dwc3_otg_exit(dwc);
 152                 spin_lock_irqsave(&dwc->lock, flags);
 153                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 154                 spin_unlock_irqrestore(&dwc->lock, flags);
 155                 dwc3_otg_update(dwc, 1);
 156                 break;
 157         default:
 158                 break;
 159         }
 160
 161         /* For DRD host or device mode only */
 162         if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
 163                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 164                 reg |= DWC3_GCTL_CORESOFTRESET;
 165                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 166
 167                 /*
 168                  * Wait for internal clocks to synchronized. DWC_usb31 and
 169                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 170                  * keep it consistent across different IPs, let's wait up to
 171                  * 100ms before clearing GCTL.CORESOFTRESET.
 172                  */
 173                 msleep(100);
 174
 175                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 176                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 177                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 178         }
 179
 180         spin_lock_irqsave(&dwc->lock, flags);
 181
 182         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 183
 184         spin_unlock_irqrestore(&dwc->lock, flags);
 185
 186         switch (dwc->desired_dr_role) {
 187         case DWC3_GCTL_PRTCAP_HOST:
 188                 ret = dwc3_host_init(dwc);
 189                 if (ret) {
 190                         dev_err(dwc->dev, "failed to initialize host\n");
 191                 } else {
 192                         if (dwc->usb2_phy)
 193                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 194                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 195                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 196                         if (dwc->dis_split_quirk) {
 197                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 198                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 199                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 200                         }
 201                 }
 202                 break;
 203         case DWC3_GCTL_PRTCAP_DEVICE:
 204                 dwc3_core_soft_reset(dwc);
 205
 206                 dwc3_event_buffers_setup(dwc);
 207
 208                 if (dwc->usb2_phy)
 209                         otg_set_vbus(dwc->usb2_phy->otg, false);
 210                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 211                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 212
 213                 ret = dwc3_gadget_init(dwc);
 214                 if (ret)
 215                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 216                 break;
 217         case DWC3_GCTL_PRTCAP_OTG:
 218                 dwc3_otg_init(dwc);
 219                 dwc3_otg_update(dwc, 0);
 220                 break;
 221         default:
 222                 break;
 223         }
 224
 225 out:
 226         pm_runtime_mark_last_busy(dwc->dev);
 227         pm_runtime_put_autosuspend(dwc->dev);
 228         mutex_unlock(&dwc->mutex);
 229 }
 230
 231 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 232 {
 233         unsigned long flags;
 234
 235         if (dwc->dr_mode != USB_DR_MODE_OTG)
 236                 return;
 237
 238         spin_lock_irqsave(&dwc->lock, flags);
 239         dwc->desired_dr_role = mode;
 240         spin_unlock_irqrestore(&dwc->lock, flags);
 241
 242         queue_work(system_freezable_wq, &dwc->drd_work);
 243 }
 244
 245 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 246 {
 247         struct dwc3             *dwc = dep->dwc;
 248         u32                     reg;
 249
 250         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 251                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 252                         DWC3_GDBGFIFOSPACE_TYPE(type));
 253
 254         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 255
 256         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 257 }
 258
 259 /**
 260  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 261  * @dwc: pointer to our context structure
 262  */
 263 int dwc3_core_soft_reset(struct dwc3 *dwc)
 264 {
 265         u32             reg;
 266         int             retries = 1000;
 267
 268         /*
 269          * We're resetting only the device side because, if we're in host mode,
 270          * XHCI driver will reset the host block. If dwc3 was configured for
 271          * host-only mode, then we can return early.
 272          */
 273         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 274                 return 0;
 275
 276         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 277         reg |= DWC3_DCTL_CSFTRST;
 278         reg &= ~DWC3_DCTL_RUN_STOP;
 279         dwc3_gadget_dctl_write_safe(dwc, reg);
 280
 281         /*
 282          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 283          * is cleared only after all the clocks are synchronized. This can
 284          * take a little more than 50ms. Set the polling rate at 20ms
 285          * for 10 times instead.
 286          */
 287         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 288                 retries = 10;
 289
 290         do {
 291                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 292                 if (!(reg & DWC3_DCTL_CSFTRST))
 293                         goto done;
 294
 295                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 296                         msleep(20);
 297                 else
 298                         udelay(1);
 299         } while (--retries);
 300
 301         dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
 302         return -ETIMEDOUT;
 303
 304 done:
 305         /*
 306          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 307          * is cleared, we must wait at least 50ms before accessing the PHY
 308          * domain (synchronization delay).
 309          */
 310         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 311                 msleep(50);
 312
 313         return 0;
 314 }
 315
 316 /*
 317  * dwc3_frame_length_adjustment - Adjusts frame length if required
 318  * @dwc3: Pointer to our controller context structure
 319  */
 320 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 321 {
 322         u32 reg;
 323         u32 dft;
 324
 325         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 326                 return;
 327
 328         if (dwc->fladj == 0)
 329                 return;
 330
 331         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 332         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 333         if (dft != dwc->fladj) {
 334                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 335                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 336                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 337         }
 338 }
 339
 340 /**
 341  * dwc3_ref_clk_period - Reference clock period configuration
 342  *              Default reference clock period depends on hardware
 343  *              configuration. For systems with reference clock that differs
 344  *              from the default, this will set clock period in DWC3_GUCTL
 345  *              register.
 346  * @dwc: Pointer to our controller context structure
 347  */
 348 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 349 {
 350         unsigned long period;
 351         unsigned long fladj;
 352         unsigned long decr;
 353         unsigned long rate;
 354         u32 reg;
 355
 356         if (dwc->ref_clk) {
 357                 rate = clk_get_rate(dwc->ref_clk);
 358                 if (!rate)
 359                         return;
 360                 period = NSEC_PER_SEC / rate;
 361         } else if (dwc->ref_clk_per) {
 362                 period = dwc->ref_clk_per;
 363                 rate = NSEC_PER_SEC / period;
 364         } else {
 365                 return;
 366         }
 367
 368         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 369         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
 370         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
 371         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 372
 373         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 374                 return;
 375
 376         /*
 377          * The calculation below is
 378          *
 379          * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
 380          *
 381          * but rearranged for fixed-point arithmetic. The division must be
 382          * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
 383          * neither does rate * period).
 384          *
 385          * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
 386          * nanoseconds of error caused by the truncation which happened during
 387          * the division when calculating rate or period (whichever one was
 388          * derived from the other). We first calculate the relative error, then
 389          * scale it to units of 8 ppm.
 390          */
 391         fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
 392         fladj -= 125000;
 393
 394         /*
 395          * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
 396          */
 397         decr = 480000000 / rate;
 398
 399         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 400         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
 401             &  ~DWC3_GFLADJ_240MHZDECR
 402             &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
 403         reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
 404             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
 405             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
 406         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 407 }
 408
 409 /**
 410  * dwc3_free_one_event_buffer - Frees one event buffer
 411  * @dwc: Pointer to our controller context structure
 412  * @evt: Pointer to event buffer to be freed
 413  */
 414 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 415                 struct dwc3_event_buffer *evt)
 416 {
 417         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 418 }
 419
 420 /**
 421  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 422  * @dwc: Pointer to our controller context structure
 423  * @length: size of the event buffer
 424  *
 425  * Returns a pointer to the allocated event buffer structure on success
 426  * otherwise ERR_PTR(errno).
 427  */
 428 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 429                 unsigned length)
 430 {
 431         struct dwc3_event_buffer        *evt;
 432
 433         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 434         if (!evt)
 435                 return ERR_PTR(-ENOMEM);
 436
 437         evt->dwc        = dwc;
 438         evt->length     = length;
 439         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 440         if (!evt->cache)
 441                 return ERR_PTR(-ENOMEM);
 442
 443         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 444                         &evt->dma, GFP_KERNEL);
 445         if (!evt->buf)
 446                 return ERR_PTR(-ENOMEM);
 447
 448         return evt;
 449 }
 450
 451 /**
 452  * dwc3_free_event_buffers - frees all allocated event buffers
 453  * @dwc: Pointer to our controller context structure
 454  */
 455 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 456 {
 457         struct dwc3_event_buffer        *evt;
 458
 459         evt = dwc->ev_buf;
 460         if (evt)
 461                 dwc3_free_one_event_buffer(dwc, evt);
 462 }
 463
 464 /**
 465  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 466  * @dwc: pointer to our controller context structure
 467  * @length: size of event buffer
 468  *
 469  * Returns 0 on success otherwise negative errno. In the error case, dwc
 470  * may contain some buffers allocated but not all which were requested.
 471  */
 472 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 473 {
 474         struct dwc3_event_buffer *evt;
 475
 476         evt = dwc3_alloc_one_event_buffer(dwc, length);
 477         if (IS_ERR(evt)) {
 478                 dev_err(dwc->dev, "can't allocate event buffer\n");
 479                 return PTR_ERR(evt);
 480         }
 481         dwc->ev_buf = evt;
 482
 483         return 0;
 484 }
 485
 486 /**
 487  * dwc3_event_buffers_setup - setup our allocated event buffers
 488  * @dwc: pointer to our controller context structure
 489  *
 490  * Returns 0 on success otherwise negative errno.
 491  */
 492 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 493 {
 494         struct dwc3_event_buffer        *evt;
 495
 496         evt = dwc->ev_buf;
 497         evt->lpos = 0;
 498         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 499                         lower_32_bits(evt->dma));
 500         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 501                         upper_32_bits(evt->dma));
 502         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 503                         DWC3_GEVNTSIZ_SIZE(evt->length));
 504         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 505
 506         return 0;
 507 }
 508
 509 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 510 {
 511         struct dwc3_event_buffer        *evt;
 512
 513         evt = dwc->ev_buf;
 514
 515         evt->lpos = 0;
 516
 517         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 518         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 519         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 520                         | DWC3_GEVNTSIZ_SIZE(0));
 521         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 522 }
 523
 524 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 525 {
 526         if (!dwc->has_hibernation)
 527                 return 0;
 528
 529         if (!dwc->nr_scratch)
 530                 return 0;
 531
 532         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 533                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 534         if (!dwc->scratchbuf)
 535                 return -ENOMEM;
 536
 537         return 0;
 538 }
 539
 540 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 541 {
 542         dma_addr_t scratch_addr;
 543         u32 param;
 544         int ret;
 545
 546         if (!dwc->has_hibernation)
 547                 return 0;
 548
 549         if (!dwc->nr_scratch)
 550                 return 0;
 551
 552          /* should never fall here */
 553         if (!WARN_ON(dwc->scratchbuf))
 554                 return 0;
 555
 556         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 557                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 558                         DMA_BIDIRECTIONAL);
 559         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 560                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 561                 ret = -EFAULT;
 562                 goto err0;
 563         }
 564
 565         dwc->scratch_addr = scratch_addr;
 566
 567         param = lower_32_bits(scratch_addr);
 568
 569         ret = dwc3_send_gadget_generic_command(dwc,
 570                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 571         if (ret < 0)
 572                 goto err1;
 573
 574         param = upper_32_bits(scratch_addr);
 575
 576         ret = dwc3_send_gadget_generic_command(dwc,
 577                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 578         if (ret < 0)
 579                 goto err1;
 580
 581         return 0;
 582
 583 err1:
 584         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 585                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 586
 587 err0:
 588         return ret;
 589 }
 590
 591 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 592 {
 593         if (!dwc->has_hibernation)
 594                 return;
 595
 596         if (!dwc->nr_scratch)
 597                 return;
 598
 599          /* should never fall here */
 600         if (!WARN_ON(dwc->scratchbuf))
 601                 return;
 602
 603         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 604                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 605         kfree(dwc->scratchbuf);
 606 }
 607
 608 static void dwc3_core_num_eps(struct dwc3 *dwc)
 609 {
 610         struct dwc3_hwparams    *parms = &dwc->hwparams;
 611
 612         dwc->num_eps = DWC3_NUM_EPS(parms);
 613 }
 614
 615 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 616 {
 617         struct dwc3_hwparams    *parms = &dwc->hwparams;
 618
 619         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 620         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 621         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 622         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 623         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 624         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 625         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 626         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 627         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 628
 629         if (DWC3_IP_IS(DWC32))
 630                 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 631 }
 632
 633 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 634 {
 635         int intf;
 636         int ret = 0;
 637
 638         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 639
 640         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 641             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 642              dwc->hsphy_interface &&
 643              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 644                 ret = dwc3_ulpi_init(dwc);
 645
 646         return ret;
 647 }
 648
 649 /**
 650  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 651  * @dwc: Pointer to our controller context structure
 652  *
 653  * Returns 0 on success. The USB PHY interfaces are configured but not
 654  * initialized. The PHY interfaces and the PHYs get initialized together with
 655  * the core in dwc3_core_init.
 656  */
 657 static int dwc3_phy_setup(struct dwc3 *dwc)
 658 {
 659         unsigned int hw_mode;
 660         u32 reg;
 661
 662         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 663
 664         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 665
 666         /*
 667          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 668          * PHYs. Also, this bit is not supposed to be used in normal operation.
 669          */
 670         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 671
 672         /*
 673          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 674          * to '0' during coreConsultant configuration. So default value
 675          * will be '0' when the core is reset. Application needs to set it
 676          * to '1' after the core initialization is completed.
 677          */
 678         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 679                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 680
 681         /*
 682          * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 683          * power-on reset, and it can be set after core initialization, which is
 684          * after device soft-reset during initialization.
 685          */
 686         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 687                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 688
 689         if (dwc->u2ss_inp3_quirk)
 690                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 691
 692         if (dwc->dis_rxdet_inp3_quirk)
 693                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 694
 695         if (dwc->req_p1p2p3_quirk)
 696                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 697
 698         if (dwc->del_p1p2p3_quirk)
 699                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 700
 701         if (dwc->del_phy_power_chg_quirk)
 702                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 703
 704         if (dwc->lfps_filter_quirk)
 705                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 706
 707         if (dwc->rx_detect_poll_quirk)
 708                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 709
 710         if (dwc->tx_de_emphasis_quirk)
 711                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 712
 713         if (dwc->dis_u3_susphy_quirk)
 714                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 715
 716         if (dwc->dis_del_phy_power_chg_quirk)
 717                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 718
 719         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 720
 721         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 722
 723         /* Select the HS PHY interface */
 724         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 725         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 726                 if (dwc->hsphy_interface &&
 727                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 728                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 729                         break;
 730                 } else if (dwc->hsphy_interface &&
 731                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 732                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 733                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 734                 } else {
 735                         /* Relying on default value. */
 736                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 737                                 break;
 738                 }
 739                 fallthrough;
 740         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 741         default:
 742                 break;
 743         }
 744
 745         switch (dwc->hsphy_mode) {
 746         case USBPHY_INTERFACE_MODE_UTMI:
 747                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 748                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 749                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 750                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 751                 break;
 752         case USBPHY_INTERFACE_MODE_UTMIW:
 753                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 754                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 755                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 756                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 757                 break;
 758         default:
 759                 break;
 760         }
 761
 762         /*
 763          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 764          * '0' during coreConsultant configuration. So default value will
 765          * be '0' when the core is reset. Application needs to set it to
 766          * '1' after the core initialization is completed.
 767          */
 768         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 769                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 770
 771         /*
 772          * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 773          * power-on reset, and it can be set after core initialization, which is
 774          * after device soft-reset during initialization.
 775          */
 776         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 777                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 778
 779         if (dwc->dis_u2_susphy_quirk)
 780                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 781
 782         if (dwc->dis_enblslpm_quirk)
 783                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 784         else
 785                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 786
 787         if (dwc->dis_u2_freeclk_exists_quirk)
 788                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 789
 790         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 791
 792         return 0;
 793 }
 794
 795 static int dwc3_clk_enable(struct dwc3 *dwc)
 796 {
 797         int ret;
 798
 799         ret = clk_prepare_enable(dwc->bus_clk);
 800         if (ret)
 801                 return ret;
 802
 803         ret = clk_prepare_enable(dwc->ref_clk);
 804         if (ret)
 805                 goto disable_bus_clk;
 806
 807         ret = clk_prepare_enable(dwc->susp_clk);
 808         if (ret)
 809                 goto disable_ref_clk;
 810
 811         return 0;
 812
 813 disable_ref_clk:
 814         clk_disable_unprepare(dwc->ref_clk);
 815 disable_bus_clk:
 816         clk_disable_unprepare(dwc->bus_clk);
 817         return ret;
 818 }
 819
 820 static void dwc3_clk_disable(struct dwc3 *dwc)
 821 {
 822         clk_disable_unprepare(dwc->susp_clk);
 823         clk_disable_unprepare(dwc->ref_clk);
 824         clk_disable_unprepare(dwc->bus_clk);
 825 }
 826
 827 static void dwc3_core_exit(struct dwc3 *dwc)
 828 {
 829         dwc3_event_buffers_cleanup(dwc);
 830
 831         usb_phy_shutdown(dwc->usb2_phy);
 832         usb_phy_shutdown(dwc->usb3_phy);
 833         phy_exit(dwc->usb2_generic_phy);
 834         phy_exit(dwc->usb3_generic_phy);
 835
 836         usb_phy_set_suspend(dwc->usb2_phy, 1);
 837         usb_phy_set_suspend(dwc->usb3_phy, 1);
 838         phy_power_off(dwc->usb2_generic_phy);
 839         phy_power_off(dwc->usb3_generic_phy);
 840         dwc3_clk_disable(dwc);
 841         reset_control_assert(dwc->reset);
 842 }
 843
 844 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 845 {
 846         u32 reg;
 847
 848         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 849         dwc->ip = DWC3_GSNPS_ID(reg);
 850
 851         /* This should read as U3 followed by revision number */
 852         if (DWC3_IP_IS(DWC3)) {
 853                 dwc->revision = reg;
 854         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 855                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 856                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 857         } else {
 858                 return false;
 859         }
 860
 861         return true;
 862 }
 863
 864 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 865 {
 866         u32 hwparams4 = dwc->hwparams.hwparams4;
 867         u32 reg;
 868
 869         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 870         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 871
 872         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 873         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 874                 /**
 875                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 876                  * issue which would cause xHCI compliance tests to fail.
 877                  *
 878                  * Because of that we cannot enable clock gating on such
 879                  * configurations.
 880                  *
 881                  * Refers to:
 882                  *
 883                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 884                  * SOF/ITP Mode Used
 885                  */
 886                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 887                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 888                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 889                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 890                 else
 891                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 892                 break;
 893         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 894                 /* enable hibernation here */
 895                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 896
 897                 /*
 898                  * REVISIT Enabling this bit so that host-mode hibernation
 899                  * will work. Device-mode hibernation is not yet implemented.
 900                  */
 901                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 902                 break;
 903         default:
 904                 /* nothing */
 905                 break;
 906         }
 907
 908         /* check if current dwc3 is on simulation board */
 909         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 910                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 911                 dwc->is_fpga = true;
 912         }
 913
 914         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 915                         "disable_scramble cannot be used on non-FPGA builds\n");
 916
 917         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 918                 reg |= DWC3_GCTL_DISSCRAMBLE;
 919         else
 920                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 921
 922         if (dwc->u2exit_lfps_quirk)
 923                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 924
 925         /*
 926          * WORKAROUND: DWC3 revisions <1.90a have a bug
 927          * where the device can fail to connect at SuperSpeed
 928          * and falls back to high-speed mode which causes
 929          * the device to enter a Connect/Disconnect loop
 930          */
 931         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 932                 reg |= DWC3_GCTL_U2RSTECN;
 933
 934         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 935 }
 936
 937 static int dwc3_core_get_phy(struct dwc3 *dwc);
 938 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 939
 940 /* set global incr burst type configuration registers */
 941 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 942 {
 943         struct device *dev = dwc->dev;
 944         /* incrx_mode : for INCR burst type. */
 945         bool incrx_mode;
 946         /* incrx_size : for size of INCRX burst. */
 947         u32 incrx_size;
 948         u32 *vals;
 949         u32 cfg;
 950         int ntype;
 951         int ret;
 952         int i;
 953
 954         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 955
 956         /*
 957          * Handle property "snps,incr-burst-type-adjustment".
 958          * Get the number of value from this property:
 959          * result <= 0, means this property is not supported.
 960          * result = 1, means INCRx burst mode supported.
 961          * result > 1, means undefined length burst mode supported.
 962          */
 963         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 964         if (ntype <= 0)
 965                 return;
 966
 967         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 968         if (!vals)
 969                 return;
 970
 971         /* Get INCR burst type, and parse it */
 972         ret = device_property_read_u32_array(dev,
 973                         "snps,incr-burst-type-adjustment", vals, ntype);
 974         if (ret) {
 975                 kfree(vals);
 976                 dev_err(dev, "Error to get property\n");
 977                 return;
 978         }
 979
 980         incrx_size = *vals;
 981
 982         if (ntype > 1) {
 983                 /* INCRX (undefined length) burst mode */
 984                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 985                 for (i = 1; i < ntype; i++) {
 986                         if (vals[i] > incrx_size)
 987                                 incrx_size = vals[i];
 988                 }
 989         } else {
 990                 /* INCRX burst mode */
 991                 incrx_mode = INCRX_BURST_MODE;
 992         }
 993
 994         kfree(vals);
 995
 996         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 997         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 998         if (incrx_mode)
 999                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1000         switch (incrx_size) {
1001         case 256:
1002                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1003                 break;
1004         case 128:
1005                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1006                 break;
1007         case 64:
1008                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1009                 break;
1010         case 32:
1011                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1012                 break;
1013         case 16:
1014                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1015                 break;
1016         case 8:
1017                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1018                 break;
1019         case 4:
1020                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1021                 break;
1022         case 1:
1023                 break;
1024         default:
1025                 dev_err(dev, "Invalid property\n");
1026                 break;
1027         }
1028
1029         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1030 }
1031
1032 /**
1033  * dwc3_core_init - Low-level initialization of DWC3 Core
1034  * @dwc: Pointer to our controller context structure
1035  *
1036  * Returns 0 on success otherwise negative errno.
1037  */
1038 static int dwc3_core_init(struct dwc3 *dwc)
1039 {
1040         unsigned int            hw_mode;
1041         u32                     reg;
1042         int                     ret;
1043
1044         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1045
1046         /*
1047          * Write Linux Version Code to our GUID register so it's easy to figure
1048          * out which kernel version a bug was found.
1049          */
1050         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1051
1052         ret = dwc3_phy_setup(dwc);
1053         if (ret)
1054                 goto err0;
1055
1056         if (!dwc->ulpi_ready) {
1057                 ret = dwc3_core_ulpi_init(dwc);
1058                 if (ret)
1059                         goto err0;
1060                 dwc->ulpi_ready = true;
1061         }
1062
1063         if (!dwc->phys_ready) {
1064                 ret = dwc3_core_get_phy(dwc);
1065                 if (ret)
1066                         goto err0a;
1067                 dwc->phys_ready = true;
1068         }
1069
1070         usb_phy_init(dwc->usb2_phy);
1071         usb_phy_init(dwc->usb3_phy);
1072         ret = phy_init(dwc->usb2_generic_phy);
1073         if (ret < 0)
1074                 goto err0a;
1075
1076         ret = phy_init(dwc->usb3_generic_phy);
1077         if (ret < 0) {
1078                 phy_exit(dwc->usb2_generic_phy);
1079                 goto err0a;
1080         }
1081
1082         ret = dwc3_core_soft_reset(dwc);
1083         if (ret)
1084                 goto err1;
1085
1086         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1087             !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1088                 if (!dwc->dis_u3_susphy_quirk) {
1089                         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1090                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1091                         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1092                 }
1093
1094                 if (!dwc->dis_u2_susphy_quirk) {
1095                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1096                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1097                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1098                 }
1099         }
1100
1101         dwc3_core_setup_global_control(dwc);
1102         dwc3_core_num_eps(dwc);
1103
1104         ret = dwc3_setup_scratch_buffers(dwc);
1105         if (ret)
1106                 goto err1;
1107
1108         /* Adjust Frame Length */
1109         dwc3_frame_length_adjustment(dwc);
1110
1111         /* Adjust Reference Clock Period */
1112         dwc3_ref_clk_period(dwc);
1113
1114         dwc3_set_incr_burst_type(dwc);
1115
1116         usb_phy_set_suspend(dwc->usb2_phy, 0);
1117         usb_phy_set_suspend(dwc->usb3_phy, 0);
1118         ret = phy_power_on(dwc->usb2_generic_phy);
1119         if (ret < 0)
1120                 goto err2;
1121
1122         ret = phy_power_on(dwc->usb3_generic_phy);
1123         if (ret < 0)
1124                 goto err3;
1125
1126         ret = dwc3_event_buffers_setup(dwc);
1127         if (ret) {
1128                 dev_err(dwc->dev, "failed to setup event buffers\n");
1129                 goto err4;
1130         }
1131
1132         /*
1133          * ENDXFER polling is available on version 3.10a and later of
1134          * the DWC_usb3 controller. It is NOT available in the
1135          * DWC_usb31 controller.
1136          */
1137         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1138                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1139                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1140                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1141         }
1142
1143         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1144                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1145
1146                 /*
1147                  * Enable hardware control of sending remote wakeup
1148                  * in HS when the device is in the L1 state.
1149                  */
1150                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1151                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1152
1153                 /*
1154                  * Decouple USB 2.0 L1 & L2 events which will allow for
1155                  * gadget driver to only receive U3/L2 suspend & wakeup
1156                  * events and prevent the more frequent L1 LPM transitions
1157                  * from interrupting the driver.
1158                  */
1159                 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1160                         reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1161
1162                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1163                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1164
1165                 if (dwc->parkmode_disable_ss_quirk)
1166                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1167
1168                 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1169                     (dwc->maximum_speed == USB_SPEED_HIGH ||
1170                      dwc->maximum_speed == USB_SPEED_FULL))
1171                         reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1172
1173                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1174         }
1175
1176         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1177             dwc->dr_mode == USB_DR_MODE_OTG) {
1178                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1179
1180                 /*
1181                  * Enable Auto retry Feature to make the controller operating in
1182                  * Host mode on seeing transaction errors(CRC errors or internal
1183                  * overrun scenerios) on IN transfers to reply to the device
1184                  * with a non-terminating retry ACK (i.e, an ACK transcation
1185                  * packet with Retry=1 & Nump != 0)
1186                  */
1187                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1188
1189                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1190         }
1191
1192         /*
1193          * Must config both number of packets and max burst settings to enable
1194          * RX and/or TX threshold.
1195          */
1196         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1197                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1198                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1199                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1200                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1201
1202                 if (rx_thr_num && rx_maxburst) {
1203                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1204                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1205
1206                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1207                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1208
1209                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1210                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1211
1212                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1213                 }
1214
1215                 if (tx_thr_num && tx_maxburst) {
1216                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1217                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1218
1219                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1220                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1221
1222                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1223                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1224
1225                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1226                 }
1227         }
1228
1229         return 0;
1230
1231 err4:
1232         phy_power_off(dwc->usb3_generic_phy);
1233
1234 err3:
1235         phy_power_off(dwc->usb2_generic_phy);
1236
1237 err2:
1238         usb_phy_set_suspend(dwc->usb2_phy, 1);
1239         usb_phy_set_suspend(dwc->usb3_phy, 1);
1240
1241 err1:
1242         usb_phy_shutdown(dwc->usb2_phy);
1243         usb_phy_shutdown(dwc->usb3_phy);
1244         phy_exit(dwc->usb2_generic_phy);
1245         phy_exit(dwc->usb3_generic_phy);
1246
1247 err0a:
1248         dwc3_ulpi_exit(dwc);
1249
1250 err0:
1251         return ret;
1252 }
1253
1254 static int dwc3_core_get_phy(struct dwc3 *dwc)
1255 {
1256         struct device           *dev = dwc->dev;
1257         struct device_node      *node = dev->of_node;
1258         int ret;
1259
1260         if (node) {
1261                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1262                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1263         } else {
1264                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1265                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1266         }
1267
1268         if (IS_ERR(dwc->usb2_phy)) {
1269                 ret = PTR_ERR(dwc->usb2_phy);
1270                 if (ret == -ENXIO || ret == -ENODEV)
1271                         dwc->usb2_phy = NULL;
1272                 else
1273                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1274         }
1275
1276         if (IS_ERR(dwc->usb3_phy)) {
1277                 ret = PTR_ERR(dwc->usb3_phy);
1278                 if (ret == -ENXIO || ret == -ENODEV)
1279                         dwc->usb3_phy = NULL;
1280                 else
1281                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1282         }
1283
1284         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1285         if (IS_ERR(dwc->usb2_generic_phy)) {
1286                 ret = PTR_ERR(dwc->usb2_generic_phy);
1287                 if (ret == -ENOSYS || ret == -ENODEV)
1288                         dwc->usb2_generic_phy = NULL;
1289                 else
1290                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1291         }
1292
1293         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1294         if (IS_ERR(dwc->usb3_generic_phy)) {
1295                 ret = PTR_ERR(dwc->usb3_generic_phy);
1296                 if (ret == -ENOSYS || ret == -ENODEV)
1297                         dwc->usb3_generic_phy = NULL;
1298                 else
1299                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int dwc3_core_init_mode(struct dwc3 *dwc)
1306 {
1307         struct device *dev = dwc->dev;
1308         int ret;
1309
1310         switch (dwc->dr_mode) {
1311         case USB_DR_MODE_PERIPHERAL:
1312                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1313
1314                 if (dwc->usb2_phy)
1315                         otg_set_vbus(dwc->usb2_phy->otg, false);
1316                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1317                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1318
1319                 ret = dwc3_gadget_init(dwc);
1320                 if (ret)
1321                         return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1322                 break;
1323         case USB_DR_MODE_HOST:
1324                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1325
1326                 if (dwc->usb2_phy)
1327                         otg_set_vbus(dwc->usb2_phy->otg, true);
1328                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1329                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1330
1331                 ret = dwc3_host_init(dwc);
1332                 if (ret)
1333                         return dev_err_probe(dev, ret, "failed to initialize host\n");
1334                 break;
1335         case USB_DR_MODE_OTG:
1336                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1337                 ret = dwc3_drd_init(dwc);
1338                 if (ret)
1339                         return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1340                 break;
1341         default:
1342                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1343                 return -EINVAL;
1344         }
1345
1346         return 0;
1347 }
1348
1349 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1350 {
1351         switch (dwc->dr_mode) {
1352         case USB_DR_MODE_PERIPHERAL:
1353                 dwc3_gadget_exit(dwc);
1354                 break;
1355         case USB_DR_MODE_HOST:
1356                 dwc3_host_exit(dwc);
1357                 break;
1358         case USB_DR_MODE_OTG:
1359                 dwc3_drd_exit(dwc);
1360                 break;
1361         default:
1362                 /* do nothing */
1363                 break;
1364         }
1365
1366         /* de-assert DRVVBUS for HOST and OTG mode */
1367         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1368 }
1369
1370 static void dwc3_get_properties(struct dwc3 *dwc)
1371 {
1372         struct device           *dev = dwc->dev;
1373         u8                      lpm_nyet_threshold;
1374         u8                      tx_de_emphasis;
1375         u8                      hird_threshold;
1376         u8                      rx_thr_num_pkt_prd = 0;
1377         u8                      rx_max_burst_prd = 0;
1378         u8                      tx_thr_num_pkt_prd = 0;
1379         u8                      tx_max_burst_prd = 0;
1380         u8                      tx_fifo_resize_max_num;
1381         const char              *usb_psy_name;
1382         int                     ret;
1383
1384         /* default to highest possible threshold */
1385         lpm_nyet_threshold = 0xf;
1386
1387         /* default to -3.5dB de-emphasis */
1388         tx_de_emphasis = 1;
1389
1390         /*
1391          * default to assert utmi_sleep_n and use maximum allowed HIRD
1392          * threshold value of 0b1100
1393          */
1394         hird_threshold = 12;
1395
1396         /*
1397          * default to a TXFIFO size large enough to fit 6 max packets.  This
1398          * allows for systems with larger bus latencies to have some headroom
1399          * for endpoints that have a large bMaxBurst value.
1400          */
1401         tx_fifo_resize_max_num = 6;
1402
1403         dwc->maximum_speed = usb_get_maximum_speed(dev);
1404         dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1405         dwc->dr_mode = usb_get_dr_mode(dev);
1406         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1407
1408         dwc->sysdev_is_parent = device_property_read_bool(dev,
1409                                 "linux,sysdev_is_parent");
1410         if (dwc->sysdev_is_parent)
1411                 dwc->sysdev = dwc->dev->parent;
1412         else
1413                 dwc->sysdev = dwc->dev;
1414
1415         ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1416         if (ret >= 0) {
1417                 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1418                 if (!dwc->usb_psy)
1419                         dev_err(dev, "couldn't get usb power supply\n");
1420         }
1421
1422         dwc->has_lpm_erratum = device_property_read_bool(dev,
1423                                 "snps,has-lpm-erratum");
1424         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1425                                 &lpm_nyet_threshold);
1426         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1427                                 "snps,is-utmi-l1-suspend");
1428         device_property_read_u8(dev, "snps,hird-threshold",
1429                                 &hird_threshold);
1430         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1431                                 "snps,dis-start-transfer-quirk");
1432         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1433                                 "snps,usb3_lpm_capable");
1434         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1435                                 "snps,usb2-lpm-disable");
1436         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1437                                 "snps,usb2-gadget-lpm-disable");
1438         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1439                                 &rx_thr_num_pkt_prd);
1440         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1441                                 &rx_max_burst_prd);
1442         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1443                                 &tx_thr_num_pkt_prd);
1444         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1445                                 &tx_max_burst_prd);
1446         dwc->do_fifo_resize = device_property_read_bool(dev,
1447                                                         "tx-fifo-resize");
1448         if (dwc->do_fifo_resize)
1449                 device_property_read_u8(dev, "tx-fifo-max-num",
1450                                         &tx_fifo_resize_max_num);
1451
1452         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1453                                 "snps,disable_scramble_quirk");
1454         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1455                                 "snps,u2exit_lfps_quirk");
1456         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1457                                 "snps,u2ss_inp3_quirk");
1458         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1459                                 "snps,req_p1p2p3_quirk");
1460         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1461                                 "snps,del_p1p2p3_quirk");
1462         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1463                                 "snps,del_phy_power_chg_quirk");
1464         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1465                                 "snps,lfps_filter_quirk");
1466         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1467                                 "snps,rx_detect_poll_quirk");
1468         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1469                                 "snps,dis_u3_susphy_quirk");
1470         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1471                                 "snps,dis_u2_susphy_quirk");
1472         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1473                                 "snps,dis_enblslpm_quirk");
1474         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1475                                 "snps,dis-u1-entry-quirk");
1476         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1477                                 "snps,dis-u2-entry-quirk");
1478         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1479                                 "snps,dis_rxdet_inp3_quirk");
1480         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1481                                 "snps,dis-u2-freeclk-exists-quirk");
1482         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1483                                 "snps,dis-del-phy-power-chg-quirk");
1484         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1485                                 "snps,dis-tx-ipgap-linecheck-quirk");
1486         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1487                                 "snps,parkmode-disable-ss-quirk");
1488
1489         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1490                                 "snps,tx_de_emphasis_quirk");
1491         device_property_read_u8(dev, "snps,tx_de_emphasis",
1492                                 &tx_de_emphasis);
1493         device_property_read_string(dev, "snps,hsphy_interface",
1494                                     &dwc->hsphy_interface);
1495         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1496                                  &dwc->fladj);
1497         device_property_read_u32(dev, "snps,ref-clock-period-ns",
1498                                  &dwc->ref_clk_per);
1499
1500         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1501                                 "snps,dis_metastability_quirk");
1502
1503         dwc->dis_split_quirk = device_property_read_bool(dev,
1504                                 "snps,dis-split-quirk");
1505
1506         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1507         dwc->tx_de_emphasis = tx_de_emphasis;
1508
1509         dwc->hird_threshold = hird_threshold;
1510
1511         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1512         dwc->rx_max_burst_prd = rx_max_burst_prd;
1513
1514         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1515         dwc->tx_max_burst_prd = tx_max_burst_prd;
1516
1517         dwc->imod_interval = 0;
1518
1519         dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1520 }
1521
1522 /* check whether the core supports IMOD */
1523 bool dwc3_has_imod(struct dwc3 *dwc)
1524 {
1525         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1526                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1527                 DWC3_IP_IS(DWC32);
1528 }
1529
1530 static void dwc3_check_params(struct dwc3 *dwc)
1531 {
1532         struct device *dev = dwc->dev;
1533         unsigned int hwparam_gen =
1534                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1535
1536         /* Check for proper value of imod_interval */
1537         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1538                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1539                 dwc->imod_interval = 0;
1540         }
1541
1542         /*
1543          * Workaround for STAR 9000961433 which affects only version
1544          * 3.00a of the DWC_usb3 core. This prevents the controller
1545          * interrupt from being masked while handling events. IMOD
1546          * allows us to work around this issue. Enable it for the
1547          * affected version.
1548          */
1549         if (!dwc->imod_interval &&
1550             DWC3_VER_IS(DWC3, 300A))
1551                 dwc->imod_interval = 1;
1552
1553         /* Check the maximum_speed parameter */
1554         switch (dwc->maximum_speed) {
1555         case USB_SPEED_FULL:
1556         case USB_SPEED_HIGH:
1557                 break;
1558         case USB_SPEED_SUPER:
1559                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1560                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1561                 break;
1562         case USB_SPEED_SUPER_PLUS:
1563                 if ((DWC3_IP_IS(DWC32) &&
1564                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1565                     (!DWC3_IP_IS(DWC32) &&
1566                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1567                         dev_warn(dev, "UDC doesn't support SSP\n");
1568                 break;
1569         default:
1570                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1571                         dwc->maximum_speed);
1572                 fallthrough;
1573         case USB_SPEED_UNKNOWN:
1574                 switch (hwparam_gen) {
1575                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1576                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1577                         break;
1578                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1579                         if (DWC3_IP_IS(DWC32))
1580                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1581                         else
1582                                 dwc->maximum_speed = USB_SPEED_SUPER;
1583                         break;
1584                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1585                         dwc->maximum_speed = USB_SPEED_HIGH;
1586                         break;
1587                 default:
1588                         dwc->maximum_speed = USB_SPEED_SUPER;
1589                         break;
1590                 }
1591                 break;
1592         }
1593
1594         /*
1595          * Currently the controller does not have visibility into the HW
1596          * parameter to determine the maximum number of lanes the HW supports.
1597          * If the number of lanes is not specified in the device property, then
1598          * set the default to support dual-lane for DWC_usb32 and single-lane
1599          * for DWC_usb31 for super-speed-plus.
1600          */
1601         if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1602                 switch (dwc->max_ssp_rate) {
1603                 case USB_SSP_GEN_2x1:
1604                         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1605                                 dev_warn(dev, "UDC only supports Gen 1\n");
1606                         break;
1607                 case USB_SSP_GEN_1x2:
1608                 case USB_SSP_GEN_2x2:
1609                         if (DWC3_IP_IS(DWC31))
1610                                 dev_warn(dev, "UDC only supports single lane\n");
1611                         break;
1612                 case USB_SSP_GEN_UNKNOWN:
1613                 default:
1614                         switch (hwparam_gen) {
1615                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1616                                 if (DWC3_IP_IS(DWC32))
1617                                         dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1618                                 else
1619                                         dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1620                                 break;
1621                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1622                                 if (DWC3_IP_IS(DWC32))
1623                                         dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1624                                 break;
1625                         }
1626                         break;
1627                 }
1628         }
1629 }
1630
1631 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1632 {
1633         struct device *dev = dwc->dev;
1634         struct device_node *np_phy;
1635         struct extcon_dev *edev = NULL;
1636         const char *name;
1637
1638         if (device_property_read_bool(dev, "extcon"))
1639                 return extcon_get_edev_by_phandle(dev, 0);
1640
1641         /*
1642          * Device tree platforms should get extcon via phandle.
1643          * On ACPI platforms, we get the name from a device property.
1644          * This device property is for kernel internal use only and
1645          * is expected to be set by the glue code.
1646          */
1647         if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1648                 return extcon_get_extcon_dev(name);
1649
1650         /*
1651          * Try to get an extcon device from the USB PHY controller's "port"
1652          * node. Check if it has the "port" node first, to avoid printing the
1653          * error message from underlying code, as it's a valid case: extcon
1654          * device (and "port" node) may be missing in case of "usb-role-switch"
1655          * or OTG mode.
1656          */
1657         np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1658         if (of_graph_is_present(np_phy)) {
1659                 struct device_node *np_conn;
1660
1661                 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1662                 if (np_conn)
1663                         edev = extcon_find_edev_by_node(np_conn);
1664                 of_node_put(np_conn);
1665         }
1666         of_node_put(np_phy);
1667
1668         return edev;
1669 }
1670
1671 static int dwc3_probe(struct platform_device *pdev)
1672 {
1673         struct device           *dev = &pdev->dev;
1674         struct resource         *res, dwc_res;
1675         struct dwc3             *dwc;
1676
1677         int                     ret;
1678
1679         void __iomem            *regs;
1680
1681         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1682         if (!dwc)
1683                 return -ENOMEM;
1684
1685         dwc->dev = dev;
1686
1687         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1688         if (!res) {
1689                 dev_err(dev, "missing memory resource\n");
1690                 return -ENODEV;
1691         }
1692
1693         dwc->xhci_resources[0].start = res->start;
1694         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1695                                         DWC3_XHCI_REGS_END;
1696         dwc->xhci_resources[0].flags = res->flags;
1697         dwc->xhci_resources[0].name = res->name;
1698
1699         /*
1700          * Request memory region but exclude xHCI regs,
1701          * since it will be requested by the xhci-plat driver.
1702          */
1703         dwc_res = *res;
1704         dwc_res.start += DWC3_GLOBALS_REGS_START;
1705
1706         regs = devm_ioremap_resource(dev, &dwc_res);
1707         if (IS_ERR(regs))
1708                 return PTR_ERR(regs);
1709
1710         dwc->regs       = regs;
1711         dwc->regs_size  = resource_size(&dwc_res);
1712
1713         dwc3_get_properties(dwc);
1714
1715         if (!dwc->sysdev_is_parent) {
1716                 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1717                 if (ret)
1718                         return ret;
1719         }
1720
1721         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1722         if (IS_ERR(dwc->reset))
1723                 return PTR_ERR(dwc->reset);
1724
1725         if (dev->of_node) {
1726                 /*
1727                  * Clocks are optional, but new DT platforms should support all
1728                  * clocks as required by the DT-binding.
1729                  * Some devices have different clock names in legacy device trees,
1730                  * check for them to retain backwards compatibility.
1731                  */
1732                 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1733                 if (IS_ERR(dwc->bus_clk))
1734                         return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1735                                              "could not get bus clock\n");
1736
1737                 if (dwc->bus_clk == NULL) {
1738                         dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1739                         if (IS_ERR(dwc->bus_clk))
1740                                 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1741                                                      "could not get bus clock\n");
1742                 }
1743
1744                 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1745                 if (IS_ERR(dwc->ref_clk))
1746                         return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1747                                              "could not get ref clock\n");
1748
1749                 if (dwc->ref_clk == NULL) {
1750                         dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1751                         if (IS_ERR(dwc->ref_clk))
1752                                 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1753                                                      "could not get ref clock\n");
1754                 }
1755
1756                 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1757                 if (IS_ERR(dwc->susp_clk))
1758                         return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1759                                              "could not get suspend clock\n");
1760
1761                 if (dwc->susp_clk == NULL) {
1762                         dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1763                         if (IS_ERR(dwc->susp_clk))
1764                                 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1765                                                      "could not get suspend clock\n");
1766                 }
1767         }
1768
1769         ret = reset_control_deassert(dwc->reset);
1770         if (ret)
1771                 return ret;
1772
1773         ret = dwc3_clk_enable(dwc);
1774         if (ret)
1775                 goto assert_reset;
1776
1777         if (!dwc3_core_is_valid(dwc)) {
1778                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1779                 ret = -ENODEV;
1780                 goto disable_clks;
1781         }
1782
1783         platform_set_drvdata(pdev, dwc);
1784         dwc3_cache_hwparams(dwc);
1785
1786         spin_lock_init(&dwc->lock);
1787         mutex_init(&dwc->mutex);
1788
1789         pm_runtime_set_active(dev);
1790         pm_runtime_use_autosuspend(dev);
1791         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1792         pm_runtime_enable(dev);
1793         ret = pm_runtime_get_sync(dev);
1794         if (ret < 0)
1795                 goto err1;
1796
1797         pm_runtime_forbid(dev);
1798
1799         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1800         if (ret) {
1801                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1802                 ret = -ENOMEM;
1803                 goto err2;
1804         }
1805
1806         dwc->edev = dwc3_get_extcon(dwc);
1807         if (IS_ERR(dwc->edev)) {
1808                 ret = PTR_ERR(dwc->edev);
1809                 dev_err_probe(dwc->dev, ret, "failed to get extcon\n");
1810                 goto err3;
1811         }
1812
1813         ret = dwc3_get_dr_mode(dwc);
1814         if (ret)
1815                 goto err3;
1816
1817         ret = dwc3_alloc_scratch_buffers(dwc);
1818         if (ret)
1819                 goto err3;
1820
1821         ret = dwc3_core_init(dwc);
1822         if (ret) {
1823                 dev_err_probe(dev, ret, "failed to initialize core\n");
1824                 goto err4;
1825         }
1826
1827         dwc3_check_params(dwc);
1828         dwc3_debugfs_init(dwc);
1829
1830         ret = dwc3_core_init_mode(dwc);
1831         if (ret)
1832                 goto err5;
1833
1834         pm_runtime_put(dev);
1835
1836         return 0;
1837
1838 err5:
1839         dwc3_debugfs_exit(dwc);
1840         dwc3_event_buffers_cleanup(dwc);
1841
1842         usb_phy_shutdown(dwc->usb2_phy);
1843         usb_phy_shutdown(dwc->usb3_phy);
1844         phy_exit(dwc->usb2_generic_phy);
1845         phy_exit(dwc->usb3_generic_phy);
1846
1847         usb_phy_set_suspend(dwc->usb2_phy, 1);
1848         usb_phy_set_suspend(dwc->usb3_phy, 1);
1849         phy_power_off(dwc->usb2_generic_phy);
1850         phy_power_off(dwc->usb3_generic_phy);
1851
1852         dwc3_ulpi_exit(dwc);
1853
1854 err4:
1855         dwc3_free_scratch_buffers(dwc);
1856
1857 err3:
1858         dwc3_free_event_buffers(dwc);
1859
1860 err2:
1861         pm_runtime_allow(&pdev->dev);
1862
1863 err1:
1864         pm_runtime_put_sync(&pdev->dev);
1865         pm_runtime_disable(&pdev->dev);
1866
1867 disable_clks:
1868         dwc3_clk_disable(dwc);
1869 assert_reset:
1870         reset_control_assert(dwc->reset);
1871
1872         if (dwc->usb_psy)
1873                 power_supply_put(dwc->usb_psy);
1874
1875         return ret;
1876 }
1877
1878 static int dwc3_remove(struct platform_device *pdev)
1879 {
1880         struct dwc3     *dwc = platform_get_drvdata(pdev);
1881
1882         pm_runtime_get_sync(&pdev->dev);
1883
1884         dwc3_core_exit_mode(dwc);
1885         dwc3_debugfs_exit(dwc);
1886
1887         dwc3_core_exit(dwc);
1888         dwc3_ulpi_exit(dwc);
1889
1890         pm_runtime_disable(&pdev->dev);
1891         pm_runtime_put_noidle(&pdev->dev);
1892         pm_runtime_set_suspended(&pdev->dev);
1893
1894         dwc3_free_event_buffers(dwc);
1895         dwc3_free_scratch_buffers(dwc);
1896
1897         if (dwc->usb_psy)
1898                 power_supply_put(dwc->usb_psy);
1899
1900         return 0;
1901 }
1902
1903 #ifdef CONFIG_PM
1904 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1905 {
1906         int ret;
1907
1908         ret = reset_control_deassert(dwc->reset);
1909         if (ret)
1910                 return ret;
1911
1912         ret = dwc3_clk_enable(dwc);
1913         if (ret)
1914                 goto assert_reset;
1915
1916         ret = dwc3_core_init(dwc);
1917         if (ret)
1918                 goto disable_clks;
1919
1920         return 0;
1921
1922 disable_clks:
1923         dwc3_clk_disable(dwc);
1924 assert_reset:
1925         reset_control_assert(dwc->reset);
1926
1927         return ret;
1928 }
1929
1930 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1931 {
1932         unsigned long   flags;
1933         u32 reg;
1934
1935         switch (dwc->current_dr_role) {
1936         case DWC3_GCTL_PRTCAP_DEVICE:
1937                 if (pm_runtime_suspended(dwc->dev))
1938                         break;
1939                 spin_lock_irqsave(&dwc->lock, flags);
1940                 dwc3_gadget_suspend(dwc);
1941                 spin_unlock_irqrestore(&dwc->lock, flags);
1942                 synchronize_irq(dwc->irq_gadget);
1943                 dwc3_core_exit(dwc);
1944                 break;
1945         case DWC3_GCTL_PRTCAP_HOST:
1946                 if (!PMSG_IS_AUTO(msg)) {
1947                         dwc3_core_exit(dwc);
1948                         break;
1949                 }
1950
1951                 /* Let controller to suspend HSPHY before PHY driver suspends */
1952                 if (dwc->dis_u2_susphy_quirk ||
1953                     dwc->dis_enblslpm_quirk) {
1954                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1955                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1956                                 DWC3_GUSB2PHYCFG_SUSPHY;
1957                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1958
1959                         /* Give some time for USB2 PHY to suspend */
1960                         usleep_range(5000, 6000);
1961                 }
1962
1963                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1964                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1965                 break;
1966         case DWC3_GCTL_PRTCAP_OTG:
1967                 /* do nothing during runtime_suspend */
1968                 if (PMSG_IS_AUTO(msg))
1969                         break;
1970
1971                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1972                         spin_lock_irqsave(&dwc->lock, flags);
1973                         dwc3_gadget_suspend(dwc);
1974                         spin_unlock_irqrestore(&dwc->lock, flags);
1975                         synchronize_irq(dwc->irq_gadget);
1976                 }
1977
1978                 dwc3_otg_exit(dwc);
1979                 dwc3_core_exit(dwc);
1980                 break;
1981         default:
1982                 /* do nothing */
1983                 break;
1984         }
1985
1986         return 0;
1987 }
1988
1989 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1990 {
1991         unsigned long   flags;
1992         int             ret;
1993         u32             reg;
1994
1995         switch (dwc->current_dr_role) {
1996         case DWC3_GCTL_PRTCAP_DEVICE:
1997                 ret = dwc3_core_init_for_resume(dwc);
1998                 if (ret)
1999                         return ret;
2000
2001                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2002                 spin_lock_irqsave(&dwc->lock, flags);
2003                 dwc3_gadget_resume(dwc);
2004                 spin_unlock_irqrestore(&dwc->lock, flags);
2005                 break;
2006         case DWC3_GCTL_PRTCAP_HOST:
2007                 if (!PMSG_IS_AUTO(msg)) {
2008                         ret = dwc3_core_init_for_resume(dwc);
2009                         if (ret)
2010                                 return ret;
2011                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2012                         break;
2013                 }
2014                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2015                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2016                 if (dwc->dis_u2_susphy_quirk)
2017                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2018
2019                 if (dwc->dis_enblslpm_quirk)
2020                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2021
2022                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2023
2024                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2025                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2026                 break;
2027         case DWC3_GCTL_PRTCAP_OTG:
2028                 /* nothing to do on runtime_resume */
2029                 if (PMSG_IS_AUTO(msg))
2030                         break;
2031
2032                 ret = dwc3_core_init_for_resume(dwc);
2033                 if (ret)
2034                         return ret;
2035
2036                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2037
2038                 dwc3_otg_init(dwc);
2039                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2040                         dwc3_otg_host_init(dwc);
2041                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2042                         spin_lock_irqsave(&dwc->lock, flags);
2043                         dwc3_gadget_resume(dwc);
2044                         spin_unlock_irqrestore(&dwc->lock, flags);
2045                 }
2046
2047                 break;
2048         default:
2049                 /* do nothing */
2050                 break;
2051         }
2052
2053         return 0;
2054 }
2055
2056 static int dwc3_runtime_checks(struct dwc3 *dwc)
2057 {
2058         switch (dwc->current_dr_role) {
2059         case DWC3_GCTL_PRTCAP_DEVICE:
2060                 if (dwc->connected)
2061                         return -EBUSY;
2062                 break;
2063         case DWC3_GCTL_PRTCAP_HOST:
2064         default:
2065                 /* do nothing */
2066                 break;
2067         }
2068
2069         return 0;
2070 }
2071
2072 static int dwc3_runtime_suspend(struct device *dev)
2073 {
2074         struct dwc3     *dwc = dev_get_drvdata(dev);
2075         int             ret;
2076
2077         if (dwc3_runtime_checks(dwc))
2078                 return -EBUSY;
2079
2080         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2081         if (ret)
2082                 return ret;
2083
2084         device_init_wakeup(dev, true);
2085
2086         return 0;
2087 }
2088
2089 static int dwc3_runtime_resume(struct device *dev)
2090 {
2091         struct dwc3     *dwc = dev_get_drvdata(dev);
2092         int             ret;
2093
2094         device_init_wakeup(dev, false);
2095
2096         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2097         if (ret)
2098                 return ret;
2099
2100         switch (dwc->current_dr_role) {
2101         case DWC3_GCTL_PRTCAP_DEVICE:
2102                 dwc3_gadget_process_pending_events(dwc);
2103                 break;
2104         case DWC3_GCTL_PRTCAP_HOST:
2105         default:
2106                 /* do nothing */
2107                 break;
2108         }
2109
2110         pm_runtime_mark_last_busy(dev);
2111
2112         return 0;
2113 }
2114
2115 static int dwc3_runtime_idle(struct device *dev)
2116 {
2117         struct dwc3     *dwc = dev_get_drvdata(dev);
2118
2119         switch (dwc->current_dr_role) {
2120         case DWC3_GCTL_PRTCAP_DEVICE:
2121                 if (dwc3_runtime_checks(dwc))
2122                         return -EBUSY;
2123                 break;
2124         case DWC3_GCTL_PRTCAP_HOST:
2125         default:
2126                 /* do nothing */
2127                 break;
2128         }
2129
2130         pm_runtime_mark_last_busy(dev);
2131         pm_runtime_autosuspend(dev);
2132
2133         return 0;
2134 }
2135 #endif /* CONFIG_PM */
2136
2137 #ifdef CONFIG_PM_SLEEP
2138 static int dwc3_suspend(struct device *dev)
2139 {
2140         struct dwc3     *dwc = dev_get_drvdata(dev);
2141         int             ret;
2142
2143         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2144         if (ret)
2145                 return ret;
2146
2147         pinctrl_pm_select_sleep_state(dev);
2148
2149         return 0;
2150 }
2151
2152 static int dwc3_resume(struct device *dev)
2153 {
2154         struct dwc3     *dwc = dev_get_drvdata(dev);
2155         int             ret;
2156
2157         pinctrl_pm_select_default_state(dev);
2158
2159         ret = dwc3_resume_common(dwc, PMSG_RESUME);
2160         if (ret)
2161                 return ret;
2162
2163         pm_runtime_disable(dev);
2164         pm_runtime_set_active(dev);
2165         pm_runtime_enable(dev);
2166
2167         return 0;
2168 }
2169
2170 static void dwc3_complete(struct device *dev)
2171 {
2172         struct dwc3     *dwc = dev_get_drvdata(dev);
2173         u32             reg;
2174
2175         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2176                         dwc->dis_split_quirk) {
2177                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2178                 reg |= DWC3_GUCTL3_SPLITDISABLE;
2179                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2180         }
2181 }
2182 #else
2183 #define dwc3_complete NULL
2184 #endif /* CONFIG_PM_SLEEP */
2185
2186 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2187         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2188         .complete = dwc3_complete,
2189         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2190                         dwc3_runtime_idle)
2191 };
2192
2193 #ifdef CONFIG_OF
2194 static const struct of_device_id of_dwc3_match[] = {
2195         {
2196                 .compatible = "snps,dwc3"
2197         },
2198         {
2199                 .compatible = "synopsys,dwc3"
2200         },
2201         { },
2202 };
2203 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2204 #endif
2205
2206 #ifdef CONFIG_ACPI
2207
2208 #define ACPI_ID_INTEL_BSW       "808622B7"
2209
2210 static const struct acpi_device_id dwc3_acpi_match[] = {
2211         { ACPI_ID_INTEL_BSW, 0 },
2212         { },
2213 };
2214 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2215 #endif
2216
2217 static struct platform_driver dwc3_driver = {
2218         .probe          = dwc3_probe,
2219         .remove         = dwc3_remove,
2220         .driver         = {
2221                 .name   = "dwc3",
2222                 .of_match_table = of_match_ptr(of_dwc3_match),
2223                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2224                 .pm     = &dwc3_dev_pm_ops,
2225         },
2226 };
2227
2228 module_platform_driver(dwc3_driver);
2229
2230 MODULE_ALIAS("platform:dwc3");
2231 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2232 MODULE_LICENSE("GPL v2");
2233 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");