drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                  * mode. If the controller supports DRD but the dr_mode is not
  85                  * specified or set to OTG, then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG &&
  88                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  89                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  90                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  91                         mode = USB_DR_MODE_PERIPHERAL;
  92         }
  93
  94         if (mode != dwc->dr_mode) {
  95                 dev_warn(dev,
  96                          "Configuration mismatch. dr_mode forced to %s\n",
  97                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  98
  99                 dwc->dr_mode = mode;
 100         }
 101
 102         return 0;
 103 }
 104
 105 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 106 {
 107         u32 reg;
 108
 109         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 110         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 111         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 112         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 113
 114         dwc->current_dr_role = mode;
 115 }
 116
 117 static void __dwc3_set_mode(struct work_struct *work)
 118 {
 119         struct dwc3 *dwc = work_to_dwc(work);
 120         unsigned long flags;
 121         int ret;
 122         u32 reg;
 123
 124         mutex_lock(&dwc->mutex);
 125
 126         pm_runtime_get_sync(dwc->dev);
 127
 128         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 129                 dwc3_otg_update(dwc, 0);
 130
 131         if (!dwc->desired_dr_role)
 132                 goto out;
 133
 134         if (dwc->desired_dr_role == dwc->current_dr_role)
 135                 goto out;
 136
 137         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 138                 goto out;
 139
 140         switch (dwc->current_dr_role) {
 141         case DWC3_GCTL_PRTCAP_HOST:
 142                 dwc3_host_exit(dwc);
 143                 break;
 144         case DWC3_GCTL_PRTCAP_DEVICE:
 145                 dwc3_gadget_exit(dwc);
 146                 dwc3_event_buffers_cleanup(dwc);
 147                 break;
 148         case DWC3_GCTL_PRTCAP_OTG:
 149                 dwc3_otg_exit(dwc);
 150                 spin_lock_irqsave(&dwc->lock, flags);
 151                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 152                 spin_unlock_irqrestore(&dwc->lock, flags);
 153                 dwc3_otg_update(dwc, 1);
 154                 break;
 155         default:
 156                 break;
 157         }
 158
 159         /*
 160          * When current_dr_role is not set, there's no role switching.
 161          * Only perform GCTL.CoreSoftReset when there's DRD role switching.
 162          */
 163         if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
 164                         DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
 165                         dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
 166                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 167                 reg |= DWC3_GCTL_CORESOFTRESET;
 168                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 169
 170                 /*
 171                  * Wait for internal clocks to synchronized. DWC_usb31 and
 172                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 173                  * keep it consistent across different IPs, let's wait up to
 174                  * 100ms before clearing GCTL.CORESOFTRESET.
 175                  */
 176                 msleep(100);
 177
 178                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 179                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 180                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 181         }
 182
 183         spin_lock_irqsave(&dwc->lock, flags);
 184
 185         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 186
 187         spin_unlock_irqrestore(&dwc->lock, flags);
 188
 189         switch (dwc->desired_dr_role) {
 190         case DWC3_GCTL_PRTCAP_HOST:
 191                 ret = dwc3_host_init(dwc);
 192                 if (ret) {
 193                         dev_err(dwc->dev, "failed to initialize host\n");
 194                 } else {
 195                         if (dwc->usb2_phy)
 196                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 197                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 198                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 199                         if (dwc->dis_split_quirk) {
 200                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 201                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 202                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 203                         }
 204                 }
 205                 break;
 206         case DWC3_GCTL_PRTCAP_DEVICE:
 207                 dwc3_core_soft_reset(dwc);
 208
 209                 dwc3_event_buffers_setup(dwc);
 210
 211                 if (dwc->usb2_phy)
 212                         otg_set_vbus(dwc->usb2_phy->otg, false);
 213                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 214                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 215
 216                 ret = dwc3_gadget_init(dwc);
 217                 if (ret)
 218                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 219                 break;
 220         case DWC3_GCTL_PRTCAP_OTG:
 221                 dwc3_otg_init(dwc);
 222                 dwc3_otg_update(dwc, 0);
 223                 break;
 224         default:
 225                 break;
 226         }
 227
 228 out:
 229         pm_runtime_mark_last_busy(dwc->dev);
 230         pm_runtime_put_autosuspend(dwc->dev);
 231         mutex_unlock(&dwc->mutex);
 232 }
 233
 234 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 235 {
 236         unsigned long flags;
 237
 238         if (dwc->dr_mode != USB_DR_MODE_OTG)
 239                 return;
 240
 241         spin_lock_irqsave(&dwc->lock, flags);
 242         dwc->desired_dr_role = mode;
 243         spin_unlock_irqrestore(&dwc->lock, flags);
 244
 245         queue_work(system_freezable_wq, &dwc->drd_work);
 246 }
 247
 248 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 249 {
 250         struct dwc3             *dwc = dep->dwc;
 251         u32                     reg;
 252
 253         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 254                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 255                         DWC3_GDBGFIFOSPACE_TYPE(type));
 256
 257         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 258
 259         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 260 }
 261
 262 /**
 263  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 264  * @dwc: pointer to our context structure
 265  */
 266 int dwc3_core_soft_reset(struct dwc3 *dwc)
 267 {
 268         u32             reg;
 269         int             retries = 1000;
 270
 271         /*
 272          * We're resetting only the device side because, if we're in host mode,
 273          * XHCI driver will reset the host block. If dwc3 was configured for
 274          * host-only mode, then we can return early.
 275          */
 276         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 277                 return 0;
 278
 279         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 280         reg |= DWC3_DCTL_CSFTRST;
 281         reg &= ~DWC3_DCTL_RUN_STOP;
 282         dwc3_gadget_dctl_write_safe(dwc, reg);
 283
 284         /*
 285          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 286          * is cleared only after all the clocks are synchronized. This can
 287          * take a little more than 50ms. Set the polling rate at 20ms
 288          * for 10 times instead.
 289          */
 290         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 291                 retries = 10;
 292
 293         do {
 294                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 295                 if (!(reg & DWC3_DCTL_CSFTRST))
 296                         goto done;
 297
 298                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 299                         msleep(20);
 300                 else
 301                         udelay(1);
 302         } while (--retries);
 303
 304         return -ETIMEDOUT;
 305
 306 done:
 307         /*
 308          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 309          * is cleared, we must wait at least 50ms before accessing the PHY
 310          * domain (synchronization delay).
 311          */
 312         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 313                 msleep(50);
 314
 315         return 0;
 316 }
 317
 318 /*
 319  * dwc3_frame_length_adjustment - Adjusts frame length if required
 320  * @dwc3: Pointer to our controller context structure
 321  */
 322 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 323 {
 324         u32 reg;
 325         u32 dft;
 326
 327         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 328                 return;
 329
 330         if (dwc->fladj == 0)
 331                 return;
 332
 333         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 334         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 335         if (dft != dwc->fladj) {
 336                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 337                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 338                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 339         }
 340 }
 341
 342 /**
 343  * dwc3_free_one_event_buffer - Frees one event buffer
 344  * @dwc: Pointer to our controller context structure
 345  * @evt: Pointer to event buffer to be freed
 346  */
 347 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 348                 struct dwc3_event_buffer *evt)
 349 {
 350         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 351 }
 352
 353 /**
 354  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 355  * @dwc: Pointer to our controller context structure
 356  * @length: size of the event buffer
 357  *
 358  * Returns a pointer to the allocated event buffer structure on success
 359  * otherwise ERR_PTR(errno).
 360  */
 361 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 362                 unsigned length)
 363 {
 364         struct dwc3_event_buffer        *evt;
 365
 366         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 367         if (!evt)
 368                 return ERR_PTR(-ENOMEM);
 369
 370         evt->dwc        = dwc;
 371         evt->length     = length;
 372         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 373         if (!evt->cache)
 374                 return ERR_PTR(-ENOMEM);
 375
 376         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 377                         &evt->dma, GFP_KERNEL);
 378         if (!evt->buf)
 379                 return ERR_PTR(-ENOMEM);
 380
 381         return evt;
 382 }
 383
 384 /**
 385  * dwc3_free_event_buffers - frees all allocated event buffers
 386  * @dwc: Pointer to our controller context structure
 387  */
 388 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 389 {
 390         struct dwc3_event_buffer        *evt;
 391
 392         evt = dwc->ev_buf;
 393         if (evt)
 394                 dwc3_free_one_event_buffer(dwc, evt);
 395 }
 396
 397 /**
 398  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 399  * @dwc: pointer to our controller context structure
 400  * @length: size of event buffer
 401  *
 402  * Returns 0 on success otherwise negative errno. In the error case, dwc
 403  * may contain some buffers allocated but not all which were requested.
 404  */
 405 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 406 {
 407         struct dwc3_event_buffer *evt;
 408
 409         evt = dwc3_alloc_one_event_buffer(dwc, length);
 410         if (IS_ERR(evt)) {
 411                 dev_err(dwc->dev, "can't allocate event buffer\n");
 412                 return PTR_ERR(evt);
 413         }
 414         dwc->ev_buf = evt;
 415
 416         return 0;
 417 }
 418
 419 /**
 420  * dwc3_event_buffers_setup - setup our allocated event buffers
 421  * @dwc: pointer to our controller context structure
 422  *
 423  * Returns 0 on success otherwise negative errno.
 424  */
 425 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 426 {
 427         struct dwc3_event_buffer        *evt;
 428
 429         evt = dwc->ev_buf;
 430         evt->lpos = 0;
 431         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 432                         lower_32_bits(evt->dma));
 433         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 434                         upper_32_bits(evt->dma));
 435         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 436                         DWC3_GEVNTSIZ_SIZE(evt->length));
 437         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 438
 439         return 0;
 440 }
 441
 442 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 443 {
 444         struct dwc3_event_buffer        *evt;
 445
 446         evt = dwc->ev_buf;
 447
 448         evt->lpos = 0;
 449
 450         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 451         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 452         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 453                         | DWC3_GEVNTSIZ_SIZE(0));
 454         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 455 }
 456
 457 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 458 {
 459         if (!dwc->has_hibernation)
 460                 return 0;
 461
 462         if (!dwc->nr_scratch)
 463                 return 0;
 464
 465         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 466                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 467         if (!dwc->scratchbuf)
 468                 return -ENOMEM;
 469
 470         return 0;
 471 }
 472
 473 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 474 {
 475         dma_addr_t scratch_addr;
 476         u32 param;
 477         int ret;
 478
 479         if (!dwc->has_hibernation)
 480                 return 0;
 481
 482         if (!dwc->nr_scratch)
 483                 return 0;
 484
 485          /* should never fall here */
 486         if (!WARN_ON(dwc->scratchbuf))
 487                 return 0;
 488
 489         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 490                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 491                         DMA_BIDIRECTIONAL);
 492         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 493                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 494                 ret = -EFAULT;
 495                 goto err0;
 496         }
 497
 498         dwc->scratch_addr = scratch_addr;
 499
 500         param = lower_32_bits(scratch_addr);
 501
 502         ret = dwc3_send_gadget_generic_command(dwc,
 503                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 504         if (ret < 0)
 505                 goto err1;
 506
 507         param = upper_32_bits(scratch_addr);
 508
 509         ret = dwc3_send_gadget_generic_command(dwc,
 510                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 511         if (ret < 0)
 512                 goto err1;
 513
 514         return 0;
 515
 516 err1:
 517         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 518                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 519
 520 err0:
 521         return ret;
 522 }
 523
 524 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 525 {
 526         if (!dwc->has_hibernation)
 527                 return;
 528
 529         if (!dwc->nr_scratch)
 530                 return;
 531
 532          /* should never fall here */
 533         if (!WARN_ON(dwc->scratchbuf))
 534                 return;
 535
 536         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 537                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 538         kfree(dwc->scratchbuf);
 539 }
 540
 541 static void dwc3_core_num_eps(struct dwc3 *dwc)
 542 {
 543         struct dwc3_hwparams    *parms = &dwc->hwparams;
 544
 545         dwc->num_eps = DWC3_NUM_EPS(parms);
 546 }
 547
 548 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 549 {
 550         struct dwc3_hwparams    *parms = &dwc->hwparams;
 551
 552         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 553         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 554         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 555         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 556         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 557         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 558         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 559         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 560         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 561 }
 562
 563 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 564 {
 565         int intf;
 566         int ret = 0;
 567
 568         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 569
 570         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 571             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 572              dwc->hsphy_interface &&
 573              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 574                 ret = dwc3_ulpi_init(dwc);
 575
 576         return ret;
 577 }
 578
 579 /**
 580  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 581  * @dwc: Pointer to our controller context structure
 582  *
 583  * Returns 0 on success. The USB PHY interfaces are configured but not
 584  * initialized. The PHY interfaces and the PHYs get initialized together with
 585  * the core in dwc3_core_init.
 586  */
 587 static int dwc3_phy_setup(struct dwc3 *dwc)
 588 {
 589         unsigned int hw_mode;
 590         u32 reg;
 591
 592         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 593
 594         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 595
 596         /*
 597          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 598          * PHYs. Also, this bit is not supposed to be used in normal operation.
 599          */
 600         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 601
 602         /*
 603          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 604          * to '0' during coreConsultant configuration. So default value
 605          * will be '0' when the core is reset. Application needs to set it
 606          * to '1' after the core initialization is completed.
 607          */
 608         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 609                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 610
 611         /*
 612          * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 613          * power-on reset, and it can be set after core initialization, which is
 614          * after device soft-reset during initialization.
 615          */
 616         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 617                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 618
 619         if (dwc->u2ss_inp3_quirk)
 620                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 621
 622         if (dwc->dis_rxdet_inp3_quirk)
 623                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 624
 625         if (dwc->req_p1p2p3_quirk)
 626                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 627
 628         if (dwc->del_p1p2p3_quirk)
 629                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 630
 631         if (dwc->del_phy_power_chg_quirk)
 632                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 633
 634         if (dwc->lfps_filter_quirk)
 635                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 636
 637         if (dwc->rx_detect_poll_quirk)
 638                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 639
 640         if (dwc->tx_de_emphasis_quirk)
 641                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 642
 643         if (dwc->dis_u3_susphy_quirk)
 644                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 645
 646         if (dwc->dis_del_phy_power_chg_quirk)
 647                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 648
 649         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 650
 651         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 652
 653         /* Select the HS PHY interface */
 654         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 655         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 656                 if (dwc->hsphy_interface &&
 657                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 658                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 659                         break;
 660                 } else if (dwc->hsphy_interface &&
 661                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 662                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 663                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 664                 } else {
 665                         /* Relying on default value. */
 666                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 667                                 break;
 668                 }
 669                 fallthrough;
 670         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 671         default:
 672                 break;
 673         }
 674
 675         switch (dwc->hsphy_mode) {
 676         case USBPHY_INTERFACE_MODE_UTMI:
 677                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 678                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 679                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 680                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 681                 break;
 682         case USBPHY_INTERFACE_MODE_UTMIW:
 683                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 684                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 685                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 686                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 687                 break;
 688         default:
 689                 break;
 690         }
 691
 692         /*
 693          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 694          * '0' during coreConsultant configuration. So default value will
 695          * be '0' when the core is reset. Application needs to set it to
 696          * '1' after the core initialization is completed.
 697          */
 698         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 699                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 700
 701         /*
 702          * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 703          * power-on reset, and it can be set after core initialization, which is
 704          * after device soft-reset during initialization.
 705          */
 706         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 707                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 708
 709         if (dwc->dis_u2_susphy_quirk)
 710                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 711
 712         if (dwc->dis_enblslpm_quirk)
 713                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 714         else
 715                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 716
 717         if (dwc->dis_u2_freeclk_exists_quirk)
 718                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 719
 720         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 721
 722         return 0;
 723 }
 724
 725 static void dwc3_core_exit(struct dwc3 *dwc)
 726 {
 727         dwc3_event_buffers_cleanup(dwc);
 728
 729         usb_phy_set_suspend(dwc->usb2_phy, 1);
 730         usb_phy_set_suspend(dwc->usb3_phy, 1);
 731         phy_power_off(dwc->usb2_generic_phy);
 732         phy_power_off(dwc->usb3_generic_phy);
 733
 734         usb_phy_shutdown(dwc->usb2_phy);
 735         usb_phy_shutdown(dwc->usb3_phy);
 736         phy_exit(dwc->usb2_generic_phy);
 737         phy_exit(dwc->usb3_generic_phy);
 738
 739         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 740         reset_control_assert(dwc->reset);
 741 }
 742
 743 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 744 {
 745         u32 reg;
 746
 747         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 748         dwc->ip = DWC3_GSNPS_ID(reg);
 749
 750         /* This should read as U3 followed by revision number */
 751         if (DWC3_IP_IS(DWC3)) {
 752                 dwc->revision = reg;
 753         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 754                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 755                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 756         } else {
 757                 return false;
 758         }
 759
 760         return true;
 761 }
 762
 763 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 764 {
 765         u32 hwparams4 = dwc->hwparams.hwparams4;
 766         u32 reg;
 767
 768         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 769         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 770
 771         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 772         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 773                 /**
 774                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 775                  * issue which would cause xHCI compliance tests to fail.
 776                  *
 777                  * Because of that we cannot enable clock gating on such
 778                  * configurations.
 779                  *
 780                  * Refers to:
 781                  *
 782                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 783                  * SOF/ITP Mode Used
 784                  */
 785                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 786                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 787                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 788                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 789                 else
 790                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 791                 break;
 792         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 793                 /* enable hibernation here */
 794                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 795
 796                 /*
 797                  * REVISIT Enabling this bit so that host-mode hibernation
 798                  * will work. Device-mode hibernation is not yet implemented.
 799                  */
 800                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 801                 break;
 802         default:
 803                 /* nothing */
 804                 break;
 805         }
 806
 807         /* check if current dwc3 is on simulation board */
 808         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 809                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 810                 dwc->is_fpga = true;
 811         }
 812
 813         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 814                         "disable_scramble cannot be used on non-FPGA builds\n");
 815
 816         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 817                 reg |= DWC3_GCTL_DISSCRAMBLE;
 818         else
 819                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 820
 821         if (dwc->u2exit_lfps_quirk)
 822                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 823
 824         /*
 825          * WORKAROUND: DWC3 revisions <1.90a have a bug
 826          * where the device can fail to connect at SuperSpeed
 827          * and falls back to high-speed mode which causes
 828          * the device to enter a Connect/Disconnect loop
 829          */
 830         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 831                 reg |= DWC3_GCTL_U2RSTECN;
 832
 833         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 834 }
 835
 836 static int dwc3_core_get_phy(struct dwc3 *dwc);
 837 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 838
 839 /* set global incr burst type configuration registers */
 840 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 841 {
 842         struct device *dev = dwc->dev;
 843         /* incrx_mode : for INCR burst type. */
 844         bool incrx_mode;
 845         /* incrx_size : for size of INCRX burst. */
 846         u32 incrx_size;
 847         u32 *vals;
 848         u32 cfg;
 849         int ntype;
 850         int ret;
 851         int i;
 852
 853         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 854
 855         /*
 856          * Handle property "snps,incr-burst-type-adjustment".
 857          * Get the number of value from this property:
 858          * result <= 0, means this property is not supported.
 859          * result = 1, means INCRx burst mode supported.
 860          * result > 1, means undefined length burst mode supported.
 861          */
 862         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 863         if (ntype <= 0)
 864                 return;
 865
 866         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 867         if (!vals) {
 868                 dev_err(dev, "Error to get memory\n");
 869                 return;
 870         }
 871
 872         /* Get INCR burst type, and parse it */
 873         ret = device_property_read_u32_array(dev,
 874                         "snps,incr-burst-type-adjustment", vals, ntype);
 875         if (ret) {
 876                 kfree(vals);
 877                 dev_err(dev, "Error to get property\n");
 878                 return;
 879         }
 880
 881         incrx_size = *vals;
 882
 883         if (ntype > 1) {
 884                 /* INCRX (undefined length) burst mode */
 885                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 886                 for (i = 1; i < ntype; i++) {
 887                         if (vals[i] > incrx_size)
 888                                 incrx_size = vals[i];
 889                 }
 890         } else {
 891                 /* INCRX burst mode */
 892                 incrx_mode = INCRX_BURST_MODE;
 893         }
 894
 895         kfree(vals);
 896
 897         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 898         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 899         if (incrx_mode)
 900                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 901         switch (incrx_size) {
 902         case 256:
 903                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 904                 break;
 905         case 128:
 906                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 907                 break;
 908         case 64:
 909                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 910                 break;
 911         case 32:
 912                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 913                 break;
 914         case 16:
 915                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 916                 break;
 917         case 8:
 918                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 919                 break;
 920         case 4:
 921                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 922                 break;
 923         case 1:
 924                 break;
 925         default:
 926                 dev_err(dev, "Invalid property\n");
 927                 break;
 928         }
 929
 930         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 931 }
 932
 933 /**
 934  * dwc3_core_init - Low-level initialization of DWC3 Core
 935  * @dwc: Pointer to our controller context structure
 936  *
 937  * Returns 0 on success otherwise negative errno.
 938  */
 939 static int dwc3_core_init(struct dwc3 *dwc)
 940 {
 941         unsigned int            hw_mode;
 942         u32                     reg;
 943         int                     ret;
 944
 945         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 946
 947         /*
 948          * Write Linux Version Code to our GUID register so it's easy to figure
 949          * out which kernel version a bug was found.
 950          */
 951         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 952
 953         ret = dwc3_phy_setup(dwc);
 954         if (ret)
 955                 goto err0;
 956
 957         if (!dwc->ulpi_ready) {
 958                 ret = dwc3_core_ulpi_init(dwc);
 959                 if (ret)
 960                         goto err0;
 961                 dwc->ulpi_ready = true;
 962         }
 963
 964         if (!dwc->phys_ready) {
 965                 ret = dwc3_core_get_phy(dwc);
 966                 if (ret)
 967                         goto err0a;
 968                 dwc->phys_ready = true;
 969         }
 970
 971         usb_phy_init(dwc->usb2_phy);
 972         usb_phy_init(dwc->usb3_phy);
 973         ret = phy_init(dwc->usb2_generic_phy);
 974         if (ret < 0)
 975                 goto err0a;
 976
 977         ret = phy_init(dwc->usb3_generic_phy);
 978         if (ret < 0) {
 979                 phy_exit(dwc->usb2_generic_phy);
 980                 goto err0a;
 981         }
 982
 983         ret = dwc3_core_soft_reset(dwc);
 984         if (ret)
 985                 goto err1;
 986
 987         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
 988             !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
 989                 if (!dwc->dis_u3_susphy_quirk) {
 990                         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 991                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 992                         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 993                 }
 994
 995                 if (!dwc->dis_u2_susphy_quirk) {
 996                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 997                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 998                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 999                 }
1000         }
1001
1002         dwc3_core_setup_global_control(dwc);
1003         dwc3_core_num_eps(dwc);
1004
1005         ret = dwc3_setup_scratch_buffers(dwc);
1006         if (ret)
1007                 goto err1;
1008
1009         /* Adjust Frame Length */
1010         dwc3_frame_length_adjustment(dwc);
1011
1012         dwc3_set_incr_burst_type(dwc);
1013
1014         usb_phy_set_suspend(dwc->usb2_phy, 0);
1015         usb_phy_set_suspend(dwc->usb3_phy, 0);
1016         ret = phy_power_on(dwc->usb2_generic_phy);
1017         if (ret < 0)
1018                 goto err2;
1019
1020         ret = phy_power_on(dwc->usb3_generic_phy);
1021         if (ret < 0)
1022                 goto err3;
1023
1024         ret = dwc3_event_buffers_setup(dwc);
1025         if (ret) {
1026                 dev_err(dwc->dev, "failed to setup event buffers\n");
1027                 goto err4;
1028         }
1029
1030         /*
1031          * ENDXFER polling is available on version 3.10a and later of
1032          * the DWC_usb3 controller. It is NOT available in the
1033          * DWC_usb31 controller.
1034          */
1035         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1036                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1037                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1038                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1039         }
1040
1041         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1042                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1043
1044                 /*
1045                  * Enable hardware control of sending remote wakeup
1046                  * in HS when the device is in the L1 state.
1047                  */
1048                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1049                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1050
1051                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1052                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1053
1054                 if (dwc->parkmode_disable_ss_quirk)
1055                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1056
1057                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1058         }
1059
1060         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1061             dwc->dr_mode == USB_DR_MODE_OTG) {
1062                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1063
1064                 /*
1065                  * Enable Auto retry Feature to make the controller operating in
1066                  * Host mode on seeing transaction errors(CRC errors or internal
1067                  * overrun scenerios) on IN transfers to reply to the device
1068                  * with a non-terminating retry ACK (i.e, an ACK transcation
1069                  * packet with Retry=1 & Nump != 0)
1070                  */
1071                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1072
1073                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1074         }
1075
1076         /*
1077          * Must config both number of packets and max burst settings to enable
1078          * RX and/or TX threshold.
1079          */
1080         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1081                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1082                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1083                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1084                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1085
1086                 if (rx_thr_num && rx_maxburst) {
1087                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1088                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1089
1090                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1091                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1092
1093                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1094                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1095
1096                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1097                 }
1098
1099                 if (tx_thr_num && tx_maxburst) {
1100                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1101                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1102
1103                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1104                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1105
1106                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1107                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1108
1109                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1110                 }
1111         }
1112
1113         return 0;
1114
1115 err4:
1116         phy_power_off(dwc->usb3_generic_phy);
1117
1118 err3:
1119         phy_power_off(dwc->usb2_generic_phy);
1120
1121 err2:
1122         usb_phy_set_suspend(dwc->usb2_phy, 1);
1123         usb_phy_set_suspend(dwc->usb3_phy, 1);
1124
1125 err1:
1126         usb_phy_shutdown(dwc->usb2_phy);
1127         usb_phy_shutdown(dwc->usb3_phy);
1128         phy_exit(dwc->usb2_generic_phy);
1129         phy_exit(dwc->usb3_generic_phy);
1130
1131 err0a:
1132         dwc3_ulpi_exit(dwc);
1133
1134 err0:
1135         return ret;
1136 }
1137
1138 static int dwc3_core_get_phy(struct dwc3 *dwc)
1139 {
1140         struct device           *dev = dwc->dev;
1141         struct device_node      *node = dev->of_node;
1142         int ret;
1143
1144         if (node) {
1145                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1146                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1147         } else {
1148                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1149                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1150         }
1151
1152         if (IS_ERR(dwc->usb2_phy)) {
1153                 ret = PTR_ERR(dwc->usb2_phy);
1154                 if (ret == -ENXIO || ret == -ENODEV) {
1155                         dwc->usb2_phy = NULL;
1156                 } else if (ret == -EPROBE_DEFER) {
1157                         return ret;
1158                 } else {
1159                         dev_err(dev, "no usb2 phy configured\n");
1160                         return ret;
1161                 }
1162         }
1163
1164         if (IS_ERR(dwc->usb3_phy)) {
1165                 ret = PTR_ERR(dwc->usb3_phy);
1166                 if (ret == -ENXIO || ret == -ENODEV) {
1167                         dwc->usb3_phy = NULL;
1168                 } else if (ret == -EPROBE_DEFER) {
1169                         return ret;
1170                 } else {
1171                         dev_err(dev, "no usb3 phy configured\n");
1172                         return ret;
1173                 }
1174         }
1175
1176         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1177         if (IS_ERR(dwc->usb2_generic_phy)) {
1178                 ret = PTR_ERR(dwc->usb2_generic_phy);
1179                 if (ret == -ENOSYS || ret == -ENODEV) {
1180                         dwc->usb2_generic_phy = NULL;
1181                 } else if (ret == -EPROBE_DEFER) {
1182                         return ret;
1183                 } else {
1184                         dev_err(dev, "no usb2 phy configured\n");
1185                         return ret;
1186                 }
1187         }
1188
1189         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1190         if (IS_ERR(dwc->usb3_generic_phy)) {
1191                 ret = PTR_ERR(dwc->usb3_generic_phy);
1192                 if (ret == -ENOSYS || ret == -ENODEV) {
1193                         dwc->usb3_generic_phy = NULL;
1194                 } else if (ret == -EPROBE_DEFER) {
1195                         return ret;
1196                 } else {
1197                         dev_err(dev, "no usb3 phy configured\n");
1198                         return ret;
1199                 }
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int dwc3_core_init_mode(struct dwc3 *dwc)
1206 {
1207         struct device *dev = dwc->dev;
1208         int ret;
1209
1210         switch (dwc->dr_mode) {
1211         case USB_DR_MODE_PERIPHERAL:
1212                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1213
1214                 if (dwc->usb2_phy)
1215                         otg_set_vbus(dwc->usb2_phy->otg, false);
1216                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1217                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1218
1219                 ret = dwc3_gadget_init(dwc);
1220                 if (ret) {
1221                         if (ret != -EPROBE_DEFER)
1222                                 dev_err(dev, "failed to initialize gadget\n");
1223                         return ret;
1224                 }
1225                 break;
1226         case USB_DR_MODE_HOST:
1227                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1228
1229                 if (dwc->usb2_phy)
1230                         otg_set_vbus(dwc->usb2_phy->otg, true);
1231                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1232                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1233
1234                 ret = dwc3_host_init(dwc);
1235                 if (ret) {
1236                         if (ret != -EPROBE_DEFER)
1237                                 dev_err(dev, "failed to initialize host\n");
1238                         return ret;
1239                 }
1240                 break;
1241         case USB_DR_MODE_OTG:
1242                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1243                 ret = dwc3_drd_init(dwc);
1244                 if (ret) {
1245                         if (ret != -EPROBE_DEFER)
1246                                 dev_err(dev, "failed to initialize dual-role\n");
1247                         return ret;
1248                 }
1249                 break;
1250         default:
1251                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1252                 return -EINVAL;
1253         }
1254
1255         return 0;
1256 }
1257
1258 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1259 {
1260         switch (dwc->dr_mode) {
1261         case USB_DR_MODE_PERIPHERAL:
1262                 dwc3_gadget_exit(dwc);
1263                 break;
1264         case USB_DR_MODE_HOST:
1265                 dwc3_host_exit(dwc);
1266                 break;
1267         case USB_DR_MODE_OTG:
1268                 dwc3_drd_exit(dwc);
1269                 break;
1270         default:
1271                 /* do nothing */
1272                 break;
1273         }
1274
1275         /* de-assert DRVVBUS for HOST and OTG mode */
1276         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1277 }
1278
1279 static void dwc3_get_properties(struct dwc3 *dwc)
1280 {
1281         struct device           *dev = dwc->dev;
1282         u8                      lpm_nyet_threshold;
1283         u8                      tx_de_emphasis;
1284         u8                      hird_threshold;
1285         u8                      rx_thr_num_pkt_prd = 0;
1286         u8                      rx_max_burst_prd = 0;
1287         u8                      tx_thr_num_pkt_prd = 0;
1288         u8                      tx_max_burst_prd = 0;
1289
1290         /* default to highest possible threshold */
1291         lpm_nyet_threshold = 0xf;
1292
1293         /* default to -3.5dB de-emphasis */
1294         tx_de_emphasis = 1;
1295
1296         /*
1297          * default to assert utmi_sleep_n and use maximum allowed HIRD
1298          * threshold value of 0b1100
1299          */
1300         hird_threshold = 12;
1301
1302         dwc->maximum_speed = usb_get_maximum_speed(dev);
1303         dwc->dr_mode = usb_get_dr_mode(dev);
1304         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1305
1306         dwc->sysdev_is_parent = device_property_read_bool(dev,
1307                                 "linux,sysdev_is_parent");
1308         if (dwc->sysdev_is_parent)
1309                 dwc->sysdev = dwc->dev->parent;
1310         else
1311                 dwc->sysdev = dwc->dev;
1312
1313         dwc->has_lpm_erratum = device_property_read_bool(dev,
1314                                 "snps,has-lpm-erratum");
1315         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1316                                 &lpm_nyet_threshold);
1317         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1318                                 "snps,is-utmi-l1-suspend");
1319         device_property_read_u8(dev, "snps,hird-threshold",
1320                                 &hird_threshold);
1321         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1322                                 "snps,dis-start-transfer-quirk");
1323         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1324                                 "snps,usb3_lpm_capable");
1325         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1326                                 "snps,usb2-lpm-disable");
1327         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1328                                 "snps,usb2-gadget-lpm-disable");
1329         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1330                                 &rx_thr_num_pkt_prd);
1331         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1332                                 &rx_max_burst_prd);
1333         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1334                                 &tx_thr_num_pkt_prd);
1335         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1336                                 &tx_max_burst_prd);
1337
1338         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1339                                 "snps,disable_scramble_quirk");
1340         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1341                                 "snps,u2exit_lfps_quirk");
1342         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1343                                 "snps,u2ss_inp3_quirk");
1344         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1345                                 "snps,req_p1p2p3_quirk");
1346         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1347                                 "snps,del_p1p2p3_quirk");
1348         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1349                                 "snps,del_phy_power_chg_quirk");
1350         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1351                                 "snps,lfps_filter_quirk");
1352         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1353                                 "snps,rx_detect_poll_quirk");
1354         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1355                                 "snps,dis_u3_susphy_quirk");
1356         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1357                                 "snps,dis_u2_susphy_quirk");
1358         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1359                                 "snps,dis_enblslpm_quirk");
1360         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1361                                 "snps,dis-u1-entry-quirk");
1362         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1363                                 "snps,dis-u2-entry-quirk");
1364         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1365                                 "snps,dis_rxdet_inp3_quirk");
1366         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1367                                 "snps,dis-u2-freeclk-exists-quirk");
1368         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1369                                 "snps,dis-del-phy-power-chg-quirk");
1370         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1371                                 "snps,dis-tx-ipgap-linecheck-quirk");
1372         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1373                                 "snps,parkmode-disable-ss-quirk");
1374
1375         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1376                                 "snps,tx_de_emphasis_quirk");
1377         device_property_read_u8(dev, "snps,tx_de_emphasis",
1378                                 &tx_de_emphasis);
1379         device_property_read_string(dev, "snps,hsphy_interface",
1380                                     &dwc->hsphy_interface);
1381         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1382                                  &dwc->fladj);
1383
1384         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1385                                 "snps,dis_metastability_quirk");
1386
1387         dwc->dis_split_quirk = device_property_read_bool(dev,
1388                                 "snps,dis-split-quirk");
1389
1390         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1391         dwc->tx_de_emphasis = tx_de_emphasis;
1392
1393         dwc->hird_threshold = hird_threshold;
1394
1395         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1396         dwc->rx_max_burst_prd = rx_max_burst_prd;
1397
1398         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1399         dwc->tx_max_burst_prd = tx_max_burst_prd;
1400
1401         dwc->imod_interval = 0;
1402 }
1403
1404 /* check whether the core supports IMOD */
1405 bool dwc3_has_imod(struct dwc3 *dwc)
1406 {
1407         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1408                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1409                 DWC3_IP_IS(DWC32);
1410 }
1411
1412 static void dwc3_check_params(struct dwc3 *dwc)
1413 {
1414         struct device *dev = dwc->dev;
1415         unsigned int hwparam_gen =
1416                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1417
1418         /* Check for proper value of imod_interval */
1419         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1420                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1421                 dwc->imod_interval = 0;
1422         }
1423
1424         /*
1425          * Workaround for STAR 9000961433 which affects only version
1426          * 3.00a of the DWC_usb3 core. This prevents the controller
1427          * interrupt from being masked while handling events. IMOD
1428          * allows us to work around this issue. Enable it for the
1429          * affected version.
1430          */
1431         if (!dwc->imod_interval &&
1432             DWC3_VER_IS(DWC3, 300A))
1433                 dwc->imod_interval = 1;
1434
1435         /* Check the maximum_speed parameter */
1436         switch (dwc->maximum_speed) {
1437         case USB_SPEED_LOW:
1438         case USB_SPEED_FULL:
1439         case USB_SPEED_HIGH:
1440                 break;
1441         case USB_SPEED_SUPER:
1442                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1443                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1444                 break;
1445         case USB_SPEED_SUPER_PLUS:
1446                 if ((DWC3_IP_IS(DWC32) &&
1447                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1448                     (!DWC3_IP_IS(DWC32) &&
1449                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1450                         dev_warn(dev, "UDC doesn't support SSP\n");
1451                 break;
1452         default:
1453                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1454                         dwc->maximum_speed);
1455                 fallthrough;
1456         case USB_SPEED_UNKNOWN:
1457                 switch (hwparam_gen) {
1458                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1459                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1460                         break;
1461                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1462                         if (DWC3_IP_IS(DWC32))
1463                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1464                         else
1465                                 dwc->maximum_speed = USB_SPEED_SUPER;
1466                         break;
1467                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1468                         dwc->maximum_speed = USB_SPEED_HIGH;
1469                         break;
1470                 default:
1471                         dwc->maximum_speed = USB_SPEED_SUPER;
1472                         break;
1473                 }
1474                 break;
1475         }
1476 }
1477
1478 static int dwc3_probe(struct platform_device *pdev)
1479 {
1480         struct device           *dev = &pdev->dev;
1481         struct resource         *res, dwc_res;
1482         struct dwc3             *dwc;
1483
1484         int                     ret;
1485
1486         void __iomem            *regs;
1487
1488         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1489         if (!dwc)
1490                 return -ENOMEM;
1491
1492         dwc->dev = dev;
1493
1494         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495         if (!res) {
1496                 dev_err(dev, "missing memory resource\n");
1497                 return -ENODEV;
1498         }
1499
1500         dwc->xhci_resources[0].start = res->start;
1501         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1502                                         DWC3_XHCI_REGS_END;
1503         dwc->xhci_resources[0].flags = res->flags;
1504         dwc->xhci_resources[0].name = res->name;
1505
1506         /*
1507          * Request memory region but exclude xHCI regs,
1508          * since it will be requested by the xhci-plat driver.
1509          */
1510         dwc_res = *res;
1511         dwc_res.start += DWC3_GLOBALS_REGS_START;
1512
1513         regs = devm_ioremap_resource(dev, &dwc_res);
1514         if (IS_ERR(regs))
1515                 return PTR_ERR(regs);
1516
1517         dwc->regs       = regs;
1518         dwc->regs_size  = resource_size(&dwc_res);
1519
1520         dwc3_get_properties(dwc);
1521
1522         dwc->reset = devm_reset_control_array_get(dev, true, true);
1523         if (IS_ERR(dwc->reset))
1524                 return PTR_ERR(dwc->reset);
1525
1526         if (dev->of_node) {
1527                 ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1528                 if (ret == -EPROBE_DEFER)
1529                         return ret;
1530                 /*
1531                  * Clocks are optional, but new DT platforms should support all
1532                  * clocks as required by the DT-binding.
1533                  */
1534                 if (ret < 0)
1535                         dwc->num_clks = 0;
1536                 else
1537                         dwc->num_clks = ret;
1538
1539         }
1540
1541         ret = reset_control_deassert(dwc->reset);
1542         if (ret)
1543                 return ret;
1544
1545         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1546         if (ret)
1547                 goto assert_reset;
1548
1549         if (!dwc3_core_is_valid(dwc)) {
1550                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1551                 ret = -ENODEV;
1552                 goto disable_clks;
1553         }
1554
1555         platform_set_drvdata(pdev, dwc);
1556         dwc3_cache_hwparams(dwc);
1557
1558         spin_lock_init(&dwc->lock);
1559         mutex_init(&dwc->mutex);
1560
1561         pm_runtime_set_active(dev);
1562         pm_runtime_use_autosuspend(dev);
1563         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1564         pm_runtime_enable(dev);
1565         ret = pm_runtime_get_sync(dev);
1566         if (ret < 0)
1567                 goto err1;
1568
1569         pm_runtime_forbid(dev);
1570
1571         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1572         if (ret) {
1573                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1574                 ret = -ENOMEM;
1575                 goto err2;
1576         }
1577
1578         ret = dwc3_get_dr_mode(dwc);
1579         if (ret)
1580                 goto err3;
1581
1582         ret = dwc3_alloc_scratch_buffers(dwc);
1583         if (ret)
1584                 goto err3;
1585
1586         ret = dwc3_core_init(dwc);
1587         if (ret) {
1588                 if (ret != -EPROBE_DEFER)
1589                         dev_err(dev, "failed to initialize core: %d\n", ret);
1590                 goto err4;
1591         }
1592
1593         dwc3_check_params(dwc);
1594         dwc3_debugfs_init(dwc);
1595
1596         ret = dwc3_core_init_mode(dwc);
1597         if (ret)
1598                 goto err5;
1599
1600         pm_runtime_put(dev);
1601
1602         return 0;
1603
1604 err5:
1605         dwc3_debugfs_exit(dwc);
1606         dwc3_event_buffers_cleanup(dwc);
1607
1608         usb_phy_set_suspend(dwc->usb2_phy, 1);
1609         usb_phy_set_suspend(dwc->usb3_phy, 1);
1610         phy_power_off(dwc->usb2_generic_phy);
1611         phy_power_off(dwc->usb3_generic_phy);
1612
1613         usb_phy_shutdown(dwc->usb2_phy);
1614         usb_phy_shutdown(dwc->usb3_phy);
1615         phy_exit(dwc->usb2_generic_phy);
1616         phy_exit(dwc->usb3_generic_phy);
1617
1618         dwc3_ulpi_exit(dwc);
1619
1620 err4:
1621         dwc3_free_scratch_buffers(dwc);
1622
1623 err3:
1624         dwc3_free_event_buffers(dwc);
1625
1626 err2:
1627         pm_runtime_allow(&pdev->dev);
1628
1629 err1:
1630         pm_runtime_put_sync(&pdev->dev);
1631         pm_runtime_disable(&pdev->dev);
1632
1633 disable_clks:
1634         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1635 assert_reset:
1636         reset_control_assert(dwc->reset);
1637
1638         return ret;
1639 }
1640
1641 static int dwc3_remove(struct platform_device *pdev)
1642 {
1643         struct dwc3     *dwc = platform_get_drvdata(pdev);
1644
1645         pm_runtime_get_sync(&pdev->dev);
1646
1647         dwc3_core_exit_mode(dwc);
1648         dwc3_debugfs_exit(dwc);
1649
1650         dwc3_core_exit(dwc);
1651         dwc3_ulpi_exit(dwc);
1652
1653         pm_runtime_disable(&pdev->dev);
1654         pm_runtime_put_noidle(&pdev->dev);
1655         pm_runtime_set_suspended(&pdev->dev);
1656
1657         dwc3_free_event_buffers(dwc);
1658         dwc3_free_scratch_buffers(dwc);
1659
1660         return 0;
1661 }
1662
1663 #ifdef CONFIG_PM
1664 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1665 {
1666         int ret;
1667
1668         ret = reset_control_deassert(dwc->reset);
1669         if (ret)
1670                 return ret;
1671
1672         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1673         if (ret)
1674                 goto assert_reset;
1675
1676         ret = dwc3_core_init(dwc);
1677         if (ret)
1678                 goto disable_clks;
1679
1680         return 0;
1681
1682 disable_clks:
1683         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1684 assert_reset:
1685         reset_control_assert(dwc->reset);
1686
1687         return ret;
1688 }
1689
1690 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1691 {
1692         unsigned long   flags;
1693         u32 reg;
1694
1695         switch (dwc->current_dr_role) {
1696         case DWC3_GCTL_PRTCAP_DEVICE:
1697                 if (pm_runtime_suspended(dwc->dev))
1698                         break;
1699                 spin_lock_irqsave(&dwc->lock, flags);
1700                 dwc3_gadget_suspend(dwc);
1701                 spin_unlock_irqrestore(&dwc->lock, flags);
1702                 synchronize_irq(dwc->irq_gadget);
1703                 dwc3_core_exit(dwc);
1704                 break;
1705         case DWC3_GCTL_PRTCAP_HOST:
1706                 if (!PMSG_IS_AUTO(msg)) {
1707                         dwc3_core_exit(dwc);
1708                         break;
1709                 }
1710
1711                 /* Let controller to suspend HSPHY before PHY driver suspends */
1712                 if (dwc->dis_u2_susphy_quirk ||
1713                     dwc->dis_enblslpm_quirk) {
1714                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1715                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1716                                 DWC3_GUSB2PHYCFG_SUSPHY;
1717                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1718
1719                         /* Give some time for USB2 PHY to suspend */
1720                         usleep_range(5000, 6000);
1721                 }
1722
1723                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1724                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1725                 break;
1726         case DWC3_GCTL_PRTCAP_OTG:
1727                 /* do nothing during runtime_suspend */
1728                 if (PMSG_IS_AUTO(msg))
1729                         break;
1730
1731                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1732                         spin_lock_irqsave(&dwc->lock, flags);
1733                         dwc3_gadget_suspend(dwc);
1734                         spin_unlock_irqrestore(&dwc->lock, flags);
1735                         synchronize_irq(dwc->irq_gadget);
1736                 }
1737
1738                 dwc3_otg_exit(dwc);
1739                 dwc3_core_exit(dwc);
1740                 break;
1741         default:
1742                 /* do nothing */
1743                 break;
1744         }
1745
1746         return 0;
1747 }
1748
1749 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1750 {
1751         unsigned long   flags;
1752         int             ret;
1753         u32             reg;
1754
1755         switch (dwc->current_dr_role) {
1756         case DWC3_GCTL_PRTCAP_DEVICE:
1757                 ret = dwc3_core_init_for_resume(dwc);
1758                 if (ret)
1759                         return ret;
1760
1761                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1762                 spin_lock_irqsave(&dwc->lock, flags);
1763                 dwc3_gadget_resume(dwc);
1764                 spin_unlock_irqrestore(&dwc->lock, flags);
1765                 break;
1766         case DWC3_GCTL_PRTCAP_HOST:
1767                 if (!PMSG_IS_AUTO(msg)) {
1768                         ret = dwc3_core_init_for_resume(dwc);
1769                         if (ret)
1770                                 return ret;
1771                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1772                         break;
1773                 }
1774                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1775                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1776                 if (dwc->dis_u2_susphy_quirk)
1777                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1778
1779                 if (dwc->dis_enblslpm_quirk)
1780                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1781
1782                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1783
1784                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1785                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1786                 break;
1787         case DWC3_GCTL_PRTCAP_OTG:
1788                 /* nothing to do on runtime_resume */
1789                 if (PMSG_IS_AUTO(msg))
1790                         break;
1791
1792                 ret = dwc3_core_init_for_resume(dwc);
1793                 if (ret)
1794                         return ret;
1795
1796                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1797
1798                 dwc3_otg_init(dwc);
1799                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1800                         dwc3_otg_host_init(dwc);
1801                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1802                         spin_lock_irqsave(&dwc->lock, flags);
1803                         dwc3_gadget_resume(dwc);
1804                         spin_unlock_irqrestore(&dwc->lock, flags);
1805                 }
1806
1807                 break;
1808         default:
1809                 /* do nothing */
1810                 break;
1811         }
1812
1813         return 0;
1814 }
1815
1816 static int dwc3_runtime_checks(struct dwc3 *dwc)
1817 {
1818         switch (dwc->current_dr_role) {
1819         case DWC3_GCTL_PRTCAP_DEVICE:
1820                 if (dwc->connected)
1821                         return -EBUSY;
1822                 break;
1823         case DWC3_GCTL_PRTCAP_HOST:
1824         default:
1825                 /* do nothing */
1826                 break;
1827         }
1828
1829         return 0;
1830 }
1831
1832 static int dwc3_runtime_suspend(struct device *dev)
1833 {
1834         struct dwc3     *dwc = dev_get_drvdata(dev);
1835         int             ret;
1836
1837         if (dwc3_runtime_checks(dwc))
1838                 return -EBUSY;
1839
1840         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1841         if (ret)
1842                 return ret;
1843
1844         device_init_wakeup(dev, true);
1845
1846         return 0;
1847 }
1848
1849 static int dwc3_runtime_resume(struct device *dev)
1850 {
1851         struct dwc3     *dwc = dev_get_drvdata(dev);
1852         int             ret;
1853
1854         device_init_wakeup(dev, false);
1855
1856         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1857         if (ret)
1858                 return ret;
1859
1860         switch (dwc->current_dr_role) {
1861         case DWC3_GCTL_PRTCAP_DEVICE:
1862                 dwc3_gadget_process_pending_events(dwc);
1863                 break;
1864         case DWC3_GCTL_PRTCAP_HOST:
1865         default:
1866                 /* do nothing */
1867                 break;
1868         }
1869
1870         pm_runtime_mark_last_busy(dev);
1871
1872         return 0;
1873 }
1874
1875 static int dwc3_runtime_idle(struct device *dev)
1876 {
1877         struct dwc3     *dwc = dev_get_drvdata(dev);
1878
1879         switch (dwc->current_dr_role) {
1880         case DWC3_GCTL_PRTCAP_DEVICE:
1881                 if (dwc3_runtime_checks(dwc))
1882                         return -EBUSY;
1883                 break;
1884         case DWC3_GCTL_PRTCAP_HOST:
1885         default:
1886                 /* do nothing */
1887                 break;
1888         }
1889
1890         pm_runtime_mark_last_busy(dev);
1891         pm_runtime_autosuspend(dev);
1892
1893         return 0;
1894 }
1895 #endif /* CONFIG_PM */
1896
1897 #ifdef CONFIG_PM_SLEEP
1898 static int dwc3_suspend(struct device *dev)
1899 {
1900         struct dwc3     *dwc = dev_get_drvdata(dev);
1901         int             ret;
1902
1903         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1904         if (ret)
1905                 return ret;
1906
1907         pinctrl_pm_select_sleep_state(dev);
1908
1909         return 0;
1910 }
1911
1912 static int dwc3_resume(struct device *dev)
1913 {
1914         struct dwc3     *dwc = dev_get_drvdata(dev);
1915         int             ret;
1916
1917         pinctrl_pm_select_default_state(dev);
1918
1919         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1920         if (ret)
1921                 return ret;
1922
1923         pm_runtime_disable(dev);
1924         pm_runtime_set_active(dev);
1925         pm_runtime_enable(dev);
1926
1927         return 0;
1928 }
1929
1930 static void dwc3_complete(struct device *dev)
1931 {
1932         struct dwc3     *dwc = dev_get_drvdata(dev);
1933         u32             reg;
1934
1935         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1936                         dwc->dis_split_quirk) {
1937                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1938                 reg |= DWC3_GUCTL3_SPLITDISABLE;
1939                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1940         }
1941 }
1942 #else
1943 #define dwc3_complete NULL
1944 #endif /* CONFIG_PM_SLEEP */
1945
1946 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1947         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1948         .complete = dwc3_complete,
1949         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1950                         dwc3_runtime_idle)
1951 };
1952
1953 #ifdef CONFIG_OF
1954 static const struct of_device_id of_dwc3_match[] = {
1955         {
1956                 .compatible = "snps,dwc3"
1957         },
1958         {
1959                 .compatible = "synopsys,dwc3"
1960         },
1961         { },
1962 };
1963 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1964 #endif
1965
1966 #ifdef CONFIG_ACPI
1967
1968 #define ACPI_ID_INTEL_BSW       "808622B7"
1969
1970 static const struct acpi_device_id dwc3_acpi_match[] = {
1971         { ACPI_ID_INTEL_BSW, 0 },
1972         { },
1973 };
1974 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1975 #endif
1976
1977 static struct platform_driver dwc3_driver = {
1978         .probe          = dwc3_probe,
1979         .remove         = dwc3_remove,
1980         .driver         = {
1981                 .name   = "dwc3",
1982                 .of_match_table = of_match_ptr(of_dwc3_match),
1983                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1984                 .pm     = &dwc3_dev_pm_ops,
1985         },
1986 };
1987
1988 module_platform_driver(dwc3_driver);
1989
1990 MODULE_ALIAS("platform:dwc3");
1991 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1992 MODULE_LICENSE("GPL v2");
1993 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");