drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * dwc_usb31 does not support OTG mode. If the controller
  84                  * supports DRD but the dr_mode is not specified or set to OTG,
  85                  * then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc))
  88                         mode = USB_DR_MODE_PERIPHERAL;
  89         }
  90
  91         if (mode != dwc->dr_mode) {
  92                 dev_warn(dev,
  93                          "Configuration mismatch. dr_mode forced to %s\n",
  94                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  95
  96                 dwc->dr_mode = mode;
  97         }
  98
  99         return 0;
 100 }
 101
 102 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 103 {
 104         u32 reg;
 105
 106         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 107         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 108         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 109         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 110
 111         dwc->current_dr_role = mode;
 112 }
 113
 114 static void __dwc3_set_mode(struct work_struct *work)
 115 {
 116         struct dwc3 *dwc = work_to_dwc(work);
 117         unsigned long flags;
 118         int ret;
 119
 120         if (dwc->dr_mode != USB_DR_MODE_OTG)
 121                 return;
 122
 123         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 124                 dwc3_otg_update(dwc, 0);
 125
 126         if (!dwc->desired_dr_role)
 127                 return;
 128
 129         if (dwc->desired_dr_role == dwc->current_dr_role)
 130                 return;
 131
 132         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 133                 return;
 134
 135         switch (dwc->current_dr_role) {
 136         case DWC3_GCTL_PRTCAP_HOST:
 137                 dwc3_host_exit(dwc);
 138                 break;
 139         case DWC3_GCTL_PRTCAP_DEVICE:
 140                 dwc3_gadget_exit(dwc);
 141                 dwc3_event_buffers_cleanup(dwc);
 142                 break;
 143         case DWC3_GCTL_PRTCAP_OTG:
 144                 dwc3_otg_exit(dwc);
 145                 spin_lock_irqsave(&dwc->lock, flags);
 146                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 147                 spin_unlock_irqrestore(&dwc->lock, flags);
 148                 dwc3_otg_update(dwc, 1);
 149                 break;
 150         default:
 151                 break;
 152         }
 153
 154         spin_lock_irqsave(&dwc->lock, flags);
 155
 156         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 157
 158         spin_unlock_irqrestore(&dwc->lock, flags);
 159
 160         switch (dwc->desired_dr_role) {
 161         case DWC3_GCTL_PRTCAP_HOST:
 162                 ret = dwc3_host_init(dwc);
 163                 if (ret) {
 164                         dev_err(dwc->dev, "failed to initialize host\n");
 165                 } else {
 166                         if (dwc->usb2_phy)
 167                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 168                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 169                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_calibrate(dwc->usb2_generic_phy);
 171                 }
 172                 break;
 173         case DWC3_GCTL_PRTCAP_DEVICE:
 174                 dwc3_event_buffers_setup(dwc);
 175
 176                 if (dwc->usb2_phy)
 177                         otg_set_vbus(dwc->usb2_phy->otg, false);
 178                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 179                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 180
 181                 ret = dwc3_gadget_init(dwc);
 182                 if (ret)
 183                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 184                 break;
 185         case DWC3_GCTL_PRTCAP_OTG:
 186                 dwc3_otg_init(dwc);
 187                 dwc3_otg_update(dwc, 0);
 188                 break;
 189         default:
 190                 break;
 191         }
 192
 193 }
 194
 195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 196 {
 197         unsigned long flags;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         dwc->desired_dr_role = mode;
 201         spin_unlock_irqrestore(&dwc->lock, flags);
 202
 203         queue_work(system_freezable_wq, &dwc->drd_work);
 204 }
 205
 206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 207 {
 208         struct dwc3             *dwc = dep->dwc;
 209         u32                     reg;
 210
 211         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 212                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 213                         DWC3_GDBGFIFOSPACE_TYPE(type));
 214
 215         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 216
 217         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 218 }
 219
 220 /**
 221  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 222  * @dwc: pointer to our context structure
 223  */
 224 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 225 {
 226         u32             reg;
 227         int             retries = 1000;
 228         int             ret;
 229
 230         usb_phy_init(dwc->usb2_phy);
 231         usb_phy_init(dwc->usb3_phy);
 232         ret = phy_init(dwc->usb2_generic_phy);
 233         if (ret < 0)
 234                 return ret;
 235
 236         ret = phy_init(dwc->usb3_generic_phy);
 237         if (ret < 0) {
 238                 phy_exit(dwc->usb2_generic_phy);
 239                 return ret;
 240         }
 241
 242         /*
 243          * We're resetting only the device side because, if we're in host mode,
 244          * XHCI driver will reset the host block. If dwc3 was configured for
 245          * host-only mode, then we can return early.
 246          */
 247         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 248                 return 0;
 249
 250         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 251         reg |= DWC3_DCTL_CSFTRST;
 252         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 253
 254         do {
 255                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 256                 if (!(reg & DWC3_DCTL_CSFTRST))
 257                         goto done;
 258
 259                 udelay(1);
 260         } while (--retries);
 261
 262         phy_exit(dwc->usb3_generic_phy);
 263         phy_exit(dwc->usb2_generic_phy);
 264
 265         return -ETIMEDOUT;
 266
 267 done:
 268         /*
 269          * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
 270          * we must wait at least 50ms before accessing the PHY domain
 271          * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
 272          */
 273         if (dwc3_is_usb31(dwc))
 274                 msleep(50);
 275
 276         return 0;
 277 }
 278
 279 static const struct clk_bulk_data dwc3_core_clks[] = {
 280         { .id = "ref" },
 281         { .id = "bus_early" },
 282         { .id = "suspend" },
 283 };
 284
 285 /*
 286  * dwc3_frame_length_adjustment - Adjusts frame length if required
 287  * @dwc3: Pointer to our controller context structure
 288  */
 289 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 290 {
 291         u32 reg;
 292         u32 dft;
 293
 294         if (dwc->revision < DWC3_REVISION_250A)
 295                 return;
 296
 297         if (dwc->fladj == 0)
 298                 return;
 299
 300         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 301         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 302         if (dft != dwc->fladj) {
 303                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 304                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 305                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 306         }
 307 }
 308
 309 /**
 310  * dwc3_free_one_event_buffer - Frees one event buffer
 311  * @dwc: Pointer to our controller context structure
 312  * @evt: Pointer to event buffer to be freed
 313  */
 314 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 315                 struct dwc3_event_buffer *evt)
 316 {
 317         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 318 }
 319
 320 /**
 321  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 322  * @dwc: Pointer to our controller context structure
 323  * @length: size of the event buffer
 324  *
 325  * Returns a pointer to the allocated event buffer structure on success
 326  * otherwise ERR_PTR(errno).
 327  */
 328 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 329                 unsigned length)
 330 {
 331         struct dwc3_event_buffer        *evt;
 332
 333         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 334         if (!evt)
 335                 return ERR_PTR(-ENOMEM);
 336
 337         evt->dwc        = dwc;
 338         evt->length     = length;
 339         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 340         if (!evt->cache)
 341                 return ERR_PTR(-ENOMEM);
 342
 343         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 344                         &evt->dma, GFP_KERNEL);
 345         if (!evt->buf)
 346                 return ERR_PTR(-ENOMEM);
 347
 348         return evt;
 349 }
 350
 351 /**
 352  * dwc3_free_event_buffers - frees all allocated event buffers
 353  * @dwc: Pointer to our controller context structure
 354  */
 355 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 356 {
 357         struct dwc3_event_buffer        *evt;
 358
 359         evt = dwc->ev_buf;
 360         if (evt)
 361                 dwc3_free_one_event_buffer(dwc, evt);
 362 }
 363
 364 /**
 365  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 366  * @dwc: pointer to our controller context structure
 367  * @length: size of event buffer
 368  *
 369  * Returns 0 on success otherwise negative errno. In the error case, dwc
 370  * may contain some buffers allocated but not all which were requested.
 371  */
 372 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 373 {
 374         struct dwc3_event_buffer *evt;
 375
 376         evt = dwc3_alloc_one_event_buffer(dwc, length);
 377         if (IS_ERR(evt)) {
 378                 dev_err(dwc->dev, "can't allocate event buffer\n");
 379                 return PTR_ERR(evt);
 380         }
 381         dwc->ev_buf = evt;
 382
 383         return 0;
 384 }
 385
 386 /**
 387  * dwc3_event_buffers_setup - setup our allocated event buffers
 388  * @dwc: pointer to our controller context structure
 389  *
 390  * Returns 0 on success otherwise negative errno.
 391  */
 392 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 393 {
 394         struct dwc3_event_buffer        *evt;
 395
 396         evt = dwc->ev_buf;
 397         evt->lpos = 0;
 398         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 399                         lower_32_bits(evt->dma));
 400         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 401                         upper_32_bits(evt->dma));
 402         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 403                         DWC3_GEVNTSIZ_SIZE(evt->length));
 404         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 405
 406         return 0;
 407 }
 408
 409 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 410 {
 411         struct dwc3_event_buffer        *evt;
 412
 413         evt = dwc->ev_buf;
 414
 415         evt->lpos = 0;
 416
 417         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 418         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 419         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 420                         | DWC3_GEVNTSIZ_SIZE(0));
 421         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 422 }
 423
 424 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 425 {
 426         if (!dwc->has_hibernation)
 427                 return 0;
 428
 429         if (!dwc->nr_scratch)
 430                 return 0;
 431
 432         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 433                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 434         if (!dwc->scratchbuf)
 435                 return -ENOMEM;
 436
 437         return 0;
 438 }
 439
 440 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 441 {
 442         dma_addr_t scratch_addr;
 443         u32 param;
 444         int ret;
 445
 446         if (!dwc->has_hibernation)
 447                 return 0;
 448
 449         if (!dwc->nr_scratch)
 450                 return 0;
 451
 452          /* should never fall here */
 453         if (!WARN_ON(dwc->scratchbuf))
 454                 return 0;
 455
 456         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 457                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 458                         DMA_BIDIRECTIONAL);
 459         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 460                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 461                 ret = -EFAULT;
 462                 goto err0;
 463         }
 464
 465         dwc->scratch_addr = scratch_addr;
 466
 467         param = lower_32_bits(scratch_addr);
 468
 469         ret = dwc3_send_gadget_generic_command(dwc,
 470                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 471         if (ret < 0)
 472                 goto err1;
 473
 474         param = upper_32_bits(scratch_addr);
 475
 476         ret = dwc3_send_gadget_generic_command(dwc,
 477                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 478         if (ret < 0)
 479                 goto err1;
 480
 481         return 0;
 482
 483 err1:
 484         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 485                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 486
 487 err0:
 488         return ret;
 489 }
 490
 491 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 492 {
 493         if (!dwc->has_hibernation)
 494                 return;
 495
 496         if (!dwc->nr_scratch)
 497                 return;
 498
 499          /* should never fall here */
 500         if (!WARN_ON(dwc->scratchbuf))
 501                 return;
 502
 503         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 504                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 505         kfree(dwc->scratchbuf);
 506 }
 507
 508 static void dwc3_core_num_eps(struct dwc3 *dwc)
 509 {
 510         struct dwc3_hwparams    *parms = &dwc->hwparams;
 511
 512         dwc->num_eps = DWC3_NUM_EPS(parms);
 513 }
 514
 515 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 516 {
 517         struct dwc3_hwparams    *parms = &dwc->hwparams;
 518
 519         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 520         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 521         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 522         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 523         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 524         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 525         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 526         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 527         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 528 }
 529
 530 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 531 {
 532         int intf;
 533         int ret = 0;
 534
 535         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 536
 537         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 538             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 539              dwc->hsphy_interface &&
 540              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 541                 ret = dwc3_ulpi_init(dwc);
 542
 543         return ret;
 544 }
 545
 546 /**
 547  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 548  * @dwc: Pointer to our controller context structure
 549  *
 550  * Returns 0 on success. The USB PHY interfaces are configured but not
 551  * initialized. The PHY interfaces and the PHYs get initialized together with
 552  * the core in dwc3_core_init.
 553  */
 554 static int dwc3_phy_setup(struct dwc3 *dwc)
 555 {
 556         u32 reg;
 557
 558         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 559
 560         /*
 561          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 562          * PHYs. Also, this bit is not supposed to be used in normal operation.
 563          */
 564         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 565
 566         /*
 567          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 568          * to '0' during coreConsultant configuration. So default value
 569          * will be '0' when the core is reset. Application needs to set it
 570          * to '1' after the core initialization is completed.
 571          */
 572         if (dwc->revision > DWC3_REVISION_194A)
 573                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 574
 575         if (dwc->u2ss_inp3_quirk)
 576                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 577
 578         if (dwc->dis_rxdet_inp3_quirk)
 579                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 580
 581         if (dwc->req_p1p2p3_quirk)
 582                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 583
 584         if (dwc->del_p1p2p3_quirk)
 585                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 586
 587         if (dwc->del_phy_power_chg_quirk)
 588                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 589
 590         if (dwc->lfps_filter_quirk)
 591                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 592
 593         if (dwc->rx_detect_poll_quirk)
 594                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 595
 596         if (dwc->tx_de_emphasis_quirk)
 597                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 598
 599         if (dwc->dis_u3_susphy_quirk)
 600                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 601
 602         if (dwc->dis_del_phy_power_chg_quirk)
 603                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 604
 605         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 606
 607         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 608
 609         /* Select the HS PHY interface */
 610         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 611         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 612                 if (dwc->hsphy_interface &&
 613                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 614                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 615                         break;
 616                 } else if (dwc->hsphy_interface &&
 617                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 618                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 619                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 620                 } else {
 621                         /* Relying on default value. */
 622                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 623                                 break;
 624                 }
 625                 /* FALLTHROUGH */
 626         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 627                 /* FALLTHROUGH */
 628         default:
 629                 break;
 630         }
 631
 632         switch (dwc->hsphy_mode) {
 633         case USBPHY_INTERFACE_MODE_UTMI:
 634                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 635                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 636                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 637                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 638                 break;
 639         case USBPHY_INTERFACE_MODE_UTMIW:
 640                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 641                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 642                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 643                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 644                 break;
 645         default:
 646                 break;
 647         }
 648
 649         /*
 650          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 651          * '0' during coreConsultant configuration. So default value will
 652          * be '0' when the core is reset. Application needs to set it to
 653          * '1' after the core initialization is completed.
 654          */
 655         if (dwc->revision > DWC3_REVISION_194A)
 656                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 657
 658         if (dwc->dis_u2_susphy_quirk)
 659                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 660
 661         if (dwc->dis_enblslpm_quirk)
 662                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 663
 664         if (dwc->dis_u2_freeclk_exists_quirk)
 665                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 666
 667         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 668
 669         return 0;
 670 }
 671
 672 static void dwc3_core_exit(struct dwc3 *dwc)
 673 {
 674         dwc3_event_buffers_cleanup(dwc);
 675
 676         usb_phy_set_suspend(dwc->usb2_phy, 1);
 677         usb_phy_set_suspend(dwc->usb3_phy, 1);
 678         phy_power_off(dwc->usb2_generic_phy);
 679         phy_power_off(dwc->usb3_generic_phy);
 680
 681         usb_phy_shutdown(dwc->usb2_phy);
 682         usb_phy_shutdown(dwc->usb3_phy);
 683         phy_exit(dwc->usb2_generic_phy);
 684         phy_exit(dwc->usb3_generic_phy);
 685
 686         clk_bulk_disable(dwc->num_clks, dwc->clks);
 687         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
 688         reset_control_assert(dwc->reset);
 689 }
 690
 691 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 692 {
 693         u32 reg;
 694
 695         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 696
 697         /* This should read as U3 followed by revision number */
 698         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 699                 /* Detected DWC_usb3 IP */
 700                 dwc->revision = reg;
 701         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 702                 /* Detected DWC_usb31 IP */
 703                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 704                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 705         } else {
 706                 return false;
 707         }
 708
 709         return true;
 710 }
 711
 712 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 713 {
 714         u32 hwparams4 = dwc->hwparams.hwparams4;
 715         u32 reg;
 716
 717         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 718         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 719
 720         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 721         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 722                 /**
 723                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 724                  * issue which would cause xHCI compliance tests to fail.
 725                  *
 726                  * Because of that we cannot enable clock gating on such
 727                  * configurations.
 728                  *
 729                  * Refers to:
 730                  *
 731                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 732                  * SOF/ITP Mode Used
 733                  */
 734                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 735                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 736                                 (dwc->revision >= DWC3_REVISION_210A &&
 737                                 dwc->revision <= DWC3_REVISION_250A))
 738                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 739                 else
 740                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 741                 break;
 742         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 743                 /* enable hibernation here */
 744                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 745
 746                 /*
 747                  * REVISIT Enabling this bit so that host-mode hibernation
 748                  * will work. Device-mode hibernation is not yet implemented.
 749                  */
 750                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 751                 break;
 752         default:
 753                 /* nothing */
 754                 break;
 755         }
 756
 757         /* check if current dwc3 is on simulation board */
 758         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 759                 dev_info(dwc->dev, "Running with FPGA optmizations\n");
 760                 dwc->is_fpga = true;
 761         }
 762
 763         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 764                         "disable_scramble cannot be used on non-FPGA builds\n");
 765
 766         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 767                 reg |= DWC3_GCTL_DISSCRAMBLE;
 768         else
 769                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 770
 771         if (dwc->u2exit_lfps_quirk)
 772                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 773
 774         /*
 775          * WORKAROUND: DWC3 revisions <1.90a have a bug
 776          * where the device can fail to connect at SuperSpeed
 777          * and falls back to high-speed mode which causes
 778          * the device to enter a Connect/Disconnect loop
 779          */
 780         if (dwc->revision < DWC3_REVISION_190A)
 781                 reg |= DWC3_GCTL_U2RSTECN;
 782
 783         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 784 }
 785
 786 static int dwc3_core_get_phy(struct dwc3 *dwc);
 787 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 788
 789 /* set global incr burst type configuration registers */
 790 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 791 {
 792         struct device *dev = dwc->dev;
 793         /* incrx_mode : for INCR burst type. */
 794         bool incrx_mode;
 795         /* incrx_size : for size of INCRX burst. */
 796         u32 incrx_size;
 797         u32 *vals;
 798         u32 cfg;
 799         int ntype;
 800         int ret;
 801         int i;
 802
 803         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 804
 805         /*
 806          * Handle property "snps,incr-burst-type-adjustment".
 807          * Get the number of value from this property:
 808          * result <= 0, means this property is not supported.
 809          * result = 1, means INCRx burst mode supported.
 810          * result > 1, means undefined length burst mode supported.
 811          */
 812         ntype = device_property_read_u32_array(dev,
 813                         "snps,incr-burst-type-adjustment", NULL, 0);
 814         if (ntype <= 0)
 815                 return;
 816
 817         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 818         if (!vals) {
 819                 dev_err(dev, "Error to get memory\n");
 820                 return;
 821         }
 822
 823         /* Get INCR burst type, and parse it */
 824         ret = device_property_read_u32_array(dev,
 825                         "snps,incr-burst-type-adjustment", vals, ntype);
 826         if (ret) {
 827                 dev_err(dev, "Error to get property\n");
 828                 return;
 829         }
 830
 831         incrx_size = *vals;
 832
 833         if (ntype > 1) {
 834                 /* INCRX (undefined length) burst mode */
 835                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 836                 for (i = 1; i < ntype; i++) {
 837                         if (vals[i] > incrx_size)
 838                                 incrx_size = vals[i];
 839                 }
 840         } else {
 841                 /* INCRX burst mode */
 842                 incrx_mode = INCRX_BURST_MODE;
 843         }
 844
 845         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 846         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 847         if (incrx_mode)
 848                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 849         switch (incrx_size) {
 850         case 256:
 851                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 852                 break;
 853         case 128:
 854                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 855                 break;
 856         case 64:
 857                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 858                 break;
 859         case 32:
 860                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 861                 break;
 862         case 16:
 863                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 864                 break;
 865         case 8:
 866                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 867                 break;
 868         case 4:
 869                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 870                 break;
 871         case 1:
 872                 break;
 873         default:
 874                 dev_err(dev, "Invalid property\n");
 875                 break;
 876         }
 877
 878         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 879 }
 880
 881 /**
 882  * dwc3_core_init - Low-level initialization of DWC3 Core
 883  * @dwc: Pointer to our controller context structure
 884  *
 885  * Returns 0 on success otherwise negative errno.
 886  */
 887 static int dwc3_core_init(struct dwc3 *dwc)
 888 {
 889         u32                     reg;
 890         int                     ret;
 891
 892         if (!dwc3_core_is_valid(dwc)) {
 893                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 894                 ret = -ENODEV;
 895                 goto err0;
 896         }
 897
 898         /*
 899          * Write Linux Version Code to our GUID register so it's easy to figure
 900          * out which kernel version a bug was found.
 901          */
 902         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 903
 904         /* Handle USB2.0-only core configuration */
 905         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 906                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 907                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 908                         dwc->maximum_speed = USB_SPEED_HIGH;
 909         }
 910
 911         ret = dwc3_phy_setup(dwc);
 912         if (ret)
 913                 goto err0;
 914
 915         if (!dwc->ulpi_ready) {
 916                 ret = dwc3_core_ulpi_init(dwc);
 917                 if (ret)
 918                         goto err0;
 919                 dwc->ulpi_ready = true;
 920         }
 921
 922         if (!dwc->phys_ready) {
 923                 ret = dwc3_core_get_phy(dwc);
 924                 if (ret)
 925                         goto err0a;
 926                 dwc->phys_ready = true;
 927         }
 928
 929         ret = dwc3_core_soft_reset(dwc);
 930         if (ret)
 931                 goto err0a;
 932
 933         dwc3_core_setup_global_control(dwc);
 934         dwc3_core_num_eps(dwc);
 935
 936         ret = dwc3_setup_scratch_buffers(dwc);
 937         if (ret)
 938                 goto err1;
 939
 940         /* Adjust Frame Length */
 941         dwc3_frame_length_adjustment(dwc);
 942
 943         dwc3_set_incr_burst_type(dwc);
 944
 945         usb_phy_set_suspend(dwc->usb2_phy, 0);
 946         usb_phy_set_suspend(dwc->usb3_phy, 0);
 947         ret = phy_power_on(dwc->usb2_generic_phy);
 948         if (ret < 0)
 949                 goto err2;
 950
 951         ret = phy_power_on(dwc->usb3_generic_phy);
 952         if (ret < 0)
 953                 goto err3;
 954
 955         ret = dwc3_event_buffers_setup(dwc);
 956         if (ret) {
 957                 dev_err(dwc->dev, "failed to setup event buffers\n");
 958                 goto err4;
 959         }
 960
 961         /*
 962          * ENDXFER polling is available on version 3.10a and later of
 963          * the DWC_usb3 controller. It is NOT available in the
 964          * DWC_usb31 controller.
 965          */
 966         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 967                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 968                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 969                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 970         }
 971
 972         if (dwc->revision >= DWC3_REVISION_250A) {
 973                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 974
 975                 /*
 976                  * Enable hardware control of sending remote wakeup
 977                  * in HS when the device is in the L1 state.
 978                  */
 979                 if (dwc->revision >= DWC3_REVISION_290A)
 980                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 981
 982                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 983                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 984
 985                 if (dwc->parkmode_disable_ss_quirk)
 986                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
 987
 988                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 989         }
 990
 991         if (dwc->dr_mode == USB_DR_MODE_HOST ||
 992             dwc->dr_mode == USB_DR_MODE_OTG) {
 993                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 994
 995                 /*
 996                  * Enable Auto retry Feature to make the controller operating in
 997                  * Host mode on seeing transaction errors(CRC errors or internal
 998                  * overrun scenerios) on IN transfers to reply to the device
 999                  * with a non-terminating retry ACK (i.e, an ACK transcation
1000                  * packet with Retry=1 & Nump != 0)
1001                  */
1002                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1003
1004                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1005         }
1006
1007         /*
1008          * Must config both number of packets and max burst settings to enable
1009          * RX and/or TX threshold.
1010          */
1011         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1012                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1013                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1014                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1015                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1016
1017                 if (rx_thr_num && rx_maxburst) {
1018                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1019                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1020
1021                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1022                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1023
1024                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1025                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1026
1027                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1028                 }
1029
1030                 if (tx_thr_num && tx_maxburst) {
1031                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1032                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1033
1034                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1035                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1036
1037                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1038                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1039
1040                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1041                 }
1042         }
1043
1044         return 0;
1045
1046 err4:
1047         phy_power_off(dwc->usb3_generic_phy);
1048
1049 err3:
1050         phy_power_off(dwc->usb2_generic_phy);
1051
1052 err2:
1053         usb_phy_set_suspend(dwc->usb2_phy, 1);
1054         usb_phy_set_suspend(dwc->usb3_phy, 1);
1055
1056 err1:
1057         usb_phy_shutdown(dwc->usb2_phy);
1058         usb_phy_shutdown(dwc->usb3_phy);
1059         phy_exit(dwc->usb2_generic_phy);
1060         phy_exit(dwc->usb3_generic_phy);
1061
1062 err0a:
1063         dwc3_ulpi_exit(dwc);
1064
1065 err0:
1066         return ret;
1067 }
1068
1069 static int dwc3_core_get_phy(struct dwc3 *dwc)
1070 {
1071         struct device           *dev = dwc->dev;
1072         struct device_node      *node = dev->of_node;
1073         int ret;
1074
1075         if (node) {
1076                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1077                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1078         } else {
1079                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1080                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1081         }
1082
1083         if (IS_ERR(dwc->usb2_phy)) {
1084                 ret = PTR_ERR(dwc->usb2_phy);
1085                 if (ret == -ENXIO || ret == -ENODEV) {
1086                         dwc->usb2_phy = NULL;
1087                 } else if (ret == -EPROBE_DEFER) {
1088                         return ret;
1089                 } else {
1090                         dev_err(dev, "no usb2 phy configured\n");
1091                         return ret;
1092                 }
1093         }
1094
1095         if (IS_ERR(dwc->usb3_phy)) {
1096                 ret = PTR_ERR(dwc->usb3_phy);
1097                 if (ret == -ENXIO || ret == -ENODEV) {
1098                         dwc->usb3_phy = NULL;
1099                 } else if (ret == -EPROBE_DEFER) {
1100                         return ret;
1101                 } else {
1102                         dev_err(dev, "no usb3 phy configured\n");
1103                         return ret;
1104                 }
1105         }
1106
1107         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1108         if (IS_ERR(dwc->usb2_generic_phy)) {
1109                 ret = PTR_ERR(dwc->usb2_generic_phy);
1110                 if (ret == -ENOSYS || ret == -ENODEV) {
1111                         dwc->usb2_generic_phy = NULL;
1112                 } else if (ret == -EPROBE_DEFER) {
1113                         return ret;
1114                 } else {
1115                         dev_err(dev, "no usb2 phy configured\n");
1116                         return ret;
1117                 }
1118         }
1119
1120         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1121         if (IS_ERR(dwc->usb3_generic_phy)) {
1122                 ret = PTR_ERR(dwc->usb3_generic_phy);
1123                 if (ret == -ENOSYS || ret == -ENODEV) {
1124                         dwc->usb3_generic_phy = NULL;
1125                 } else if (ret == -EPROBE_DEFER) {
1126                         return ret;
1127                 } else {
1128                         dev_err(dev, "no usb3 phy configured\n");
1129                         return ret;
1130                 }
1131         }
1132
1133         return 0;
1134 }
1135
1136 static int dwc3_core_init_mode(struct dwc3 *dwc)
1137 {
1138         struct device *dev = dwc->dev;
1139         int ret;
1140
1141         switch (dwc->dr_mode) {
1142         case USB_DR_MODE_PERIPHERAL:
1143                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1144
1145                 if (dwc->usb2_phy)
1146                         otg_set_vbus(dwc->usb2_phy->otg, false);
1147                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1148                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1149
1150                 ret = dwc3_gadget_init(dwc);
1151                 if (ret) {
1152                         if (ret != -EPROBE_DEFER)
1153                                 dev_err(dev, "failed to initialize gadget\n");
1154                         return ret;
1155                 }
1156                 break;
1157         case USB_DR_MODE_HOST:
1158                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1159
1160                 if (dwc->usb2_phy)
1161                         otg_set_vbus(dwc->usb2_phy->otg, true);
1162                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1163                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1164
1165                 ret = dwc3_host_init(dwc);
1166                 if (ret) {
1167                         if (ret != -EPROBE_DEFER)
1168                                 dev_err(dev, "failed to initialize host\n");
1169                         return ret;
1170                 }
1171                 phy_calibrate(dwc->usb2_generic_phy);
1172                 break;
1173         case USB_DR_MODE_OTG:
1174                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1175                 ret = dwc3_drd_init(dwc);
1176                 if (ret) {
1177                         if (ret != -EPROBE_DEFER)
1178                                 dev_err(dev, "failed to initialize dual-role\n");
1179                         return ret;
1180                 }
1181                 break;
1182         default:
1183                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1184                 return -EINVAL;
1185         }
1186
1187         return 0;
1188 }
1189
1190 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1191 {
1192         switch (dwc->dr_mode) {
1193         case USB_DR_MODE_PERIPHERAL:
1194                 dwc3_gadget_exit(dwc);
1195                 break;
1196         case USB_DR_MODE_HOST:
1197                 dwc3_host_exit(dwc);
1198                 break;
1199         case USB_DR_MODE_OTG:
1200                 dwc3_drd_exit(dwc);
1201                 break;
1202         default:
1203                 /* do nothing */
1204                 break;
1205         }
1206
1207         /* de-assert DRVVBUS for HOST and OTG mode */
1208         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1209 }
1210
1211 static void dwc3_get_properties(struct dwc3 *dwc)
1212 {
1213         struct device           *dev = dwc->dev;
1214         u8                      lpm_nyet_threshold;
1215         u8                      tx_de_emphasis;
1216         u8                      hird_threshold;
1217         u8                      rx_thr_num_pkt_prd = 0;
1218         u8                      rx_max_burst_prd = 0;
1219         u8                      tx_thr_num_pkt_prd = 0;
1220         u8                      tx_max_burst_prd = 0;
1221
1222         /* default to highest possible threshold */
1223         lpm_nyet_threshold = 0xf;
1224
1225         /* default to -3.5dB de-emphasis */
1226         tx_de_emphasis = 1;
1227
1228         /*
1229          * default to assert utmi_sleep_n and use maximum allowed HIRD
1230          * threshold value of 0b1100
1231          */
1232         hird_threshold = 12;
1233
1234         dwc->maximum_speed = usb_get_maximum_speed(dev);
1235         dwc->dr_mode = usb_get_dr_mode(dev);
1236         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1237
1238         dwc->sysdev_is_parent = device_property_read_bool(dev,
1239                                 "linux,sysdev_is_parent");
1240         if (dwc->sysdev_is_parent)
1241                 dwc->sysdev = dwc->dev->parent;
1242         else
1243                 dwc->sysdev = dwc->dev;
1244
1245         dwc->has_lpm_erratum = device_property_read_bool(dev,
1246                                 "snps,has-lpm-erratum");
1247         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1248                                 &lpm_nyet_threshold);
1249         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1250                                 "snps,is-utmi-l1-suspend");
1251         device_property_read_u8(dev, "snps,hird-threshold",
1252                                 &hird_threshold);
1253         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1254                                 "snps,usb3_lpm_capable");
1255         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1256                                 &rx_thr_num_pkt_prd);
1257         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1258                                 &rx_max_burst_prd);
1259         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1260                                 &tx_thr_num_pkt_prd);
1261         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1262                                 &tx_max_burst_prd);
1263
1264         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1265                                 "snps,disable_scramble_quirk");
1266         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1267                                 "snps,u2exit_lfps_quirk");
1268         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1269                                 "snps,u2ss_inp3_quirk");
1270         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1271                                 "snps,req_p1p2p3_quirk");
1272         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1273                                 "snps,del_p1p2p3_quirk");
1274         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1275                                 "snps,del_phy_power_chg_quirk");
1276         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1277                                 "snps,lfps_filter_quirk");
1278         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1279                                 "snps,rx_detect_poll_quirk");
1280         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1281                                 "snps,dis_u3_susphy_quirk");
1282         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1283                                 "snps,dis_u2_susphy_quirk");
1284         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1285                                 "snps,dis_enblslpm_quirk");
1286         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1287                                 "snps,dis_rxdet_inp3_quirk");
1288         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1289                                 "snps,dis-u2-freeclk-exists-quirk");
1290         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1291                                 "snps,dis-del-phy-power-chg-quirk");
1292         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1293                                 "snps,dis-tx-ipgap-linecheck-quirk");
1294         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1295                                 "snps,parkmode-disable-ss-quirk");
1296
1297         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1298                                 "snps,tx_de_emphasis_quirk");
1299         device_property_read_u8(dev, "snps,tx_de_emphasis",
1300                                 &tx_de_emphasis);
1301         device_property_read_string(dev, "snps,hsphy_interface",
1302                                     &dwc->hsphy_interface);
1303         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1304                                  &dwc->fladj);
1305
1306         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1307                                 "snps,dis_metastability_quirk");
1308
1309         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1310         dwc->tx_de_emphasis = tx_de_emphasis;
1311
1312         dwc->hird_threshold = hird_threshold
1313                 | (dwc->is_utmi_l1_suspend << 4);
1314
1315         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1316         dwc->rx_max_burst_prd = rx_max_burst_prd;
1317
1318         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1319         dwc->tx_max_burst_prd = tx_max_burst_prd;
1320
1321         dwc->imod_interval = 0;
1322 }
1323
1324 /* check whether the core supports IMOD */
1325 bool dwc3_has_imod(struct dwc3 *dwc)
1326 {
1327         return ((dwc3_is_usb3(dwc) &&
1328                  dwc->revision >= DWC3_REVISION_300A) ||
1329                 (dwc3_is_usb31(dwc) &&
1330                  dwc->revision >= DWC3_USB31_REVISION_120A));
1331 }
1332
1333 static void dwc3_check_params(struct dwc3 *dwc)
1334 {
1335         struct device *dev = dwc->dev;
1336
1337         /* Check for proper value of imod_interval */
1338         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1339                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1340                 dwc->imod_interval = 0;
1341         }
1342
1343         /*
1344          * Workaround for STAR 9000961433 which affects only version
1345          * 3.00a of the DWC_usb3 core. This prevents the controller
1346          * interrupt from being masked while handling events. IMOD
1347          * allows us to work around this issue. Enable it for the
1348          * affected version.
1349          */
1350         if (!dwc->imod_interval &&
1351             (dwc->revision == DWC3_REVISION_300A))
1352                 dwc->imod_interval = 1;
1353
1354         /* Check the maximum_speed parameter */
1355         switch (dwc->maximum_speed) {
1356         case USB_SPEED_LOW:
1357         case USB_SPEED_FULL:
1358         case USB_SPEED_HIGH:
1359         case USB_SPEED_SUPER:
1360         case USB_SPEED_SUPER_PLUS:
1361                 break;
1362         default:
1363                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1364                         dwc->maximum_speed);
1365                 /* fall through */
1366         case USB_SPEED_UNKNOWN:
1367                 /* default to superspeed */
1368                 dwc->maximum_speed = USB_SPEED_SUPER;
1369
1370                 /*
1371                  * default to superspeed plus if we are capable.
1372                  */
1373                 if (dwc3_is_usb31(dwc) &&
1374                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1375                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1376                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1377
1378                 break;
1379         }
1380 }
1381
1382 static int dwc3_probe(struct platform_device *pdev)
1383 {
1384         struct device           *dev = &pdev->dev;
1385         struct resource         *res, dwc_res;
1386         struct dwc3             *dwc;
1387
1388         int                     ret;
1389
1390         void __iomem            *regs;
1391
1392         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1393         if (!dwc)
1394                 return -ENOMEM;
1395
1396         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1397                                  GFP_KERNEL);
1398         if (!dwc->clks)
1399                 return -ENOMEM;
1400
1401         dwc->dev = dev;
1402
1403         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1404         if (!res) {
1405                 dev_err(dev, "missing memory resource\n");
1406                 return -ENODEV;
1407         }
1408
1409         dwc->xhci_resources[0].start = res->start;
1410         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1411                                         DWC3_XHCI_REGS_END;
1412         dwc->xhci_resources[0].flags = res->flags;
1413         dwc->xhci_resources[0].name = res->name;
1414
1415         /*
1416          * Request memory region but exclude xHCI regs,
1417          * since it will be requested by the xhci-plat driver.
1418          */
1419         dwc_res = *res;
1420         dwc_res.start += DWC3_GLOBALS_REGS_START;
1421
1422         regs = devm_ioremap_resource(dev, &dwc_res);
1423         if (IS_ERR(regs))
1424                 return PTR_ERR(regs);
1425
1426         dwc->regs       = regs;
1427         dwc->regs_size  = resource_size(&dwc_res);
1428
1429         dwc3_get_properties(dwc);
1430
1431         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1432         if (IS_ERR(dwc->reset))
1433                 return PTR_ERR(dwc->reset);
1434
1435         if (dev->of_node) {
1436                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1437
1438                 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1439                 if (ret == -EPROBE_DEFER)
1440                         return ret;
1441                 /*
1442                  * Clocks are optional, but new DT platforms should support all
1443                  * clocks as required by the DT-binding.
1444                  */
1445                 if (ret)
1446                         dwc->num_clks = 0;
1447         }
1448
1449         ret = reset_control_deassert(dwc->reset);
1450         if (ret)
1451                 goto put_clks;
1452
1453         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1454         if (ret)
1455                 goto assert_reset;
1456
1457         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1458         if (ret)
1459                 goto unprepare_clks;
1460
1461         platform_set_drvdata(pdev, dwc);
1462         dwc3_cache_hwparams(dwc);
1463
1464         spin_lock_init(&dwc->lock);
1465
1466         pm_runtime_set_active(dev);
1467         pm_runtime_use_autosuspend(dev);
1468         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1469         pm_runtime_enable(dev);
1470         ret = pm_runtime_get_sync(dev);
1471         if (ret < 0)
1472                 goto err1;
1473
1474         pm_runtime_forbid(dev);
1475
1476         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1477         if (ret) {
1478                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1479                 ret = -ENOMEM;
1480                 goto err2;
1481         }
1482
1483         ret = dwc3_get_dr_mode(dwc);
1484         if (ret)
1485                 goto err3;
1486
1487         ret = dwc3_alloc_scratch_buffers(dwc);
1488         if (ret)
1489                 goto err3;
1490
1491         ret = dwc3_core_init(dwc);
1492         if (ret) {
1493                 if (ret != -EPROBE_DEFER)
1494                         dev_err(dev, "failed to initialize core: %d\n", ret);
1495                 goto err4;
1496         }
1497
1498         dwc3_check_params(dwc);
1499         dwc3_debugfs_init(dwc);
1500
1501         ret = dwc3_core_init_mode(dwc);
1502         if (ret)
1503                 goto err5;
1504
1505         pm_runtime_put(dev);
1506
1507         return 0;
1508
1509 err5:
1510         dwc3_debugfs_exit(dwc);
1511         dwc3_event_buffers_cleanup(dwc);
1512
1513         usb_phy_set_suspend(dwc->usb2_phy, 1);
1514         usb_phy_set_suspend(dwc->usb3_phy, 1);
1515         phy_power_off(dwc->usb2_generic_phy);
1516         phy_power_off(dwc->usb3_generic_phy);
1517
1518         usb_phy_shutdown(dwc->usb2_phy);
1519         usb_phy_shutdown(dwc->usb3_phy);
1520         phy_exit(dwc->usb2_generic_phy);
1521         phy_exit(dwc->usb3_generic_phy);
1522
1523         dwc3_ulpi_exit(dwc);
1524
1525 err4:
1526         dwc3_free_scratch_buffers(dwc);
1527
1528 err3:
1529         dwc3_free_event_buffers(dwc);
1530
1531 err2:
1532         pm_runtime_allow(&pdev->dev);
1533
1534 err1:
1535         pm_runtime_put_sync(&pdev->dev);
1536         pm_runtime_disable(&pdev->dev);
1537
1538         clk_bulk_disable(dwc->num_clks, dwc->clks);
1539 unprepare_clks:
1540         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1541 assert_reset:
1542         reset_control_assert(dwc->reset);
1543 put_clks:
1544         clk_bulk_put(dwc->num_clks, dwc->clks);
1545
1546         return ret;
1547 }
1548
1549 static int dwc3_remove(struct platform_device *pdev)
1550 {
1551         struct dwc3     *dwc = platform_get_drvdata(pdev);
1552
1553         pm_runtime_get_sync(&pdev->dev);
1554
1555         dwc3_core_exit_mode(dwc);
1556         dwc3_debugfs_exit(dwc);
1557
1558         dwc3_core_exit(dwc);
1559         dwc3_ulpi_exit(dwc);
1560
1561         pm_runtime_disable(&pdev->dev);
1562         pm_runtime_put_noidle(&pdev->dev);
1563         pm_runtime_set_suspended(&pdev->dev);
1564
1565         dwc3_free_event_buffers(dwc);
1566         dwc3_free_scratch_buffers(dwc);
1567         clk_bulk_put(dwc->num_clks, dwc->clks);
1568
1569         return 0;
1570 }
1571
1572 #ifdef CONFIG_PM
1573 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1574 {
1575         int ret;
1576
1577         ret = reset_control_deassert(dwc->reset);
1578         if (ret)
1579                 return ret;
1580
1581         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1582         if (ret)
1583                 goto assert_reset;
1584
1585         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1586         if (ret)
1587                 goto unprepare_clks;
1588
1589         ret = dwc3_core_init(dwc);
1590         if (ret)
1591                 goto disable_clks;
1592
1593         return 0;
1594
1595 disable_clks:
1596         clk_bulk_disable(dwc->num_clks, dwc->clks);
1597 unprepare_clks:
1598         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1599 assert_reset:
1600         reset_control_assert(dwc->reset);
1601
1602         return ret;
1603 }
1604
1605 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1606 {
1607         unsigned long   flags;
1608         u32 reg;
1609
1610         switch (dwc->current_dr_role) {
1611         case DWC3_GCTL_PRTCAP_DEVICE:
1612                 spin_lock_irqsave(&dwc->lock, flags);
1613                 dwc3_gadget_suspend(dwc);
1614                 spin_unlock_irqrestore(&dwc->lock, flags);
1615                 synchronize_irq(dwc->irq_gadget);
1616                 dwc3_core_exit(dwc);
1617                 break;
1618         case DWC3_GCTL_PRTCAP_HOST:
1619                 if (!PMSG_IS_AUTO(msg)) {
1620                         dwc3_core_exit(dwc);
1621                         break;
1622                 }
1623
1624                 /* Let controller to suspend HSPHY before PHY driver suspends */
1625                 if (dwc->dis_u2_susphy_quirk ||
1626                     dwc->dis_enblslpm_quirk) {
1627                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1628                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1629                                 DWC3_GUSB2PHYCFG_SUSPHY;
1630                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1631
1632                         /* Give some time for USB2 PHY to suspend */
1633                         usleep_range(5000, 6000);
1634                 }
1635
1636                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1637                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1638                 break;
1639         case DWC3_GCTL_PRTCAP_OTG:
1640                 /* do nothing during runtime_suspend */
1641                 if (PMSG_IS_AUTO(msg))
1642                         break;
1643
1644                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1645                         spin_lock_irqsave(&dwc->lock, flags);
1646                         dwc3_gadget_suspend(dwc);
1647                         spin_unlock_irqrestore(&dwc->lock, flags);
1648                         synchronize_irq(dwc->irq_gadget);
1649                 }
1650
1651                 dwc3_otg_exit(dwc);
1652                 dwc3_core_exit(dwc);
1653                 break;
1654         default:
1655                 /* do nothing */
1656                 break;
1657         }
1658
1659         return 0;
1660 }
1661
1662 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1663 {
1664         unsigned long   flags;
1665         int             ret;
1666         u32             reg;
1667
1668         switch (dwc->current_dr_role) {
1669         case DWC3_GCTL_PRTCAP_DEVICE:
1670                 ret = dwc3_core_init_for_resume(dwc);
1671                 if (ret)
1672                         return ret;
1673
1674                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1675                 spin_lock_irqsave(&dwc->lock, flags);
1676                 dwc3_gadget_resume(dwc);
1677                 spin_unlock_irqrestore(&dwc->lock, flags);
1678                 break;
1679         case DWC3_GCTL_PRTCAP_HOST:
1680                 if (!PMSG_IS_AUTO(msg)) {
1681                         ret = dwc3_core_init_for_resume(dwc);
1682                         if (ret)
1683                                 return ret;
1684                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1685                         break;
1686                 }
1687                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1688                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1689                 if (dwc->dis_u2_susphy_quirk)
1690                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1691
1692                 if (dwc->dis_enblslpm_quirk)
1693                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1694
1695                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1696
1697                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1698                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1699                 break;
1700         case DWC3_GCTL_PRTCAP_OTG:
1701                 /* nothing to do on runtime_resume */
1702                 if (PMSG_IS_AUTO(msg))
1703                         break;
1704
1705                 ret = dwc3_core_init_for_resume(dwc);
1706                 if (ret)
1707                         return ret;
1708
1709                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1710
1711                 dwc3_otg_init(dwc);
1712                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1713                         dwc3_otg_host_init(dwc);
1714                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1715                         spin_lock_irqsave(&dwc->lock, flags);
1716                         dwc3_gadget_resume(dwc);
1717                         spin_unlock_irqrestore(&dwc->lock, flags);
1718                 }
1719
1720                 break;
1721         default:
1722                 /* do nothing */
1723                 break;
1724         }
1725
1726         return 0;
1727 }
1728
1729 static int dwc3_runtime_checks(struct dwc3 *dwc)
1730 {
1731         switch (dwc->current_dr_role) {
1732         case DWC3_GCTL_PRTCAP_DEVICE:
1733                 if (dwc->connected)
1734                         return -EBUSY;
1735                 break;
1736         case DWC3_GCTL_PRTCAP_HOST:
1737         default:
1738                 /* do nothing */
1739                 break;
1740         }
1741
1742         return 0;
1743 }
1744
1745 static int dwc3_runtime_suspend(struct device *dev)
1746 {
1747         struct dwc3     *dwc = dev_get_drvdata(dev);
1748         int             ret;
1749
1750         if (dwc3_runtime_checks(dwc))
1751                 return -EBUSY;
1752
1753         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1754         if (ret)
1755                 return ret;
1756
1757         device_init_wakeup(dev, true);
1758
1759         return 0;
1760 }
1761
1762 static int dwc3_runtime_resume(struct device *dev)
1763 {
1764         struct dwc3     *dwc = dev_get_drvdata(dev);
1765         int             ret;
1766
1767         device_init_wakeup(dev, false);
1768
1769         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1770         if (ret)
1771                 return ret;
1772
1773         switch (dwc->current_dr_role) {
1774         case DWC3_GCTL_PRTCAP_DEVICE:
1775                 dwc3_gadget_process_pending_events(dwc);
1776                 break;
1777         case DWC3_GCTL_PRTCAP_HOST:
1778         default:
1779                 /* do nothing */
1780                 break;
1781         }
1782
1783         pm_runtime_mark_last_busy(dev);
1784
1785         return 0;
1786 }
1787
1788 static int dwc3_runtime_idle(struct device *dev)
1789 {
1790         struct dwc3     *dwc = dev_get_drvdata(dev);
1791
1792         switch (dwc->current_dr_role) {
1793         case DWC3_GCTL_PRTCAP_DEVICE:
1794                 if (dwc3_runtime_checks(dwc))
1795                         return -EBUSY;
1796                 break;
1797         case DWC3_GCTL_PRTCAP_HOST:
1798         default:
1799                 /* do nothing */
1800                 break;
1801         }
1802
1803         pm_runtime_mark_last_busy(dev);
1804         pm_runtime_autosuspend(dev);
1805
1806         return 0;
1807 }
1808 #endif /* CONFIG_PM */
1809
1810 #ifdef CONFIG_PM_SLEEP
1811 static int dwc3_suspend(struct device *dev)
1812 {
1813         struct dwc3     *dwc = dev_get_drvdata(dev);
1814         int             ret;
1815
1816         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1817         if (ret)
1818                 return ret;
1819
1820         pinctrl_pm_select_sleep_state(dev);
1821
1822         return 0;
1823 }
1824
1825 static int dwc3_resume(struct device *dev)
1826 {
1827         struct dwc3     *dwc = dev_get_drvdata(dev);
1828         int             ret;
1829
1830         pinctrl_pm_select_default_state(dev);
1831
1832         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1833         if (ret)
1834                 return ret;
1835
1836         pm_runtime_disable(dev);
1837         pm_runtime_set_active(dev);
1838         pm_runtime_enable(dev);
1839
1840         return 0;
1841 }
1842 #endif /* CONFIG_PM_SLEEP */
1843
1844 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1845         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1846         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1847                         dwc3_runtime_idle)
1848 };
1849
1850 #ifdef CONFIG_OF
1851 static const struct of_device_id of_dwc3_match[] = {
1852         {
1853                 .compatible = "snps,dwc3"
1854         },
1855         {
1856                 .compatible = "synopsys,dwc3"
1857         },
1858         { },
1859 };
1860 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1861 #endif
1862
1863 #ifdef CONFIG_ACPI
1864
1865 #define ACPI_ID_INTEL_BSW       "808622B7"
1866
1867 static const struct acpi_device_id dwc3_acpi_match[] = {
1868         { ACPI_ID_INTEL_BSW, 0 },
1869         { },
1870 };
1871 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1872 #endif
1873
1874 static struct platform_driver dwc3_driver = {
1875         .probe          = dwc3_probe,
1876         .remove         = dwc3_remove,
1877         .driver         = {
1878                 .name   = "dwc3",
1879                 .of_match_table = of_match_ptr(of_dwc3_match),
1880                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1881                 .pm     = &dwc3_dev_pm_ops,
1882         },
1883 };
1884
1885 module_platform_driver(dwc3_driver);
1886
1887 MODULE_ALIAS("platform:dwc3");
1888 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1889 MODULE_LICENSE("GPL v2");
1890 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");